14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland #include "dm_services.h" 264562236bSHarry Wentland #include "dc.h" 274562236bSHarry Wentland #include "dc_bios_types.h" 284562236bSHarry Wentland #include "core_types.h" 294562236bSHarry Wentland #include "core_status.h" 304562236bSHarry Wentland #include "resource.h" 314562236bSHarry Wentland #include "dm_helpers.h" 324562236bSHarry Wentland #include "dce110_hw_sequencer.h" 334562236bSHarry Wentland #include "dce110_timing_generator.h" 3498489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 3587401969SAndrew Jiang #include "gpio_service_interface.h" 364562236bSHarry Wentland 373eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 381663ae1cSBhawanpreet Lakha #include "dce110_compressor.h" 391663ae1cSBhawanpreet Lakha #endif 401663ae1cSBhawanpreet Lakha 414562236bSHarry Wentland #include "bios/bios_parser_helper.h" 424562236bSHarry Wentland #include "timing_generator.h" 434562236bSHarry Wentland #include "mem_input.h" 444562236bSHarry Wentland #include "opp.h" 454562236bSHarry Wentland #include "ipp.h" 464562236bSHarry Wentland #include "transform.h" 474562236bSHarry Wentland #include "stream_encoder.h" 484562236bSHarry Wentland #include "link_encoder.h" 4987401969SAndrew Jiang #include "link_hwss.h" 504562236bSHarry Wentland #include "clock_source.h" 515e7773a2SAnthony Koo #include "abm.h" 524562236bSHarry Wentland #include "audio.h" 5308b16886SZeyu Fan #include "reg_helper.h" 544562236bSHarry Wentland 554562236bSHarry Wentland /* include DCE11 register header files */ 564562236bSHarry Wentland #include "dce/dce_11_0_d.h" 574562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 58e266fdf6SVitaly Prosyak #include "custom_float.h" 594562236bSHarry Wentland 6087401969SAndrew Jiang /* 6187401969SAndrew Jiang * All values are in milliseconds; 6287401969SAndrew Jiang * For eDP, after power-up/power/down, 6387401969SAndrew Jiang * 300/500 msec max. delay from LCDVCC to black video generation 6487401969SAndrew Jiang */ 6587401969SAndrew Jiang #define PANEL_POWER_UP_TIMEOUT 300 6687401969SAndrew Jiang #define PANEL_POWER_DOWN_TIMEOUT 500 6787401969SAndrew Jiang #define HPD_CHECK_INTERVAL 10 6887401969SAndrew Jiang 695eefbc40SYue Hin Lau #define CTX \ 705eefbc40SYue Hin Lau hws->ctx 715eefbc40SYue Hin Lau #define REG(reg)\ 725eefbc40SYue Hin Lau hws->regs->reg 735eefbc40SYue Hin Lau 745eefbc40SYue Hin Lau #undef FN 755eefbc40SYue Hin Lau #define FN(reg_name, field_name) \ 765eefbc40SYue Hin Lau hws->shifts->field_name, hws->masks->field_name 775eefbc40SYue Hin Lau 784562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 794562236bSHarry Wentland uint32_t crtc; 804562236bSHarry Wentland }; 814562236bSHarry Wentland 824562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 834562236bSHarry Wentland { 844562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 854562236bSHarry Wentland }, 864562236bSHarry Wentland { 874562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 884562236bSHarry Wentland }, 894562236bSHarry Wentland { 904562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 914562236bSHarry Wentland }, 924562236bSHarry Wentland { 934562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 944562236bSHarry Wentland } 954562236bSHarry Wentland }; 964562236bSHarry Wentland 974562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 984562236bSHarry Wentland (reg + reg_offsets[id].blnd) 994562236bSHarry Wentland 1004562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 1014562236bSHarry Wentland (reg + reg_offsets[id].crtc) 1024562236bSHarry Wentland 1034562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 1044562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 1054562236bSHarry Wentland 1064562236bSHarry Wentland /******************************************************************************* 1074562236bSHarry Wentland * Private definitions 1084562236bSHarry Wentland ******************************************************************************/ 1094562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 1104562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 1114562236bSHarry Wentland { 1124562236bSHarry Wentland uint32_t addr; 1134562236bSHarry Wentland uint32_t value = 0; 1144562236bSHarry Wentland uint32_t chunk_int = 0; 1154562236bSHarry Wentland uint32_t chunk_mul = 0; 1164562236bSHarry Wentland 1174562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 1184562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1194562236bSHarry Wentland 1204562236bSHarry Wentland set_reg_field_value( 1214562236bSHarry Wentland value, 1224562236bSHarry Wentland 0, 1234562236bSHarry Wentland DVMM_PTE_CONTROL, 1244562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1254562236bSHarry Wentland 1264562236bSHarry Wentland set_reg_field_value( 1274562236bSHarry Wentland value, 1284562236bSHarry Wentland 1, 1294562236bSHarry Wentland DVMM_PTE_CONTROL, 1304562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1314562236bSHarry Wentland 1324562236bSHarry Wentland set_reg_field_value( 1334562236bSHarry Wentland value, 1344562236bSHarry Wentland 1, 1354562236bSHarry Wentland DVMM_PTE_CONTROL, 1364562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1374562236bSHarry Wentland 1384562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1394562236bSHarry Wentland 1404562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1414562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1424562236bSHarry Wentland 1434562236bSHarry Wentland chunk_int = get_reg_field_value( 1444562236bSHarry Wentland value, 1454562236bSHarry Wentland DVMM_PTE_REQ, 1464562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1474562236bSHarry Wentland 1484562236bSHarry Wentland chunk_mul = get_reg_field_value( 1494562236bSHarry Wentland value, 1504562236bSHarry Wentland DVMM_PTE_REQ, 1514562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1524562236bSHarry Wentland 1534562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1544562236bSHarry Wentland 1554562236bSHarry Wentland set_reg_field_value( 1564562236bSHarry Wentland value, 1574562236bSHarry Wentland 255, 1584562236bSHarry Wentland DVMM_PTE_REQ, 1594562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1604562236bSHarry Wentland 1614562236bSHarry Wentland set_reg_field_value( 1624562236bSHarry Wentland value, 1634562236bSHarry Wentland 4, 1644562236bSHarry Wentland DVMM_PTE_REQ, 1654562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1664562236bSHarry Wentland 1674562236bSHarry Wentland set_reg_field_value( 1684562236bSHarry Wentland value, 1694562236bSHarry Wentland 4, 1704562236bSHarry Wentland DVMM_PTE_REQ, 1714562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1724562236bSHarry Wentland 1734562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1744562236bSHarry Wentland } 1754562236bSHarry Wentland } 1764562236bSHarry Wentland /**************************************************************************/ 1774562236bSHarry Wentland 1784562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1794562236bSHarry Wentland struct dc_context *ctx, 1804562236bSHarry Wentland bool clock_gating) 1814562236bSHarry Wentland { 1824562236bSHarry Wentland /*TODO*/ 1834562236bSHarry Wentland } 1844562236bSHarry Wentland 1854562236bSHarry Wentland static bool dce110_enable_display_power_gating( 186fb3466a4SBhawanpreet Lakha struct dc *dc, 1874562236bSHarry Wentland uint8_t controller_id, 1884562236bSHarry Wentland struct dc_bios *dcb, 1894562236bSHarry Wentland enum pipe_gating_control power_gating) 1904562236bSHarry Wentland { 1914562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 1924562236bSHarry Wentland enum bp_pipe_control_action cntl; 1934562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 1944562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1954562236bSHarry Wentland 1964562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 1974562236bSHarry Wentland return true; 1984562236bSHarry Wentland 1994562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 2004562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 2014562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 2024562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 2034562236bSHarry Wentland else 2044562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 2054562236bSHarry Wentland 2064562236bSHarry Wentland if (controller_id == underlay_idx) 2074562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 2084562236bSHarry Wentland 2094562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 2104562236bSHarry Wentland 2114562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 2124562236bSHarry Wentland dcb, controller_id + 1, cntl); 2134562236bSHarry Wentland 2144562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 2154562236bSHarry Wentland * by default when command table is called 2164562236bSHarry Wentland * 2174562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 2184562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 2194562236bSHarry Wentland * than 3. 2204562236bSHarry Wentland */ 2214562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 2224562236bSHarry Wentland dm_write_reg(ctx, 2234562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2244562236bSHarry Wentland 0); 2254562236bSHarry Wentland } 2264562236bSHarry Wentland 2274562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2284562236bSHarry Wentland dce110_init_pte(ctx); 2294562236bSHarry Wentland 2304562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2314562236bSHarry Wentland return true; 2324562236bSHarry Wentland else 2334562236bSHarry Wentland return false; 2344562236bSHarry Wentland } 2354562236bSHarry Wentland 2364562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2373be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2384562236bSHarry Wentland { 2394562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2404562236bSHarry Wentland 2413be5262eSHarry Wentland switch (plane_state->format) { 2424562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2438693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2444562236bSHarry Wentland prescale_params->scale = 0x2020; 2454562236bSHarry Wentland break; 2464562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2474562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2484562236bSHarry Wentland prescale_params->scale = 0x2008; 2494562236bSHarry Wentland break; 2504562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2514562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2524562236bSHarry Wentland prescale_params->scale = 0x2000; 2534562236bSHarry Wentland break; 2544562236bSHarry Wentland default: 2554562236bSHarry Wentland ASSERT(false); 256d7194cf6SAric Cyr break; 2574562236bSHarry Wentland } 2584562236bSHarry Wentland } 2594562236bSHarry Wentland 260a6114e85SHarry Wentland static bool 261a6114e85SHarry Wentland dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, 2623be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2634562236bSHarry Wentland { 26486a66c4eSHarry Wentland struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2657b0c470fSLeo (Sunpeng) Li const struct dc_transfer_func *tf = NULL; 26690e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 26790e508baSAnthony Koo bool result = true; 26890e508baSAnthony Koo 26990e508baSAnthony Koo if (ipp == NULL) 27090e508baSAnthony Koo return false; 27190e508baSAnthony Koo 2723be5262eSHarry Wentland if (plane_state->in_transfer_func) 2733be5262eSHarry Wentland tf = plane_state->in_transfer_func; 27490e508baSAnthony Koo 2753be5262eSHarry Wentland build_prescale_params(&prescale_params, plane_state); 27690e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 27790e508baSAnthony Koo 278405c50a0SAndrew Jiang if (plane_state->gamma_correction && dce_use_lut(plane_state->format)) 2793be5262eSHarry Wentland ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 280d7194cf6SAric Cyr 28190e508baSAnthony Koo if (tf == NULL) { 28290e508baSAnthony Koo /* Default case if no input transfer function specified */ 283a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 2847b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_PREDEFINED) { 2857b0c470fSLeo (Sunpeng) Li switch (tf->tf) { 28690e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 287a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 28890e508baSAnthony Koo break; 28990e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 290a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 29190e508baSAnthony Koo break; 29290e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 293a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 29490e508baSAnthony Koo break; 29590e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 29690e508baSAnthony Koo default: 29790e508baSAnthony Koo result = false; 298d7194cf6SAric Cyr break; 29990e508baSAnthony Koo } 3007b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_BYPASS) { 30170063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 30290e508baSAnthony Koo } else { 30390e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 30490e508baSAnthony Koo result = false; 30590e508baSAnthony Koo } 30690e508baSAnthony Koo 30790e508baSAnthony Koo return result; 30890e508baSAnthony Koo } 30990e508baSAnthony Koo 310bd1be8e8SHarry Wentland static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 311fcd2f4bfSAmy Zhang struct curve_points *arr_points, 312fcd2f4bfSAmy Zhang uint32_t hw_points_num) 313fcd2f4bfSAmy Zhang { 314fcd2f4bfSAmy Zhang struct custom_float_format fmt; 315fcd2f4bfSAmy Zhang 316fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 317fcd2f4bfSAmy Zhang 318fcd2f4bfSAmy Zhang uint32_t i = 0; 319fcd2f4bfSAmy Zhang 320fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 321fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 322fcd2f4bfSAmy Zhang fmt.sign = true; 323fcd2f4bfSAmy Zhang 324bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 325fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 326fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 327fcd2f4bfSAmy Zhang return false; 328fcd2f4bfSAmy Zhang } 329fcd2f4bfSAmy Zhang 330bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 331fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 332fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 333fcd2f4bfSAmy Zhang return false; 334fcd2f4bfSAmy Zhang } 335fcd2f4bfSAmy Zhang 336bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 337fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 338fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 339fcd2f4bfSAmy Zhang return false; 340fcd2f4bfSAmy Zhang } 341fcd2f4bfSAmy Zhang 342fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 343fcd2f4bfSAmy Zhang fmt.sign = false; 344fcd2f4bfSAmy Zhang 345bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 346fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 347fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 348fcd2f4bfSAmy Zhang return false; 349fcd2f4bfSAmy Zhang } 350fcd2f4bfSAmy Zhang 351bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 352fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 353fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 354fcd2f4bfSAmy Zhang return false; 355fcd2f4bfSAmy Zhang } 356fcd2f4bfSAmy Zhang 3574d06ccd0SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 3584d06ccd0SHarry Wentland &arr_points[1].custom_float_slope)) { 359fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 360fcd2f4bfSAmy Zhang return false; 361fcd2f4bfSAmy Zhang } 362fcd2f4bfSAmy Zhang 363fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 364fcd2f4bfSAmy Zhang fmt.sign = true; 365fcd2f4bfSAmy Zhang 366fcd2f4bfSAmy Zhang while (i != hw_points_num) { 367bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->red, &fmt, 368fcd2f4bfSAmy Zhang &rgb->red_reg)) { 369fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 370fcd2f4bfSAmy Zhang return false; 371fcd2f4bfSAmy Zhang } 372fcd2f4bfSAmy Zhang 373bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->green, &fmt, 374fcd2f4bfSAmy Zhang &rgb->green_reg)) { 375fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 376fcd2f4bfSAmy Zhang return false; 377fcd2f4bfSAmy Zhang } 378fcd2f4bfSAmy Zhang 379bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->blue, &fmt, 380fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 381fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 382fcd2f4bfSAmy Zhang return false; 383fcd2f4bfSAmy Zhang } 384fcd2f4bfSAmy Zhang 385bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 386fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 387fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 388fcd2f4bfSAmy Zhang return false; 389fcd2f4bfSAmy Zhang } 390fcd2f4bfSAmy Zhang 391bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 392fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 393fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 394fcd2f4bfSAmy Zhang return false; 395fcd2f4bfSAmy Zhang } 396fcd2f4bfSAmy Zhang 397bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 398fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 399fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 400fcd2f4bfSAmy Zhang return false; 401fcd2f4bfSAmy Zhang } 402fcd2f4bfSAmy Zhang 403fcd2f4bfSAmy Zhang ++rgb; 404fcd2f4bfSAmy Zhang ++i; 405fcd2f4bfSAmy Zhang } 406fcd2f4bfSAmy Zhang 407fcd2f4bfSAmy Zhang return true; 408fcd2f4bfSAmy Zhang } 409fcd2f4bfSAmy Zhang 410b310b081SHarry Wentland static bool 411b310b081SHarry Wentland dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 412b310b081SHarry Wentland struct pwl_params *regamma_params) 413fcd2f4bfSAmy Zhang { 41423ae4f8eSAmy Zhang struct curve_points *arr_points; 41523ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 41623ae4f8eSAmy Zhang struct pwl_result_data *rgb; 41723ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 418fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 419fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 420fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 421fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 422fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 423fcd2f4bfSAmy Zhang 424fcd2f4bfSAmy Zhang int32_t segment_start, segment_end; 42523ae4f8eSAmy Zhang uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; 42623ae4f8eSAmy Zhang 427b310b081SHarry Wentland if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 42823ae4f8eSAmy Zhang return false; 42923ae4f8eSAmy Zhang 43023ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 43123ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 43223ae4f8eSAmy Zhang hw_points = 0; 433fcd2f4bfSAmy Zhang 434fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 435fcd2f4bfSAmy Zhang 436fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 437534db198SAmy Zhang /* 16 segments 438fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 439fcd2f4bfSAmy Zhang */ 440fcd2f4bfSAmy Zhang segment_start = -11; 441fcd2f4bfSAmy Zhang segment_end = 5; 442fcd2f4bfSAmy Zhang 443534db198SAmy Zhang seg_distr[0] = 2; 444534db198SAmy Zhang seg_distr[1] = 2; 445534db198SAmy Zhang seg_distr[2] = 2; 446534db198SAmy Zhang seg_distr[3] = 2; 447534db198SAmy Zhang seg_distr[4] = 2; 448534db198SAmy Zhang seg_distr[5] = 2; 449534db198SAmy Zhang seg_distr[6] = 3; 450534db198SAmy Zhang seg_distr[7] = 4; 451534db198SAmy Zhang seg_distr[8] = 4; 452534db198SAmy Zhang seg_distr[9] = 4; 453534db198SAmy Zhang seg_distr[10] = 4; 454534db198SAmy Zhang seg_distr[11] = 5; 455534db198SAmy Zhang seg_distr[12] = 5; 456534db198SAmy Zhang seg_distr[13] = 5; 457534db198SAmy Zhang seg_distr[14] = 5; 458534db198SAmy Zhang seg_distr[15] = 5; 459534db198SAmy Zhang 460fcd2f4bfSAmy Zhang } else { 461534db198SAmy Zhang /* 10 segments 462fcd2f4bfSAmy Zhang * segment is from 2^-10 to 2^0 463fcd2f4bfSAmy Zhang */ 464fcd2f4bfSAmy Zhang segment_start = -10; 465fcd2f4bfSAmy Zhang segment_end = 0; 466534db198SAmy Zhang 467534db198SAmy Zhang seg_distr[0] = 3; 468534db198SAmy Zhang seg_distr[1] = 4; 469534db198SAmy Zhang seg_distr[2] = 4; 470534db198SAmy Zhang seg_distr[3] = 4; 471534db198SAmy Zhang seg_distr[4] = 4; 472534db198SAmy Zhang seg_distr[5] = 4; 473534db198SAmy Zhang seg_distr[6] = 4; 474534db198SAmy Zhang seg_distr[7] = 4; 475534db198SAmy Zhang seg_distr[8] = 5; 476534db198SAmy Zhang seg_distr[9] = 5; 477534db198SAmy Zhang seg_distr[10] = -1; 478534db198SAmy Zhang seg_distr[11] = -1; 479534db198SAmy Zhang seg_distr[12] = -1; 480534db198SAmy Zhang seg_distr[13] = -1; 481534db198SAmy Zhang seg_distr[14] = -1; 482534db198SAmy Zhang seg_distr[15] = -1; 483fcd2f4bfSAmy Zhang } 484fcd2f4bfSAmy Zhang 485534db198SAmy Zhang for (k = 0; k < 16; k++) { 486534db198SAmy Zhang if (seg_distr[k] != -1) 487534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 488534db198SAmy Zhang } 489534db198SAmy Zhang 490fcd2f4bfSAmy Zhang j = 0; 491534db198SAmy Zhang for (k = 0; k < (segment_end - segment_start); k++) { 492534db198SAmy Zhang increment = 32 / (1 << seg_distr[k]); 493534db198SAmy Zhang start_index = (segment_start + k + 25) * 32; 494534db198SAmy Zhang for (i = start_index; i < start_index + 32; i += increment) { 495534db198SAmy Zhang if (j == hw_points - 1) 496fcd2f4bfSAmy Zhang break; 497fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 498fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 499fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 500fcd2f4bfSAmy Zhang j++; 501fcd2f4bfSAmy Zhang } 502534db198SAmy Zhang } 503534db198SAmy Zhang 504534db198SAmy Zhang /* last point */ 505534db198SAmy Zhang start_index = (segment_end + 25) * 32; 506b310b081SHarry Wentland rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 507b310b081SHarry Wentland rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 508b310b081SHarry Wentland rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 509fcd2f4bfSAmy Zhang 510fcd2f4bfSAmy Zhang arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 511fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_start)); 512fcd2f4bfSAmy Zhang arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), 513fcd2f4bfSAmy Zhang dal_fixed31_32_from_int(segment_end)); 514fcd2f4bfSAmy Zhang 515fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 516fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 517fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 518fcd2f4bfSAmy Zhang 519fcd2f4bfSAmy Zhang y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); 520fcd2f4bfSAmy Zhang 521fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 522b310b081SHarry Wentland arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, 523fcd2f4bfSAmy Zhang arr_points[0].x); 524fcd2f4bfSAmy Zhang 525fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 526fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 527fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 528fcd2f4bfSAmy Zhang 529fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 530fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 531fcd2f4bfSAmy Zhang */ 532fcd2f4bfSAmy Zhang y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); 533fcd2f4bfSAmy Zhang 534fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 535fcd2f4bfSAmy Zhang 536fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_zero; 537fcd2f4bfSAmy Zhang 538fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 539fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 540fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 541fcd2f4bfSAmy Zhang */ 542b310b081SHarry Wentland const struct fixed31_32 end_value = dal_fixed31_32_from_int(125); 543fcd2f4bfSAmy Zhang 544fcd2f4bfSAmy Zhang arr_points[1].slope = dal_fixed31_32_div( 545fcd2f4bfSAmy Zhang dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), 546fcd2f4bfSAmy Zhang dal_fixed31_32_sub(end_value, arr_points[1].x)); 547fcd2f4bfSAmy Zhang } 548fcd2f4bfSAmy Zhang 549fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 550fcd2f4bfSAmy Zhang 551534db198SAmy Zhang i = 1; 552534db198SAmy Zhang for (k = 0; k < 16 && i < 16; k++) { 553534db198SAmy Zhang if (seg_distr[k] != -1) { 554b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 555534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 556b310b081SHarry Wentland regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 557fcd2f4bfSAmy Zhang } 558534db198SAmy Zhang i++; 559534db198SAmy Zhang } 560534db198SAmy Zhang 561534db198SAmy Zhang if (seg_distr[k] != -1) 562b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 563fcd2f4bfSAmy Zhang 56423ae4f8eSAmy Zhang rgb = rgb_resulted; 56523ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 566fcd2f4bfSAmy Zhang 567fcd2f4bfSAmy Zhang i = 1; 568fcd2f4bfSAmy Zhang 569fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 570fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red)) 571fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 572fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green)) 573fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 574fcd2f4bfSAmy Zhang if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) 575fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 576fcd2f4bfSAmy Zhang 577b310b081SHarry Wentland rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red); 578b310b081SHarry Wentland rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green); 579b310b081SHarry Wentland rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); 580fcd2f4bfSAmy Zhang 581fcd2f4bfSAmy Zhang ++rgb_plus_1; 582fcd2f4bfSAmy Zhang ++rgb; 583fcd2f4bfSAmy Zhang ++i; 584fcd2f4bfSAmy Zhang } 585fcd2f4bfSAmy Zhang 586fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 587fcd2f4bfSAmy Zhang 588fcd2f4bfSAmy Zhang return true; 589fcd2f4bfSAmy Zhang } 590fcd2f4bfSAmy Zhang 591a6114e85SHarry Wentland static bool 592a6114e85SHarry Wentland dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx, 5930971c40eSHarry Wentland const struct dc_stream_state *stream) 59490e508baSAnthony Koo { 59586a66c4eSHarry Wentland struct transform *xfm = pipe_ctx->plane_res.xfm; 5964562236bSHarry Wentland 5977a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, true); 5987a09f5beSYue Hin Lau xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 5994562236bSHarry Wentland 6004fa086b9SLeo (Sunpeng) Li if (stream->out_transfer_func && 601efd52204SHarry Wentland stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 602efd52204SHarry Wentland stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 6037a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 604efd52204SHarry Wentland } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 605efd52204SHarry Wentland &xfm->regamma_params)) { 6067a09f5beSYue Hin Lau xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 6077a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 6084562236bSHarry Wentland } else { 6097a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 6104562236bSHarry Wentland } 6114562236bSHarry Wentland 6127a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, false); 6134562236bSHarry Wentland 614cc0cb445SLeon Elazar return true; 6154562236bSHarry Wentland } 6164562236bSHarry Wentland 6174562236bSHarry Wentland static enum dc_status bios_parser_crtc_source_select( 6184562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 6194562236bSHarry Wentland { 6204562236bSHarry Wentland struct dc_bios *dcb; 6214562236bSHarry Wentland /* call VBIOS table to set CRTC source for the HW 6224562236bSHarry Wentland * encoder block 6234562236bSHarry Wentland * note: video bios clears all FMT setting here. */ 6244562236bSHarry Wentland struct bp_crtc_source_select crtc_source_select = {0}; 625b73a22d3SHarry Wentland const struct dc_sink *sink = pipe_ctx->stream->sink; 6264562236bSHarry Wentland 6278e9c4c8cSHarry Wentland crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id; 628e07f541fSYongqiang Sun crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1; 6294562236bSHarry Wentland /*TODO: Need to un-hardcode color depth, dp_audio and account for 6304562236bSHarry Wentland * the case where signal and sink signal is different (translator 6314562236bSHarry Wentland * encoder)*/ 6324562236bSHarry Wentland crtc_source_select.signal = pipe_ctx->stream->signal; 6334562236bSHarry Wentland crtc_source_select.enable_dp_audio = false; 6344562236bSHarry Wentland crtc_source_select.sink_signal = pipe_ctx->stream->signal; 6351b7441b0SCharlene Liu 6361b7441b0SCharlene Liu switch (pipe_ctx->stream->timing.display_color_depth) { 6371b7441b0SCharlene Liu case COLOR_DEPTH_666: 6381b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR; 6391b7441b0SCharlene Liu break; 6401b7441b0SCharlene Liu case COLOR_DEPTH_888: 6414562236bSHarry Wentland crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 6421b7441b0SCharlene Liu break; 6431b7441b0SCharlene Liu case COLOR_DEPTH_101010: 6441b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR; 6451b7441b0SCharlene Liu break; 6461b7441b0SCharlene Liu case COLOR_DEPTH_121212: 6471b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR; 6481b7441b0SCharlene Liu break; 6491b7441b0SCharlene Liu default: 6501b7441b0SCharlene Liu BREAK_TO_DEBUGGER(); 6511b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 6521b7441b0SCharlene Liu break; 6531b7441b0SCharlene Liu } 6544562236bSHarry Wentland 6554562236bSHarry Wentland dcb = sink->ctx->dc_bios; 6564562236bSHarry Wentland 6574562236bSHarry Wentland if (BP_RESULT_OK != dcb->funcs->crtc_source_select( 6584562236bSHarry Wentland dcb, 6594562236bSHarry Wentland &crtc_source_select)) { 6604562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 6614562236bSHarry Wentland } 6624562236bSHarry Wentland 6634562236bSHarry Wentland return DC_OK; 6644562236bSHarry Wentland } 6654562236bSHarry Wentland 6664562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6674562236bSHarry Wentland { 66886e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 66986e2e1beSHersen Wu 6708e9c4c8cSHarry Wentland if (pipe_ctx->stream_res.stream_enc == NULL) 67186e2e1beSHersen Wu return; /* this is not root pipe */ 67286e2e1beSHersen Wu 6734562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 6748e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 6758e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 67696c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6774562236bSHarry Wentland else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 6788e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 6798e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 68096c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6814562236bSHarry Wentland } 6824562236bSHarry Wentland 6834562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6844562236bSHarry Wentland { 6854562236bSHarry Wentland enum dc_lane_count lane_count = 686d0778ebfSHarry Wentland pipe_ctx->stream->sink->link->cur_link_settings.lane_count; 6874562236bSHarry Wentland 6884fa086b9SLeo (Sunpeng) Li struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 689d0778ebfSHarry Wentland struct dc_link *link = pipe_ctx->stream->sink->link; 6904562236bSHarry Wentland 6914562236bSHarry Wentland /* 1. update AVI info frame (HDMI, DP) 6924562236bSHarry Wentland * we always need to update info frame 6934562236bSHarry Wentland */ 6944562236bSHarry Wentland uint32_t active_total_with_borders; 6954562236bSHarry Wentland uint32_t early_control = 0; 6966b670fa9SHarry Wentland struct timing_generator *tg = pipe_ctx->stream_res.tg; 6974562236bSHarry Wentland 6984562236bSHarry Wentland /* TODOFPGA may change to hwss.update_info_frame */ 6994562236bSHarry Wentland dce110_update_info_frame(pipe_ctx); 7004562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 7014562236bSHarry Wentland active_total_with_borders = 7024562236bSHarry Wentland timing->h_addressable 7034562236bSHarry Wentland + timing->h_border_left 7044562236bSHarry Wentland + timing->h_border_right; 7054562236bSHarry Wentland 7064562236bSHarry Wentland if (lane_count != 0) 7074562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 7084562236bSHarry Wentland 7094562236bSHarry Wentland if (early_control == 0) 7104562236bSHarry Wentland early_control = lane_count; 7114562236bSHarry Wentland 7124562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 7134562236bSHarry Wentland 7144562236bSHarry Wentland /* enable audio only within mode set */ 715afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 7164562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7178e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 7184562236bSHarry Wentland } 7194562236bSHarry Wentland 7204562236bSHarry Wentland /* For MST, there are multiply stream go to only one link. 7214562236bSHarry Wentland * connect DIG back_end to front_end while enable_stream and 7224562236bSHarry Wentland * disconnect them during disable_stream 7234562236bSHarry Wentland * BY this, it is logic clean to separate stream and link */ 7244562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 7258e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->id, true); 7264562236bSHarry Wentland 7274562236bSHarry Wentland } 7284562236bSHarry Wentland 7295eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 7305eefbc40SYue Hin Lau static bool is_panel_backlight_on(struct dce_hwseq *hws) 7315eefbc40SYue Hin Lau { 7325eefbc40SYue Hin Lau uint32_t value; 7335eefbc40SYue Hin Lau 7345eefbc40SYue Hin Lau REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value); 7355eefbc40SYue Hin Lau 7365eefbc40SYue Hin Lau return value; 7375eefbc40SYue Hin Lau } 7385eefbc40SYue Hin Lau 73987401969SAndrew Jiang static bool is_panel_powered_on(struct dce_hwseq *hws) 74087401969SAndrew Jiang { 74187401969SAndrew Jiang uint32_t value; 74287401969SAndrew Jiang 74387401969SAndrew Jiang REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value); 74487401969SAndrew Jiang return value == 1; 74587401969SAndrew Jiang } 74687401969SAndrew Jiang 7475eefbc40SYue Hin Lau static enum bp_result link_transmitter_control( 74887401969SAndrew Jiang struct dc_bios *bios, 7495eefbc40SYue Hin Lau struct bp_transmitter_control *cntl) 7505eefbc40SYue Hin Lau { 7515eefbc40SYue Hin Lau enum bp_result result; 7525eefbc40SYue Hin Lau 75387401969SAndrew Jiang result = bios->funcs->transmitter_control(bios, cntl); 7545eefbc40SYue Hin Lau 7555eefbc40SYue Hin Lau return result; 7565eefbc40SYue Hin Lau } 7575eefbc40SYue Hin Lau 75887401969SAndrew Jiang /* 75987401969SAndrew Jiang * @brief 76087401969SAndrew Jiang * eDP only. 76187401969SAndrew Jiang */ 76287401969SAndrew Jiang void hwss_edp_wait_for_hpd_ready( 763069d418fSAndrew Jiang struct dc_link *link, 76487401969SAndrew Jiang bool power_up) 76587401969SAndrew Jiang { 766069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 767069d418fSAndrew Jiang struct graphics_object_id connector = link->link_enc->connector; 76887401969SAndrew Jiang struct gpio *hpd; 76987401969SAndrew Jiang bool edp_hpd_high = false; 77087401969SAndrew Jiang uint32_t time_elapsed = 0; 77187401969SAndrew Jiang uint32_t timeout = power_up ? 77287401969SAndrew Jiang PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 77387401969SAndrew Jiang 77487401969SAndrew Jiang if (dal_graphics_object_id_get_connector_id(connector) 77587401969SAndrew Jiang != CONNECTOR_ID_EDP) { 77687401969SAndrew Jiang BREAK_TO_DEBUGGER(); 77787401969SAndrew Jiang return; 77887401969SAndrew Jiang } 77987401969SAndrew Jiang 78087401969SAndrew Jiang if (!power_up) 78187401969SAndrew Jiang /* 78287401969SAndrew Jiang * From KV, we will not HPD low after turning off VCC - 78387401969SAndrew Jiang * instead, we will check the SW timer in power_up(). 78487401969SAndrew Jiang */ 78587401969SAndrew Jiang return; 78687401969SAndrew Jiang 78787401969SAndrew Jiang /* 78887401969SAndrew Jiang * When we power on/off the eDP panel, 78987401969SAndrew Jiang * we need to wait until SENSE bit is high/low. 79087401969SAndrew Jiang */ 79187401969SAndrew Jiang 79287401969SAndrew Jiang /* obtain HPD */ 79387401969SAndrew Jiang /* TODO what to do with this? */ 79487401969SAndrew Jiang hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 79587401969SAndrew Jiang 79687401969SAndrew Jiang if (!hpd) { 79787401969SAndrew Jiang BREAK_TO_DEBUGGER(); 79887401969SAndrew Jiang return; 79987401969SAndrew Jiang } 80087401969SAndrew Jiang 80187401969SAndrew Jiang dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 80287401969SAndrew Jiang 80387401969SAndrew Jiang /* wait until timeout or panel detected */ 80487401969SAndrew Jiang 80587401969SAndrew Jiang do { 80687401969SAndrew Jiang uint32_t detected = 0; 80787401969SAndrew Jiang 80887401969SAndrew Jiang dal_gpio_get_value(hpd, &detected); 80987401969SAndrew Jiang 81087401969SAndrew Jiang if (!(detected ^ power_up)) { 81187401969SAndrew Jiang edp_hpd_high = true; 81287401969SAndrew Jiang break; 81387401969SAndrew Jiang } 81487401969SAndrew Jiang 81587401969SAndrew Jiang msleep(HPD_CHECK_INTERVAL); 81687401969SAndrew Jiang 81787401969SAndrew Jiang time_elapsed += HPD_CHECK_INTERVAL; 81887401969SAndrew Jiang } while (time_elapsed < timeout); 81987401969SAndrew Jiang 82087401969SAndrew Jiang dal_gpio_close(hpd); 82187401969SAndrew Jiang 82287401969SAndrew Jiang dal_gpio_destroy_irq(&hpd); 82387401969SAndrew Jiang 82487401969SAndrew Jiang if (false == edp_hpd_high) { 82587401969SAndrew Jiang dm_logger_write(ctx->logger, LOG_ERROR, 82687401969SAndrew Jiang "%s: wait timed out!\n", __func__); 82787401969SAndrew Jiang } 82887401969SAndrew Jiang } 82987401969SAndrew Jiang 83087401969SAndrew Jiang void hwss_edp_power_control( 831069d418fSAndrew Jiang struct dc_link *link, 83287401969SAndrew Jiang bool power_up) 83387401969SAndrew Jiang { 834069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 83587401969SAndrew Jiang struct dce_hwseq *hwseq = ctx->dc->hwseq; 83687401969SAndrew Jiang struct bp_transmitter_control cntl = { 0 }; 83787401969SAndrew Jiang enum bp_result bp_result; 83887401969SAndrew Jiang 83987401969SAndrew Jiang 840069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 84187401969SAndrew Jiang != CONNECTOR_ID_EDP) { 84287401969SAndrew Jiang BREAK_TO_DEBUGGER(); 84387401969SAndrew Jiang return; 84487401969SAndrew Jiang } 84587401969SAndrew Jiang 84687401969SAndrew Jiang if (power_up != is_panel_powered_on(hwseq)) { 84787401969SAndrew Jiang /* Send VBIOS command to prompt eDP panel power */ 84887401969SAndrew Jiang 84987401969SAndrew Jiang dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, 85087401969SAndrew Jiang "%s: Panel Power action: %s\n", 85187401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 85287401969SAndrew Jiang 85387401969SAndrew Jiang cntl.action = power_up ? 85487401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_ON : 85587401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_OFF; 856069d418fSAndrew Jiang cntl.transmitter = link->link_enc->transmitter; 857069d418fSAndrew Jiang cntl.connector_obj_id = link->link_enc->connector; 85887401969SAndrew Jiang cntl.coherent = false; 85987401969SAndrew Jiang cntl.lanes_number = LANE_COUNT_FOUR; 860069d418fSAndrew Jiang cntl.hpd_sel = link->link_enc->hpd_source; 86187401969SAndrew Jiang 86287401969SAndrew Jiang bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 86387401969SAndrew Jiang 86487401969SAndrew Jiang if (bp_result != BP_RESULT_OK) 86587401969SAndrew Jiang dm_logger_write(ctx->logger, LOG_ERROR, 86687401969SAndrew Jiang "%s: Panel Power bp_result: %d\n", 86787401969SAndrew Jiang __func__, bp_result); 86887401969SAndrew Jiang } else { 86987401969SAndrew Jiang dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, 87087401969SAndrew Jiang "%s: Skipping Panel Power action: %s\n", 87187401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 87287401969SAndrew Jiang } 87387401969SAndrew Jiang } 8745eefbc40SYue Hin Lau 8755eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 8765eefbc40SYue Hin Lau /* 8775eefbc40SYue Hin Lau * @brief 8785eefbc40SYue Hin Lau * eDP only. Control the backlight of the eDP panel 8795eefbc40SYue Hin Lau */ 88087401969SAndrew Jiang void hwss_edp_backlight_control( 8815eefbc40SYue Hin Lau struct dc_link *link, 8825eefbc40SYue Hin Lau bool enable) 8835eefbc40SYue Hin Lau { 884069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 885069d418fSAndrew Jiang struct dce_hwseq *hws = ctx->dc->hwseq; 8865eefbc40SYue Hin Lau struct bp_transmitter_control cntl = { 0 }; 8875eefbc40SYue Hin Lau 888069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 8895eefbc40SYue Hin Lau != CONNECTOR_ID_EDP) { 8905eefbc40SYue Hin Lau BREAK_TO_DEBUGGER(); 8915eefbc40SYue Hin Lau return; 8925eefbc40SYue Hin Lau } 8935eefbc40SYue Hin Lau 8945eefbc40SYue Hin Lau if (enable && is_panel_backlight_on(hws)) { 8955eefbc40SYue Hin Lau dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, 8965eefbc40SYue Hin Lau "%s: panel already powered up. Do nothing.\n", 8975eefbc40SYue Hin Lau __func__); 8985eefbc40SYue Hin Lau return; 8995eefbc40SYue Hin Lau } 9005eefbc40SYue Hin Lau 9015eefbc40SYue Hin Lau /* Send VBIOS command to control eDP panel backlight */ 9025eefbc40SYue Hin Lau 9035eefbc40SYue Hin Lau dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, 9045eefbc40SYue Hin Lau "%s: backlight action: %s\n", 9055eefbc40SYue Hin Lau __func__, (enable ? "On":"Off")); 9065eefbc40SYue Hin Lau 9075eefbc40SYue Hin Lau cntl.action = enable ? 9085eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_ON : 9095eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_OFF; 91087401969SAndrew Jiang 9115eefbc40SYue Hin Lau /*cntl.engine_id = ctx->engine;*/ 9125eefbc40SYue Hin Lau cntl.transmitter = link->link_enc->transmitter; 9135eefbc40SYue Hin Lau cntl.connector_obj_id = link->link_enc->connector; 9145eefbc40SYue Hin Lau /*todo: unhardcode*/ 9155eefbc40SYue Hin Lau cntl.lanes_number = LANE_COUNT_FOUR; 9165eefbc40SYue Hin Lau cntl.hpd_sel = link->link_enc->hpd_source; 917cf1835f0SCharlene Liu cntl.signal = SIGNAL_TYPE_EDP; 9185eefbc40SYue Hin Lau 9195eefbc40SYue Hin Lau /* For eDP, the following delays might need to be considered 9205eefbc40SYue Hin Lau * after link training completed: 9215eefbc40SYue Hin Lau * idle period - min. accounts for required BS-Idle pattern, 9225eefbc40SYue Hin Lau * max. allows for source frame synchronization); 9235eefbc40SYue Hin Lau * 50 msec max. delay from valid video data from source 9245eefbc40SYue Hin Lau * to video on dislpay or backlight enable. 9255eefbc40SYue Hin Lau * 9265eefbc40SYue Hin Lau * Disable the delay for now. 9275eefbc40SYue Hin Lau * Enable it in the future if necessary. 9285eefbc40SYue Hin Lau */ 9295eefbc40SYue Hin Lau /* dc_service_sleep_in_milliseconds(50); */ 930069d418fSAndrew Jiang link_transmitter_control(ctx->dc_bios, &cntl); 9315eefbc40SYue Hin Lau } 9325eefbc40SYue Hin Lau 9334176664bSCharlene Liu void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) 9344562236bSHarry Wentland { 9350971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 936d0778ebfSHarry Wentland struct dc_link *link = stream->sink->link; 9374176664bSCharlene Liu struct dc *dc = pipe_ctx->stream->ctx->dc; 9384562236bSHarry Wentland 9392b7c97d6SCharlene Liu if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 9402b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 9412b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc); 9422b7c97d6SCharlene Liu 9432b7c97d6SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 9442b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 9452b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc); 9462b7c97d6SCharlene Liu 9472b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 9482b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc, true); 949afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio) { 9507c357e61SCharlene Liu if (option != KEEP_ACQUIRED_RESOURCE || 9517c357e61SCharlene Liu !dc->debug.az_endpoint_mute_only) { 9527c357e61SCharlene Liu /*only disalbe az_endpoint if power down or free*/ 953afaacef4SHarry Wentland pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 9547c357e61SCharlene Liu } 9554562236bSHarry Wentland 9564562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 9578e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 9588e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 9594562236bSHarry Wentland else 9608e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 9618e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 9624176664bSCharlene Liu /*don't free audio if it is from retrain or internal disable stream*/ 9634176664bSCharlene Liu if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) { 9644176664bSCharlene Liu /*we have to dynamic arbitrate the audio endpoints*/ 9654176664bSCharlene Liu pipe_ctx->stream_res.audio = NULL; 9664176664bSCharlene Liu /*we free the resource, need reset is_audio_acquired*/ 9674176664bSCharlene Liu update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false); 9684176664bSCharlene Liu } 9694562236bSHarry Wentland 9704562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 9714562236bSHarry Wentland * add audio mode list change flag */ 9724562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 9734562236bSHarry Wentland * stream->stream_engine_id); 9744562236bSHarry Wentland */ 9754562236bSHarry Wentland } 9764562236bSHarry Wentland 9774562236bSHarry Wentland /* blank at encoder level */ 978904623eeSYongqiang Sun if (dc_is_dp_signal(pipe_ctx->stream->signal)) 9798e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); 980904623eeSYongqiang Sun 9814562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 9824562236bSHarry Wentland link->link_enc, 9838e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->id, 9844562236bSHarry Wentland false); 9854562236bSHarry Wentland 9864562236bSHarry Wentland } 9874562236bSHarry Wentland 9884562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 9894562236bSHarry Wentland struct dc_link_settings *link_settings) 9904562236bSHarry Wentland { 9914562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 99241b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 99341b49742SCharlene Liu struct dc_link *link = stream->sink->link; 9944562236bSHarry Wentland 9954562236bSHarry Wentland /* only 3 items below are used by unblank */ 9966235b23cSTony Cheng params.pixel_clk_khz = 9974fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.pix_clk_khz; 9984562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 99941b49742SCharlene Liu 100041b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10018e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 100241b49742SCharlene Liu 100341b49742SCharlene Liu if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 100441b49742SCharlene Liu link->dc->hwss.edp_backlight_control(link, true); 100541b49742SCharlene Liu } 100641b49742SCharlene Liu void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 100741b49742SCharlene Liu { 100841b49742SCharlene Liu struct encoder_unblank_param params = { { 0 } }; 100941b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 101041b49742SCharlene Liu struct dc_link *link = stream->sink->link; 101141b49742SCharlene Liu 101241b49742SCharlene Liu if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) 101341b49742SCharlene Liu link->dc->hwss.edp_backlight_control(link, false); 101441b49742SCharlene Liu 101541b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 101641b49742SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); 10174562236bSHarry Wentland } 10184562236bSHarry Wentland 101915e17335SCharlene Liu 102015e17335SCharlene Liu void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 102115e17335SCharlene Liu { 10228e9c4c8cSHarry Wentland if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 10238e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 102415e17335SCharlene Liu } 102515e17335SCharlene Liu 10264562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 10274562236bSHarry Wentland { 10284562236bSHarry Wentland switch (crtc_id) { 10294562236bSHarry Wentland case CONTROLLER_ID_D0: 10304562236bSHarry Wentland return DTO_SOURCE_ID0; 10314562236bSHarry Wentland case CONTROLLER_ID_D1: 10324562236bSHarry Wentland return DTO_SOURCE_ID1; 10334562236bSHarry Wentland case CONTROLLER_ID_D2: 10344562236bSHarry Wentland return DTO_SOURCE_ID2; 10354562236bSHarry Wentland case CONTROLLER_ID_D3: 10364562236bSHarry Wentland return DTO_SOURCE_ID3; 10374562236bSHarry Wentland case CONTROLLER_ID_D4: 10384562236bSHarry Wentland return DTO_SOURCE_ID4; 10394562236bSHarry Wentland case CONTROLLER_ID_D5: 10404562236bSHarry Wentland return DTO_SOURCE_ID5; 10414562236bSHarry Wentland default: 10424562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 10434562236bSHarry Wentland } 10444562236bSHarry Wentland } 10454562236bSHarry Wentland 10464562236bSHarry Wentland static void build_audio_output( 1047ab8db3e1SAndrey Grodzovsky struct dc_state *state, 10484562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 10494562236bSHarry Wentland struct audio_output *audio_output) 10504562236bSHarry Wentland { 10510971c40eSHarry Wentland const struct dc_stream_state *stream = pipe_ctx->stream; 10528e9c4c8cSHarry Wentland audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 10534562236bSHarry Wentland 10544562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 10554562236bSHarry Wentland 10564562236bSHarry Wentland /* audio_crtc_info */ 10574562236bSHarry Wentland 10584562236bSHarry Wentland audio_output->crtc_info.h_total = 10594fa086b9SLeo (Sunpeng) Li stream->timing.h_total; 10604562236bSHarry Wentland 10614562236bSHarry Wentland /* 10624562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 10634562236bSHarry Wentland * need to specify actual active signal portion 10644562236bSHarry Wentland */ 10654562236bSHarry Wentland audio_output->crtc_info.h_active = 10664fa086b9SLeo (Sunpeng) Li stream->timing.h_addressable 10674fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_left 10684fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_right; 10694562236bSHarry Wentland 10704562236bSHarry Wentland audio_output->crtc_info.v_active = 10714fa086b9SLeo (Sunpeng) Li stream->timing.v_addressable 10724fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_top 10734fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_bottom; 10744562236bSHarry Wentland 10754562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 10764562236bSHarry Wentland 10774562236bSHarry Wentland audio_output->crtc_info.interlaced = 10784fa086b9SLeo (Sunpeng) Li stream->timing.flags.INTERLACE; 10794562236bSHarry Wentland 10804562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 10814fa086b9SLeo (Sunpeng) Li (stream->timing.pix_clk_khz*1000)/ 10824fa086b9SLeo (Sunpeng) Li (stream->timing.h_total*stream->timing.v_total); 10834562236bSHarry Wentland 10844562236bSHarry Wentland audio_output->crtc_info.color_depth = 10854fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth; 10864562236bSHarry Wentland 10874562236bSHarry Wentland audio_output->crtc_info.requested_pixel_clock = 108810688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; 10894562236bSHarry Wentland 10904562236bSHarry Wentland audio_output->crtc_info.calculated_pixel_clock = 109110688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; 10924562236bSHarry Wentland 109387b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 109487b58768SCharlene Liu if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && 109587b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock == 10964fa086b9SLeo (Sunpeng) Li stream->timing.pix_clk_khz) { 109710688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 109887b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock = 109987b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock/2; 110087b58768SCharlene Liu audio_output->crtc_info.calculated_pixel_clock = 110110688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2; 110287b58768SCharlene Liu 110387b58768SCharlene Liu } 110487b58768SCharlene Liu } 110587b58768SCharlene Liu 11064562236bSHarry Wentland if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 11074562236bSHarry Wentland pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 11084562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 1109ab8db3e1SAndrey Grodzovsky state->dis_clk->funcs->get_dp_ref_clk_frequency( 1110ab8db3e1SAndrey Grodzovsky state->dis_clk); 11114562236bSHarry Wentland } 11124562236bSHarry Wentland 11134562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 11144562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 11154562236bSHarry Wentland 11164562236bSHarry Wentland audio_output->pll_info.dto_source = 11174562236bSHarry Wentland translate_to_dto_source( 1118e07f541fSYongqiang Sun pipe_ctx->stream_res.tg->inst + 1); 11194562236bSHarry Wentland 11204562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 11214562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 11224562236bSHarry Wentland 11234562236bSHarry Wentland audio_output->pll_info.ss_percentage = 11244562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 11254562236bSHarry Wentland } 11264562236bSHarry Wentland 11274562236bSHarry Wentland static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 11284562236bSHarry Wentland struct tg_color *color) 11294562236bSHarry Wentland { 11304562236bSHarry Wentland uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4; 11314562236bSHarry Wentland 11326702a9acSHarry Wentland switch (pipe_ctx->plane_res.scl_data.format) { 11334562236bSHarry Wentland case PIXEL_FORMAT_ARGB8888: 11344562236bSHarry Wentland /* set boarder color to red */ 11354562236bSHarry Wentland color->color_r_cr = color_value; 11364562236bSHarry Wentland break; 11374562236bSHarry Wentland 11384562236bSHarry Wentland case PIXEL_FORMAT_ARGB2101010: 11394562236bSHarry Wentland /* set boarder color to blue */ 11404562236bSHarry Wentland color->color_b_cb = color_value; 11414562236bSHarry Wentland break; 114287449a90SAnthony Koo case PIXEL_FORMAT_420BPP8: 11434562236bSHarry Wentland /* set boarder color to green */ 11444562236bSHarry Wentland color->color_g_y = color_value; 11454562236bSHarry Wentland break; 114687449a90SAnthony Koo case PIXEL_FORMAT_420BPP10: 114787449a90SAnthony Koo /* set boarder color to yellow */ 114887449a90SAnthony Koo color->color_g_y = color_value; 114987449a90SAnthony Koo color->color_r_cr = color_value; 115087449a90SAnthony Koo break; 11514562236bSHarry Wentland case PIXEL_FORMAT_FP16: 11524562236bSHarry Wentland /* set boarder color to white */ 11534562236bSHarry Wentland color->color_r_cr = color_value; 11544562236bSHarry Wentland color->color_b_cb = color_value; 11554562236bSHarry Wentland color->color_g_y = color_value; 11564562236bSHarry Wentland break; 11574562236bSHarry Wentland default: 11584562236bSHarry Wentland break; 11594562236bSHarry Wentland } 11604562236bSHarry Wentland } 11614562236bSHarry Wentland 1162fb3466a4SBhawanpreet Lakha static void program_scaler(const struct dc *dc, 11634562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 11644562236bSHarry Wentland { 11654562236bSHarry Wentland struct tg_color color = {0}; 11664562236bSHarry Wentland 1167ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1168ff5ef992SAlex Deucher /* TOFPGA */ 116986a66c4eSHarry Wentland if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1170ff5ef992SAlex Deucher return; 1171ff5ef992SAlex Deucher #endif 1172ff5ef992SAlex Deucher 1173fb3466a4SBhawanpreet Lakha if (dc->debug.surface_visual_confirm) 11744562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 11754562236bSHarry Wentland else 11764562236bSHarry Wentland color_space_to_black_color(dc, 11774fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space, 11784562236bSHarry Wentland &color); 11794562236bSHarry Wentland 118086a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 118186a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, 11826702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.depth, 11834562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 11844562236bSHarry Wentland 11856b670fa9SHarry Wentland if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) 11866b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 11876b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 11884562236bSHarry Wentland &color); 11894562236bSHarry Wentland 119086a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 11916702a9acSHarry Wentland &pipe_ctx->plane_res.scl_data); 11924562236bSHarry Wentland } 11934562236bSHarry Wentland 11944b5e7d62SHersen Wu static enum dc_status dce110_prog_pixclk_crtc_otg( 11954562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1196608ac7bbSJerry Zuo struct dc_state *context, 1197fb3466a4SBhawanpreet Lakha struct dc *dc) 11984562236bSHarry Wentland { 11990971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1200608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 12014562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 12024562236bSHarry Wentland struct tg_color black_color = {0}; 12034562236bSHarry Wentland 12044562236bSHarry Wentland if (!pipe_ctx_old->stream) { 12054562236bSHarry Wentland 12064562236bSHarry Wentland /* program blank color */ 12074562236bSHarry Wentland color_space_to_black_color(dc, 12084fa086b9SLeo (Sunpeng) Li stream->output_color_space, &black_color); 12096b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank_color( 12106b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 12114562236bSHarry Wentland &black_color); 12124b5e7d62SHersen Wu 12134562236bSHarry Wentland /* 12144562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 12154562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 12164562236bSHarry Wentland */ 12176b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 12184562236bSHarry Wentland 12194562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 12204562236bSHarry Wentland pipe_ctx->clock_source, 122110688217SHarry Wentland &pipe_ctx->stream_res.pix_clk_params, 12224562236bSHarry Wentland &pipe_ctx->pll_settings)) { 12234562236bSHarry Wentland BREAK_TO_DEBUGGER(); 12244562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 12254562236bSHarry Wentland } 12264562236bSHarry Wentland 12276b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->program_timing( 12286b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 12294fa086b9SLeo (Sunpeng) Li &stream->timing, 12304562236bSHarry Wentland true); 123194267b3dSSylvia Tsai 12326b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 12336b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 123494267b3dSSylvia Tsai 0x182); 12354562236bSHarry Wentland } 12364562236bSHarry Wentland 12374562236bSHarry Wentland if (!pipe_ctx_old->stream) { 12386b670fa9SHarry Wentland if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 12396b670fa9SHarry Wentland pipe_ctx->stream_res.tg)) { 12404562236bSHarry Wentland BREAK_TO_DEBUGGER(); 12414562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 12424562236bSHarry Wentland } 12434562236bSHarry Wentland } 12444562236bSHarry Wentland 124594267b3dSSylvia Tsai 124694267b3dSSylvia Tsai 12474562236bSHarry Wentland return DC_OK; 12484562236bSHarry Wentland } 12494562236bSHarry Wentland 12504562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 12514562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1252608ac7bbSJerry Zuo struct dc_state *context, 1253fb3466a4SBhawanpreet Lakha struct dc *dc) 12544562236bSHarry Wentland { 12550971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1256608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 12574562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 12584562236bSHarry Wentland 12594562236bSHarry Wentland /* */ 12604562236bSHarry Wentland dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); 12614562236bSHarry Wentland 1262f0c4d997SCorbin McElhanney /* FPGA does not program backend */ 1263f0c4d997SCorbin McElhanney if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 1264a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1265a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 12664562236bSHarry Wentland COLOR_SPACE_YCBCR601, 12674fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth, 12684562236bSHarry Wentland pipe_ctx->stream->signal); 12694562236bSHarry Wentland 1270a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1271a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 12724562236bSHarry Wentland &stream->bit_depth_params, 12734562236bSHarry Wentland &stream->clamping); 12744562236bSHarry Wentland return DC_OK; 1275181a888fSCharlene Liu } 12764562236bSHarry Wentland /* TODO: move to stream encoder */ 12774562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 12784562236bSHarry Wentland if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { 12794562236bSHarry Wentland BREAK_TO_DEBUGGER(); 12804562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 12814562236bSHarry Wentland } 1282f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1283f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp, 1284f0c4d997SCorbin McElhanney COLOR_SPACE_YCBCR601, 1285f0c4d997SCorbin McElhanney stream->timing.display_color_depth, 1286f0c4d997SCorbin McElhanney pipe_ctx->stream->signal); 12874562236bSHarry Wentland 12884562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 12894562236bSHarry Wentland stream->sink->link->link_enc->funcs->setup( 12904562236bSHarry Wentland stream->sink->link->link_enc, 12914562236bSHarry Wentland pipe_ctx->stream->signal); 12924562236bSHarry Wentland 1293ab3c1798SVitaly Prosyak if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 12948e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync( 12958e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 12966b670fa9SHarry Wentland pipe_ctx->stream_res.tg->inst, 12974fa086b9SLeo (Sunpeng) Li stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); 1298ab3c1798SVitaly Prosyak 1299ab3c1798SVitaly Prosyak 1300a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1301a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 1302181a888fSCharlene Liu &stream->bit_depth_params, 1303181a888fSCharlene Liu &stream->clamping); 1304603767f9STony Cheng 13054562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 13068e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute( 13078e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 13084fa086b9SLeo (Sunpeng) Li &stream->timing, 13094fa086b9SLeo (Sunpeng) Li stream->output_color_space); 13104562236bSHarry Wentland 13114562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 13128e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute( 13138e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 13144fa086b9SLeo (Sunpeng) Li &stream->timing, 13154562236bSHarry Wentland stream->phy_pix_clk, 1316afaacef4SHarry Wentland pipe_ctx->stream_res.audio != NULL); 13174562236bSHarry Wentland 13184562236bSHarry Wentland if (dc_is_dvi_signal(pipe_ctx->stream->signal)) 13198e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute( 13208e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 13214fa086b9SLeo (Sunpeng) Li &stream->timing, 13224562236bSHarry Wentland (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? 13234562236bSHarry Wentland true : false); 13244562236bSHarry Wentland 132515e17335SCharlene Liu resource_build_info_frame(pipe_ctx); 13263639fa68SZeyu Fan dce110_update_info_frame(pipe_ctx); 13274562236bSHarry Wentland if (!pipe_ctx_old->stream) { 1328d050f8edSHersen Wu if (!pipe_ctx->stream->dpms_off) 1329ab8db3e1SAndrey Grodzovsky core_link_enable_stream(context, pipe_ctx); 13304562236bSHarry Wentland } 13314562236bSHarry Wentland 13326702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 13334562236bSHarry Wentland 133494267b3dSSylvia Tsai pipe_ctx->stream->sink->link->psr_enabled = false; 133594267b3dSSylvia Tsai 13364562236bSHarry Wentland return DC_OK; 13374562236bSHarry Wentland } 13384562236bSHarry Wentland 13394562236bSHarry Wentland /******************************************************************************/ 13404562236bSHarry Wentland 1341fb3466a4SBhawanpreet Lakha static void power_down_encoders(struct dc *dc) 13424562236bSHarry Wentland { 13434562236bSHarry Wentland int i; 1344a0c38ebaSCharlene Liu enum connector_id connector_id; 134568d77dd8SAndrew Jiang enum signal_type signal = SIGNAL_TYPE_NONE; 1346b9b171ffSHersen Wu 1347b9b171ffSHersen Wu /* do not know BIOS back-front mapping, simply blank all. It will not 1348b9b171ffSHersen Wu * hurt for non-DP 1349b9b171ffSHersen Wu */ 1350b9b171ffSHersen Wu for (i = 0; i < dc->res_pool->stream_enc_count; i++) { 1351b9b171ffSHersen Wu dc->res_pool->stream_enc[i]->funcs->dp_blank( 1352b9b171ffSHersen Wu dc->res_pool->stream_enc[i]); 1353b9b171ffSHersen Wu } 1354b9b171ffSHersen Wu 13554562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 1356a0c38ebaSCharlene Liu connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id); 1357a0c38ebaSCharlene Liu if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || 1358a0c38ebaSCharlene Liu (connector_id == CONNECTOR_ID_EDP)) { 1359a0c38ebaSCharlene Liu 1360a0c38ebaSCharlene Liu if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) 1361a0c38ebaSCharlene Liu dp_receiver_power_ctrl(dc->links[i], false); 1362904623eeSYongqiang Sun if (connector_id == CONNECTOR_ID_EDP) 136368d77dd8SAndrew Jiang signal = SIGNAL_TYPE_EDP; 1364a0c38ebaSCharlene Liu } 1365a0c38ebaSCharlene Liu 13664562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 1367069d418fSAndrew Jiang dc->links[i]->link_enc, signal); 13684562236bSHarry Wentland } 13694562236bSHarry Wentland } 13704562236bSHarry Wentland 1371fb3466a4SBhawanpreet Lakha static void power_down_controllers(struct dc *dc) 13724562236bSHarry Wentland { 13734562236bSHarry Wentland int i; 13744562236bSHarry Wentland 13754562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 13764562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 13774562236bSHarry Wentland dc->res_pool->timing_generators[i]); 13784562236bSHarry Wentland } 13794562236bSHarry Wentland } 13804562236bSHarry Wentland 1381fb3466a4SBhawanpreet Lakha static void power_down_clock_sources(struct dc *dc) 13824562236bSHarry Wentland { 13834562236bSHarry Wentland int i; 13844562236bSHarry Wentland 13854562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 13864562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 13874562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 13884562236bSHarry Wentland 13894562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 13904562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 13914562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 13924562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 13934562236bSHarry Wentland } 13944562236bSHarry Wentland } 13954562236bSHarry Wentland 1396fb3466a4SBhawanpreet Lakha static void power_down_all_hw_blocks(struct dc *dc) 13974562236bSHarry Wentland { 13984562236bSHarry Wentland power_down_encoders(dc); 13994562236bSHarry Wentland 14004562236bSHarry Wentland power_down_controllers(dc); 14014562236bSHarry Wentland 14024562236bSHarry Wentland power_down_clock_sources(dc); 14031663ae1cSBhawanpreet Lakha 14043eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 14052f3bfb27SRoman Li if (dc->fbc_compressor) 14061663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 14071663ae1cSBhawanpreet Lakha #endif 14084562236bSHarry Wentland } 14094562236bSHarry Wentland 14104562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 1411fb3466a4SBhawanpreet Lakha struct dc *dc) 14124562236bSHarry Wentland { 14134562236bSHarry Wentland int i; 14144562236bSHarry Wentland struct timing_generator *tg; 14154562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 14164562236bSHarry Wentland 14174562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 14184562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 14194562236bSHarry Wentland 14200a87425aSTony Cheng if (tg->funcs->disable_vga) 14214562236bSHarry Wentland tg->funcs->disable_vga(tg); 14224562236bSHarry Wentland 14234562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 14244562236bSHarry Wentland * powergating. */ 14254562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 14264562236bSHarry Wentland true); 14274562236bSHarry Wentland 1428e6c258cbSYongqiang Sun dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 14297f914a62SYongqiang Sun dc->hwss.disable_plane(dc, 1430e6c258cbSYongqiang Sun &dc->current_state->res_ctx.pipe_ctx[i]); 14314562236bSHarry Wentland } 14324562236bSHarry Wentland } 14334562236bSHarry Wentland 1434cf1835f0SCharlene Liu static struct dc_link *get_link_for_edp( 1435cf1835f0SCharlene Liu struct dc *dc) 1436cf1835f0SCharlene Liu { 1437cf1835f0SCharlene Liu int i; 1438cf1835f0SCharlene Liu struct dc_link *link = NULL; 1439cf1835f0SCharlene Liu 1440cf1835f0SCharlene Liu /* check if there is an eDP panel not in use */ 1441cf1835f0SCharlene Liu for (i = 0; i < dc->link_count; i++) { 1442cf1835f0SCharlene Liu if (dc->links[i]->local_sink && 1443cf1835f0SCharlene Liu dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1444cf1835f0SCharlene Liu link = dc->links[i]; 1445cf1835f0SCharlene Liu break; 1446cf1835f0SCharlene Liu } 1447cf1835f0SCharlene Liu } 1448cf1835f0SCharlene Liu 1449cf1835f0SCharlene Liu return link; 1450cf1835f0SCharlene Liu } 1451cf1835f0SCharlene Liu static struct dc_link *get_link_for_edp_not_in_use( 145225292028SYongqiang Sun struct dc *dc, 145325292028SYongqiang Sun struct dc_state *context) 145425292028SYongqiang Sun { 145525292028SYongqiang Sun int i; 145625292028SYongqiang Sun struct dc_link *link = NULL; 145725292028SYongqiang Sun 145825292028SYongqiang Sun /* check if eDP panel is suppose to be set mode, if yes, no need to disable */ 145925292028SYongqiang Sun for (i = 0; i < context->stream_count; i++) { 146025292028SYongqiang Sun if (context->streams[i]->signal == SIGNAL_TYPE_EDP) 146125292028SYongqiang Sun return NULL; 146225292028SYongqiang Sun } 146325292028SYongqiang Sun 146425292028SYongqiang Sun /* check if there is an eDP panel not in use */ 146525292028SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 146625292028SYongqiang Sun if (dc->links[i]->local_sink && 146725292028SYongqiang Sun dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 146825292028SYongqiang Sun link = dc->links[i]; 146925292028SYongqiang Sun break; 147025292028SYongqiang Sun } 147125292028SYongqiang Sun } 147225292028SYongqiang Sun 147325292028SYongqiang Sun return link; 147425292028SYongqiang Sun } 147525292028SYongqiang Sun 14764562236bSHarry Wentland /** 14774562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 14784562236bSHarry Wentland * 1. Power down all DC HW blocks 14794562236bSHarry Wentland * 2. Disable VGA engine on all controllers 14804562236bSHarry Wentland * 3. Enable power gating for controller 14814562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 14824562236bSHarry Wentland */ 148325292028SYongqiang Sun void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 14844562236bSHarry Wentland { 1485cf1835f0SCharlene Liu struct dc_link *edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context); 14864562236bSHarry Wentland 1487cf1835f0SCharlene Liu struct dc_link *edp_link = get_link_for_edp(dc); 1488cf1835f0SCharlene Liu 1489cf1835f0SCharlene Liu if (edp_link) 1490cf1835f0SCharlene Liu /*we need turn off backlight before DP_blank and encoder powered down*/ 1491cf1835f0SCharlene Liu dc->hwss.edp_backlight_control(edp_link, false); 149225292028SYongqiang Sun 149325292028SYongqiang Sun power_down_all_hw_blocks(dc); 14944562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 149525292028SYongqiang Sun 1496cf1835f0SCharlene Liu if (edp_link_to_turnoff) 1497cf1835f0SCharlene Liu dc->hwss.edp_power_control(edp_link_to_turnoff, false); 149825292028SYongqiang Sun 14994562236bSHarry Wentland bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 15004562236bSHarry Wentland } 15014562236bSHarry Wentland 15024562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 15034562236bSHarry Wentland struct bw_fixed blackout_duration, 15040971c40eSHarry Wentland const struct dc_stream_state *stream) 15054562236bSHarry Wentland { 15064562236bSHarry Wentland uint32_t total_dest_line_time_ns; 15074562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 15084562236bSHarry Wentland 15094562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 15104562236bSHarry Wentland 15114562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 15124fa086b9SLeo (Sunpeng) Li stream->timing.h_total / 15134fa086b9SLeo (Sunpeng) Li stream->timing.pix_clk_khz + 15144562236bSHarry Wentland pstate_blackout_duration_ns; 15154562236bSHarry Wentland 15164562236bSHarry Wentland return total_dest_line_time_ns; 15174562236bSHarry Wentland } 15184562236bSHarry Wentland 15194562236bSHarry Wentland void dce110_set_displaymarks( 1520fb3466a4SBhawanpreet Lakha const struct dc *dc, 1521608ac7bbSJerry Zuo struct dc_state *context) 15224562236bSHarry Wentland { 15234562236bSHarry Wentland uint8_t i, num_pipes; 15244562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 15254562236bSHarry Wentland 15264562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 15274562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 15284562236bSHarry Wentland uint32_t total_dest_line_time_ns; 15294562236bSHarry Wentland 15304562236bSHarry Wentland if (pipe_ctx->stream == NULL) 15314562236bSHarry Wentland continue; 15324562236bSHarry Wentland 15334562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 153477a4ea53SBhawanpreet Lakha dc->bw_vbios->blackout_duration, pipe_ctx->stream); 153586a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 153686a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 15379037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 15389037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 15399037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 15404562236bSHarry Wentland total_dest_line_time_ns); 15414562236bSHarry Wentland if (i == underlay_idx) { 15424562236bSHarry Wentland num_pipes++; 154386a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 154486a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 15459037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 15469037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 15479037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 15484562236bSHarry Wentland total_dest_line_time_ns); 15494562236bSHarry Wentland } 15504562236bSHarry Wentland num_pipes++; 15514562236bSHarry Wentland } 15524562236bSHarry Wentland } 15534562236bSHarry Wentland 1554a2b8659dSTony Cheng static void set_safe_displaymarks( 1555a2b8659dSTony Cheng struct resource_context *res_ctx, 1556a2b8659dSTony Cheng const struct resource_pool *pool) 15574562236bSHarry Wentland { 15584562236bSHarry Wentland int i; 1559a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 15609037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 15614562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 15629037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 15634562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 15644562236bSHarry Wentland 15654562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 15668feabd03SYue Hin Lau if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 15674562236bSHarry Wentland continue; 15684562236bSHarry Wentland 156986a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 157086a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 15714562236bSHarry Wentland nbp_marks, 15724562236bSHarry Wentland max_marks, 15734562236bSHarry Wentland max_marks, 15744562236bSHarry Wentland MAX_WATERMARK); 15758feabd03SYue Hin Lau 15764562236bSHarry Wentland if (i == underlay_idx) 157786a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 157886a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 15794562236bSHarry Wentland nbp_marks, 15804562236bSHarry Wentland max_marks, 15814562236bSHarry Wentland max_marks, 15824562236bSHarry Wentland MAX_WATERMARK); 15838feabd03SYue Hin Lau 15844562236bSHarry Wentland } 15854562236bSHarry Wentland } 15864562236bSHarry Wentland 15874562236bSHarry Wentland /******************************************************************************* 15884562236bSHarry Wentland * Public functions 15894562236bSHarry Wentland ******************************************************************************/ 15904562236bSHarry Wentland 15914562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 15924562236bSHarry Wentland int num_pipes, int vmin, int vmax) 15934562236bSHarry Wentland { 15944562236bSHarry Wentland int i = 0; 15954562236bSHarry Wentland struct drr_params params = {0}; 15964562236bSHarry Wentland 15974562236bSHarry Wentland params.vertical_total_max = vmax; 15984562236bSHarry Wentland params.vertical_total_min = vmin; 15994562236bSHarry Wentland 16004562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 16014562236bSHarry Wentland * some GSL stuff 16024562236bSHarry Wentland */ 16034562236bSHarry Wentland 16044562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 16056b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, ¶ms); 16064562236bSHarry Wentland } 16074562236bSHarry Wentland } 16084562236bSHarry Wentland 160972ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 161072ada5f7SEric Cook int num_pipes, 161172ada5f7SEric Cook struct crtc_position *position) 161272ada5f7SEric Cook { 161372ada5f7SEric Cook int i = 0; 161472ada5f7SEric Cook 161572ada5f7SEric Cook /* TODO: handle pipes > 1 161672ada5f7SEric Cook */ 161772ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 16186b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 161972ada5f7SEric Cook } 162072ada5f7SEric Cook 16214562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 162294267b3dSSylvia Tsai int num_pipes, const struct dc_static_screen_events *events) 16234562236bSHarry Wentland { 16244562236bSHarry Wentland unsigned int i; 162594267b3dSSylvia Tsai unsigned int value = 0; 162694267b3dSSylvia Tsai 162794267b3dSSylvia Tsai if (events->overlay_update) 162894267b3dSSylvia Tsai value |= 0x100; 162994267b3dSSylvia Tsai if (events->surface_update) 163094267b3dSSylvia Tsai value |= 0x80; 163194267b3dSSylvia Tsai if (events->cursor_update) 163294267b3dSSylvia Tsai value |= 0x2; 16334562236bSHarry Wentland 16343eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 1635c3aa1d67SBhawanpreet Lakha value |= 0x84; 1636c3aa1d67SBhawanpreet Lakha #endif 1637c3aa1d67SBhawanpreet Lakha 16384562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 16396b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs-> 16406b670fa9SHarry Wentland set_static_screen_control(pipe_ctx[i]->stream_res.tg, value); 16414562236bSHarry Wentland } 16424562236bSHarry Wentland 16434562236bSHarry Wentland /* unit: in_khz before mode set, get pixel clock from context. ASIC register 16444562236bSHarry Wentland * may not be programmed yet. 16454562236bSHarry Wentland * TODO: after mode set, pre_mode_set = false, 16464562236bSHarry Wentland * may read PLL register to get pixel clock 16474562236bSHarry Wentland */ 16484562236bSHarry Wentland static uint32_t get_max_pixel_clock_for_all_paths( 1649fb3466a4SBhawanpreet Lakha struct dc *dc, 1650608ac7bbSJerry Zuo struct dc_state *context, 16514562236bSHarry Wentland bool pre_mode_set) 16524562236bSHarry Wentland { 16534562236bSHarry Wentland uint32_t max_pix_clk = 0; 16544562236bSHarry Wentland int i; 16554562236bSHarry Wentland 16564562236bSHarry Wentland if (!pre_mode_set) { 16574562236bSHarry Wentland /* TODO: read ASIC register to get pixel clock */ 16584562236bSHarry Wentland ASSERT(0); 16594562236bSHarry Wentland } 16604562236bSHarry Wentland 16614562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 16624562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 16634562236bSHarry Wentland 16644562236bSHarry Wentland if (pipe_ctx->stream == NULL) 16654562236bSHarry Wentland continue; 16664562236bSHarry Wentland 16674562236bSHarry Wentland /* do not check under lay */ 16684562236bSHarry Wentland if (pipe_ctx->top_pipe) 16694562236bSHarry Wentland continue; 16704562236bSHarry Wentland 167110688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk) 16724562236bSHarry Wentland max_pix_clk = 167310688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; 16744562236bSHarry Wentland } 16754562236bSHarry Wentland 16764562236bSHarry Wentland if (max_pix_clk == 0) 16774562236bSHarry Wentland ASSERT(0); 16784562236bSHarry Wentland 16794562236bSHarry Wentland return max_pix_clk; 16804562236bSHarry Wentland } 16814562236bSHarry Wentland 1682f6baff4dSHarry Wentland /* 1683f6baff4dSHarry Wentland * Find clock state based on clock requested. if clock value is 0, simply 16844562236bSHarry Wentland * set clock state as requested without finding clock state by clock value 16854562236bSHarry Wentland */ 1686f6baff4dSHarry Wentland 16874562236bSHarry Wentland static void apply_min_clocks( 1688fb3466a4SBhawanpreet Lakha struct dc *dc, 1689608ac7bbSJerry Zuo struct dc_state *context, 1690e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state *clocks_state, 16914562236bSHarry Wentland bool pre_mode_set) 16924562236bSHarry Wentland { 16934562236bSHarry Wentland struct state_dependent_clocks req_clocks = {0}; 16944562236bSHarry Wentland 16954562236bSHarry Wentland if (!pre_mode_set) { 16964562236bSHarry Wentland /* set clock_state without verification */ 1697ab8db3e1SAndrey Grodzovsky if (context->dis_clk->funcs->set_min_clocks_state) { 1698ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->set_min_clocks_state( 1699ab8db3e1SAndrey Grodzovsky context->dis_clk, *clocks_state); 17004562236bSHarry Wentland return; 17015d6d185fSDmytro Laktyushkin } 17024562236bSHarry Wentland 17032c8ad2d5SAlex Deucher /* TODO: This is incorrect. Figure out how to fix. */ 1704ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1705ab8db3e1SAndrey Grodzovsky context->dis_clk, 17062c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAY_CLK, 1707ab8db3e1SAndrey Grodzovsky context->dis_clk->cur_clocks_value.dispclk_in_khz, 17082c8ad2d5SAlex Deucher pre_mode_set, 17092c8ad2d5SAlex Deucher false); 17102c8ad2d5SAlex Deucher 1711ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1712ab8db3e1SAndrey Grodzovsky context->dis_clk, 17132c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_PIXELCLK, 1714ab8db3e1SAndrey Grodzovsky context->dis_clk->cur_clocks_value.max_pixelclk_in_khz, 17152c8ad2d5SAlex Deucher pre_mode_set, 17162c8ad2d5SAlex Deucher false); 17172c8ad2d5SAlex Deucher 1718ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1719ab8db3e1SAndrey Grodzovsky context->dis_clk, 17202c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 1721ab8db3e1SAndrey Grodzovsky context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz, 17222c8ad2d5SAlex Deucher pre_mode_set, 17232c8ad2d5SAlex Deucher false); 17242c8ad2d5SAlex Deucher return; 17254562236bSHarry Wentland } 17264562236bSHarry Wentland 17274562236bSHarry Wentland /* get the required state based on state dependent clocks: 17284562236bSHarry Wentland * display clock and pixel clock 17294562236bSHarry Wentland */ 17309037d802SDmytro Laktyushkin req_clocks.display_clk_khz = context->bw.dce.dispclk_khz; 17314562236bSHarry Wentland 17324562236bSHarry Wentland req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( 17334562236bSHarry Wentland dc, context, true); 17344562236bSHarry Wentland 1735ab8db3e1SAndrey Grodzovsky if (context->dis_clk->funcs->get_required_clocks_state) { 1736ab8db3e1SAndrey Grodzovsky *clocks_state = context->dis_clk->funcs->get_required_clocks_state( 1737ab8db3e1SAndrey Grodzovsky context->dis_clk, &req_clocks); 1738ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->set_min_clocks_state( 1739ab8db3e1SAndrey Grodzovsky context->dis_clk, *clocks_state); 17404562236bSHarry Wentland } else { 1741ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1742ab8db3e1SAndrey Grodzovsky context->dis_clk, 17432c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAY_CLK, 17442c8ad2d5SAlex Deucher req_clocks.display_clk_khz, 17452c8ad2d5SAlex Deucher pre_mode_set, 17462c8ad2d5SAlex Deucher false); 17472c8ad2d5SAlex Deucher 1748ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1749ab8db3e1SAndrey Grodzovsky context->dis_clk, 17502c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_PIXELCLK, 17512c8ad2d5SAlex Deucher req_clocks.pixel_clk_khz, 17522c8ad2d5SAlex Deucher pre_mode_set, 17532c8ad2d5SAlex Deucher false); 17542c8ad2d5SAlex Deucher 1755ab8db3e1SAndrey Grodzovsky context->dis_clk->funcs->apply_clock_voltage_request( 1756ab8db3e1SAndrey Grodzovsky context->dis_clk, 17572c8ad2d5SAlex Deucher DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 17582c8ad2d5SAlex Deucher req_clocks.pixel_clk_khz, 17592c8ad2d5SAlex Deucher pre_mode_set, 17602c8ad2d5SAlex Deucher false); 17614562236bSHarry Wentland } 17624562236bSHarry Wentland } 17634562236bSHarry Wentland 17643eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 1765690b5e39SRoman Li 1766690b5e39SRoman Li /* 1767690b5e39SRoman Li * Check if FBC can be enabled 1768690b5e39SRoman Li */ 17699c6569deSHarry Wentland static bool should_enable_fbc(struct dc *dc, 17703bc4aaa9SRoman Li struct dc_state *context, 17713bc4aaa9SRoman Li uint32_t *pipe_idx) 1772690b5e39SRoman Li { 17733bc4aaa9SRoman Li uint32_t i; 17743bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = NULL; 17753bc4aaa9SRoman Li struct resource_context *res_ctx = &context->res_ctx; 17763bc4aaa9SRoman Li 1777690b5e39SRoman Li 1778690b5e39SRoman Li ASSERT(dc->fbc_compressor); 1779690b5e39SRoman Li 1780690b5e39SRoman Li /* FBC memory should be allocated */ 1781690b5e39SRoman Li if (!dc->ctx->fbc_gpu_addr) 17829c6569deSHarry Wentland return false; 1783690b5e39SRoman Li 1784690b5e39SRoman Li /* Only supports single display */ 1785690b5e39SRoman Li if (context->stream_count != 1) 17869c6569deSHarry Wentland return false; 1787690b5e39SRoman Li 17883bc4aaa9SRoman Li for (i = 0; i < dc->res_pool->pipe_count; i++) { 17893bc4aaa9SRoman Li if (res_ctx->pipe_ctx[i].stream) { 17903bc4aaa9SRoman Li pipe_ctx = &res_ctx->pipe_ctx[i]; 17913bc4aaa9SRoman Li *pipe_idx = i; 17923bc4aaa9SRoman Li break; 17933bc4aaa9SRoman Li } 17943bc4aaa9SRoman Li } 17953bc4aaa9SRoman Li 1796690b5e39SRoman Li /* Only supports eDP */ 1797690b5e39SRoman Li if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP) 17989c6569deSHarry Wentland return false; 1799690b5e39SRoman Li 1800690b5e39SRoman Li /* PSR should not be enabled */ 1801690b5e39SRoman Li if (pipe_ctx->stream->sink->link->psr_enabled) 18029c6569deSHarry Wentland return false; 1803690b5e39SRoman Li 180493984bbcSShirish S /* Nothing to compress */ 180593984bbcSShirish S if (!pipe_ctx->plane_state) 18069c6569deSHarry Wentland return false; 180793984bbcSShirish S 180805230fa9SRoman Li /* Only for non-linear tiling */ 180905230fa9SRoman Li if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 18109c6569deSHarry Wentland return false; 181105230fa9SRoman Li 18129c6569deSHarry Wentland return true; 1813690b5e39SRoman Li } 1814690b5e39SRoman Li 1815690b5e39SRoman Li /* 1816690b5e39SRoman Li * Enable FBC 1817690b5e39SRoman Li */ 18189c6569deSHarry Wentland static void enable_fbc(struct dc *dc, 1819608ac7bbSJerry Zuo struct dc_state *context) 1820690b5e39SRoman Li { 18213bc4aaa9SRoman Li uint32_t pipe_idx = 0; 18223bc4aaa9SRoman Li 18233bc4aaa9SRoman Li if (should_enable_fbc(dc, context, &pipe_idx)) { 1824690b5e39SRoman Li /* Program GRPH COMPRESSED ADDRESS and PITCH */ 1825690b5e39SRoman Li struct compr_addr_and_pitch_params params = {0, 0, 0}; 1826690b5e39SRoman Li struct compressor *compr = dc->fbc_compressor; 18273bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 18283bc4aaa9SRoman Li 1829690b5e39SRoman Li 18309c6569deSHarry Wentland params.source_view_width = pipe_ctx->stream->timing.h_addressable; 18319c6569deSHarry Wentland params.source_view_height = pipe_ctx->stream->timing.v_addressable; 1832690b5e39SRoman Li 1833690b5e39SRoman Li compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 1834690b5e39SRoman Li 1835690b5e39SRoman Li compr->funcs->surface_address_and_pitch(compr, ¶ms); 1836690b5e39SRoman Li compr->funcs->set_fbc_invalidation_triggers(compr, 1); 1837690b5e39SRoman Li 1838690b5e39SRoman Li compr->funcs->enable_fbc(compr, ¶ms); 1839690b5e39SRoman Li } 1840690b5e39SRoman Li } 1841690b5e39SRoman Li #endif 1842690b5e39SRoman Li 184354e8695eSDmytro Laktyushkin static void dce110_reset_hw_ctx_wrap( 1844fb3466a4SBhawanpreet Lakha struct dc *dc, 1845608ac7bbSJerry Zuo struct dc_state *context) 18464562236bSHarry Wentland { 18474562236bSHarry Wentland int i; 18484562236bSHarry Wentland 18494562236bSHarry Wentland /* Reset old context */ 18504562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 1851a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 18524562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 1853608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 18544562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 18554562236bSHarry Wentland 18564562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 18574562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 18584562236bSHarry Wentland * PHY when not already disabled. 18594562236bSHarry Wentland */ 18604562236bSHarry Wentland 18614562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 18624562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 18634562236bSHarry Wentland continue; 18644562236bSHarry Wentland 18654562236bSHarry Wentland if (!pipe_ctx->stream || 186654e8695eSDmytro Laktyushkin pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 186721e67d4dSHarry Wentland struct clock_source *old_clk = pipe_ctx_old->clock_source; 186821e67d4dSHarry Wentland 1869827f11e9SLeo (Sunpeng) Li /* Disable if new stream is null. O/w, if stream is 1870827f11e9SLeo (Sunpeng) Li * disabled already, no need to disable again. 1871827f11e9SLeo (Sunpeng) Li */ 1872827f11e9SLeo (Sunpeng) Li if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) 18734176664bSCharlene Liu core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE); 1874d050f8edSHersen Wu 18756b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 18766b670fa9SHarry Wentland if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 187754e8695eSDmytro Laktyushkin dm_error("DC: failed to blank crtc!\n"); 187854e8695eSDmytro Laktyushkin BREAK_TO_DEBUGGER(); 187954e8695eSDmytro Laktyushkin } 18806b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 188186a66c4eSHarry Wentland pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 1882608ac7bbSJerry Zuo pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 188354e8695eSDmytro Laktyushkin 188421e67d4dSHarry Wentland if (old_clk) 188521e67d4dSHarry Wentland old_clk->funcs->cs_power_down(old_clk); 188621e67d4dSHarry Wentland 18877f914a62SYongqiang Sun dc->hwss.disable_plane(dc, pipe_ctx_old); 188854e8695eSDmytro Laktyushkin 188954e8695eSDmytro Laktyushkin pipe_ctx_old->stream = NULL; 189054e8695eSDmytro Laktyushkin } 18914562236bSHarry Wentland } 18924562236bSHarry Wentland } 18934562236bSHarry Wentland 1894cf437593SDmytro Laktyushkin 18954562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 1896fb3466a4SBhawanpreet Lakha struct dc *dc, 1897608ac7bbSJerry Zuo struct dc_state *context) 18984562236bSHarry Wentland { 18994562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 19004562236bSHarry Wentland enum dc_status status; 19014562236bSHarry Wentland int i; 1902e9c58bb4SDmytro Laktyushkin enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID; 19034562236bSHarry Wentland 19044562236bSHarry Wentland /* Reset old context */ 19054562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 19064562236bSHarry Wentland dc->hwss.reset_hw_ctx_wrap(dc, context); 19074562236bSHarry Wentland 19084562236bSHarry Wentland /* Skip applying if no targets */ 1909ab2541b6SAric Cyr if (context->stream_count <= 0) 19104562236bSHarry Wentland return DC_OK; 19114562236bSHarry Wentland 19124562236bSHarry Wentland /* Apply new context */ 19134562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 19144562236bSHarry Wentland 19154562236bSHarry Wentland /* below is for real asic only */ 1916a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 19174562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 1918608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 19194562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 19204562236bSHarry Wentland 19214562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 19224562236bSHarry Wentland continue; 19234562236bSHarry Wentland 19244562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 19254562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 19264562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 19274562236bSHarry Wentland pipe_ctx->clock_source, i); 19284562236bSHarry Wentland continue; 19294562236bSHarry Wentland } 19304562236bSHarry Wentland 19314562236bSHarry Wentland dc->hwss.enable_display_power_gating( 19324562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 19334562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 19344562236bSHarry Wentland } 19354562236bSHarry Wentland 1936a2b8659dSTony Cheng set_safe_displaymarks(&context->res_ctx, dc->res_pool); 19371663ae1cSBhawanpreet Lakha 19383eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 19392f3bfb27SRoman Li if (dc->fbc_compressor) 19401663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 19411663ae1cSBhawanpreet Lakha #endif 19424562236bSHarry Wentland /*TODO: when pplib works*/ 19434562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, true); 19444562236bSHarry Wentland 1945ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 19463639fa68SZeyu Fan if (dc->ctx->dce_version >= DCN_VERSION_1_0) { 19479037d802SDmytro Laktyushkin if (context->bw.dcn.calc_clk.fclk_khz 1948608ac7bbSJerry Zuo > dc->current_state->bw.dcn.cur_clk.fclk_khz) { 1949ff5ef992SAlex Deucher struct dm_pp_clock_for_voltage_req clock; 1950ff5ef992SAlex Deucher 1951ff5ef992SAlex Deucher clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; 19529037d802SDmytro Laktyushkin clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; 1953ff5ef992SAlex Deucher dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); 1954608ac7bbSJerry Zuo dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; 1955c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; 1956ff5ef992SAlex Deucher } 19579037d802SDmytro Laktyushkin if (context->bw.dcn.calc_clk.dcfclk_khz 1958608ac7bbSJerry Zuo > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { 1959ff5ef992SAlex Deucher struct dm_pp_clock_for_voltage_req clock; 1960ff5ef992SAlex Deucher 1961ff5ef992SAlex Deucher clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; 19629037d802SDmytro Laktyushkin clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; 1963ff5ef992SAlex Deucher dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); 1964608ac7bbSJerry Zuo dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; 1965c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; 1966ff5ef992SAlex Deucher } 1967c66a54dcSDmytro Laktyushkin if (context->bw.dcn.calc_clk.dispclk_khz 1968608ac7bbSJerry Zuo > dc->current_state->bw.dcn.cur_clk.dispclk_khz) { 1969c66a54dcSDmytro Laktyushkin dc->res_pool->display_clock->funcs->set_clock( 1970c66a54dcSDmytro Laktyushkin dc->res_pool->display_clock, 1971c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz); 1972608ac7bbSJerry Zuo dc->current_state->bw.dcn.cur_clk.dispclk_khz = 1973c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz; 1974c66a54dcSDmytro Laktyushkin context->bw.dcn.cur_clk.dispclk_khz = 1975c66a54dcSDmytro Laktyushkin context->bw.dcn.calc_clk.dispclk_khz; 1976c66a54dcSDmytro Laktyushkin } 1977c66a54dcSDmytro Laktyushkin } else 1978ff5ef992SAlex Deucher #endif 19799037d802SDmytro Laktyushkin if (context->bw.dce.dispclk_khz 1980608ac7bbSJerry Zuo > dc->current_state->bw.dce.dispclk_khz) { 1981a2b8659dSTony Cheng dc->res_pool->display_clock->funcs->set_clock( 1982a2b8659dSTony Cheng dc->res_pool->display_clock, 19839037d802SDmytro Laktyushkin context->bw.dce.dispclk_khz * 115 / 100); 19841ce71fcdSCharlene Liu } 1985ab8812a3SHersen Wu /* program audio wall clock. use HDMI as clock source if HDMI 1986ab8812a3SHersen Wu * audio active. Otherwise, use DP as clock source 1987ab8812a3SHersen Wu * first, loop to find any HDMI audio, if not, loop find DP audio 1988ab8812a3SHersen Wu */ 19894562236bSHarry Wentland /* Setup audio rate clock source */ 19904562236bSHarry Wentland /* Issue: 19914562236bSHarry Wentland * Audio lag happened on DP monitor when unplug a HDMI monitor 19924562236bSHarry Wentland * 19934562236bSHarry Wentland * Cause: 19944562236bSHarry Wentland * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 19954562236bSHarry Wentland * is set to either dto0 or dto1, audio should work fine. 19964562236bSHarry Wentland * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 19974562236bSHarry Wentland * set to dto0 will cause audio lag. 19984562236bSHarry Wentland * 19994562236bSHarry Wentland * Solution: 20004562236bSHarry Wentland * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 20014562236bSHarry Wentland * find first available pipe with audio, setup audio wall DTO per topology 20024562236bSHarry Wentland * instead of per pipe. 20034562236bSHarry Wentland */ 2004a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2005ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2006ab8812a3SHersen Wu 2007ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2008ab8812a3SHersen Wu continue; 2009ab8812a3SHersen Wu 2010ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 2011ab8812a3SHersen Wu continue; 2012ab8812a3SHersen Wu 2013ab8812a3SHersen Wu if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 2014ab8812a3SHersen Wu continue; 2015ab8812a3SHersen Wu 2016afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 2017ab8812a3SHersen Wu struct audio_output audio_output; 2018ab8812a3SHersen Wu 2019ab8db3e1SAndrey Grodzovsky build_audio_output(context, pipe_ctx, &audio_output); 2020ab8812a3SHersen Wu 2021afaacef4SHarry Wentland pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2022afaacef4SHarry Wentland pipe_ctx->stream_res.audio, 2023ab8812a3SHersen Wu pipe_ctx->stream->signal, 2024ab8812a3SHersen Wu &audio_output.crtc_info, 2025ab8812a3SHersen Wu &audio_output.pll_info); 2026ab8812a3SHersen Wu break; 2027ab8812a3SHersen Wu } 2028ab8812a3SHersen Wu } 2029ab8812a3SHersen Wu 2030ab8812a3SHersen Wu /* no HDMI audio is found, try DP audio */ 2031a2b8659dSTony Cheng if (i == dc->res_pool->pipe_count) { 2032a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2033ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2034ab8812a3SHersen Wu 2035ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2036ab8812a3SHersen Wu continue; 2037ab8812a3SHersen Wu 2038ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 2039ab8812a3SHersen Wu continue; 2040ab8812a3SHersen Wu 2041ab8812a3SHersen Wu if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 2042ab8812a3SHersen Wu continue; 2043ab8812a3SHersen Wu 2044afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 2045ab8812a3SHersen Wu struct audio_output audio_output; 2046ab8812a3SHersen Wu 2047ab8db3e1SAndrey Grodzovsky build_audio_output(context, pipe_ctx, &audio_output); 2048ab8812a3SHersen Wu 2049afaacef4SHarry Wentland pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2050afaacef4SHarry Wentland pipe_ctx->stream_res.audio, 2051ab8812a3SHersen Wu pipe_ctx->stream->signal, 2052ab8812a3SHersen Wu &audio_output.crtc_info, 2053ab8812a3SHersen Wu &audio_output.pll_info); 2054ab8812a3SHersen Wu break; 2055ab8812a3SHersen Wu } 2056ab8812a3SHersen Wu } 2057ab8812a3SHersen Wu } 2058ab8812a3SHersen Wu 2059a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2060ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 2061608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 2062ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2063ab8812a3SHersen Wu 2064ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2065ab8812a3SHersen Wu continue; 2066ab8812a3SHersen Wu 2067ab8812a3SHersen Wu if (pipe_ctx->stream == pipe_ctx_old->stream) 2068ab8812a3SHersen Wu continue; 2069ab8812a3SHersen Wu 20705b92d9d4SHarry Wentland if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2071313bf4ffSYongqiang Sun continue; 2072313bf4ffSYongqiang Sun 2073ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 2074ab8812a3SHersen Wu continue; 2075ab8812a3SHersen Wu 2076afaacef4SHarry Wentland if (context->res_ctx.pipe_ctx[i].stream_res.audio != NULL) { 2077ab8812a3SHersen Wu 20784562236bSHarry Wentland struct audio_output audio_output; 20794562236bSHarry Wentland 2080ab8db3e1SAndrey Grodzovsky build_audio_output(context, pipe_ctx, &audio_output); 20814562236bSHarry Wentland 20824562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 20838e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 20848e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 2085afaacef4SHarry Wentland pipe_ctx->stream_res.audio->inst, 20864fa086b9SLeo (Sunpeng) Li &pipe_ctx->stream->audio_info); 20874562236bSHarry Wentland else 20888e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 20898e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 2090afaacef4SHarry Wentland pipe_ctx->stream_res.audio->inst, 20914fa086b9SLeo (Sunpeng) Li &pipe_ctx->stream->audio_info, 20924562236bSHarry Wentland &audio_output.crtc_info); 20934562236bSHarry Wentland 2094afaacef4SHarry Wentland pipe_ctx->stream_res.audio->funcs->az_configure( 2095afaacef4SHarry Wentland pipe_ctx->stream_res.audio, 20964562236bSHarry Wentland pipe_ctx->stream->signal, 20974562236bSHarry Wentland &audio_output.crtc_info, 20984fa086b9SLeo (Sunpeng) Li &pipe_ctx->stream->audio_info); 20994562236bSHarry Wentland } 21004562236bSHarry Wentland 21014562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 21024562236bSHarry Wentland pipe_ctx, 21034562236bSHarry Wentland context, 21044562236bSHarry Wentland dc); 21054562236bSHarry Wentland 21064562236bSHarry Wentland if (DC_OK != status) 21074562236bSHarry Wentland return status; 21084562236bSHarry Wentland } 21094562236bSHarry Wentland 21106bf52028SHersen Wu /* pplib is notified if disp_num changed */ 2111cf437593SDmytro Laktyushkin dc->hwss.set_bandwidth(dc, context, true); 21124562236bSHarry Wentland 21134562236bSHarry Wentland /* to save power */ 21144562236bSHarry Wentland apply_min_clocks(dc, context, &clocks_state, false); 21154562236bSHarry Wentland 21164562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, false); 21174562236bSHarry Wentland 21183eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 2119690b5e39SRoman Li if (dc->fbc_compressor) 2120690b5e39SRoman Li enable_fbc(dc, context); 2121690b5e39SRoman Li 2122690b5e39SRoman Li #endif 2123cf437593SDmytro Laktyushkin 21244562236bSHarry Wentland return DC_OK; 21254562236bSHarry Wentland } 21264562236bSHarry Wentland 21274562236bSHarry Wentland /******************************************************************************* 21284562236bSHarry Wentland * Front End programming 21294562236bSHarry Wentland ******************************************************************************/ 21304562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 21314562236bSHarry Wentland { 21324562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 21334562236bSHarry Wentland 21344562236bSHarry Wentland default_adjust.force_hw_default = false; 213534996173SHarry Wentland default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 213634996173SHarry Wentland default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 21374562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 21386702a9acSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 21394562236bSHarry Wentland 21404562236bSHarry Wentland /* display color depth */ 21414562236bSHarry Wentland default_adjust.color_depth = 21424fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.display_color_depth; 21434562236bSHarry Wentland 21444562236bSHarry Wentland /* Lb color depth */ 21456702a9acSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 21464562236bSHarry Wentland 214786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 214886a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, &default_adjust); 21494562236bSHarry Wentland } 21504562236bSHarry Wentland 2151b06b7680SLeon Elazar 2152b06b7680SLeon Elazar /******************************************************************************* 2153b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 2154b06b7680SLeon Elazar * Blender + CRTC 2155b06b7680SLeon Elazar * 2156b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 2157b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 2158b06b7680SLeon Elazar * 2159b06b7680SLeon Elazar * |----------------------------------------------- | 2160b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 2161b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 2162b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 2163b06b7680SLeon Elazar * |------------------------------------------------| 2164b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 2165b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 2166b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 2167b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 2168b06b7680SLeon Elazar * -------------------------------------------------| 2169b06b7680SLeon Elazar * 2170b06b7680SLeon Elazar ******************************************************************************/ 2171fb3466a4SBhawanpreet Lakha static void program_surface_visibility(const struct dc *dc, 21724562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 21734562236bSHarry Wentland { 21744562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2175b06b7680SLeon Elazar bool blank_target = false; 21764562236bSHarry Wentland 21774562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 2178b06b7680SLeon Elazar 2179b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 2180b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2181b06b7680SLeon Elazar 21823be5262eSHarry Wentland if (pipe_ctx->bottom_pipe->plane_state->visible) { 21833be5262eSHarry Wentland if (pipe_ctx->plane_state->visible) 21844562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 21854562236bSHarry Wentland else 21864562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 2187b06b7680SLeon Elazar 21883be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2189b06b7680SLeon Elazar blank_target = true; 2190b06b7680SLeon Elazar 21913be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2192b06b7680SLeon Elazar blank_target = true; 2193b06b7680SLeon Elazar 2194e07f541fSYongqiang Sun dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 21956b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2196b06b7680SLeon Elazar 21974562236bSHarry Wentland } 21984562236bSHarry Wentland 21991bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 22001bf56e62SZeyu Fan { 2201146a9f63SKrunoslav Kovac int i = 0; 22021bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 22031bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 22041bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 22051bf56e62SZeyu Fan 22061bf56e62SZeyu Fan 22074fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 22081bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2209146a9f63SKrunoslav Kovac 2210146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2211146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2212146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 22131bf56e62SZeyu Fan } 22141bf56e62SZeyu Fan 221586a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 22161bf56e62SZeyu Fan } 22171bf56e62SZeyu Fan 22184562236bSHarry Wentland /** 22194562236bSHarry Wentland * TODO REMOVE, USE UPDATE INSTEAD 22204562236bSHarry Wentland */ 22214562236bSHarry Wentland static void set_plane_config( 2222fb3466a4SBhawanpreet Lakha const struct dc *dc, 22234562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 22244562236bSHarry Wentland struct resource_context *res_ctx) 22254562236bSHarry Wentland { 222686a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 22273be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 22284562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 22294562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 22304562236bSHarry Wentland unsigned int i; 22314562236bSHarry Wentland 22324562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 22334562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 22344562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 22354562236bSHarry Wentland 2236e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 22374562236bSHarry Wentland 22384562236bSHarry Wentland set_default_colors(pipe_ctx); 223956ef6ed9SAnthony Koo if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 22404562236bSHarry Wentland tbl_entry.color_space = 22414fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 22424562236bSHarry Wentland 22434562236bSHarry Wentland for (i = 0; i < 12; i++) 22444562236bSHarry Wentland tbl_entry.regval[i] = 22454fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 22464562236bSHarry Wentland 224786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 224886a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 22494562236bSHarry Wentland } 22504562236bSHarry Wentland 22514fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 22524562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2253146a9f63SKrunoslav Kovac 2254146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2255146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2256146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 22574562236bSHarry Wentland } 22584562236bSHarry Wentland 225986a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 22604562236bSHarry Wentland 22616702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 22624562236bSHarry Wentland program_scaler(dc, pipe_ctx); 22634562236bSHarry Wentland 2264b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 22654562236bSHarry Wentland 22664562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 22674562236bSHarry Wentland mi, 22683be5262eSHarry Wentland plane_state->format, 22693be5262eSHarry Wentland &plane_state->tiling_info, 22703be5262eSHarry Wentland &plane_state->plane_size, 22713be5262eSHarry Wentland plane_state->rotation, 22724562236bSHarry Wentland NULL, 22734b28b76bSDmytro Laktyushkin false); 22744b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 22753be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 22764562236bSHarry Wentland 2277fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 22784562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 227986a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 22803be5262eSHarry Wentland plane_state->format, 22813be5262eSHarry Wentland &plane_state->tiling_info, 22823be5262eSHarry Wentland plane_state->rotation); 22834562236bSHarry Wentland } 22844562236bSHarry Wentland 2285fb3466a4SBhawanpreet Lakha static void update_plane_addr(const struct dc *dc, 22864562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 22874562236bSHarry Wentland { 22883be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 22894562236bSHarry Wentland 22903be5262eSHarry Wentland if (plane_state == NULL) 22914562236bSHarry Wentland return; 22924562236bSHarry Wentland 229386a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 229486a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 22953be5262eSHarry Wentland &plane_state->address, 22963be5262eSHarry Wentland plane_state->flip_immediate); 22974562236bSHarry Wentland 22983be5262eSHarry Wentland plane_state->status.requested_address = plane_state->address; 22994562236bSHarry Wentland } 23004562236bSHarry Wentland 23014562236bSHarry Wentland void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 23024562236bSHarry Wentland { 23033be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 23044562236bSHarry Wentland 23053be5262eSHarry Wentland if (plane_state == NULL) 23064562236bSHarry Wentland return; 23074562236bSHarry Wentland 23083be5262eSHarry Wentland plane_state->status.is_flip_pending = 230986a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 231086a66c4eSHarry Wentland pipe_ctx->plane_res.mi); 23114562236bSHarry Wentland 23123be5262eSHarry Wentland if (plane_state->status.is_flip_pending && !plane_state->visible) 231386a66c4eSHarry Wentland pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 23144562236bSHarry Wentland 231586a66c4eSHarry Wentland plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 231686a66c4eSHarry Wentland if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 23176b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 23183be5262eSHarry Wentland plane_state->status.is_right_eye =\ 23196b670fa9SHarry Wentland !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 23207f5c22d1SVitaly Prosyak } 23214562236bSHarry Wentland } 23224562236bSHarry Wentland 2323fb3466a4SBhawanpreet Lakha void dce110_power_down(struct dc *dc) 23244562236bSHarry Wentland { 23254562236bSHarry Wentland power_down_all_hw_blocks(dc); 23264562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 23274562236bSHarry Wentland } 23284562236bSHarry Wentland 23294562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 23304562236bSHarry Wentland struct dc_context *dc_ctx, 23314562236bSHarry Wentland struct timing_generator *tg) 23324562236bSHarry Wentland { 23334562236bSHarry Wentland bool rc = false; 23344562236bSHarry Wentland 23354562236bSHarry Wentland /* To avoid endless loop we wait at most 23364562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 23374562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 23384562236bSHarry Wentland uint32_t i; 23394562236bSHarry Wentland 23404562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 23414562236bSHarry Wentland 23424562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 23434562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 23444562236bSHarry Wentland break; 23454562236bSHarry Wentland } 23464562236bSHarry Wentland 23474562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 23484562236bSHarry Wentland rc = true; 23494562236bSHarry Wentland /* usually occurs at i=1 */ 23504562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 23514562236bSHarry Wentland i); 23524562236bSHarry Wentland break; 23534562236bSHarry Wentland } 23544562236bSHarry Wentland 23554562236bSHarry Wentland /* Wait for one frame. */ 23564562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 23574562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 23584562236bSHarry Wentland } 23594562236bSHarry Wentland 23604562236bSHarry Wentland if (false == rc) 23614562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 23624562236bSHarry Wentland 23634562236bSHarry Wentland return rc; 23644562236bSHarry Wentland } 23654562236bSHarry Wentland 23664562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 23674562236bSHarry Wentland static void dce110_enable_timing_synchronization( 2368fb3466a4SBhawanpreet Lakha struct dc *dc, 23694562236bSHarry Wentland int group_index, 23704562236bSHarry Wentland int group_size, 23714562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 23724562236bSHarry Wentland { 23734562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 23744562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 23754562236bSHarry Wentland int i; 23764562236bSHarry Wentland 23774562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 23784562236bSHarry Wentland 23794562236bSHarry Wentland /* Designate a single TG in the group as a master. 23804562236bSHarry Wentland * Since HW doesn't care which one, we always assign 23814562236bSHarry Wentland * the 1st one in the group. */ 23824562236bSHarry Wentland gsl_params.gsl_group = 0; 23836b670fa9SHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 23844562236bSHarry Wentland 23854562236bSHarry Wentland for (i = 0; i < group_size; i++) 23866b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 23876b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg, &gsl_params); 23884562236bSHarry Wentland 23894562236bSHarry Wentland /* Reset slave controllers on master VSync */ 23904562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 23914562236bSHarry Wentland 23924562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 23936b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2394fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2395fa2123dbSMikita Lipski gsl_params.gsl_group); 23964562236bSHarry Wentland 23974562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 23984562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 23996b670fa9SHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2400fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2401fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg); 24024562236bSHarry Wentland } 24034562236bSHarry Wentland 24044562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 24054562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 24064562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 24074562236bSHarry Wentland for (i = 0; i < group_size; i++) 24086b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 24094562236bSHarry Wentland 24104562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 24114562236bSHarry Wentland } 24124562236bSHarry Wentland 2413fa2123dbSMikita Lipski static void dce110_enable_per_frame_crtc_position_reset( 2414fa2123dbSMikita Lipski struct dc *dc, 2415fa2123dbSMikita Lipski int group_size, 2416fa2123dbSMikita Lipski struct pipe_ctx *grouped_pipes[]) 2417fa2123dbSMikita Lipski { 2418fa2123dbSMikita Lipski struct dc_context *dc_ctx = dc->ctx; 2419fa2123dbSMikita Lipski struct dcp_gsl_params gsl_params = { 0 }; 2420fa2123dbSMikita Lipski int i; 2421fa2123dbSMikita Lipski 2422fa2123dbSMikita Lipski gsl_params.gsl_group = 0; 2423fa2123dbSMikita Lipski gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst; 2424fa2123dbSMikita Lipski 2425fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2426fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2427fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, &gsl_params); 2428fa2123dbSMikita Lipski 2429fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2430fa2123dbSMikita Lipski 2431fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2432fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2433fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2434fa2123dbSMikita Lipski gsl_params.gsl_master, 2435fa2123dbSMikita Lipski &grouped_pipes[i]->stream->triggered_crtc_reset); 2436fa2123dbSMikita Lipski 2437fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2438fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2439fa2123dbSMikita Lipski wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2440fa2123dbSMikita Lipski 2441fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2442fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2443fa2123dbSMikita Lipski 2444fa2123dbSMikita Lipski } 2445fa2123dbSMikita Lipski 2446fb3466a4SBhawanpreet Lakha static void init_hw(struct dc *dc) 24474562236bSHarry Wentland { 24484562236bSHarry Wentland int i; 24494562236bSHarry Wentland struct dc_bios *bp; 24504562236bSHarry Wentland struct transform *xfm; 24515e7773a2SAnthony Koo struct abm *abm; 24524562236bSHarry Wentland 24534562236bSHarry Wentland bp = dc->ctx->dc_bios; 24544562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 24554562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 24564562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 24574562236bSHarry Wentland 24584562236bSHarry Wentland dc->hwss.enable_display_power_gating( 24594562236bSHarry Wentland dc, i, bp, 24604562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 24614562236bSHarry Wentland dc->hwss.enable_display_power_gating( 24624562236bSHarry Wentland dc, i, bp, 24634562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 24644562236bSHarry Wentland dc->hwss.enable_display_pipe_clock_gating( 24654562236bSHarry Wentland dc->ctx, 24664562236bSHarry Wentland true); 24674562236bSHarry Wentland } 24684562236bSHarry Wentland 2469e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 24704562236bSHarry Wentland /***************************************/ 24714562236bSHarry Wentland 24724562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 24734562236bSHarry Wentland /****************************************/ 24744562236bSHarry Wentland /* Power up AND update implementation according to the 24754562236bSHarry Wentland * required signal (which may be different from the 24764562236bSHarry Wentland * default signal on connector). */ 2477d0778ebfSHarry Wentland struct dc_link *link = dc->links[i]; 2478069d418fSAndrew Jiang 2479069d418fSAndrew Jiang if (link->link_enc->connector.id == CONNECTOR_ID_EDP) 2480069d418fSAndrew Jiang dc->hwss.edp_power_control(link, true); 2481069d418fSAndrew Jiang 24824562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 24834562236bSHarry Wentland } 24844562236bSHarry Wentland 24854562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 24864562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 24874562236bSHarry Wentland 24884562236bSHarry Wentland tg->funcs->disable_vga(tg); 24894562236bSHarry Wentland 24904562236bSHarry Wentland /* Blank controller using driver code instead of 24914562236bSHarry Wentland * command table. */ 24924562236bSHarry Wentland tg->funcs->set_blank(tg, true); 24934b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 24944562236bSHarry Wentland } 24954562236bSHarry Wentland 24964562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 24974562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 24984562236bSHarry Wentland audio->funcs->hw_init(audio); 24994562236bSHarry Wentland } 25005e7773a2SAnthony Koo 25015e7773a2SAnthony Koo abm = dc->res_pool->abm; 25026728b30cSAnthony Koo if (abm != NULL) { 25036728b30cSAnthony Koo abm->funcs->init_backlight(abm); 25045e7773a2SAnthony Koo abm->funcs->abm_init(abm); 25054562236bSHarry Wentland } 25063eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 25072f3bfb27SRoman Li if (dc->fbc_compressor) 25081663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 25091663ae1cSBhawanpreet Lakha #endif 2510690b5e39SRoman Li 25116728b30cSAnthony Koo } 25124562236bSHarry Wentland 251328f72454SJordan Lazare void dce110_fill_display_configs( 2514608ac7bbSJerry Zuo const struct dc_state *context, 2515cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg) 25164562236bSHarry Wentland { 2517cf437593SDmytro Laktyushkin int j; 2518cf437593SDmytro Laktyushkin int num_cfgs = 0; 2519cf437593SDmytro Laktyushkin 2520cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 2521cf437593SDmytro Laktyushkin int k; 2522cf437593SDmytro Laktyushkin 25230971c40eSHarry Wentland const struct dc_stream_state *stream = context->streams[j]; 2524cf437593SDmytro Laktyushkin struct dm_pp_single_disp_config *cfg = 2525cf437593SDmytro Laktyushkin &pp_display_cfg->disp_configs[num_cfgs]; 2526cf437593SDmytro Laktyushkin const struct pipe_ctx *pipe_ctx = NULL; 2527cf437593SDmytro Laktyushkin 2528cf437593SDmytro Laktyushkin for (k = 0; k < MAX_PIPES; k++) 2529cf437593SDmytro Laktyushkin if (stream == context->res_ctx.pipe_ctx[k].stream) { 2530cf437593SDmytro Laktyushkin pipe_ctx = &context->res_ctx.pipe_ctx[k]; 2531cf437593SDmytro Laktyushkin break; 25324562236bSHarry Wentland } 25334562236bSHarry Wentland 2534cf437593SDmytro Laktyushkin ASSERT(pipe_ctx != NULL); 2535cf437593SDmytro Laktyushkin 2536631aaa0aSHersen Wu /* only notify active stream */ 2537631aaa0aSHersen Wu if (stream->dpms_off) 2538631aaa0aSHersen Wu continue; 2539631aaa0aSHersen Wu 2540cf437593SDmytro Laktyushkin num_cfgs++; 2541cf437593SDmytro Laktyushkin cfg->signal = pipe_ctx->stream->signal; 2542e07f541fSYongqiang Sun cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; 25434fa086b9SLeo (Sunpeng) Li cfg->src_height = stream->src.height; 25444fa086b9SLeo (Sunpeng) Li cfg->src_width = stream->src.width; 2545cf437593SDmytro Laktyushkin cfg->ddi_channel_mapping = 2546cf437593SDmytro Laktyushkin stream->sink->link->ddi_channel_mapping.raw; 2547cf437593SDmytro Laktyushkin cfg->transmitter = 2548cf437593SDmytro Laktyushkin stream->sink->link->link_enc->transmitter; 2549cf437593SDmytro Laktyushkin cfg->link_settings.lane_count = 2550d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.lane_count; 2551cf437593SDmytro Laktyushkin cfg->link_settings.link_rate = 2552d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.link_rate; 2553cf437593SDmytro Laktyushkin cfg->link_settings.link_spread = 2554d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.link_spread; 2555cf437593SDmytro Laktyushkin cfg->sym_clock = stream->phy_pix_clk; 2556cf437593SDmytro Laktyushkin /* Round v_refresh*/ 25574fa086b9SLeo (Sunpeng) Li cfg->v_refresh = stream->timing.pix_clk_khz * 1000; 25584fa086b9SLeo (Sunpeng) Li cfg->v_refresh /= stream->timing.h_total; 25594fa086b9SLeo (Sunpeng) Li cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) 25604fa086b9SLeo (Sunpeng) Li / stream->timing.v_total; 2561cf437593SDmytro Laktyushkin } 2562cf437593SDmytro Laktyushkin 2563cf437593SDmytro Laktyushkin pp_display_cfg->display_count = num_cfgs; 2564cf437593SDmytro Laktyushkin } 2565cf437593SDmytro Laktyushkin 2566608ac7bbSJerry Zuo uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) 2567cf437593SDmytro Laktyushkin { 2568cf437593SDmytro Laktyushkin uint8_t j; 2569cf437593SDmytro Laktyushkin uint32_t min_vertical_blank_time = -1; 2570cf437593SDmytro Laktyushkin 2571cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 25720971c40eSHarry Wentland struct dc_stream_state *stream = context->streams[j]; 2573cf437593SDmytro Laktyushkin uint32_t vertical_blank_in_pixels = 0; 2574cf437593SDmytro Laktyushkin uint32_t vertical_blank_time = 0; 2575cf437593SDmytro Laktyushkin 2576cf437593SDmytro Laktyushkin vertical_blank_in_pixels = stream->timing.h_total * 2577cf437593SDmytro Laktyushkin (stream->timing.v_total 2578cf437593SDmytro Laktyushkin - stream->timing.v_addressable); 2579cf437593SDmytro Laktyushkin 2580cf437593SDmytro Laktyushkin vertical_blank_time = vertical_blank_in_pixels 2581cf437593SDmytro Laktyushkin * 1000 / stream->timing.pix_clk_khz; 2582cf437593SDmytro Laktyushkin 2583cf437593SDmytro Laktyushkin if (min_vertical_blank_time > vertical_blank_time) 2584cf437593SDmytro Laktyushkin min_vertical_blank_time = vertical_blank_time; 2585cf437593SDmytro Laktyushkin } 2586cf437593SDmytro Laktyushkin 2587cf437593SDmytro Laktyushkin return min_vertical_blank_time; 2588cf437593SDmytro Laktyushkin } 2589cf437593SDmytro Laktyushkin 2590cf437593SDmytro Laktyushkin static int determine_sclk_from_bounding_box( 2591fb3466a4SBhawanpreet Lakha const struct dc *dc, 2592cf437593SDmytro Laktyushkin int required_sclk) 25934562236bSHarry Wentland { 25944562236bSHarry Wentland int i; 25954562236bSHarry Wentland 2596cf437593SDmytro Laktyushkin /* 2597cf437593SDmytro Laktyushkin * Some asics do not give us sclk levels, so we just report the actual 2598cf437593SDmytro Laktyushkin * required sclk 2599cf437593SDmytro Laktyushkin */ 2600cf437593SDmytro Laktyushkin if (dc->sclk_lvls.num_levels == 0) 2601cf437593SDmytro Laktyushkin return required_sclk; 26024562236bSHarry Wentland 2603cf437593SDmytro Laktyushkin for (i = 0; i < dc->sclk_lvls.num_levels; i++) { 2604cf437593SDmytro Laktyushkin if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) 2605cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[i]; 2606cf437593SDmytro Laktyushkin } 2607cf437593SDmytro Laktyushkin /* 2608cf437593SDmytro Laktyushkin * even maximum level could not satisfy requirement, this 2609cf437593SDmytro Laktyushkin * is unexpected at this stage, should have been caught at 2610cf437593SDmytro Laktyushkin * validation time 2611cf437593SDmytro Laktyushkin */ 2612cf437593SDmytro Laktyushkin ASSERT(0); 2613cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; 26144562236bSHarry Wentland } 26154562236bSHarry Wentland 2616cf437593SDmytro Laktyushkin static void pplib_apply_display_requirements( 2617fb3466a4SBhawanpreet Lakha struct dc *dc, 2618608ac7bbSJerry Zuo struct dc_state *context) 2619cf437593SDmytro Laktyushkin { 2620cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; 2621cf437593SDmytro Laktyushkin 2622cf437593SDmytro Laktyushkin pp_display_cfg->all_displays_in_sync = 26239037d802SDmytro Laktyushkin context->bw.dce.all_displays_in_sync; 2624cf437593SDmytro Laktyushkin pp_display_cfg->nb_pstate_switch_disable = 26259037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_enable == false; 2626cf437593SDmytro Laktyushkin pp_display_cfg->cpu_cc6_disable = 26279037d802SDmytro Laktyushkin context->bw.dce.cpuc_state_change_enable == false; 2628cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_disable = 26299037d802SDmytro Laktyushkin context->bw.dce.cpup_state_change_enable == false; 2630cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_separation_time = 26319037d802SDmytro Laktyushkin context->bw.dce.blackout_recovery_time_us; 2632cf437593SDmytro Laktyushkin 26339037d802SDmytro Laktyushkin pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz 2634cf437593SDmytro Laktyushkin / MEMORY_TYPE_MULTIPLIER; 2635cf437593SDmytro Laktyushkin 2636cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( 2637cf437593SDmytro Laktyushkin dc, 26389037d802SDmytro Laktyushkin context->bw.dce.sclk_khz); 2639cf437593SDmytro Laktyushkin 2640cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_deep_sleep_khz 26419037d802SDmytro Laktyushkin = context->bw.dce.sclk_deep_sleep_khz; 2642cf437593SDmytro Laktyushkin 2643cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_us = 264428f72454SJordan Lazare dce110_get_min_vblank_time_us(context); 2645cf437593SDmytro Laktyushkin /* TODO: dce11.2*/ 2646cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; 2647cf437593SDmytro Laktyushkin 26489037d802SDmytro Laktyushkin pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz; 2649cf437593SDmytro Laktyushkin 265028f72454SJordan Lazare dce110_fill_display_configs(context, pp_display_cfg); 2651cf437593SDmytro Laktyushkin 2652cf437593SDmytro Laktyushkin /* TODO: is this still applicable?*/ 2653cf437593SDmytro Laktyushkin if (pp_display_cfg->display_count == 1) { 2654cf437593SDmytro Laktyushkin const struct dc_crtc_timing *timing = 26554fa086b9SLeo (Sunpeng) Li &context->streams[0]->timing; 2656cf437593SDmytro Laktyushkin 2657cf437593SDmytro Laktyushkin pp_display_cfg->crtc_index = 2658cf437593SDmytro Laktyushkin pp_display_cfg->disp_configs[0].pipe_idx; 2659cf437593SDmytro Laktyushkin pp_display_cfg->line_time_in_us = timing->h_total * 1000 2660cf437593SDmytro Laktyushkin / timing->pix_clk_khz; 2661cf437593SDmytro Laktyushkin } 2662cf437593SDmytro Laktyushkin 2663cf437593SDmytro Laktyushkin if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( 2664cf437593SDmytro Laktyushkin struct dm_pp_display_configuration)) != 0) 2665cf437593SDmytro Laktyushkin dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); 2666cf437593SDmytro Laktyushkin 2667cf437593SDmytro Laktyushkin dc->prev_display_config = *pp_display_cfg; 2668cf437593SDmytro Laktyushkin } 2669cf437593SDmytro Laktyushkin 2670cf437593SDmytro Laktyushkin static void dce110_set_bandwidth( 2671fb3466a4SBhawanpreet Lakha struct dc *dc, 2672608ac7bbSJerry Zuo struct dc_state *context, 2673cf437593SDmytro Laktyushkin bool decrease_allowed) 2674cf437593SDmytro Laktyushkin { 26752180e7ccSDmytro Laktyushkin dce110_set_displaymarks(dc, context); 2676cf437593SDmytro Laktyushkin 2677608ac7bbSJerry Zuo if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { 2678a2b8659dSTony Cheng dc->res_pool->display_clock->funcs->set_clock( 2679a2b8659dSTony Cheng dc->res_pool->display_clock, 26809037d802SDmytro Laktyushkin context->bw.dce.dispclk_khz * 115 / 100); 2681608ac7bbSJerry Zuo dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; 2682cf437593SDmytro Laktyushkin } 2683cf437593SDmytro Laktyushkin 2684cf437593SDmytro Laktyushkin pplib_apply_display_requirements(dc, context); 26854562236bSHarry Wentland } 26864562236bSHarry Wentland 26874562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 2688fb3466a4SBhawanpreet Lakha struct dc *dc, struct pipe_ctx *pipe_ctx) 26894562236bSHarry Wentland { 269086a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 26914562236bSHarry Wentland struct pipe_ctx *old_pipe = NULL; 26923be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 26934562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 26944562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 26954562236bSHarry Wentland unsigned int i; 26964562236bSHarry Wentland 26974562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 26984562236bSHarry Wentland 2699608ac7bbSJerry Zuo if (dc->current_state) 2700608ac7bbSJerry Zuo old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 27014562236bSHarry Wentland 27024562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 27034562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 27044562236bSHarry Wentland 2705e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 27064562236bSHarry Wentland 27074562236bSHarry Wentland set_default_colors(pipe_ctx); 27084fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 27094562236bSHarry Wentland == true) { 27104562236bSHarry Wentland tbl_entry.color_space = 27114fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 27124562236bSHarry Wentland 27134562236bSHarry Wentland for (i = 0; i < 12; i++) 27144562236bSHarry Wentland tbl_entry.regval[i] = 27154fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 27164562236bSHarry Wentland 271786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 271886a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 27194562236bSHarry Wentland } 27204562236bSHarry Wentland 27214fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 27224562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2723146a9f63SKrunoslav Kovac 2724146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2725146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2726146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 27274562236bSHarry Wentland } 27284562236bSHarry Wentland 272986a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 27304562236bSHarry Wentland 27316702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2732c1473558SAndrey Grodzovsky 27334562236bSHarry Wentland program_scaler(dc, pipe_ctx); 27344562236bSHarry Wentland 27353eab7916SShirish S #if defined(CONFIG_DRM_AMD_DC_FBC) 2736e008b0bcSRoman Li if (dc->fbc_compressor && old_pipe->stream) { 2737e008b0bcSRoman Li if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 2738e008b0bcSRoman Li dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2739e008b0bcSRoman Li else 2740e008b0bcSRoman Li enable_fbc(dc, dc->current_state); 2741e008b0bcSRoman Li } 2742e008b0bcSRoman Li #endif 2743e008b0bcSRoman Li 27444562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 27454562236bSHarry Wentland mi, 27463be5262eSHarry Wentland plane_state->format, 27473be5262eSHarry Wentland &plane_state->tiling_info, 27483be5262eSHarry Wentland &plane_state->plane_size, 27493be5262eSHarry Wentland plane_state->rotation, 2750624d7c47SYongqiang Sun NULL, 27514b28b76bSDmytro Laktyushkin false); 27524b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 27533be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 27544562236bSHarry Wentland 2755fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 27564562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 275786a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 27583be5262eSHarry Wentland plane_state->format, 27593be5262eSHarry Wentland &plane_state->tiling_info, 27603be5262eSHarry Wentland plane_state->rotation); 27614562236bSHarry Wentland 2762067c878aSYongqiang Sun /* Moved programming gamma from dc to hwss */ 2763405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update || 2764405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2765405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.gamma_change) 2766a6114e85SHarry Wentland dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); 2767405c50a0SAndrew Jiang 2768405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update) 2769a6114e85SHarry Wentland dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); 2770067c878aSYongqiang Sun 27714562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 27724562236bSHarry Wentland "Pipe:%d 0x%x: addr hi:0x%x, " 27734562236bSHarry Wentland "addr low:0x%x, " 27744562236bSHarry Wentland "src: %d, %d, %d," 27754562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 27764562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 27774562236bSHarry Wentland pipe_ctx->pipe_idx, 27783be5262eSHarry Wentland pipe_ctx->plane_state, 27793be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.high_part, 27803be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.low_part, 27813be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.x, 27823be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.y, 27833be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.width, 27843be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.height, 27853be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.x, 27863be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.y, 27873be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.width, 27883be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.height, 27893be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.x, 27903be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.y, 27913be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.width, 27923be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.height); 27934562236bSHarry Wentland 27944562236bSHarry Wentland dm_logger_write(dc->ctx->logger, LOG_SURFACE, 27954562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 27964562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 27974562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 27984562236bSHarry Wentland pipe_ctx->pipe_idx, 27996702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.width, 28006702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.height, 28016702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.x, 28026702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.y, 28036702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.width, 28046702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.height, 28056702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.x, 28066702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.y); 28074562236bSHarry Wentland } 28084562236bSHarry Wentland 28094562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 2810fb3466a4SBhawanpreet Lakha struct dc *dc, 28113e9ad616SEric Yang const struct dc_stream_state *stream, 28123e9ad616SEric Yang int num_planes, 2813608ac7bbSJerry Zuo struct dc_state *context) 28144562236bSHarry Wentland { 28152194e3aeSRoman Li int i; 28164562236bSHarry Wentland 28173e9ad616SEric Yang if (num_planes == 0) 28184562236bSHarry Wentland return; 28194562236bSHarry Wentland 28203e9ad616SEric Yang for (i = 0; i < dc->res_pool->pipe_count; i++) { 28213dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 28223dc780ecSYongqiang Sun struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 28233dc780ecSYongqiang Sun 28242194e3aeSRoman Li if (stream == pipe_ctx->stream) { 28253dc780ecSYongqiang Sun if (!pipe_ctx->top_pipe && 28263dc780ecSYongqiang Sun (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) 28273dc780ecSYongqiang Sun dc->hwss.pipe_control_lock(dc, pipe_ctx, true); 28283e9ad616SEric Yang } 28293e9ad616SEric Yang } 28303e9ad616SEric Yang 2831a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 28324562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 28334562236bSHarry Wentland 2834a2607aefSHarry Wentland if (pipe_ctx->stream != stream) 28354562236bSHarry Wentland continue; 28364562236bSHarry Wentland 28373b21b6d2SJerry Zuo /* Need to allocate mem before program front end for Fiji */ 28383b21b6d2SJerry Zuo pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 28393b21b6d2SJerry Zuo pipe_ctx->plane_res.mi, 28403b21b6d2SJerry Zuo pipe_ctx->stream->timing.h_total, 28413b21b6d2SJerry Zuo pipe_ctx->stream->timing.v_total, 28423b21b6d2SJerry Zuo pipe_ctx->stream->timing.pix_clk_khz, 28433b21b6d2SJerry Zuo context->stream_count); 28443b21b6d2SJerry Zuo 28454562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 28464f804817SYongqiang Sun 28474f804817SYongqiang Sun dc->hwss.update_plane_addr(dc, pipe_ctx); 28484f804817SYongqiang Sun 2849b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 28504562236bSHarry Wentland 28514562236bSHarry Wentland } 28523dc780ecSYongqiang Sun 28533dc780ecSYongqiang Sun for (i = 0; i < dc->res_pool->pipe_count; i++) { 28543dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 28553dc780ecSYongqiang Sun struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 28563dc780ecSYongqiang Sun 28573dc780ecSYongqiang Sun if ((stream == pipe_ctx->stream) && 28583dc780ecSYongqiang Sun (!pipe_ctx->top_pipe) && 28593dc780ecSYongqiang Sun (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) 28603dc780ecSYongqiang Sun dc->hwss.pipe_control_lock(dc, pipe_ctx, false); 28613dc780ecSYongqiang Sun } 28624562236bSHarry Wentland } 28634562236bSHarry Wentland 2864e6c258cbSYongqiang Sun static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 28654562236bSHarry Wentland { 2866bc373a89SRoman Li int fe_idx = pipe_ctx->plane_res.mi ? 2867bc373a89SRoman Li pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2868e6c258cbSYongqiang Sun 28697950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 2870608ac7bbSJerry Zuo if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 28714562236bSHarry Wentland return; 28724562236bSHarry Wentland 28734562236bSHarry Wentland dc->hwss.enable_display_power_gating( 2874cfe4645eSDmytro Laktyushkin dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2875cfe4645eSDmytro Laktyushkin 2876cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2877cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]); 28784562236bSHarry Wentland } 28794562236bSHarry Wentland 28806be425f3SEric Yang static void dce110_wait_for_mpcc_disconnect( 2881fb3466a4SBhawanpreet Lakha struct dc *dc, 28826be425f3SEric Yang struct resource_pool *res_pool, 28836be425f3SEric Yang struct pipe_ctx *pipe_ctx) 2884b6762f0cSEric Yang { 2885b6762f0cSEric Yang /* do nothing*/ 2886b6762f0cSEric Yang } 2887b6762f0cSEric Yang 2888bdf9a1a0SYue Hin Lau static void program_csc_matrix(struct pipe_ctx *pipe_ctx, 2889bdf9a1a0SYue Hin Lau enum dc_color_space colorspace, 2890bdf9a1a0SYue Hin Lau uint16_t *matrix) 2891bdf9a1a0SYue Hin Lau { 2892bdf9a1a0SYue Hin Lau int i; 2893bdf9a1a0SYue Hin Lau struct out_csc_color_matrix tbl_entry; 2894bdf9a1a0SYue Hin Lau 2895bdf9a1a0SYue Hin Lau if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 2896bdf9a1a0SYue Hin Lau == true) { 2897bdf9a1a0SYue Hin Lau enum dc_color_space color_space = 2898bdf9a1a0SYue Hin Lau pipe_ctx->stream->output_color_space; 2899bdf9a1a0SYue Hin Lau 2900bdf9a1a0SYue Hin Lau //uint16_t matrix[12]; 2901bdf9a1a0SYue Hin Lau for (i = 0; i < 12; i++) 2902bdf9a1a0SYue Hin Lau tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 2903bdf9a1a0SYue Hin Lau 2904bdf9a1a0SYue Hin Lau tbl_entry.color_space = color_space; 2905bdf9a1a0SYue Hin Lau //tbl_entry.regval = matrix; 290686a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry); 2907bdf9a1a0SYue Hin Lau } 2908bdf9a1a0SYue Hin Lau } 2909bdf9a1a0SYue Hin Lau 29106bf52028SHersen Wu static void ready_shared_resources(struct dc *dc, struct dc_state *context) {} 291141f97c07SHersen Wu 291241f97c07SHersen Wu static void optimize_shared_resources(struct dc *dc) {} 291341f97c07SHersen Wu 29144562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 29151bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 2916bdf9a1a0SYue Hin Lau .program_csc_matrix = program_csc_matrix, 29174562236bSHarry Wentland .init_hw = init_hw, 29184562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 29194562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 29204562236bSHarry Wentland .set_plane_config = set_plane_config, 29214562236bSHarry Wentland .update_plane_addr = update_plane_addr, 29224562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 2923d7194cf6SAric Cyr .set_input_transfer_func = dce110_set_input_transfer_func, 292490e508baSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 29254562236bSHarry Wentland .power_down = dce110_power_down, 29264562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 29274562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 2928fa2123dbSMikita Lipski .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 29294562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 29304562236bSHarry Wentland .enable_stream = dce110_enable_stream, 29314562236bSHarry Wentland .disable_stream = dce110_disable_stream, 29324562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 293341b49742SCharlene Liu .blank_stream = dce110_blank_stream, 29344562236bSHarry Wentland .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 29354562236bSHarry Wentland .enable_display_power_gating = dce110_enable_display_power_gating, 29367f914a62SYongqiang Sun .disable_plane = dce110_power_down_fe, 29374562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 29384562236bSHarry Wentland .set_bandwidth = dce110_set_bandwidth, 29394562236bSHarry Wentland .set_drr = set_drr, 294072ada5f7SEric Cook .get_position = get_position, 29414562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 294254e8695eSDmytro Laktyushkin .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 29434b5e7d62SHersen Wu .prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg, 294415e17335SCharlene Liu .setup_stereo = NULL, 294515e17335SCharlene Liu .set_avmute = dce110_set_avmute, 294641f97c07SHersen Wu .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 294741f97c07SHersen Wu .ready_shared_resources = ready_shared_resources, 294841f97c07SHersen Wu .optimize_shared_resources = optimize_shared_resources, 2949631aaa0aSHersen Wu .pplib_apply_display_requirements = pplib_apply_display_requirements, 295087401969SAndrew Jiang .edp_backlight_control = hwss_edp_backlight_control, 295187401969SAndrew Jiang .edp_power_control = hwss_edp_power_control, 2952904623eeSYongqiang Sun .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, 29534562236bSHarry Wentland }; 29544562236bSHarry Wentland 2955c13b408bSDave Airlie void dce110_hw_sequencer_construct(struct dc *dc) 29564562236bSHarry Wentland { 29574562236bSHarry Wentland dc->hwss = dce110_funcs; 29584562236bSHarry Wentland } 29594562236bSHarry Wentland 2960