14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland #include "dm_services.h" 264562236bSHarry Wentland #include "dc.h" 274562236bSHarry Wentland #include "dc_bios_types.h" 284562236bSHarry Wentland #include "core_types.h" 294562236bSHarry Wentland #include "core_status.h" 304562236bSHarry Wentland #include "resource.h" 314562236bSHarry Wentland #include "dm_helpers.h" 324562236bSHarry Wentland #include "dce110_hw_sequencer.h" 334562236bSHarry Wentland #include "dce110_timing_generator.h" 3498489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 3587401969SAndrew Jiang #include "gpio_service_interface.h" 364562236bSHarry Wentland 371663ae1cSBhawanpreet Lakha #include "dce110_compressor.h" 381663ae1cSBhawanpreet Lakha 394562236bSHarry Wentland #include "bios/bios_parser_helper.h" 404562236bSHarry Wentland #include "timing_generator.h" 414562236bSHarry Wentland #include "mem_input.h" 424562236bSHarry Wentland #include "opp.h" 434562236bSHarry Wentland #include "ipp.h" 444562236bSHarry Wentland #include "transform.h" 454562236bSHarry Wentland #include "stream_encoder.h" 464562236bSHarry Wentland #include "link_encoder.h" 4787401969SAndrew Jiang #include "link_hwss.h" 484562236bSHarry Wentland #include "clock_source.h" 495e7773a2SAnthony Koo #include "abm.h" 504562236bSHarry Wentland #include "audio.h" 5108b16886SZeyu Fan #include "reg_helper.h" 524562236bSHarry Wentland 534562236bSHarry Wentland /* include DCE11 register header files */ 544562236bSHarry Wentland #include "dce/dce_11_0_d.h" 554562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 56e266fdf6SVitaly Prosyak #include "custom_float.h" 574562236bSHarry Wentland 584cac1e6dSYongqiang Sun #include "atomfirmware.h" 594cac1e6dSYongqiang Sun 6087401969SAndrew Jiang /* 6187401969SAndrew Jiang * All values are in milliseconds; 6287401969SAndrew Jiang * For eDP, after power-up/power/down, 6387401969SAndrew Jiang * 300/500 msec max. delay from LCDVCC to black video generation 6487401969SAndrew Jiang */ 6587401969SAndrew Jiang #define PANEL_POWER_UP_TIMEOUT 300 6687401969SAndrew Jiang #define PANEL_POWER_DOWN_TIMEOUT 500 6787401969SAndrew Jiang #define HPD_CHECK_INTERVAL 10 6887401969SAndrew Jiang 695eefbc40SYue Hin Lau #define CTX \ 705eefbc40SYue Hin Lau hws->ctx 715d4b05ddSBhawanpreet Lakha 725d4b05ddSBhawanpreet Lakha #define DC_LOGGER_INIT() 735d4b05ddSBhawanpreet Lakha 745eefbc40SYue Hin Lau #define REG(reg)\ 755eefbc40SYue Hin Lau hws->regs->reg 765eefbc40SYue Hin Lau 775eefbc40SYue Hin Lau #undef FN 785eefbc40SYue Hin Lau #define FN(reg_name, field_name) \ 795eefbc40SYue Hin Lau hws->shifts->field_name, hws->masks->field_name 805eefbc40SYue Hin Lau 814562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 824562236bSHarry Wentland uint32_t crtc; 834562236bSHarry Wentland }; 844562236bSHarry Wentland 854562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 864562236bSHarry Wentland { 874562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 884562236bSHarry Wentland }, 894562236bSHarry Wentland { 904562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 914562236bSHarry Wentland }, 924562236bSHarry Wentland { 934562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 944562236bSHarry Wentland }, 954562236bSHarry Wentland { 964562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 974562236bSHarry Wentland } 984562236bSHarry Wentland }; 994562236bSHarry Wentland 1004562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 1014562236bSHarry Wentland (reg + reg_offsets[id].blnd) 1024562236bSHarry Wentland 1034562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 1044562236bSHarry Wentland (reg + reg_offsets[id].crtc) 1054562236bSHarry Wentland 1064562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 1074562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 1084562236bSHarry Wentland 1094562236bSHarry Wentland /******************************************************************************* 1104562236bSHarry Wentland * Private definitions 1114562236bSHarry Wentland ******************************************************************************/ 1124562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 1134562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 1144562236bSHarry Wentland { 1154562236bSHarry Wentland uint32_t addr; 1164562236bSHarry Wentland uint32_t value = 0; 1174562236bSHarry Wentland uint32_t chunk_int = 0; 1184562236bSHarry Wentland uint32_t chunk_mul = 0; 1194562236bSHarry Wentland 1204562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 1214562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1224562236bSHarry Wentland 1234562236bSHarry Wentland set_reg_field_value( 1244562236bSHarry Wentland value, 1254562236bSHarry Wentland 0, 1264562236bSHarry Wentland DVMM_PTE_CONTROL, 1274562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1284562236bSHarry Wentland 1294562236bSHarry Wentland set_reg_field_value( 1304562236bSHarry Wentland value, 1314562236bSHarry Wentland 1, 1324562236bSHarry Wentland DVMM_PTE_CONTROL, 1334562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1344562236bSHarry Wentland 1354562236bSHarry Wentland set_reg_field_value( 1364562236bSHarry Wentland value, 1374562236bSHarry Wentland 1, 1384562236bSHarry Wentland DVMM_PTE_CONTROL, 1394562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1404562236bSHarry Wentland 1414562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1424562236bSHarry Wentland 1434562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1444562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1454562236bSHarry Wentland 1464562236bSHarry Wentland chunk_int = get_reg_field_value( 1474562236bSHarry Wentland value, 1484562236bSHarry Wentland DVMM_PTE_REQ, 1494562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1504562236bSHarry Wentland 1514562236bSHarry Wentland chunk_mul = get_reg_field_value( 1524562236bSHarry Wentland value, 1534562236bSHarry Wentland DVMM_PTE_REQ, 1544562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1554562236bSHarry Wentland 1564562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1574562236bSHarry Wentland 1584562236bSHarry Wentland set_reg_field_value( 1594562236bSHarry Wentland value, 1604562236bSHarry Wentland 255, 1614562236bSHarry Wentland DVMM_PTE_REQ, 1624562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1634562236bSHarry Wentland 1644562236bSHarry Wentland set_reg_field_value( 1654562236bSHarry Wentland value, 1664562236bSHarry Wentland 4, 1674562236bSHarry Wentland DVMM_PTE_REQ, 1684562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1694562236bSHarry Wentland 1704562236bSHarry Wentland set_reg_field_value( 1714562236bSHarry Wentland value, 1724562236bSHarry Wentland 4, 1734562236bSHarry Wentland DVMM_PTE_REQ, 1744562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1754562236bSHarry Wentland 1764562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1774562236bSHarry Wentland } 1784562236bSHarry Wentland } 1794562236bSHarry Wentland /**************************************************************************/ 1804562236bSHarry Wentland 1814562236bSHarry Wentland static void enable_display_pipe_clock_gating( 1824562236bSHarry Wentland struct dc_context *ctx, 1834562236bSHarry Wentland bool clock_gating) 1844562236bSHarry Wentland { 1854562236bSHarry Wentland /*TODO*/ 1864562236bSHarry Wentland } 1874562236bSHarry Wentland 1884562236bSHarry Wentland static bool dce110_enable_display_power_gating( 189fb3466a4SBhawanpreet Lakha struct dc *dc, 1904562236bSHarry Wentland uint8_t controller_id, 1914562236bSHarry Wentland struct dc_bios *dcb, 1924562236bSHarry Wentland enum pipe_gating_control power_gating) 1934562236bSHarry Wentland { 1944562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 1954562236bSHarry Wentland enum bp_pipe_control_action cntl; 1964562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 1974562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 1984562236bSHarry Wentland 1994562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 2004562236bSHarry Wentland return true; 2014562236bSHarry Wentland 2024562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 2034562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 2044562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 2054562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 2064562236bSHarry Wentland else 2074562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 2084562236bSHarry Wentland 2094562236bSHarry Wentland if (controller_id == underlay_idx) 2104562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 2114562236bSHarry Wentland 2124562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 2134562236bSHarry Wentland 2144562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 2154562236bSHarry Wentland dcb, controller_id + 1, cntl); 2164562236bSHarry Wentland 2174562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 2184562236bSHarry Wentland * by default when command table is called 2194562236bSHarry Wentland * 2204562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 2214562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 2224562236bSHarry Wentland * than 3. 2234562236bSHarry Wentland */ 2244562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 2254562236bSHarry Wentland dm_write_reg(ctx, 2264562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2274562236bSHarry Wentland 0); 2284562236bSHarry Wentland } 2294562236bSHarry Wentland 2304562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2314562236bSHarry Wentland dce110_init_pte(ctx); 2324562236bSHarry Wentland 2334562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2344562236bSHarry Wentland return true; 2354562236bSHarry Wentland else 2364562236bSHarry Wentland return false; 2374562236bSHarry Wentland } 2384562236bSHarry Wentland 2394562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2403be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2414562236bSHarry Wentland { 2424562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2434562236bSHarry Wentland 2443be5262eSHarry Wentland switch (plane_state->format) { 2454562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2468693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2474562236bSHarry Wentland prescale_params->scale = 0x2020; 2484562236bSHarry Wentland break; 2494562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2504562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2514562236bSHarry Wentland prescale_params->scale = 0x2008; 2524562236bSHarry Wentland break; 2534562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2544562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2554562236bSHarry Wentland prescale_params->scale = 0x2000; 2564562236bSHarry Wentland break; 2574562236bSHarry Wentland default: 2584562236bSHarry Wentland ASSERT(false); 259d7194cf6SAric Cyr break; 2604562236bSHarry Wentland } 2614562236bSHarry Wentland } 2624562236bSHarry Wentland 263a6114e85SHarry Wentland static bool 264a6114e85SHarry Wentland dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, 2653be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2664562236bSHarry Wentland { 26786a66c4eSHarry Wentland struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2687b0c470fSLeo (Sunpeng) Li const struct dc_transfer_func *tf = NULL; 26990e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 27090e508baSAnthony Koo bool result = true; 27190e508baSAnthony Koo 27290e508baSAnthony Koo if (ipp == NULL) 27390e508baSAnthony Koo return false; 27490e508baSAnthony Koo 2753be5262eSHarry Wentland if (plane_state->in_transfer_func) 2763be5262eSHarry Wentland tf = plane_state->in_transfer_func; 27790e508baSAnthony Koo 2783be5262eSHarry Wentland build_prescale_params(&prescale_params, plane_state); 27990e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 28090e508baSAnthony Koo 28184ffa801SLeo (Sunpeng) Li if (plane_state->gamma_correction && 28284ffa801SLeo (Sunpeng) Li !plane_state->gamma_correction->is_identity && 28384ffa801SLeo (Sunpeng) Li dce_use_lut(plane_state->format)) 2843be5262eSHarry Wentland ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 285d7194cf6SAric Cyr 28690e508baSAnthony Koo if (tf == NULL) { 28790e508baSAnthony Koo /* Default case if no input transfer function specified */ 288a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 2897b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_PREDEFINED) { 2907b0c470fSLeo (Sunpeng) Li switch (tf->tf) { 29190e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 292a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 29390e508baSAnthony Koo break; 29490e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 295a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 29690e508baSAnthony Koo break; 29790e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 298a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 29990e508baSAnthony Koo break; 30090e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 30190e508baSAnthony Koo default: 30290e508baSAnthony Koo result = false; 303d7194cf6SAric Cyr break; 30490e508baSAnthony Koo } 3057b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_BYPASS) { 30670063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 30790e508baSAnthony Koo } else { 30890e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 30990e508baSAnthony Koo result = false; 31090e508baSAnthony Koo } 31190e508baSAnthony Koo 31290e508baSAnthony Koo return result; 31390e508baSAnthony Koo } 31490e508baSAnthony Koo 315bd1be8e8SHarry Wentland static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 316fcd2f4bfSAmy Zhang struct curve_points *arr_points, 317fcd2f4bfSAmy Zhang uint32_t hw_points_num) 318fcd2f4bfSAmy Zhang { 319fcd2f4bfSAmy Zhang struct custom_float_format fmt; 320fcd2f4bfSAmy Zhang 321fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 322fcd2f4bfSAmy Zhang 323fcd2f4bfSAmy Zhang uint32_t i = 0; 324fcd2f4bfSAmy Zhang 325fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 326fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 327fcd2f4bfSAmy Zhang fmt.sign = true; 328fcd2f4bfSAmy Zhang 329bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 330fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 331fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 332fcd2f4bfSAmy Zhang return false; 333fcd2f4bfSAmy Zhang } 334fcd2f4bfSAmy Zhang 335bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 336fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 337fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 338fcd2f4bfSAmy Zhang return false; 339fcd2f4bfSAmy Zhang } 340fcd2f4bfSAmy Zhang 341bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 342fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 343fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 344fcd2f4bfSAmy Zhang return false; 345fcd2f4bfSAmy Zhang } 346fcd2f4bfSAmy Zhang 347fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 348fcd2f4bfSAmy Zhang fmt.sign = false; 349fcd2f4bfSAmy Zhang 350bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 351fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 352fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 353fcd2f4bfSAmy Zhang return false; 354fcd2f4bfSAmy Zhang } 355fcd2f4bfSAmy Zhang 356bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 357fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 358fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 359fcd2f4bfSAmy Zhang return false; 360fcd2f4bfSAmy Zhang } 361fcd2f4bfSAmy Zhang 3624d06ccd0SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 3634d06ccd0SHarry Wentland &arr_points[1].custom_float_slope)) { 364fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 365fcd2f4bfSAmy Zhang return false; 366fcd2f4bfSAmy Zhang } 367fcd2f4bfSAmy Zhang 368fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 369fcd2f4bfSAmy Zhang fmt.sign = true; 370fcd2f4bfSAmy Zhang 371fcd2f4bfSAmy Zhang while (i != hw_points_num) { 372bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->red, &fmt, 373fcd2f4bfSAmy Zhang &rgb->red_reg)) { 374fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 375fcd2f4bfSAmy Zhang return false; 376fcd2f4bfSAmy Zhang } 377fcd2f4bfSAmy Zhang 378bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->green, &fmt, 379fcd2f4bfSAmy Zhang &rgb->green_reg)) { 380fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 381fcd2f4bfSAmy Zhang return false; 382fcd2f4bfSAmy Zhang } 383fcd2f4bfSAmy Zhang 384bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->blue, &fmt, 385fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 386fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 387fcd2f4bfSAmy Zhang return false; 388fcd2f4bfSAmy Zhang } 389fcd2f4bfSAmy Zhang 390bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 391fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 392fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 393fcd2f4bfSAmy Zhang return false; 394fcd2f4bfSAmy Zhang } 395fcd2f4bfSAmy Zhang 396bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 397fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 398fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 399fcd2f4bfSAmy Zhang return false; 400fcd2f4bfSAmy Zhang } 401fcd2f4bfSAmy Zhang 402bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 403fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 404fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 405fcd2f4bfSAmy Zhang return false; 406fcd2f4bfSAmy Zhang } 407fcd2f4bfSAmy Zhang 408fcd2f4bfSAmy Zhang ++rgb; 409fcd2f4bfSAmy Zhang ++i; 410fcd2f4bfSAmy Zhang } 411fcd2f4bfSAmy Zhang 412fcd2f4bfSAmy Zhang return true; 413fcd2f4bfSAmy Zhang } 414fcd2f4bfSAmy Zhang 41508616da5SLeo (Sunpeng) Li #define MAX_LOW_POINT 25 4168f8372c7SKrunoslav Kovac #define NUMBER_REGIONS 16 4178f8372c7SKrunoslav Kovac #define NUMBER_SW_SEGMENTS 16 4188f8372c7SKrunoslav Kovac 419b310b081SHarry Wentland static bool 420b310b081SHarry Wentland dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 421b310b081SHarry Wentland struct pwl_params *regamma_params) 422fcd2f4bfSAmy Zhang { 42323ae4f8eSAmy Zhang struct curve_points *arr_points; 42423ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 42523ae4f8eSAmy Zhang struct pwl_result_data *rgb; 42623ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 427fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 428fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 429fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 430fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 431fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 432fcd2f4bfSAmy Zhang 4338f8372c7SKrunoslav Kovac int32_t region_start, region_end; 4348f8372c7SKrunoslav Kovac uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 43523ae4f8eSAmy Zhang 436b310b081SHarry Wentland if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 43723ae4f8eSAmy Zhang return false; 43823ae4f8eSAmy Zhang 43923ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 44023ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 44123ae4f8eSAmy Zhang hw_points = 0; 442fcd2f4bfSAmy Zhang 443fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 444fcd2f4bfSAmy Zhang 445fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 446534db198SAmy Zhang /* 16 segments 447fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 448fcd2f4bfSAmy Zhang */ 44908616da5SLeo (Sunpeng) Li region_start = -11; 45008616da5SLeo (Sunpeng) Li region_end = region_start + NUMBER_REGIONS; 451fcd2f4bfSAmy Zhang 4528f8372c7SKrunoslav Kovac for (i = 0; i < NUMBER_REGIONS; i++) 4538f8372c7SKrunoslav Kovac seg_distr[i] = 4; 454534db198SAmy Zhang 455fcd2f4bfSAmy Zhang } else { 456534db198SAmy Zhang /* 10 segments 457fc6de1c5SLeo (Sunpeng) Li * segment is from 2^-10 to 2^1 458fc6de1c5SLeo (Sunpeng) Li * We include an extra segment for range [2^0, 2^1). This is to 459fc6de1c5SLeo (Sunpeng) Li * ensure that colors with normalized values of 1 don't miss the 460fc6de1c5SLeo (Sunpeng) Li * LUT. 461fcd2f4bfSAmy Zhang */ 4628f8372c7SKrunoslav Kovac region_start = -10; 463fc6de1c5SLeo (Sunpeng) Li region_end = 1; 464534db198SAmy Zhang 4658f8372c7SKrunoslav Kovac seg_distr[0] = 4; 466534db198SAmy Zhang seg_distr[1] = 4; 467534db198SAmy Zhang seg_distr[2] = 4; 468534db198SAmy Zhang seg_distr[3] = 4; 469534db198SAmy Zhang seg_distr[4] = 4; 470534db198SAmy Zhang seg_distr[5] = 4; 471534db198SAmy Zhang seg_distr[6] = 4; 472534db198SAmy Zhang seg_distr[7] = 4; 4738f8372c7SKrunoslav Kovac seg_distr[8] = 4; 4748f8372c7SKrunoslav Kovac seg_distr[9] = 4; 475fc6de1c5SLeo (Sunpeng) Li seg_distr[10] = 0; 476534db198SAmy Zhang seg_distr[11] = -1; 477534db198SAmy Zhang seg_distr[12] = -1; 478534db198SAmy Zhang seg_distr[13] = -1; 479534db198SAmy Zhang seg_distr[14] = -1; 480534db198SAmy Zhang seg_distr[15] = -1; 481fcd2f4bfSAmy Zhang } 482fcd2f4bfSAmy Zhang 483534db198SAmy Zhang for (k = 0; k < 16; k++) { 484534db198SAmy Zhang if (seg_distr[k] != -1) 485534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 486534db198SAmy Zhang } 487534db198SAmy Zhang 488fcd2f4bfSAmy Zhang j = 0; 4898f8372c7SKrunoslav Kovac for (k = 0; k < (region_end - region_start); k++) { 490ec47734aSLeo (Sunpeng) Li increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 4918f8372c7SKrunoslav Kovac start_index = (region_start + k + MAX_LOW_POINT) * 4928f8372c7SKrunoslav Kovac NUMBER_SW_SEGMENTS; 4938f8372c7SKrunoslav Kovac for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 4948f8372c7SKrunoslav Kovac i += increment) { 495534db198SAmy Zhang if (j == hw_points - 1) 496fcd2f4bfSAmy Zhang break; 497fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 498fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 499fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 500fcd2f4bfSAmy Zhang j++; 501fcd2f4bfSAmy Zhang } 502534db198SAmy Zhang } 503534db198SAmy Zhang 504534db198SAmy Zhang /* last point */ 5058f8372c7SKrunoslav Kovac start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 506b310b081SHarry Wentland rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 507b310b081SHarry Wentland rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 508b310b081SHarry Wentland rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 509fcd2f4bfSAmy Zhang 510eb0e5154SDmytro Laktyushkin arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 511eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_start)); 512eb0e5154SDmytro Laktyushkin arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 513eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_end)); 514fcd2f4bfSAmy Zhang 515fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 516fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 517fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 518fcd2f4bfSAmy Zhang 519eb0e5154SDmytro Laktyushkin y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 520fcd2f4bfSAmy Zhang 521fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 522eb0e5154SDmytro Laktyushkin arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 523fcd2f4bfSAmy Zhang arr_points[0].x); 524fcd2f4bfSAmy Zhang 525fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 526fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 527fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 528fcd2f4bfSAmy Zhang 529fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 530fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 531fcd2f4bfSAmy Zhang */ 532eb0e5154SDmytro Laktyushkin y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 533fcd2f4bfSAmy Zhang 534fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 535fcd2f4bfSAmy Zhang 536eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_zero; 537fcd2f4bfSAmy Zhang 538fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 539fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 540fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 541fcd2f4bfSAmy Zhang */ 542eb0e5154SDmytro Laktyushkin const struct fixed31_32 end_value = dc_fixpt_from_int(125); 543fcd2f4bfSAmy Zhang 544eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_div( 545eb0e5154SDmytro Laktyushkin dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 546eb0e5154SDmytro Laktyushkin dc_fixpt_sub(end_value, arr_points[1].x)); 547fcd2f4bfSAmy Zhang } 548fcd2f4bfSAmy Zhang 549fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 550fcd2f4bfSAmy Zhang 551534db198SAmy Zhang i = 1; 552534db198SAmy Zhang for (k = 0; k < 16 && i < 16; k++) { 553534db198SAmy Zhang if (seg_distr[k] != -1) { 554b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 555534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 556b310b081SHarry Wentland regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 557fcd2f4bfSAmy Zhang } 558534db198SAmy Zhang i++; 559534db198SAmy Zhang } 560534db198SAmy Zhang 561534db198SAmy Zhang if (seg_distr[k] != -1) 562b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 563fcd2f4bfSAmy Zhang 56423ae4f8eSAmy Zhang rgb = rgb_resulted; 56523ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 566fcd2f4bfSAmy Zhang 567fcd2f4bfSAmy Zhang i = 1; 568fcd2f4bfSAmy Zhang 569fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 570eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 571fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 572eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 573fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 574eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 575fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 576fcd2f4bfSAmy Zhang 577eb0e5154SDmytro Laktyushkin rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 578eb0e5154SDmytro Laktyushkin rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 579eb0e5154SDmytro Laktyushkin rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 580fcd2f4bfSAmy Zhang 581fcd2f4bfSAmy Zhang ++rgb_plus_1; 582fcd2f4bfSAmy Zhang ++rgb; 583fcd2f4bfSAmy Zhang ++i; 584fcd2f4bfSAmy Zhang } 585fcd2f4bfSAmy Zhang 586fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 587fcd2f4bfSAmy Zhang 588fcd2f4bfSAmy Zhang return true; 589fcd2f4bfSAmy Zhang } 590fcd2f4bfSAmy Zhang 591a6114e85SHarry Wentland static bool 592a6114e85SHarry Wentland dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx, 5930971c40eSHarry Wentland const struct dc_stream_state *stream) 59490e508baSAnthony Koo { 59586a66c4eSHarry Wentland struct transform *xfm = pipe_ctx->plane_res.xfm; 5964562236bSHarry Wentland 5977a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, true); 5987a09f5beSYue Hin Lau xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 5994562236bSHarry Wentland 6004fa086b9SLeo (Sunpeng) Li if (stream->out_transfer_func && 601efd52204SHarry Wentland stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 602efd52204SHarry Wentland stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 6037a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 604efd52204SHarry Wentland } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 605efd52204SHarry Wentland &xfm->regamma_params)) { 6067a09f5beSYue Hin Lau xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 6077a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 6084562236bSHarry Wentland } else { 6097a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 6104562236bSHarry Wentland } 6114562236bSHarry Wentland 6127a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, false); 6134562236bSHarry Wentland 614cc0cb445SLeon Elazar return true; 6154562236bSHarry Wentland } 6164562236bSHarry Wentland 6174562236bSHarry Wentland static enum dc_status bios_parser_crtc_source_select( 6184562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 6194562236bSHarry Wentland { 6204562236bSHarry Wentland struct dc_bios *dcb; 6214562236bSHarry Wentland /* call VBIOS table to set CRTC source for the HW 6224562236bSHarry Wentland * encoder block 6234562236bSHarry Wentland * note: video bios clears all FMT setting here. */ 6244562236bSHarry Wentland struct bp_crtc_source_select crtc_source_select = {0}; 625b73a22d3SHarry Wentland const struct dc_sink *sink = pipe_ctx->stream->sink; 6264562236bSHarry Wentland 6278e9c4c8cSHarry Wentland crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id; 628e07f541fSYongqiang Sun crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1; 6294562236bSHarry Wentland /*TODO: Need to un-hardcode color depth, dp_audio and account for 6304562236bSHarry Wentland * the case where signal and sink signal is different (translator 6314562236bSHarry Wentland * encoder)*/ 6324562236bSHarry Wentland crtc_source_select.signal = pipe_ctx->stream->signal; 6334562236bSHarry Wentland crtc_source_select.enable_dp_audio = false; 6344562236bSHarry Wentland crtc_source_select.sink_signal = pipe_ctx->stream->signal; 6351b7441b0SCharlene Liu 6361b7441b0SCharlene Liu switch (pipe_ctx->stream->timing.display_color_depth) { 6371b7441b0SCharlene Liu case COLOR_DEPTH_666: 6381b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR; 6391b7441b0SCharlene Liu break; 6401b7441b0SCharlene Liu case COLOR_DEPTH_888: 6414562236bSHarry Wentland crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 6421b7441b0SCharlene Liu break; 6431b7441b0SCharlene Liu case COLOR_DEPTH_101010: 6441b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR; 6451b7441b0SCharlene Liu break; 6461b7441b0SCharlene Liu case COLOR_DEPTH_121212: 6471b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR; 6481b7441b0SCharlene Liu break; 6491b7441b0SCharlene Liu default: 6501b7441b0SCharlene Liu BREAK_TO_DEBUGGER(); 6511b7441b0SCharlene Liu crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR; 6521b7441b0SCharlene Liu break; 6531b7441b0SCharlene Liu } 6544562236bSHarry Wentland 6554562236bSHarry Wentland dcb = sink->ctx->dc_bios; 6564562236bSHarry Wentland 6574562236bSHarry Wentland if (BP_RESULT_OK != dcb->funcs->crtc_source_select( 6584562236bSHarry Wentland dcb, 6594562236bSHarry Wentland &crtc_source_select)) { 6604562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 6614562236bSHarry Wentland } 6624562236bSHarry Wentland 6634562236bSHarry Wentland return DC_OK; 6644562236bSHarry Wentland } 6654562236bSHarry Wentland 6664562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6674562236bSHarry Wentland { 6686f0db2dcSKrunoslav Kovac bool is_hdmi; 6696f0db2dcSKrunoslav Kovac bool is_dp; 6706f0db2dcSKrunoslav Kovac 67186e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 67286e2e1beSHersen Wu 6738e9c4c8cSHarry Wentland if (pipe_ctx->stream_res.stream_enc == NULL) 67486e2e1beSHersen Wu return; /* this is not root pipe */ 67586e2e1beSHersen Wu 6766f0db2dcSKrunoslav Kovac is_hdmi = dc_is_hdmi_signal(pipe_ctx->stream->signal); 6776f0db2dcSKrunoslav Kovac is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 6786f0db2dcSKrunoslav Kovac 6796f0db2dcSKrunoslav Kovac if (!is_hdmi && !is_dp) 6806f0db2dcSKrunoslav Kovac return; 6816f0db2dcSKrunoslav Kovac 6826f0db2dcSKrunoslav Kovac if (is_hdmi) 6838e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 6848e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 68596c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6866f0db2dcSKrunoslav Kovac else 6878e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 6888e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 68996c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6904562236bSHarry Wentland } 6914562236bSHarry Wentland 6924562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6934562236bSHarry Wentland { 6944562236bSHarry Wentland enum dc_lane_count lane_count = 695d0778ebfSHarry Wentland pipe_ctx->stream->sink->link->cur_link_settings.lane_count; 6964562236bSHarry Wentland 6974fa086b9SLeo (Sunpeng) Li struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 698d0778ebfSHarry Wentland struct dc_link *link = pipe_ctx->stream->sink->link; 6994562236bSHarry Wentland 700f215a57dSEric Yang 7014562236bSHarry Wentland uint32_t active_total_with_borders; 7024562236bSHarry Wentland uint32_t early_control = 0; 7036b670fa9SHarry Wentland struct timing_generator *tg = pipe_ctx->stream_res.tg; 7044562236bSHarry Wentland 705f215a57dSEric Yang /* For MST, there are multiply stream go to only one link. 706f215a57dSEric Yang * connect DIG back_end to front_end while enable_stream and 707f215a57dSEric Yang * disconnect them during disable_stream 708f215a57dSEric Yang * BY this, it is logic clean to separate stream and link */ 709f215a57dSEric Yang link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 710f215a57dSEric Yang pipe_ctx->stream_res.stream_enc->id, true); 711f215a57dSEric Yang 712f215a57dSEric Yang /* update AVI info frame (HDMI, DP)*/ 713f215a57dSEric Yang /* TODO: FPGA may change to hwss.update_info_frame */ 7144562236bSHarry Wentland dce110_update_info_frame(pipe_ctx); 715f215a57dSEric Yang 7164562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 7174562236bSHarry Wentland active_total_with_borders = 7184562236bSHarry Wentland timing->h_addressable 7194562236bSHarry Wentland + timing->h_border_left 7204562236bSHarry Wentland + timing->h_border_right; 7214562236bSHarry Wentland 7224562236bSHarry Wentland if (lane_count != 0) 7234562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 7244562236bSHarry Wentland 7254562236bSHarry Wentland if (early_control == 0) 7264562236bSHarry Wentland early_control = lane_count; 7274562236bSHarry Wentland 7284562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 7294562236bSHarry Wentland 7304562236bSHarry Wentland /* enable audio only within mode set */ 731afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 7324562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7338e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 7344562236bSHarry Wentland } 7354562236bSHarry Wentland 736f215a57dSEric Yang 737f215a57dSEric Yang 7384562236bSHarry Wentland 7394562236bSHarry Wentland } 7404562236bSHarry Wentland 7415eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 7425eefbc40SYue Hin Lau static bool is_panel_backlight_on(struct dce_hwseq *hws) 7435eefbc40SYue Hin Lau { 7445eefbc40SYue Hin Lau uint32_t value; 7455eefbc40SYue Hin Lau 7465eefbc40SYue Hin Lau REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value); 7475eefbc40SYue Hin Lau 7485eefbc40SYue Hin Lau return value; 7495eefbc40SYue Hin Lau } 7505eefbc40SYue Hin Lau 75187401969SAndrew Jiang static bool is_panel_powered_on(struct dce_hwseq *hws) 75287401969SAndrew Jiang { 753d03f3f63SEric Yang uint32_t pwr_seq_state, dig_on, dig_on_ovrd; 75487401969SAndrew Jiang 755d03f3f63SEric Yang 756d03f3f63SEric Yang REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); 757d03f3f63SEric Yang 758d03f3f63SEric Yang REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd); 759d03f3f63SEric Yang 760d03f3f63SEric Yang return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1); 76187401969SAndrew Jiang } 76287401969SAndrew Jiang 7635eefbc40SYue Hin Lau static enum bp_result link_transmitter_control( 76487401969SAndrew Jiang struct dc_bios *bios, 7655eefbc40SYue Hin Lau struct bp_transmitter_control *cntl) 7665eefbc40SYue Hin Lau { 7675eefbc40SYue Hin Lau enum bp_result result; 7685eefbc40SYue Hin Lau 76987401969SAndrew Jiang result = bios->funcs->transmitter_control(bios, cntl); 7705eefbc40SYue Hin Lau 7715eefbc40SYue Hin Lau return result; 7725eefbc40SYue Hin Lau } 7735eefbc40SYue Hin Lau 77487401969SAndrew Jiang /* 77587401969SAndrew Jiang * @brief 77687401969SAndrew Jiang * eDP only. 77787401969SAndrew Jiang */ 77887401969SAndrew Jiang void hwss_edp_wait_for_hpd_ready( 779069d418fSAndrew Jiang struct dc_link *link, 78087401969SAndrew Jiang bool power_up) 78187401969SAndrew Jiang { 782069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 783069d418fSAndrew Jiang struct graphics_object_id connector = link->link_enc->connector; 78487401969SAndrew Jiang struct gpio *hpd; 78587401969SAndrew Jiang bool edp_hpd_high = false; 78687401969SAndrew Jiang uint32_t time_elapsed = 0; 78787401969SAndrew Jiang uint32_t timeout = power_up ? 78887401969SAndrew Jiang PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 78987401969SAndrew Jiang 79087401969SAndrew Jiang if (dal_graphics_object_id_get_connector_id(connector) 79187401969SAndrew Jiang != CONNECTOR_ID_EDP) { 79287401969SAndrew Jiang BREAK_TO_DEBUGGER(); 79387401969SAndrew Jiang return; 79487401969SAndrew Jiang } 79587401969SAndrew Jiang 79687401969SAndrew Jiang if (!power_up) 79787401969SAndrew Jiang /* 79887401969SAndrew Jiang * From KV, we will not HPD low after turning off VCC - 79987401969SAndrew Jiang * instead, we will check the SW timer in power_up(). 80087401969SAndrew Jiang */ 80187401969SAndrew Jiang return; 80287401969SAndrew Jiang 80387401969SAndrew Jiang /* 80487401969SAndrew Jiang * When we power on/off the eDP panel, 80587401969SAndrew Jiang * we need to wait until SENSE bit is high/low. 80687401969SAndrew Jiang */ 80787401969SAndrew Jiang 80887401969SAndrew Jiang /* obtain HPD */ 80987401969SAndrew Jiang /* TODO what to do with this? */ 81087401969SAndrew Jiang hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 81187401969SAndrew Jiang 81287401969SAndrew Jiang if (!hpd) { 81387401969SAndrew Jiang BREAK_TO_DEBUGGER(); 81487401969SAndrew Jiang return; 81587401969SAndrew Jiang } 81687401969SAndrew Jiang 81787401969SAndrew Jiang dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 81887401969SAndrew Jiang 81987401969SAndrew Jiang /* wait until timeout or panel detected */ 82087401969SAndrew Jiang 82187401969SAndrew Jiang do { 82287401969SAndrew Jiang uint32_t detected = 0; 82387401969SAndrew Jiang 82487401969SAndrew Jiang dal_gpio_get_value(hpd, &detected); 82587401969SAndrew Jiang 82687401969SAndrew Jiang if (!(detected ^ power_up)) { 82787401969SAndrew Jiang edp_hpd_high = true; 82887401969SAndrew Jiang break; 82987401969SAndrew Jiang } 83087401969SAndrew Jiang 83187401969SAndrew Jiang msleep(HPD_CHECK_INTERVAL); 83287401969SAndrew Jiang 83387401969SAndrew Jiang time_elapsed += HPD_CHECK_INTERVAL; 83487401969SAndrew Jiang } while (time_elapsed < timeout); 83587401969SAndrew Jiang 83687401969SAndrew Jiang dal_gpio_close(hpd); 83787401969SAndrew Jiang 83887401969SAndrew Jiang dal_gpio_destroy_irq(&hpd); 83987401969SAndrew Jiang 84087401969SAndrew Jiang if (false == edp_hpd_high) { 8411296423bSBhawanpreet Lakha DC_LOG_ERROR( 84287401969SAndrew Jiang "%s: wait timed out!\n", __func__); 84387401969SAndrew Jiang } 84487401969SAndrew Jiang } 84587401969SAndrew Jiang 84687401969SAndrew Jiang void hwss_edp_power_control( 847069d418fSAndrew Jiang struct dc_link *link, 84887401969SAndrew Jiang bool power_up) 84987401969SAndrew Jiang { 850069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 85187401969SAndrew Jiang struct dce_hwseq *hwseq = ctx->dc->hwseq; 85287401969SAndrew Jiang struct bp_transmitter_control cntl = { 0 }; 85387401969SAndrew Jiang enum bp_result bp_result; 85487401969SAndrew Jiang 85587401969SAndrew Jiang 856069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 85787401969SAndrew Jiang != CONNECTOR_ID_EDP) { 85887401969SAndrew Jiang BREAK_TO_DEBUGGER(); 85987401969SAndrew Jiang return; 86087401969SAndrew Jiang } 86187401969SAndrew Jiang 86287401969SAndrew Jiang if (power_up != is_panel_powered_on(hwseq)) { 86387401969SAndrew Jiang /* Send VBIOS command to prompt eDP panel power */ 86478d5d04dSCharlene Liu if (power_up) { 86578d5d04dSCharlene Liu unsigned long long current_ts = dm_get_timestamp(ctx); 86678d5d04dSCharlene Liu unsigned long long duration_in_ms = 86793ed1814SHugo Hu div64_u64(dm_get_elapse_time_in_ns( 86878d5d04dSCharlene Liu ctx, 86978d5d04dSCharlene Liu current_ts, 87093ed1814SHugo Hu link->link_trace.time_stamp.edp_poweroff), 1000000); 87178d5d04dSCharlene Liu unsigned long long wait_time_ms = 0; 87278d5d04dSCharlene Liu 87378d5d04dSCharlene Liu /* max 500ms from LCDVDD off to on */ 87478d5d04dSCharlene Liu if (link->link_trace.time_stamp.edp_poweroff == 0) 87578d5d04dSCharlene Liu wait_time_ms = 500; 87678d5d04dSCharlene Liu else if (duration_in_ms < 500) 87778d5d04dSCharlene Liu wait_time_ms = 500 - duration_in_ms; 87878d5d04dSCharlene Liu 87978d5d04dSCharlene Liu if (wait_time_ms) { 88078d5d04dSCharlene Liu msleep(wait_time_ms); 88178d5d04dSCharlene Liu dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 88278d5d04dSCharlene Liu __func__, wait_time_ms); 88378d5d04dSCharlene Liu } 88478d5d04dSCharlene Liu 88578d5d04dSCharlene Liu } 88687401969SAndrew Jiang 8871296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 88887401969SAndrew Jiang "%s: Panel Power action: %s\n", 88987401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 89087401969SAndrew Jiang 89187401969SAndrew Jiang cntl.action = power_up ? 89287401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_ON : 89387401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_OFF; 894069d418fSAndrew Jiang cntl.transmitter = link->link_enc->transmitter; 895069d418fSAndrew Jiang cntl.connector_obj_id = link->link_enc->connector; 89687401969SAndrew Jiang cntl.coherent = false; 89787401969SAndrew Jiang cntl.lanes_number = LANE_COUNT_FOUR; 898069d418fSAndrew Jiang cntl.hpd_sel = link->link_enc->hpd_source; 89987401969SAndrew Jiang bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 90087401969SAndrew Jiang 90178d5d04dSCharlene Liu if (!power_up) 90278d5d04dSCharlene Liu /*save driver power off time stamp*/ 90378d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); 90478d5d04dSCharlene Liu else 90578d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); 90678d5d04dSCharlene Liu 90787401969SAndrew Jiang if (bp_result != BP_RESULT_OK) 9081296423bSBhawanpreet Lakha DC_LOG_ERROR( 90987401969SAndrew Jiang "%s: Panel Power bp_result: %d\n", 91087401969SAndrew Jiang __func__, bp_result); 91187401969SAndrew Jiang } else { 9121296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 91387401969SAndrew Jiang "%s: Skipping Panel Power action: %s\n", 91487401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 91587401969SAndrew Jiang } 91687401969SAndrew Jiang } 9175eefbc40SYue Hin Lau 9185eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 9195eefbc40SYue Hin Lau /* 9205eefbc40SYue Hin Lau * @brief 9215eefbc40SYue Hin Lau * eDP only. Control the backlight of the eDP panel 9225eefbc40SYue Hin Lau */ 92387401969SAndrew Jiang void hwss_edp_backlight_control( 9245eefbc40SYue Hin Lau struct dc_link *link, 9255eefbc40SYue Hin Lau bool enable) 9265eefbc40SYue Hin Lau { 927069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 928069d418fSAndrew Jiang struct dce_hwseq *hws = ctx->dc->hwseq; 9295eefbc40SYue Hin Lau struct bp_transmitter_control cntl = { 0 }; 9305eefbc40SYue Hin Lau 931069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 9325eefbc40SYue Hin Lau != CONNECTOR_ID_EDP) { 9335eefbc40SYue Hin Lau BREAK_TO_DEBUGGER(); 9345eefbc40SYue Hin Lau return; 9355eefbc40SYue Hin Lau } 9365eefbc40SYue Hin Lau 9375eefbc40SYue Hin Lau if (enable && is_panel_backlight_on(hws)) { 9381296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 9395eefbc40SYue Hin Lau "%s: panel already powered up. Do nothing.\n", 9405eefbc40SYue Hin Lau __func__); 9415eefbc40SYue Hin Lau return; 9425eefbc40SYue Hin Lau } 9435eefbc40SYue Hin Lau 9445eefbc40SYue Hin Lau /* Send VBIOS command to control eDP panel backlight */ 9455eefbc40SYue Hin Lau 9461296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 9475eefbc40SYue Hin Lau "%s: backlight action: %s\n", 9485eefbc40SYue Hin Lau __func__, (enable ? "On":"Off")); 9495eefbc40SYue Hin Lau 9505eefbc40SYue Hin Lau cntl.action = enable ? 9515eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_ON : 9525eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_OFF; 95387401969SAndrew Jiang 9545eefbc40SYue Hin Lau /*cntl.engine_id = ctx->engine;*/ 9555eefbc40SYue Hin Lau cntl.transmitter = link->link_enc->transmitter; 9565eefbc40SYue Hin Lau cntl.connector_obj_id = link->link_enc->connector; 9575eefbc40SYue Hin Lau /*todo: unhardcode*/ 9585eefbc40SYue Hin Lau cntl.lanes_number = LANE_COUNT_FOUR; 9595eefbc40SYue Hin Lau cntl.hpd_sel = link->link_enc->hpd_source; 960cf1835f0SCharlene Liu cntl.signal = SIGNAL_TYPE_EDP; 9615eefbc40SYue Hin Lau 9625eefbc40SYue Hin Lau /* For eDP, the following delays might need to be considered 9635eefbc40SYue Hin Lau * after link training completed: 9645eefbc40SYue Hin Lau * idle period - min. accounts for required BS-Idle pattern, 9655eefbc40SYue Hin Lau * max. allows for source frame synchronization); 9665eefbc40SYue Hin Lau * 50 msec max. delay from valid video data from source 9675eefbc40SYue Hin Lau * to video on dislpay or backlight enable. 9685eefbc40SYue Hin Lau * 9695eefbc40SYue Hin Lau * Disable the delay for now. 9705eefbc40SYue Hin Lau * Enable it in the future if necessary. 9715eefbc40SYue Hin Lau */ 9725eefbc40SYue Hin Lau /* dc_service_sleep_in_milliseconds(50); */ 9735180d4a4SCharlene Liu /*edp 1.2*/ 9745180d4a4SCharlene Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 9755180d4a4SCharlene Liu edp_receiver_ready_T7(link); 976069d418fSAndrew Jiang link_transmitter_control(ctx->dc_bios, &cntl); 97769b9723aSCharlene Liu /*edp 1.2*/ 9785180d4a4SCharlene Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) 97969b9723aSCharlene Liu edp_receiver_ready_T9(link); 9805eefbc40SYue Hin Lau } 9815eefbc40SYue Hin Lau 9821a05873fSAnthony Koo void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 9834562236bSHarry Wentland { 9841a05873fSAnthony Koo struct dc *core_dc = pipe_ctx->stream->ctx->dc; 9851a05873fSAnthony Koo /* notify audio driver for audio modes of monitor */ 9861a05873fSAnthony Koo struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu; 9871a05873fSAnthony Koo unsigned int i, num_audio = 1; 9881a05873fSAnthony Koo 9891a05873fSAnthony Koo if (pipe_ctx->stream_res.audio) { 9901a05873fSAnthony Koo for (i = 0; i < MAX_PIPES; i++) { 9911a05873fSAnthony Koo /*current_state not updated yet*/ 9921a05873fSAnthony Koo if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 9931a05873fSAnthony Koo num_audio++; 9941a05873fSAnthony Koo } 9951a05873fSAnthony Koo 9961a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 9971a05873fSAnthony Koo 9981a05873fSAnthony Koo if (num_audio == 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL) 9991a05873fSAnthony Koo /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 10001a05873fSAnthony Koo pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); 10011a05873fSAnthony Koo /* un-mute audio */ 10021a05873fSAnthony Koo /* TODO: audio should be per stream rather than per link */ 10031a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 10041a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, false); 10051a05873fSAnthony Koo } 10061a05873fSAnthony Koo } 10071a05873fSAnthony Koo 10081a05873fSAnthony Koo void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) 10091a05873fSAnthony Koo { 10104176664bSCharlene Liu struct dc *dc = pipe_ctx->stream->ctx->dc; 10114562236bSHarry Wentland 10122b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 10132b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc, true); 1014afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio) { 10157c357e61SCharlene Liu if (option != KEEP_ACQUIRED_RESOURCE || 10167c357e61SCharlene Liu !dc->debug.az_endpoint_mute_only) { 10177c357e61SCharlene Liu /*only disalbe az_endpoint if power down or free*/ 1018afaacef4SHarry Wentland pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 10197c357e61SCharlene Liu } 10204562236bSHarry Wentland 10214562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10228e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 10238e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 10244562236bSHarry Wentland else 10258e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 10268e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 10274176664bSCharlene Liu /*don't free audio if it is from retrain or internal disable stream*/ 10284176664bSCharlene Liu if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) { 10294176664bSCharlene Liu /*we have to dynamic arbitrate the audio endpoints*/ 10304176664bSCharlene Liu /*we free the resource, need reset is_audio_acquired*/ 10314176664bSCharlene Liu update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false); 1032fb5fb63aSCharlene Liu pipe_ctx->stream_res.audio = NULL; 10334176664bSCharlene Liu } 10344562236bSHarry Wentland 10354562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 10364562236bSHarry Wentland * add audio mode list change flag */ 10374562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 10384562236bSHarry Wentland * stream->stream_engine_id); 10394562236bSHarry Wentland */ 10404562236bSHarry Wentland } 10411a05873fSAnthony Koo } 10424562236bSHarry Wentland 10431a05873fSAnthony Koo void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) 10441a05873fSAnthony Koo { 10451a05873fSAnthony Koo struct dc_stream_state *stream = pipe_ctx->stream; 10461a05873fSAnthony Koo struct dc_link *link = stream->sink->link; 10471a05873fSAnthony Koo struct dc *dc = pipe_ctx->stream->ctx->dc; 10481a05873fSAnthony Koo 10491a05873fSAnthony Koo if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 10501a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 10511a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 10521a05873fSAnthony Koo 10531a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10541a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 10551a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 10561a05873fSAnthony Koo 10571a05873fSAnthony Koo dc->hwss.disable_audio_stream(pipe_ctx, option); 1058904623eeSYongqiang Sun 10594562236bSHarry Wentland link->link_enc->funcs->connect_dig_be_to_fe( 10604562236bSHarry Wentland link->link_enc, 10618e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->id, 10624562236bSHarry Wentland false); 10634562236bSHarry Wentland 10644562236bSHarry Wentland } 10654562236bSHarry Wentland 10664562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 10674562236bSHarry Wentland struct dc_link_settings *link_settings) 10684562236bSHarry Wentland { 10694562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 107041b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 107141b49742SCharlene Liu struct dc_link *link = stream->sink->link; 10724562236bSHarry Wentland 10734562236bSHarry Wentland /* only 3 items below are used by unblank */ 10746235b23cSTony Cheng params.pixel_clk_khz = 10754fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.pix_clk_khz; 10764562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 107741b49742SCharlene Liu 107841b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 10798e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 108041b49742SCharlene Liu 108114d6f644SYongqiang Sun if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 108241b49742SCharlene Liu link->dc->hwss.edp_backlight_control(link, true); 10835282cbe3SYongqiang Sun stream->bl_pwm_level = EDP_BACKLIGHT_RAMP_DISABLE_LEVEL; 108414d6f644SYongqiang Sun } 108541b49742SCharlene Liu } 108641b49742SCharlene Liu void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 108741b49742SCharlene Liu { 108841b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 108941b49742SCharlene Liu struct dc_link *link = stream->sink->link; 109041b49742SCharlene Liu 1091ab892598SRoman Li if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 109241b49742SCharlene Liu link->dc->hwss.edp_backlight_control(link, false); 1093ab892598SRoman Li dc_link_set_abm_disable(link); 1094ab892598SRoman Li } 109541b49742SCharlene Liu 109641b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 109741b49742SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); 10984562236bSHarry Wentland } 10994562236bSHarry Wentland 110015e17335SCharlene Liu 110115e17335SCharlene Liu void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 110215e17335SCharlene Liu { 11038e9c4c8cSHarry Wentland if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 11048e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 110515e17335SCharlene Liu } 110615e17335SCharlene Liu 11074562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 11084562236bSHarry Wentland { 11094562236bSHarry Wentland switch (crtc_id) { 11104562236bSHarry Wentland case CONTROLLER_ID_D0: 11114562236bSHarry Wentland return DTO_SOURCE_ID0; 11124562236bSHarry Wentland case CONTROLLER_ID_D1: 11134562236bSHarry Wentland return DTO_SOURCE_ID1; 11144562236bSHarry Wentland case CONTROLLER_ID_D2: 11154562236bSHarry Wentland return DTO_SOURCE_ID2; 11164562236bSHarry Wentland case CONTROLLER_ID_D3: 11174562236bSHarry Wentland return DTO_SOURCE_ID3; 11184562236bSHarry Wentland case CONTROLLER_ID_D4: 11194562236bSHarry Wentland return DTO_SOURCE_ID4; 11204562236bSHarry Wentland case CONTROLLER_ID_D5: 11214562236bSHarry Wentland return DTO_SOURCE_ID5; 11224562236bSHarry Wentland default: 11234562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 11244562236bSHarry Wentland } 11254562236bSHarry Wentland } 11264562236bSHarry Wentland 11274562236bSHarry Wentland static void build_audio_output( 1128ab8db3e1SAndrey Grodzovsky struct dc_state *state, 11294562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 11304562236bSHarry Wentland struct audio_output *audio_output) 11314562236bSHarry Wentland { 11320971c40eSHarry Wentland const struct dc_stream_state *stream = pipe_ctx->stream; 11338e9c4c8cSHarry Wentland audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 11344562236bSHarry Wentland 11354562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 11364562236bSHarry Wentland 11374562236bSHarry Wentland /* audio_crtc_info */ 11384562236bSHarry Wentland 11394562236bSHarry Wentland audio_output->crtc_info.h_total = 11404fa086b9SLeo (Sunpeng) Li stream->timing.h_total; 11414562236bSHarry Wentland 11424562236bSHarry Wentland /* 11434562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 11444562236bSHarry Wentland * need to specify actual active signal portion 11454562236bSHarry Wentland */ 11464562236bSHarry Wentland audio_output->crtc_info.h_active = 11474fa086b9SLeo (Sunpeng) Li stream->timing.h_addressable 11484fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_left 11494fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_right; 11504562236bSHarry Wentland 11514562236bSHarry Wentland audio_output->crtc_info.v_active = 11524fa086b9SLeo (Sunpeng) Li stream->timing.v_addressable 11534fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_top 11544fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_bottom; 11554562236bSHarry Wentland 11564562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 11574562236bSHarry Wentland 11584562236bSHarry Wentland audio_output->crtc_info.interlaced = 11594fa086b9SLeo (Sunpeng) Li stream->timing.flags.INTERLACE; 11604562236bSHarry Wentland 11614562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 11624fa086b9SLeo (Sunpeng) Li (stream->timing.pix_clk_khz*1000)/ 11634fa086b9SLeo (Sunpeng) Li (stream->timing.h_total*stream->timing.v_total); 11644562236bSHarry Wentland 11654562236bSHarry Wentland audio_output->crtc_info.color_depth = 11664fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth; 11674562236bSHarry Wentland 11684562236bSHarry Wentland audio_output->crtc_info.requested_pixel_clock = 116910688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; 11704562236bSHarry Wentland 11714562236bSHarry Wentland audio_output->crtc_info.calculated_pixel_clock = 117210688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; 11734562236bSHarry Wentland 117487b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 117587b58768SCharlene Liu if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && 117687b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock == 11774fa086b9SLeo (Sunpeng) Li stream->timing.pix_clk_khz) { 117810688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 117987b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock = 118087b58768SCharlene Liu audio_output->crtc_info.requested_pixel_clock/2; 118187b58768SCharlene Liu audio_output->crtc_info.calculated_pixel_clock = 118210688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2; 118387b58768SCharlene Liu 118487b58768SCharlene Liu } 118587b58768SCharlene Liu } 118687b58768SCharlene Liu 11874562236bSHarry Wentland if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 11884562236bSHarry Wentland pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 11894562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 1190ab8db3e1SAndrey Grodzovsky state->dis_clk->funcs->get_dp_ref_clk_frequency( 1191ab8db3e1SAndrey Grodzovsky state->dis_clk); 11924562236bSHarry Wentland } 11934562236bSHarry Wentland 11944562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 11954562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 11964562236bSHarry Wentland 11974562236bSHarry Wentland audio_output->pll_info.dto_source = 11984562236bSHarry Wentland translate_to_dto_source( 1199e07f541fSYongqiang Sun pipe_ctx->stream_res.tg->inst + 1); 12004562236bSHarry Wentland 12014562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 12024562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 12034562236bSHarry Wentland 12044562236bSHarry Wentland audio_output->pll_info.ss_percentage = 12054562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 12064562236bSHarry Wentland } 12074562236bSHarry Wentland 12084562236bSHarry Wentland static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, 12094562236bSHarry Wentland struct tg_color *color) 12104562236bSHarry Wentland { 12112a54bd6eSJerry (Fangzhi) Zuo uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; 12124562236bSHarry Wentland 12136702a9acSHarry Wentland switch (pipe_ctx->plane_res.scl_data.format) { 12144562236bSHarry Wentland case PIXEL_FORMAT_ARGB8888: 12154562236bSHarry Wentland /* set boarder color to red */ 12164562236bSHarry Wentland color->color_r_cr = color_value; 12174562236bSHarry Wentland break; 12184562236bSHarry Wentland 12194562236bSHarry Wentland case PIXEL_FORMAT_ARGB2101010: 12204562236bSHarry Wentland /* set boarder color to blue */ 12214562236bSHarry Wentland color->color_b_cb = color_value; 12224562236bSHarry Wentland break; 122387449a90SAnthony Koo case PIXEL_FORMAT_420BPP8: 12244562236bSHarry Wentland /* set boarder color to green */ 12254562236bSHarry Wentland color->color_g_y = color_value; 12264562236bSHarry Wentland break; 122787449a90SAnthony Koo case PIXEL_FORMAT_420BPP10: 122887449a90SAnthony Koo /* set boarder color to yellow */ 122987449a90SAnthony Koo color->color_g_y = color_value; 123087449a90SAnthony Koo color->color_r_cr = color_value; 123187449a90SAnthony Koo break; 12324562236bSHarry Wentland case PIXEL_FORMAT_FP16: 12334562236bSHarry Wentland /* set boarder color to white */ 12344562236bSHarry Wentland color->color_r_cr = color_value; 12354562236bSHarry Wentland color->color_b_cb = color_value; 12364562236bSHarry Wentland color->color_g_y = color_value; 12374562236bSHarry Wentland break; 12384562236bSHarry Wentland default: 12394562236bSHarry Wentland break; 12404562236bSHarry Wentland } 12414562236bSHarry Wentland } 12424562236bSHarry Wentland 1243fb3466a4SBhawanpreet Lakha static void program_scaler(const struct dc *dc, 12444562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 12454562236bSHarry Wentland { 12464562236bSHarry Wentland struct tg_color color = {0}; 12474562236bSHarry Wentland 1248ff5ef992SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1249ff5ef992SAlex Deucher /* TOFPGA */ 125086a66c4eSHarry Wentland if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1251ff5ef992SAlex Deucher return; 1252ff5ef992SAlex Deucher #endif 1253ff5ef992SAlex Deucher 1254fb3466a4SBhawanpreet Lakha if (dc->debug.surface_visual_confirm) 12554562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 12564562236bSHarry Wentland else 12574562236bSHarry Wentland color_space_to_black_color(dc, 12584fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space, 12594562236bSHarry Wentland &color); 12604562236bSHarry Wentland 126186a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 126286a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, 12636702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.depth, 12644562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 12654562236bSHarry Wentland 12666b670fa9SHarry Wentland if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) 12676b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 12686b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 12694562236bSHarry Wentland &color); 12704562236bSHarry Wentland 127186a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 12726702a9acSHarry Wentland &pipe_ctx->plane_res.scl_data); 12734562236bSHarry Wentland } 12744562236bSHarry Wentland 12753158223eSEric Bernstein static enum dc_status dce110_enable_stream_timing( 12764562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1277608ac7bbSJerry Zuo struct dc_state *context, 1278fb3466a4SBhawanpreet Lakha struct dc *dc) 12794562236bSHarry Wentland { 12800971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1281608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 12824562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 12834562236bSHarry Wentland struct tg_color black_color = {0}; 12844562236bSHarry Wentland 12854562236bSHarry Wentland if (!pipe_ctx_old->stream) { 12864562236bSHarry Wentland 12874562236bSHarry Wentland /* program blank color */ 12884562236bSHarry Wentland color_space_to_black_color(dc, 12894fa086b9SLeo (Sunpeng) Li stream->output_color_space, &black_color); 12906b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank_color( 12916b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 12924562236bSHarry Wentland &black_color); 12934b5e7d62SHersen Wu 12944562236bSHarry Wentland /* 12954562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 12964562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 12974562236bSHarry Wentland */ 12986b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 12994562236bSHarry Wentland 13004562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 13014562236bSHarry Wentland pipe_ctx->clock_source, 130210688217SHarry Wentland &pipe_ctx->stream_res.pix_clk_params, 13034562236bSHarry Wentland &pipe_ctx->pll_settings)) { 13044562236bSHarry Wentland BREAK_TO_DEBUGGER(); 13054562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 13064562236bSHarry Wentland } 13074562236bSHarry Wentland 13086b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->program_timing( 13096b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 13104fa086b9SLeo (Sunpeng) Li &stream->timing, 13114562236bSHarry Wentland true); 131294267b3dSSylvia Tsai 13136b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 13146b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 131594267b3dSSylvia Tsai 0x182); 13164562236bSHarry Wentland } 13174562236bSHarry Wentland 13184562236bSHarry Wentland if (!pipe_ctx_old->stream) { 13196b670fa9SHarry Wentland if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 13206b670fa9SHarry Wentland pipe_ctx->stream_res.tg)) { 13214562236bSHarry Wentland BREAK_TO_DEBUGGER(); 13224562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 13234562236bSHarry Wentland } 13244562236bSHarry Wentland } 13254562236bSHarry Wentland 132694267b3dSSylvia Tsai 132794267b3dSSylvia Tsai 13284562236bSHarry Wentland return DC_OK; 13294562236bSHarry Wentland } 13304562236bSHarry Wentland 13314562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 13324562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1333608ac7bbSJerry Zuo struct dc_state *context, 1334fb3466a4SBhawanpreet Lakha struct dc *dc) 13354562236bSHarry Wentland { 13360971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1337608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 13384562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 13394562236bSHarry Wentland 13401a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 13411a05873fSAnthony Koo struct audio_output audio_output; 13421a05873fSAnthony Koo 13431a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 13441a05873fSAnthony Koo 13451a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 13461a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 13471a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 13481a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 13491a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 13501a05873fSAnthony Koo else 13511a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 13521a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 13531a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 13541a05873fSAnthony Koo &pipe_ctx->stream->audio_info, 13551a05873fSAnthony Koo &audio_output.crtc_info); 13561a05873fSAnthony Koo 13571a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_configure( 13581a05873fSAnthony Koo pipe_ctx->stream_res.audio, 13591a05873fSAnthony Koo pipe_ctx->stream->signal, 13601a05873fSAnthony Koo &audio_output.crtc_info, 13611a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 13621a05873fSAnthony Koo } 13631a05873fSAnthony Koo 13644562236bSHarry Wentland /* */ 13653158223eSEric Bernstein dc->hwss.enable_stream_timing(pipe_ctx, context, dc); 13664562236bSHarry Wentland 1367f0c4d997SCorbin McElhanney /* FPGA does not program backend */ 1368f0c4d997SCorbin McElhanney if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 1369a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1370a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 13714562236bSHarry Wentland COLOR_SPACE_YCBCR601, 13724fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth, 13734562236bSHarry Wentland pipe_ctx->stream->signal); 13744562236bSHarry Wentland 1375a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1376a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 13774562236bSHarry Wentland &stream->bit_depth_params, 13784562236bSHarry Wentland &stream->clamping); 13794562236bSHarry Wentland return DC_OK; 1380181a888fSCharlene Liu } 13814562236bSHarry Wentland /* TODO: move to stream encoder */ 13824562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 13834562236bSHarry Wentland if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) { 13844562236bSHarry Wentland BREAK_TO_DEBUGGER(); 13854562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 13864562236bSHarry Wentland } 1387f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1388f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp, 1389f0c4d997SCorbin McElhanney COLOR_SPACE_YCBCR601, 1390f0c4d997SCorbin McElhanney stream->timing.display_color_depth, 1391f0c4d997SCorbin McElhanney pipe_ctx->stream->signal); 13924562236bSHarry Wentland 13934562236bSHarry Wentland if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 13944562236bSHarry Wentland stream->sink->link->link_enc->funcs->setup( 13954562236bSHarry Wentland stream->sink->link->link_enc, 13964562236bSHarry Wentland pipe_ctx->stream->signal); 13974562236bSHarry Wentland 1398ab3c1798SVitaly Prosyak if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) 13998e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync( 14008e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 14016b670fa9SHarry Wentland pipe_ctx->stream_res.tg->inst, 14024fa086b9SLeo (Sunpeng) Li stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); 1403ab3c1798SVitaly Prosyak 1404ab3c1798SVitaly Prosyak 1405a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1406a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 1407181a888fSCharlene Liu &stream->bit_depth_params, 1408181a888fSCharlene Liu &stream->clamping); 1409603767f9STony Cheng 14104562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 14118e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute( 14128e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 14134fa086b9SLeo (Sunpeng) Li &stream->timing, 14144fa086b9SLeo (Sunpeng) Li stream->output_color_space); 14154562236bSHarry Wentland 14164562236bSHarry Wentland if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 14178e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute( 14188e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 14194fa086b9SLeo (Sunpeng) Li &stream->timing, 14204562236bSHarry Wentland stream->phy_pix_clk, 1421afaacef4SHarry Wentland pipe_ctx->stream_res.audio != NULL); 14224562236bSHarry Wentland 14234562236bSHarry Wentland if (dc_is_dvi_signal(pipe_ctx->stream->signal)) 14248e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute( 14258e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 14264fa086b9SLeo (Sunpeng) Li &stream->timing, 14274562236bSHarry Wentland (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? 14284562236bSHarry Wentland true : false); 14294562236bSHarry Wentland 143015e17335SCharlene Liu resource_build_info_frame(pipe_ctx); 14313639fa68SZeyu Fan dce110_update_info_frame(pipe_ctx); 1432f0362823SYongqiang Sun if (!pipe_ctx_old->stream) 1433ab8db3e1SAndrey Grodzovsky core_link_enable_stream(context, pipe_ctx); 14344562236bSHarry Wentland 14356702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 14364562236bSHarry Wentland 143794267b3dSSylvia Tsai pipe_ctx->stream->sink->link->psr_enabled = false; 143894267b3dSSylvia Tsai 14394562236bSHarry Wentland return DC_OK; 14404562236bSHarry Wentland } 14414562236bSHarry Wentland 14424562236bSHarry Wentland /******************************************************************************/ 14434562236bSHarry Wentland 1444fb3466a4SBhawanpreet Lakha static void power_down_encoders(struct dc *dc) 14454562236bSHarry Wentland { 14464562236bSHarry Wentland int i; 1447a0c38ebaSCharlene Liu enum connector_id connector_id; 144868d77dd8SAndrew Jiang enum signal_type signal = SIGNAL_TYPE_NONE; 1449b9b171ffSHersen Wu 1450b9b171ffSHersen Wu /* do not know BIOS back-front mapping, simply blank all. It will not 1451b9b171ffSHersen Wu * hurt for non-DP 1452b9b171ffSHersen Wu */ 1453b9b171ffSHersen Wu for (i = 0; i < dc->res_pool->stream_enc_count; i++) { 1454b9b171ffSHersen Wu dc->res_pool->stream_enc[i]->funcs->dp_blank( 1455b9b171ffSHersen Wu dc->res_pool->stream_enc[i]); 1456b9b171ffSHersen Wu } 1457b9b171ffSHersen Wu 14584562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 1459a0c38ebaSCharlene Liu connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id); 1460a0c38ebaSCharlene Liu if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || 1461a0c38ebaSCharlene Liu (connector_id == CONNECTOR_ID_EDP)) { 1462a0c38ebaSCharlene Liu 1463a0c38ebaSCharlene Liu if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) 1464a0c38ebaSCharlene Liu dp_receiver_power_ctrl(dc->links[i], false); 1465904623eeSYongqiang Sun if (connector_id == CONNECTOR_ID_EDP) 146668d77dd8SAndrew Jiang signal = SIGNAL_TYPE_EDP; 1467a0c38ebaSCharlene Liu } 1468a0c38ebaSCharlene Liu 14694562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 1470069d418fSAndrew Jiang dc->links[i]->link_enc, signal); 14714562236bSHarry Wentland } 14724562236bSHarry Wentland } 14734562236bSHarry Wentland 1474fb3466a4SBhawanpreet Lakha static void power_down_controllers(struct dc *dc) 14754562236bSHarry Wentland { 14764562236bSHarry Wentland int i; 14774562236bSHarry Wentland 14787f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 14794562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 14804562236bSHarry Wentland dc->res_pool->timing_generators[i]); 14814562236bSHarry Wentland } 14824562236bSHarry Wentland } 14834562236bSHarry Wentland 1484fb3466a4SBhawanpreet Lakha static void power_down_clock_sources(struct dc *dc) 14854562236bSHarry Wentland { 14864562236bSHarry Wentland int i; 14874562236bSHarry Wentland 14884562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 14894562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 14904562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 14914562236bSHarry Wentland 14924562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 14934562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 14944562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 14954562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 14964562236bSHarry Wentland } 14974562236bSHarry Wentland } 14984562236bSHarry Wentland 1499fb3466a4SBhawanpreet Lakha static void power_down_all_hw_blocks(struct dc *dc) 15004562236bSHarry Wentland { 15014562236bSHarry Wentland power_down_encoders(dc); 15024562236bSHarry Wentland 15034562236bSHarry Wentland power_down_controllers(dc); 15044562236bSHarry Wentland 15054562236bSHarry Wentland power_down_clock_sources(dc); 15061663ae1cSBhawanpreet Lakha 15072f3bfb27SRoman Li if (dc->fbc_compressor) 15081663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 15094562236bSHarry Wentland } 15104562236bSHarry Wentland 15114562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 1512fb3466a4SBhawanpreet Lakha struct dc *dc) 15134562236bSHarry Wentland { 15144562236bSHarry Wentland int i; 15154562236bSHarry Wentland struct timing_generator *tg; 15164562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 15174562236bSHarry Wentland 15187f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 15194562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 15204562236bSHarry Wentland 15210a87425aSTony Cheng if (tg->funcs->disable_vga) 15224562236bSHarry Wentland tg->funcs->disable_vga(tg); 15237f93c1deSCharlene Liu } 15247f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->pipe_count; i++) { 15254562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 15264562236bSHarry Wentland * powergating. */ 15274562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 15284562236bSHarry Wentland true); 15294562236bSHarry Wentland 1530e6c258cbSYongqiang Sun dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 15317f914a62SYongqiang Sun dc->hwss.disable_plane(dc, 1532e6c258cbSYongqiang Sun &dc->current_state->res_ctx.pipe_ctx[i]); 15334562236bSHarry Wentland } 15344562236bSHarry Wentland } 15354562236bSHarry Wentland 1536f0c0761bSYongqiang Sun static struct dc_link *get_link_for_edp(struct dc *dc) 1537339cc82aSYongqiang Sun { 1538339cc82aSYongqiang Sun int i; 1539339cc82aSYongqiang Sun 1540f0c0761bSYongqiang Sun for (i = 0; i < dc->link_count; i++) { 1541f0c0761bSYongqiang Sun if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP) 1542f0c0761bSYongqiang Sun return dc->links[i]; 1543339cc82aSYongqiang Sun } 1544f0c0761bSYongqiang Sun return NULL; 1545339cc82aSYongqiang Sun } 1546339cc82aSYongqiang Sun 1547cf1835f0SCharlene Liu static struct dc_link *get_link_for_edp_not_in_use( 154825292028SYongqiang Sun struct dc *dc, 154925292028SYongqiang Sun struct dc_state *context) 155025292028SYongqiang Sun { 155125292028SYongqiang Sun int i; 155225292028SYongqiang Sun struct dc_link *link = NULL; 155325292028SYongqiang Sun 155425292028SYongqiang Sun /* check if eDP panel is suppose to be set mode, if yes, no need to disable */ 155525292028SYongqiang Sun for (i = 0; i < context->stream_count; i++) { 155625292028SYongqiang Sun if (context->streams[i]->signal == SIGNAL_TYPE_EDP) 155725292028SYongqiang Sun return NULL; 155825292028SYongqiang Sun } 155925292028SYongqiang Sun 156025292028SYongqiang Sun /* check if there is an eDP panel not in use */ 156125292028SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 156225292028SYongqiang Sun if (dc->links[i]->local_sink && 156325292028SYongqiang Sun dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 156425292028SYongqiang Sun link = dc->links[i]; 156525292028SYongqiang Sun break; 156625292028SYongqiang Sun } 156725292028SYongqiang Sun } 156825292028SYongqiang Sun 156925292028SYongqiang Sun return link; 157025292028SYongqiang Sun } 157125292028SYongqiang Sun 15724562236bSHarry Wentland /** 15734562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 15744562236bSHarry Wentland * 1. Power down all DC HW blocks 15754562236bSHarry Wentland * 2. Disable VGA engine on all controllers 15764562236bSHarry Wentland * 3. Enable power gating for controller 15774562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 15784562236bSHarry Wentland */ 157925292028SYongqiang Sun void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 15804562236bSHarry Wentland { 15814cac1e6dSYongqiang Sun struct dc_link *edp_link_to_turnoff = NULL; 1582f0c0761bSYongqiang Sun struct dc_link *edp_link = get_link_for_edp(dc); 1583f0c0761bSYongqiang Sun bool can_eDP_fast_boot_optimize = false; 15844cac1e6dSYongqiang Sun 1585f0c0761bSYongqiang Sun if (edp_link) { 1586f0c0761bSYongqiang Sun can_eDP_fast_boot_optimize = 1587f0c0761bSYongqiang Sun edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc); 1588f0c0761bSYongqiang Sun } 1589f0c0761bSYongqiang Sun 1590f0c0761bSYongqiang Sun if (can_eDP_fast_boot_optimize) { 15914cac1e6dSYongqiang Sun edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context); 15924cac1e6dSYongqiang Sun 15932c37e49aSYongqiang Sun /* if OS doesn't light up eDP and eDP link is available, we want to disable 15942c37e49aSYongqiang Sun * If resume from S4/S5, should optimization. 15952c37e49aSYongqiang Sun */ 1596f0c0761bSYongqiang Sun if (!edp_link_to_turnoff) 15974cac1e6dSYongqiang Sun dc->apply_edp_fast_boot_optimization = true; 15984cac1e6dSYongqiang Sun } 15994cac1e6dSYongqiang Sun 16004cac1e6dSYongqiang Sun if (!dc->apply_edp_fast_boot_optimization) { 16014cac1e6dSYongqiang Sun if (edp_link_to_turnoff) { 16024cac1e6dSYongqiang Sun /*turn off backlight before DP_blank and encoder powered down*/ 16034cac1e6dSYongqiang Sun dc->hwss.edp_backlight_control(edp_link_to_turnoff, false); 1604c5fc7f59SCharlene Liu } 1605c5fc7f59SCharlene Liu /*resume from S3, no vbios posting, no need to power down again*/ 160625292028SYongqiang Sun power_down_all_hw_blocks(dc); 16074562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 1608cf1835f0SCharlene Liu if (edp_link_to_turnoff) 1609cf1835f0SCharlene Liu dc->hwss.edp_power_control(edp_link_to_turnoff, false); 1610c5fc7f59SCharlene Liu } 16114562236bSHarry Wentland bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); 16124562236bSHarry Wentland } 16134562236bSHarry Wentland 16144562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 16154562236bSHarry Wentland struct bw_fixed blackout_duration, 16160971c40eSHarry Wentland const struct dc_stream_state *stream) 16174562236bSHarry Wentland { 16184562236bSHarry Wentland uint32_t total_dest_line_time_ns; 16194562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 16204562236bSHarry Wentland 16214562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 16224562236bSHarry Wentland 16234562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 16244fa086b9SLeo (Sunpeng) Li stream->timing.h_total / 16254fa086b9SLeo (Sunpeng) Li stream->timing.pix_clk_khz + 16264562236bSHarry Wentland pstate_blackout_duration_ns; 16274562236bSHarry Wentland 16284562236bSHarry Wentland return total_dest_line_time_ns; 16294562236bSHarry Wentland } 16304562236bSHarry Wentland 1631f774b339SEric Yang static void dce110_set_displaymarks( 1632fb3466a4SBhawanpreet Lakha const struct dc *dc, 1633608ac7bbSJerry Zuo struct dc_state *context) 16344562236bSHarry Wentland { 16354562236bSHarry Wentland uint8_t i, num_pipes; 16364562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 16374562236bSHarry Wentland 16384562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 16394562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 16404562236bSHarry Wentland uint32_t total_dest_line_time_ns; 16414562236bSHarry Wentland 16424562236bSHarry Wentland if (pipe_ctx->stream == NULL) 16434562236bSHarry Wentland continue; 16444562236bSHarry Wentland 16454562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 164677a4ea53SBhawanpreet Lakha dc->bw_vbios->blackout_duration, pipe_ctx->stream); 164786a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 164886a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 16499037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 16509037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 16513722c794SMikita Lipski context->bw.dce.stutter_entry_wm_ns[num_pipes], 16529037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 16534562236bSHarry Wentland total_dest_line_time_ns); 16544562236bSHarry Wentland if (i == underlay_idx) { 16554562236bSHarry Wentland num_pipes++; 165686a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 165786a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 16589037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_wm_ns[num_pipes], 16599037d802SDmytro Laktyushkin context->bw.dce.stutter_exit_wm_ns[num_pipes], 16609037d802SDmytro Laktyushkin context->bw.dce.urgent_wm_ns[num_pipes], 16614562236bSHarry Wentland total_dest_line_time_ns); 16624562236bSHarry Wentland } 16634562236bSHarry Wentland num_pipes++; 16644562236bSHarry Wentland } 16654562236bSHarry Wentland } 16664562236bSHarry Wentland 1667fab55d61SDmytro Laktyushkin void dce110_set_safe_displaymarks( 1668a2b8659dSTony Cheng struct resource_context *res_ctx, 1669a2b8659dSTony Cheng const struct resource_pool *pool) 16704562236bSHarry Wentland { 16714562236bSHarry Wentland int i; 1672a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 16739037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 16744562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 16759037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 16764562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 16773722c794SMikita Lipski struct dce_watermarks min_marks = { 0, 0, 0, 0}; 16784562236bSHarry Wentland 16794562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 16808feabd03SYue Hin Lau if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 16814562236bSHarry Wentland continue; 16824562236bSHarry Wentland 168386a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 168486a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 16854562236bSHarry Wentland nbp_marks, 16864562236bSHarry Wentland max_marks, 16873722c794SMikita Lipski min_marks, 16884562236bSHarry Wentland max_marks, 16894562236bSHarry Wentland MAX_WATERMARK); 16908feabd03SYue Hin Lau 16914562236bSHarry Wentland if (i == underlay_idx) 169286a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 169386a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 16944562236bSHarry Wentland nbp_marks, 16954562236bSHarry Wentland max_marks, 16964562236bSHarry Wentland max_marks, 16974562236bSHarry Wentland MAX_WATERMARK); 16988feabd03SYue Hin Lau 16994562236bSHarry Wentland } 17004562236bSHarry Wentland } 17014562236bSHarry Wentland 17024562236bSHarry Wentland /******************************************************************************* 17034562236bSHarry Wentland * Public functions 17044562236bSHarry Wentland ******************************************************************************/ 17054562236bSHarry Wentland 17064562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 17074562236bSHarry Wentland int num_pipes, int vmin, int vmax) 17084562236bSHarry Wentland { 17094562236bSHarry Wentland int i = 0; 17104562236bSHarry Wentland struct drr_params params = {0}; 17114562236bSHarry Wentland 17124562236bSHarry Wentland params.vertical_total_max = vmax; 17134562236bSHarry Wentland params.vertical_total_min = vmin; 17144562236bSHarry Wentland 17154562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 17164562236bSHarry Wentland * some GSL stuff 17174562236bSHarry Wentland */ 17184562236bSHarry Wentland 17194562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 17206b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, ¶ms); 17214562236bSHarry Wentland } 17224562236bSHarry Wentland } 17234562236bSHarry Wentland 172472ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 172572ada5f7SEric Cook int num_pipes, 172672ada5f7SEric Cook struct crtc_position *position) 172772ada5f7SEric Cook { 172872ada5f7SEric Cook int i = 0; 172972ada5f7SEric Cook 173072ada5f7SEric Cook /* TODO: handle pipes > 1 173172ada5f7SEric Cook */ 173272ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 17336b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 173472ada5f7SEric Cook } 173572ada5f7SEric Cook 17364562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 173794267b3dSSylvia Tsai int num_pipes, const struct dc_static_screen_events *events) 17384562236bSHarry Wentland { 17394562236bSHarry Wentland unsigned int i; 174094267b3dSSylvia Tsai unsigned int value = 0; 174194267b3dSSylvia Tsai 174294267b3dSSylvia Tsai if (events->overlay_update) 174394267b3dSSylvia Tsai value |= 0x100; 174494267b3dSSylvia Tsai if (events->surface_update) 174594267b3dSSylvia Tsai value |= 0x80; 174694267b3dSSylvia Tsai if (events->cursor_update) 174794267b3dSSylvia Tsai value |= 0x2; 1748ed8462acSCharlene Liu if (events->force_trigger) 1749ed8462acSCharlene Liu value |= 0x1; 17504562236bSHarry Wentland 1751c3aa1d67SBhawanpreet Lakha value |= 0x84; 1752c3aa1d67SBhawanpreet Lakha 17534562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 17546b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs-> 17556b670fa9SHarry Wentland set_static_screen_control(pipe_ctx[i]->stream_res.tg, value); 17564562236bSHarry Wentland } 17574562236bSHarry Wentland 17584562236bSHarry Wentland /* unit: in_khz before mode set, get pixel clock from context. ASIC register 1759fab55d61SDmytro Laktyushkin * may not be programmed yet 17604562236bSHarry Wentland */ 17614562236bSHarry Wentland static uint32_t get_max_pixel_clock_for_all_paths( 1762fb3466a4SBhawanpreet Lakha struct dc *dc, 1763fab55d61SDmytro Laktyushkin struct dc_state *context) 17644562236bSHarry Wentland { 17654562236bSHarry Wentland uint32_t max_pix_clk = 0; 17664562236bSHarry Wentland int i; 17674562236bSHarry Wentland 17684562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 17694562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 17704562236bSHarry Wentland 17714562236bSHarry Wentland if (pipe_ctx->stream == NULL) 17724562236bSHarry Wentland continue; 17734562236bSHarry Wentland 17744562236bSHarry Wentland /* do not check under lay */ 17754562236bSHarry Wentland if (pipe_ctx->top_pipe) 17764562236bSHarry Wentland continue; 17774562236bSHarry Wentland 177810688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk) 17794562236bSHarry Wentland max_pix_clk = 178010688217SHarry Wentland pipe_ctx->stream_res.pix_clk_params.requested_pix_clk; 17814562236bSHarry Wentland } 17824562236bSHarry Wentland 17834562236bSHarry Wentland return max_pix_clk; 17844562236bSHarry Wentland } 17854562236bSHarry Wentland 1786f6baff4dSHarry Wentland /* 1787690b5e39SRoman Li * Check if FBC can be enabled 1788690b5e39SRoman Li */ 17899c6569deSHarry Wentland static bool should_enable_fbc(struct dc *dc, 17903bc4aaa9SRoman Li struct dc_state *context, 17913bc4aaa9SRoman Li uint32_t *pipe_idx) 1792690b5e39SRoman Li { 17933bc4aaa9SRoman Li uint32_t i; 17943bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = NULL; 17953bc4aaa9SRoman Li struct resource_context *res_ctx = &context->res_ctx; 17963bc4aaa9SRoman Li 1797690b5e39SRoman Li 1798690b5e39SRoman Li ASSERT(dc->fbc_compressor); 1799690b5e39SRoman Li 1800690b5e39SRoman Li /* FBC memory should be allocated */ 1801690b5e39SRoman Li if (!dc->ctx->fbc_gpu_addr) 18029c6569deSHarry Wentland return false; 1803690b5e39SRoman Li 1804690b5e39SRoman Li /* Only supports single display */ 1805690b5e39SRoman Li if (context->stream_count != 1) 18069c6569deSHarry Wentland return false; 1807690b5e39SRoman Li 18083bc4aaa9SRoman Li for (i = 0; i < dc->res_pool->pipe_count; i++) { 18093bc4aaa9SRoman Li if (res_ctx->pipe_ctx[i].stream) { 18103bc4aaa9SRoman Li pipe_ctx = &res_ctx->pipe_ctx[i]; 18113bc4aaa9SRoman Li *pipe_idx = i; 18123bc4aaa9SRoman Li break; 18133bc4aaa9SRoman Li } 18143bc4aaa9SRoman Li } 18153bc4aaa9SRoman Li 18167a840773SRoman Li /* Pipe context should be found */ 18177a840773SRoman Li ASSERT(pipe_ctx); 18187a840773SRoman Li 1819690b5e39SRoman Li /* Only supports eDP */ 1820690b5e39SRoman Li if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP) 18219c6569deSHarry Wentland return false; 1822690b5e39SRoman Li 1823690b5e39SRoman Li /* PSR should not be enabled */ 1824690b5e39SRoman Li if (pipe_ctx->stream->sink->link->psr_enabled) 18259c6569deSHarry Wentland return false; 1826690b5e39SRoman Li 182793984bbcSShirish S /* Nothing to compress */ 182893984bbcSShirish S if (!pipe_ctx->plane_state) 18299c6569deSHarry Wentland return false; 183093984bbcSShirish S 183105230fa9SRoman Li /* Only for non-linear tiling */ 183205230fa9SRoman Li if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 18339c6569deSHarry Wentland return false; 183405230fa9SRoman Li 18359c6569deSHarry Wentland return true; 1836690b5e39SRoman Li } 1837690b5e39SRoman Li 1838690b5e39SRoman Li /* 1839690b5e39SRoman Li * Enable FBC 1840690b5e39SRoman Li */ 18419c6569deSHarry Wentland static void enable_fbc(struct dc *dc, 1842608ac7bbSJerry Zuo struct dc_state *context) 1843690b5e39SRoman Li { 18443bc4aaa9SRoman Li uint32_t pipe_idx = 0; 18453bc4aaa9SRoman Li 18463bc4aaa9SRoman Li if (should_enable_fbc(dc, context, &pipe_idx)) { 1847690b5e39SRoman Li /* Program GRPH COMPRESSED ADDRESS and PITCH */ 1848690b5e39SRoman Li struct compr_addr_and_pitch_params params = {0, 0, 0}; 1849690b5e39SRoman Li struct compressor *compr = dc->fbc_compressor; 18503bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 18513bc4aaa9SRoman Li 1852690b5e39SRoman Li 18539c6569deSHarry Wentland params.source_view_width = pipe_ctx->stream->timing.h_addressable; 18549c6569deSHarry Wentland params.source_view_height = pipe_ctx->stream->timing.v_addressable; 1855690b5e39SRoman Li 1856690b5e39SRoman Li compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 1857690b5e39SRoman Li 1858690b5e39SRoman Li compr->funcs->surface_address_and_pitch(compr, ¶ms); 1859690b5e39SRoman Li compr->funcs->set_fbc_invalidation_triggers(compr, 1); 1860690b5e39SRoman Li 1861690b5e39SRoman Li compr->funcs->enable_fbc(compr, ¶ms); 1862690b5e39SRoman Li } 1863690b5e39SRoman Li } 1864690b5e39SRoman Li 186554e8695eSDmytro Laktyushkin static void dce110_reset_hw_ctx_wrap( 1866fb3466a4SBhawanpreet Lakha struct dc *dc, 1867608ac7bbSJerry Zuo struct dc_state *context) 18684562236bSHarry Wentland { 18694562236bSHarry Wentland int i; 18704562236bSHarry Wentland 18714562236bSHarry Wentland /* Reset old context */ 18724562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 1873a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 18744562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 1875608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 18764562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 18774562236bSHarry Wentland 18784562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 18794562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 18804562236bSHarry Wentland * PHY when not already disabled. 18814562236bSHarry Wentland */ 18824562236bSHarry Wentland 18834562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 18844562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 18854562236bSHarry Wentland continue; 18864562236bSHarry Wentland 18874562236bSHarry Wentland if (!pipe_ctx->stream || 188854e8695eSDmytro Laktyushkin pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 188921e67d4dSHarry Wentland struct clock_source *old_clk = pipe_ctx_old->clock_source; 189021e67d4dSHarry Wentland 1891827f11e9SLeo (Sunpeng) Li /* Disable if new stream is null. O/w, if stream is 1892827f11e9SLeo (Sunpeng) Li * disabled already, no need to disable again. 1893827f11e9SLeo (Sunpeng) Li */ 1894827f11e9SLeo (Sunpeng) Li if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) 18954176664bSCharlene Liu core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE); 1896d050f8edSHersen Wu 18976b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 18986b670fa9SHarry Wentland if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 189954e8695eSDmytro Laktyushkin dm_error("DC: failed to blank crtc!\n"); 190054e8695eSDmytro Laktyushkin BREAK_TO_DEBUGGER(); 190154e8695eSDmytro Laktyushkin } 19026b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 190386a66c4eSHarry Wentland pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 1904608ac7bbSJerry Zuo pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 190554e8695eSDmytro Laktyushkin 190621e67d4dSHarry Wentland if (old_clk) 190721e67d4dSHarry Wentland old_clk->funcs->cs_power_down(old_clk); 190821e67d4dSHarry Wentland 19097f914a62SYongqiang Sun dc->hwss.disable_plane(dc, pipe_ctx_old); 191054e8695eSDmytro Laktyushkin 191154e8695eSDmytro Laktyushkin pipe_ctx_old->stream = NULL; 191254e8695eSDmytro Laktyushkin } 19134562236bSHarry Wentland } 19144562236bSHarry Wentland } 19154562236bSHarry Wentland 19161a05873fSAnthony Koo static void dce110_setup_audio_dto( 19171a05873fSAnthony Koo struct dc *dc, 19181a05873fSAnthony Koo struct dc_state *context) 19191a05873fSAnthony Koo { 19201a05873fSAnthony Koo int i; 19211a05873fSAnthony Koo 19221a05873fSAnthony Koo /* program audio wall clock. use HDMI as clock source if HDMI 19231a05873fSAnthony Koo * audio active. Otherwise, use DP as clock source 19241a05873fSAnthony Koo * first, loop to find any HDMI audio, if not, loop find DP audio 19251a05873fSAnthony Koo */ 19261a05873fSAnthony Koo /* Setup audio rate clock source */ 19271a05873fSAnthony Koo /* Issue: 19281a05873fSAnthony Koo * Audio lag happened on DP monitor when unplug a HDMI monitor 19291a05873fSAnthony Koo * 19301a05873fSAnthony Koo * Cause: 19311a05873fSAnthony Koo * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 19321a05873fSAnthony Koo * is set to either dto0 or dto1, audio should work fine. 19331a05873fSAnthony Koo * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 19341a05873fSAnthony Koo * set to dto0 will cause audio lag. 19351a05873fSAnthony Koo * 19361a05873fSAnthony Koo * Solution: 19371a05873fSAnthony Koo * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 19381a05873fSAnthony Koo * find first available pipe with audio, setup audio wall DTO per topology 19391a05873fSAnthony Koo * instead of per pipe. 19401a05873fSAnthony Koo */ 19411a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 19421a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 19431a05873fSAnthony Koo 19441a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 19451a05873fSAnthony Koo continue; 19461a05873fSAnthony Koo 19471a05873fSAnthony Koo if (pipe_ctx->top_pipe) 19481a05873fSAnthony Koo continue; 19491a05873fSAnthony Koo 19501a05873fSAnthony Koo if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 19511a05873fSAnthony Koo continue; 19521a05873fSAnthony Koo 19531a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 19541a05873fSAnthony Koo struct audio_output audio_output; 19551a05873fSAnthony Koo 19561a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 19571a05873fSAnthony Koo 19581a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 19591a05873fSAnthony Koo pipe_ctx->stream_res.audio, 19601a05873fSAnthony Koo pipe_ctx->stream->signal, 19611a05873fSAnthony Koo &audio_output.crtc_info, 19621a05873fSAnthony Koo &audio_output.pll_info); 19631a05873fSAnthony Koo break; 19641a05873fSAnthony Koo } 19651a05873fSAnthony Koo } 19661a05873fSAnthony Koo 19671a05873fSAnthony Koo /* no HDMI audio is found, try DP audio */ 19681a05873fSAnthony Koo if (i == dc->res_pool->pipe_count) { 19691a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 19701a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 19711a05873fSAnthony Koo 19721a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 19731a05873fSAnthony Koo continue; 19741a05873fSAnthony Koo 19751a05873fSAnthony Koo if (pipe_ctx->top_pipe) 19761a05873fSAnthony Koo continue; 19771a05873fSAnthony Koo 19781a05873fSAnthony Koo if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 19791a05873fSAnthony Koo continue; 19801a05873fSAnthony Koo 19811a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 19821a05873fSAnthony Koo struct audio_output audio_output; 19831a05873fSAnthony Koo 19841a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 19851a05873fSAnthony Koo 19861a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 19871a05873fSAnthony Koo pipe_ctx->stream_res.audio, 19881a05873fSAnthony Koo pipe_ctx->stream->signal, 19891a05873fSAnthony Koo &audio_output.crtc_info, 19901a05873fSAnthony Koo &audio_output.pll_info); 19911a05873fSAnthony Koo break; 19921a05873fSAnthony Koo } 19931a05873fSAnthony Koo } 19941a05873fSAnthony Koo } 19951a05873fSAnthony Koo } 1996cf437593SDmytro Laktyushkin 19974562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 1998fb3466a4SBhawanpreet Lakha struct dc *dc, 1999608ac7bbSJerry Zuo struct dc_state *context) 20004562236bSHarry Wentland { 20014562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 20024562236bSHarry Wentland enum dc_status status; 20034562236bSHarry Wentland int i; 20044562236bSHarry Wentland 20054562236bSHarry Wentland /* Reset old context */ 20064562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 20074562236bSHarry Wentland dc->hwss.reset_hw_ctx_wrap(dc, context); 20084562236bSHarry Wentland 20094562236bSHarry Wentland /* Skip applying if no targets */ 2010ab2541b6SAric Cyr if (context->stream_count <= 0) 20114562236bSHarry Wentland return DC_OK; 20124562236bSHarry Wentland 20134562236bSHarry Wentland /* Apply new context */ 20144562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 20154562236bSHarry Wentland 20164562236bSHarry Wentland /* below is for real asic only */ 2017a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 20184562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2019608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 20204562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 20214562236bSHarry Wentland 20224562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 20234562236bSHarry Wentland continue; 20244562236bSHarry Wentland 20254562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 20264562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 20274562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 20284562236bSHarry Wentland pipe_ctx->clock_source, i); 20294562236bSHarry Wentland continue; 20304562236bSHarry Wentland } 20314562236bSHarry Wentland 20324562236bSHarry Wentland dc->hwss.enable_display_power_gating( 20334562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 20344562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 20354562236bSHarry Wentland } 20364562236bSHarry Wentland 20372f3bfb27SRoman Li if (dc->fbc_compressor) 20381663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 20395099114bSAlex Deucher 20401a05873fSAnthony Koo dce110_setup_audio_dto(dc, context); 2041ab8812a3SHersen Wu 2042a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2043ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 2044608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 2045ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2046ab8812a3SHersen Wu 2047ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2048ab8812a3SHersen Wu continue; 2049ab8812a3SHersen Wu 2050ab8812a3SHersen Wu if (pipe_ctx->stream == pipe_ctx_old->stream) 2051ab8812a3SHersen Wu continue; 2052ab8812a3SHersen Wu 20535b92d9d4SHarry Wentland if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2054313bf4ffSYongqiang Sun continue; 2055313bf4ffSYongqiang Sun 2056ab8812a3SHersen Wu if (pipe_ctx->top_pipe) 2057ab8812a3SHersen Wu continue; 2058ab8812a3SHersen Wu 20594562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 20604562236bSHarry Wentland pipe_ctx, 20614562236bSHarry Wentland context, 20624562236bSHarry Wentland dc); 20634562236bSHarry Wentland 20644562236bSHarry Wentland if (DC_OK != status) 20654562236bSHarry Wentland return status; 20664562236bSHarry Wentland } 20674562236bSHarry Wentland 20684562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, false); 20694562236bSHarry Wentland 2070690b5e39SRoman Li if (dc->fbc_compressor) 2071690b5e39SRoman Li enable_fbc(dc, context); 2072690b5e39SRoman Li 20734562236bSHarry Wentland return DC_OK; 20744562236bSHarry Wentland } 20754562236bSHarry Wentland 20764562236bSHarry Wentland /******************************************************************************* 20774562236bSHarry Wentland * Front End programming 20784562236bSHarry Wentland ******************************************************************************/ 20794562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 20804562236bSHarry Wentland { 20814562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 20824562236bSHarry Wentland 20834562236bSHarry Wentland default_adjust.force_hw_default = false; 208434996173SHarry Wentland default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 208534996173SHarry Wentland default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 20864562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 20876702a9acSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 20884562236bSHarry Wentland 20894562236bSHarry Wentland /* display color depth */ 20904562236bSHarry Wentland default_adjust.color_depth = 20914fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.display_color_depth; 20924562236bSHarry Wentland 20934562236bSHarry Wentland /* Lb color depth */ 20946702a9acSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 20954562236bSHarry Wentland 209686a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 209786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, &default_adjust); 20984562236bSHarry Wentland } 20994562236bSHarry Wentland 2100b06b7680SLeon Elazar 2101b06b7680SLeon Elazar /******************************************************************************* 2102b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 2103b06b7680SLeon Elazar * Blender + CRTC 2104b06b7680SLeon Elazar * 2105b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 2106b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 2107b06b7680SLeon Elazar * 2108b06b7680SLeon Elazar * |----------------------------------------------- | 2109b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 2110b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 2111b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 2112b06b7680SLeon Elazar * |------------------------------------------------| 2113b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 2114b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 2115b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 2116b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 2117b06b7680SLeon Elazar * -------------------------------------------------| 2118b06b7680SLeon Elazar * 2119b06b7680SLeon Elazar ******************************************************************************/ 2120fb3466a4SBhawanpreet Lakha static void program_surface_visibility(const struct dc *dc, 21214562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 21224562236bSHarry Wentland { 21234562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2124b06b7680SLeon Elazar bool blank_target = false; 21254562236bSHarry Wentland 21264562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 2127b06b7680SLeon Elazar 2128b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 2129b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2130b06b7680SLeon Elazar 21313be5262eSHarry Wentland if (pipe_ctx->bottom_pipe->plane_state->visible) { 21323be5262eSHarry Wentland if (pipe_ctx->plane_state->visible) 21334562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 21344562236bSHarry Wentland else 21354562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 2136b06b7680SLeon Elazar 21373be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2138b06b7680SLeon Elazar blank_target = true; 2139b06b7680SLeon Elazar 21403be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2141b06b7680SLeon Elazar blank_target = true; 2142b06b7680SLeon Elazar 2143e07f541fSYongqiang Sun dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 21446b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2145b06b7680SLeon Elazar 21464562236bSHarry Wentland } 21474562236bSHarry Wentland 21481bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 21491bf56e62SZeyu Fan { 2150146a9f63SKrunoslav Kovac int i = 0; 21511bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 21521bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 21531bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 21541bf56e62SZeyu Fan 21551bf56e62SZeyu Fan 21564fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 21571bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2158146a9f63SKrunoslav Kovac 2159146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2160146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2161146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 21621bf56e62SZeyu Fan } 21631bf56e62SZeyu Fan 216486a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 21651bf56e62SZeyu Fan } 2166fb3466a4SBhawanpreet Lakha static void update_plane_addr(const struct dc *dc, 21674562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 21684562236bSHarry Wentland { 21693be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 21704562236bSHarry Wentland 21713be5262eSHarry Wentland if (plane_state == NULL) 21724562236bSHarry Wentland return; 21734562236bSHarry Wentland 217486a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 217586a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 21763be5262eSHarry Wentland &plane_state->address, 21773be5262eSHarry Wentland plane_state->flip_immediate); 21784562236bSHarry Wentland 21793be5262eSHarry Wentland plane_state->status.requested_address = plane_state->address; 21804562236bSHarry Wentland } 21814562236bSHarry Wentland 2182f774b339SEric Yang static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 21834562236bSHarry Wentland { 21843be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 21854562236bSHarry Wentland 21863be5262eSHarry Wentland if (plane_state == NULL) 21874562236bSHarry Wentland return; 21884562236bSHarry Wentland 21893be5262eSHarry Wentland plane_state->status.is_flip_pending = 219086a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 219186a66c4eSHarry Wentland pipe_ctx->plane_res.mi); 21924562236bSHarry Wentland 21933be5262eSHarry Wentland if (plane_state->status.is_flip_pending && !plane_state->visible) 219486a66c4eSHarry Wentland pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 21954562236bSHarry Wentland 219686a66c4eSHarry Wentland plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 219786a66c4eSHarry Wentland if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 21986b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 21993be5262eSHarry Wentland plane_state->status.is_right_eye =\ 22006b670fa9SHarry Wentland !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 22017f5c22d1SVitaly Prosyak } 22024562236bSHarry Wentland } 22034562236bSHarry Wentland 2204fb3466a4SBhawanpreet Lakha void dce110_power_down(struct dc *dc) 22054562236bSHarry Wentland { 22064562236bSHarry Wentland power_down_all_hw_blocks(dc); 22074562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 22084562236bSHarry Wentland } 22094562236bSHarry Wentland 22104562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 22114562236bSHarry Wentland struct dc_context *dc_ctx, 22124562236bSHarry Wentland struct timing_generator *tg) 22134562236bSHarry Wentland { 22144562236bSHarry Wentland bool rc = false; 22154562236bSHarry Wentland 22164562236bSHarry Wentland /* To avoid endless loop we wait at most 22174562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 22184562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 22194562236bSHarry Wentland uint32_t i; 22204562236bSHarry Wentland 22214562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 22224562236bSHarry Wentland 22234562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 22244562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 22254562236bSHarry Wentland break; 22264562236bSHarry Wentland } 22274562236bSHarry Wentland 22284562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 22294562236bSHarry Wentland rc = true; 22304562236bSHarry Wentland /* usually occurs at i=1 */ 22314562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 22324562236bSHarry Wentland i); 22334562236bSHarry Wentland break; 22344562236bSHarry Wentland } 22354562236bSHarry Wentland 22364562236bSHarry Wentland /* Wait for one frame. */ 22374562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 22384562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 22394562236bSHarry Wentland } 22404562236bSHarry Wentland 22414562236bSHarry Wentland if (false == rc) 22424562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 22434562236bSHarry Wentland 22444562236bSHarry Wentland return rc; 22454562236bSHarry Wentland } 22464562236bSHarry Wentland 22474562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 22484562236bSHarry Wentland static void dce110_enable_timing_synchronization( 2249fb3466a4SBhawanpreet Lakha struct dc *dc, 22504562236bSHarry Wentland int group_index, 22514562236bSHarry Wentland int group_size, 22524562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 22534562236bSHarry Wentland { 22544562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 22554562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 22564562236bSHarry Wentland int i; 22574562236bSHarry Wentland 22584562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 22594562236bSHarry Wentland 22604562236bSHarry Wentland /* Designate a single TG in the group as a master. 22614562236bSHarry Wentland * Since HW doesn't care which one, we always assign 22624562236bSHarry Wentland * the 1st one in the group. */ 22634562236bSHarry Wentland gsl_params.gsl_group = 0; 22646b670fa9SHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 22654562236bSHarry Wentland 22664562236bSHarry Wentland for (i = 0; i < group_size; i++) 22676b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 22686b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg, &gsl_params); 22694562236bSHarry Wentland 22704562236bSHarry Wentland /* Reset slave controllers on master VSync */ 22714562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 22724562236bSHarry Wentland 22734562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 22746b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2275fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2276fa2123dbSMikita Lipski gsl_params.gsl_group); 22774562236bSHarry Wentland 22784562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 22794562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 22806b670fa9SHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2281fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2282fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg); 22834562236bSHarry Wentland } 22844562236bSHarry Wentland 22854562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 22864562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 22874562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 22884562236bSHarry Wentland for (i = 0; i < group_size; i++) 22896b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 22904562236bSHarry Wentland 22914562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 22924562236bSHarry Wentland } 22934562236bSHarry Wentland 2294fa2123dbSMikita Lipski static void dce110_enable_per_frame_crtc_position_reset( 2295fa2123dbSMikita Lipski struct dc *dc, 2296fa2123dbSMikita Lipski int group_size, 2297fa2123dbSMikita Lipski struct pipe_ctx *grouped_pipes[]) 2298fa2123dbSMikita Lipski { 2299fa2123dbSMikita Lipski struct dc_context *dc_ctx = dc->ctx; 2300fa2123dbSMikita Lipski struct dcp_gsl_params gsl_params = { 0 }; 2301fa2123dbSMikita Lipski int i; 2302fa2123dbSMikita Lipski 2303fa2123dbSMikita Lipski gsl_params.gsl_group = 0; 2304fa2123dbSMikita Lipski gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst; 2305fa2123dbSMikita Lipski 2306fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2307fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2308fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, &gsl_params); 2309fa2123dbSMikita Lipski 2310fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2311fa2123dbSMikita Lipski 2312fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2313fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2314fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2315fa2123dbSMikita Lipski gsl_params.gsl_master, 2316fa2123dbSMikita Lipski &grouped_pipes[i]->stream->triggered_crtc_reset); 2317fa2123dbSMikita Lipski 2318fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2319fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2320fa2123dbSMikita Lipski wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2321fa2123dbSMikita Lipski 2322fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2323fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2324fa2123dbSMikita Lipski 2325fa2123dbSMikita Lipski } 2326fa2123dbSMikita Lipski 2327fb3466a4SBhawanpreet Lakha static void init_hw(struct dc *dc) 23284562236bSHarry Wentland { 23294562236bSHarry Wentland int i; 23304562236bSHarry Wentland struct dc_bios *bp; 23314562236bSHarry Wentland struct transform *xfm; 23325e7773a2SAnthony Koo struct abm *abm; 23334562236bSHarry Wentland 23344562236bSHarry Wentland bp = dc->ctx->dc_bios; 23354562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 23364562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 23374562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 23384562236bSHarry Wentland 23394562236bSHarry Wentland dc->hwss.enable_display_power_gating( 23404562236bSHarry Wentland dc, i, bp, 23414562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 23424562236bSHarry Wentland dc->hwss.enable_display_power_gating( 23434562236bSHarry Wentland dc, i, bp, 23444562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 23454562236bSHarry Wentland dc->hwss.enable_display_pipe_clock_gating( 23464562236bSHarry Wentland dc->ctx, 23474562236bSHarry Wentland true); 23484562236bSHarry Wentland } 23494562236bSHarry Wentland 2350e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 23514562236bSHarry Wentland /***************************************/ 23524562236bSHarry Wentland 23534562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 23544562236bSHarry Wentland /****************************************/ 23554562236bSHarry Wentland /* Power up AND update implementation according to the 23564562236bSHarry Wentland * required signal (which may be different from the 23574562236bSHarry Wentland * default signal on connector). */ 2358d0778ebfSHarry Wentland struct dc_link *link = dc->links[i]; 2359069d418fSAndrew Jiang 2360069d418fSAndrew Jiang if (link->link_enc->connector.id == CONNECTOR_ID_EDP) 2361069d418fSAndrew Jiang dc->hwss.edp_power_control(link, true); 2362069d418fSAndrew Jiang 23634562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 23644562236bSHarry Wentland } 23654562236bSHarry Wentland 23664562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 23674562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 23684562236bSHarry Wentland 23694562236bSHarry Wentland tg->funcs->disable_vga(tg); 23704562236bSHarry Wentland 23714562236bSHarry Wentland /* Blank controller using driver code instead of 23724562236bSHarry Wentland * command table. */ 23734562236bSHarry Wentland tg->funcs->set_blank(tg, true); 23744b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 23754562236bSHarry Wentland } 23764562236bSHarry Wentland 23774562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 23784562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 23794562236bSHarry Wentland audio->funcs->hw_init(audio); 23804562236bSHarry Wentland } 23815e7773a2SAnthony Koo 23825e7773a2SAnthony Koo abm = dc->res_pool->abm; 23836728b30cSAnthony Koo if (abm != NULL) { 23846728b30cSAnthony Koo abm->funcs->init_backlight(abm); 23855e7773a2SAnthony Koo abm->funcs->abm_init(abm); 23864562236bSHarry Wentland } 23875099114bSAlex Deucher 23882f3bfb27SRoman Li if (dc->fbc_compressor) 23891663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2390690b5e39SRoman Li 23916728b30cSAnthony Koo } 23924562236bSHarry Wentland 239328f72454SJordan Lazare void dce110_fill_display_configs( 2394608ac7bbSJerry Zuo const struct dc_state *context, 2395cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg) 23964562236bSHarry Wentland { 2397cf437593SDmytro Laktyushkin int j; 2398cf437593SDmytro Laktyushkin int num_cfgs = 0; 2399cf437593SDmytro Laktyushkin 2400cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 2401cf437593SDmytro Laktyushkin int k; 2402cf437593SDmytro Laktyushkin 24030971c40eSHarry Wentland const struct dc_stream_state *stream = context->streams[j]; 2404cf437593SDmytro Laktyushkin struct dm_pp_single_disp_config *cfg = 2405cf437593SDmytro Laktyushkin &pp_display_cfg->disp_configs[num_cfgs]; 2406cf437593SDmytro Laktyushkin const struct pipe_ctx *pipe_ctx = NULL; 2407cf437593SDmytro Laktyushkin 2408cf437593SDmytro Laktyushkin for (k = 0; k < MAX_PIPES; k++) 2409cf437593SDmytro Laktyushkin if (stream == context->res_ctx.pipe_ctx[k].stream) { 2410cf437593SDmytro Laktyushkin pipe_ctx = &context->res_ctx.pipe_ctx[k]; 2411cf437593SDmytro Laktyushkin break; 24124562236bSHarry Wentland } 24134562236bSHarry Wentland 2414cf437593SDmytro Laktyushkin ASSERT(pipe_ctx != NULL); 2415cf437593SDmytro Laktyushkin 2416631aaa0aSHersen Wu /* only notify active stream */ 2417631aaa0aSHersen Wu if (stream->dpms_off) 2418631aaa0aSHersen Wu continue; 2419631aaa0aSHersen Wu 2420cf437593SDmytro Laktyushkin num_cfgs++; 2421cf437593SDmytro Laktyushkin cfg->signal = pipe_ctx->stream->signal; 2422e07f541fSYongqiang Sun cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; 24234fa086b9SLeo (Sunpeng) Li cfg->src_height = stream->src.height; 24244fa086b9SLeo (Sunpeng) Li cfg->src_width = stream->src.width; 2425cf437593SDmytro Laktyushkin cfg->ddi_channel_mapping = 2426cf437593SDmytro Laktyushkin stream->sink->link->ddi_channel_mapping.raw; 2427cf437593SDmytro Laktyushkin cfg->transmitter = 2428cf437593SDmytro Laktyushkin stream->sink->link->link_enc->transmitter; 2429cf437593SDmytro Laktyushkin cfg->link_settings.lane_count = 2430d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.lane_count; 2431cf437593SDmytro Laktyushkin cfg->link_settings.link_rate = 2432d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.link_rate; 2433cf437593SDmytro Laktyushkin cfg->link_settings.link_spread = 2434d0778ebfSHarry Wentland stream->sink->link->cur_link_settings.link_spread; 2435cf437593SDmytro Laktyushkin cfg->sym_clock = stream->phy_pix_clk; 2436cf437593SDmytro Laktyushkin /* Round v_refresh*/ 24374fa086b9SLeo (Sunpeng) Li cfg->v_refresh = stream->timing.pix_clk_khz * 1000; 24384fa086b9SLeo (Sunpeng) Li cfg->v_refresh /= stream->timing.h_total; 24394fa086b9SLeo (Sunpeng) Li cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) 24404fa086b9SLeo (Sunpeng) Li / stream->timing.v_total; 2441cf437593SDmytro Laktyushkin } 2442cf437593SDmytro Laktyushkin 2443cf437593SDmytro Laktyushkin pp_display_cfg->display_count = num_cfgs; 2444cf437593SDmytro Laktyushkin } 2445cf437593SDmytro Laktyushkin 2446608ac7bbSJerry Zuo uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) 2447cf437593SDmytro Laktyushkin { 2448cf437593SDmytro Laktyushkin uint8_t j; 2449cf437593SDmytro Laktyushkin uint32_t min_vertical_blank_time = -1; 2450cf437593SDmytro Laktyushkin 2451cf437593SDmytro Laktyushkin for (j = 0; j < context->stream_count; j++) { 24520971c40eSHarry Wentland struct dc_stream_state *stream = context->streams[j]; 2453cf437593SDmytro Laktyushkin uint32_t vertical_blank_in_pixels = 0; 2454cf437593SDmytro Laktyushkin uint32_t vertical_blank_time = 0; 2455cf437593SDmytro Laktyushkin 2456cf437593SDmytro Laktyushkin vertical_blank_in_pixels = stream->timing.h_total * 2457cf437593SDmytro Laktyushkin (stream->timing.v_total 2458cf437593SDmytro Laktyushkin - stream->timing.v_addressable); 2459cf437593SDmytro Laktyushkin 2460cf437593SDmytro Laktyushkin vertical_blank_time = vertical_blank_in_pixels 2461cf437593SDmytro Laktyushkin * 1000 / stream->timing.pix_clk_khz; 2462cf437593SDmytro Laktyushkin 2463cf437593SDmytro Laktyushkin if (min_vertical_blank_time > vertical_blank_time) 2464cf437593SDmytro Laktyushkin min_vertical_blank_time = vertical_blank_time; 2465cf437593SDmytro Laktyushkin } 2466cf437593SDmytro Laktyushkin 2467cf437593SDmytro Laktyushkin return min_vertical_blank_time; 2468cf437593SDmytro Laktyushkin } 2469cf437593SDmytro Laktyushkin 2470cf437593SDmytro Laktyushkin static int determine_sclk_from_bounding_box( 2471fb3466a4SBhawanpreet Lakha const struct dc *dc, 2472cf437593SDmytro Laktyushkin int required_sclk) 24734562236bSHarry Wentland { 24744562236bSHarry Wentland int i; 24754562236bSHarry Wentland 2476cf437593SDmytro Laktyushkin /* 2477cf437593SDmytro Laktyushkin * Some asics do not give us sclk levels, so we just report the actual 2478cf437593SDmytro Laktyushkin * required sclk 2479cf437593SDmytro Laktyushkin */ 2480cf437593SDmytro Laktyushkin if (dc->sclk_lvls.num_levels == 0) 2481cf437593SDmytro Laktyushkin return required_sclk; 24824562236bSHarry Wentland 2483cf437593SDmytro Laktyushkin for (i = 0; i < dc->sclk_lvls.num_levels; i++) { 2484cf437593SDmytro Laktyushkin if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) 2485cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[i]; 2486cf437593SDmytro Laktyushkin } 2487cf437593SDmytro Laktyushkin /* 2488cf437593SDmytro Laktyushkin * even maximum level could not satisfy requirement, this 2489cf437593SDmytro Laktyushkin * is unexpected at this stage, should have been caught at 2490cf437593SDmytro Laktyushkin * validation time 2491cf437593SDmytro Laktyushkin */ 2492cf437593SDmytro Laktyushkin ASSERT(0); 2493cf437593SDmytro Laktyushkin return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; 24944562236bSHarry Wentland } 24954562236bSHarry Wentland 2496cf437593SDmytro Laktyushkin static void pplib_apply_display_requirements( 2497fb3466a4SBhawanpreet Lakha struct dc *dc, 2498608ac7bbSJerry Zuo struct dc_state *context) 2499cf437593SDmytro Laktyushkin { 2500cf437593SDmytro Laktyushkin struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; 2501cf437593SDmytro Laktyushkin 2502cf437593SDmytro Laktyushkin pp_display_cfg->all_displays_in_sync = 25039037d802SDmytro Laktyushkin context->bw.dce.all_displays_in_sync; 2504cf437593SDmytro Laktyushkin pp_display_cfg->nb_pstate_switch_disable = 25059037d802SDmytro Laktyushkin context->bw.dce.nbp_state_change_enable == false; 2506cf437593SDmytro Laktyushkin pp_display_cfg->cpu_cc6_disable = 25079037d802SDmytro Laktyushkin context->bw.dce.cpuc_state_change_enable == false; 2508cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_disable = 25099037d802SDmytro Laktyushkin context->bw.dce.cpup_state_change_enable == false; 2510cf437593SDmytro Laktyushkin pp_display_cfg->cpu_pstate_separation_time = 25119037d802SDmytro Laktyushkin context->bw.dce.blackout_recovery_time_us; 2512cf437593SDmytro Laktyushkin 25139037d802SDmytro Laktyushkin pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz 2514cf437593SDmytro Laktyushkin / MEMORY_TYPE_MULTIPLIER; 2515cf437593SDmytro Laktyushkin 2516cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( 2517cf437593SDmytro Laktyushkin dc, 25189037d802SDmytro Laktyushkin context->bw.dce.sclk_khz); 2519cf437593SDmytro Laktyushkin 2520cf437593SDmytro Laktyushkin pp_display_cfg->min_engine_clock_deep_sleep_khz 25219037d802SDmytro Laktyushkin = context->bw.dce.sclk_deep_sleep_khz; 2522cf437593SDmytro Laktyushkin 2523cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_us = 252428f72454SJordan Lazare dce110_get_min_vblank_time_us(context); 2525cf437593SDmytro Laktyushkin /* TODO: dce11.2*/ 2526cf437593SDmytro Laktyushkin pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; 2527cf437593SDmytro Laktyushkin 25289037d802SDmytro Laktyushkin pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz; 2529cf437593SDmytro Laktyushkin 253028f72454SJordan Lazare dce110_fill_display_configs(context, pp_display_cfg); 2531cf437593SDmytro Laktyushkin 2532cf437593SDmytro Laktyushkin /* TODO: is this still applicable?*/ 2533cf437593SDmytro Laktyushkin if (pp_display_cfg->display_count == 1) { 2534cf437593SDmytro Laktyushkin const struct dc_crtc_timing *timing = 25354fa086b9SLeo (Sunpeng) Li &context->streams[0]->timing; 2536cf437593SDmytro Laktyushkin 2537cf437593SDmytro Laktyushkin pp_display_cfg->crtc_index = 2538cf437593SDmytro Laktyushkin pp_display_cfg->disp_configs[0].pipe_idx; 2539cf437593SDmytro Laktyushkin pp_display_cfg->line_time_in_us = timing->h_total * 1000 2540cf437593SDmytro Laktyushkin / timing->pix_clk_khz; 2541cf437593SDmytro Laktyushkin } 2542cf437593SDmytro Laktyushkin 2543cf437593SDmytro Laktyushkin if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof( 2544cf437593SDmytro Laktyushkin struct dm_pp_display_configuration)) != 0) 2545cf437593SDmytro Laktyushkin dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); 2546cf437593SDmytro Laktyushkin 2547cf437593SDmytro Laktyushkin dc->prev_display_config = *pp_display_cfg; 2548cf437593SDmytro Laktyushkin } 2549cf437593SDmytro Laktyushkin 2550cf437593SDmytro Laktyushkin static void dce110_set_bandwidth( 2551fb3466a4SBhawanpreet Lakha struct dc *dc, 2552608ac7bbSJerry Zuo struct dc_state *context, 2553cf437593SDmytro Laktyushkin bool decrease_allowed) 2554cf437593SDmytro Laktyushkin { 2555fab55d61SDmytro Laktyushkin struct dc_clocks req_clks; 2556fab55d61SDmytro Laktyushkin 2557fab55d61SDmytro Laktyushkin req_clks.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100; 2558fab55d61SDmytro Laktyushkin req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context); 2559fab55d61SDmytro Laktyushkin 2560fab55d61SDmytro Laktyushkin if (decrease_allowed) 25612180e7ccSDmytro Laktyushkin dce110_set_displaymarks(dc, context); 2562fab55d61SDmytro Laktyushkin else 2563fab55d61SDmytro Laktyushkin dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2564cf437593SDmytro Laktyushkin 25656ca11246SDmytro Laktyushkin dc->res_pool->dccg->funcs->update_clocks( 25666ca11246SDmytro Laktyushkin dc->res_pool->dccg, 2567fab55d61SDmytro Laktyushkin &req_clks, 2568fab55d61SDmytro Laktyushkin decrease_allowed); 2569cf437593SDmytro Laktyushkin pplib_apply_display_requirements(dc, context); 25704562236bSHarry Wentland } 25714562236bSHarry Wentland 25724562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 2573fb3466a4SBhawanpreet Lakha struct dc *dc, struct pipe_ctx *pipe_ctx) 25744562236bSHarry Wentland { 257586a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 25764562236bSHarry Wentland struct pipe_ctx *old_pipe = NULL; 25773be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 25784562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 25794562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 258087ac8fb0SShirish S unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 25814562236bSHarry Wentland unsigned int i; 25825d4b05ddSBhawanpreet Lakha DC_LOGGER_INIT(); 25834562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 25844562236bSHarry Wentland 2585608ac7bbSJerry Zuo if (dc->current_state) 2586608ac7bbSJerry Zuo old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; 25874562236bSHarry Wentland 25884562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 25894562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 25904562236bSHarry Wentland 2591e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 25924562236bSHarry Wentland 25934562236bSHarry Wentland set_default_colors(pipe_ctx); 25944fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 25954562236bSHarry Wentland == true) { 25964562236bSHarry Wentland tbl_entry.color_space = 25974fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 25984562236bSHarry Wentland 25994562236bSHarry Wentland for (i = 0; i < 12; i++) 26004562236bSHarry Wentland tbl_entry.regval[i] = 26014fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 26024562236bSHarry Wentland 260386a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 260486a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 26054562236bSHarry Wentland } 26064562236bSHarry Wentland 26074fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 26084562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2609146a9f63SKrunoslav Kovac 2610146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2611146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2612146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 26134562236bSHarry Wentland } 26144562236bSHarry Wentland 261586a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 26164562236bSHarry Wentland 26176702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2618c1473558SAndrey Grodzovsky 26194562236bSHarry Wentland program_scaler(dc, pipe_ctx); 26204562236bSHarry Wentland 262187ac8fb0SShirish S /* fbc not applicable on Underlay pipe */ 262287ac8fb0SShirish S if (dc->fbc_compressor && old_pipe->stream && 262387ac8fb0SShirish S pipe_ctx->pipe_idx != underlay_idx) { 2624e008b0bcSRoman Li if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 2625e008b0bcSRoman Li dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2626e008b0bcSRoman Li else 2627e008b0bcSRoman Li enable_fbc(dc, dc->current_state); 2628e008b0bcSRoman Li } 2629e008b0bcSRoman Li 26304562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 26314562236bSHarry Wentland mi, 26323be5262eSHarry Wentland plane_state->format, 26333be5262eSHarry Wentland &plane_state->tiling_info, 26343be5262eSHarry Wentland &plane_state->plane_size, 26353be5262eSHarry Wentland plane_state->rotation, 2636624d7c47SYongqiang Sun NULL, 26374b28b76bSDmytro Laktyushkin false); 26384b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 26393be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 26404562236bSHarry Wentland 2641fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 26424562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 264386a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 26443be5262eSHarry Wentland plane_state->format, 26453be5262eSHarry Wentland &plane_state->tiling_info, 26463be5262eSHarry Wentland plane_state->rotation); 26474562236bSHarry Wentland 2648067c878aSYongqiang Sun /* Moved programming gamma from dc to hwss */ 2649405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update || 2650405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2651405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.gamma_change) 2652a6114e85SHarry Wentland dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); 2653405c50a0SAndrew Jiang 2654405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update) 2655a6114e85SHarry Wentland dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); 2656067c878aSYongqiang Sun 26571296423bSBhawanpreet Lakha DC_LOG_SURFACE( 26583032deb5SBhawanpreet Lakha "Pipe:%d %p: addr hi:0x%x, " 26594562236bSHarry Wentland "addr low:0x%x, " 26604562236bSHarry Wentland "src: %d, %d, %d," 26614562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 26624562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 26634562236bSHarry Wentland pipe_ctx->pipe_idx, 26643032deb5SBhawanpreet Lakha (void *) pipe_ctx->plane_state, 26653be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.high_part, 26663be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.low_part, 26673be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.x, 26683be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.y, 26693be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.width, 26703be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.height, 26713be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.x, 26723be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.y, 26733be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.width, 26743be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.height, 26753be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.x, 26763be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.y, 26773be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.width, 26783be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.height); 26794562236bSHarry Wentland 26801296423bSBhawanpreet Lakha DC_LOG_SURFACE( 26814562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 26824562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 26834562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 26844562236bSHarry Wentland pipe_ctx->pipe_idx, 26856702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.width, 26866702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.height, 26876702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.x, 26886702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.y, 26896702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.width, 26906702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.height, 26916702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.x, 26926702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.y); 26934562236bSHarry Wentland } 26944562236bSHarry Wentland 26954562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 2696fb3466a4SBhawanpreet Lakha struct dc *dc, 26973e9ad616SEric Yang const struct dc_stream_state *stream, 26983e9ad616SEric Yang int num_planes, 2699608ac7bbSJerry Zuo struct dc_state *context) 27004562236bSHarry Wentland { 27012194e3aeSRoman Li int i; 27024562236bSHarry Wentland 27033e9ad616SEric Yang if (num_planes == 0) 27044562236bSHarry Wentland return; 27054562236bSHarry Wentland 27063e9ad616SEric Yang for (i = 0; i < dc->res_pool->pipe_count; i++) { 27073dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 27083dc780ecSYongqiang Sun struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 27093dc780ecSYongqiang Sun 27102194e3aeSRoman Li if (stream == pipe_ctx->stream) { 27113dc780ecSYongqiang Sun if (!pipe_ctx->top_pipe && 27123dc780ecSYongqiang Sun (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) 27133dc780ecSYongqiang Sun dc->hwss.pipe_control_lock(dc, pipe_ctx, true); 27143e9ad616SEric Yang } 27153e9ad616SEric Yang } 27163e9ad616SEric Yang 2717a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 27184562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 27194562236bSHarry Wentland 2720a2607aefSHarry Wentland if (pipe_ctx->stream != stream) 27214562236bSHarry Wentland continue; 27224562236bSHarry Wentland 27233b21b6d2SJerry Zuo /* Need to allocate mem before program front end for Fiji */ 27243b21b6d2SJerry Zuo pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 27253b21b6d2SJerry Zuo pipe_ctx->plane_res.mi, 27263b21b6d2SJerry Zuo pipe_ctx->stream->timing.h_total, 27273b21b6d2SJerry Zuo pipe_ctx->stream->timing.v_total, 27283b21b6d2SJerry Zuo pipe_ctx->stream->timing.pix_clk_khz, 27293b21b6d2SJerry Zuo context->stream_count); 27303b21b6d2SJerry Zuo 27314562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 27324f804817SYongqiang Sun 27334f804817SYongqiang Sun dc->hwss.update_plane_addr(dc, pipe_ctx); 27344f804817SYongqiang Sun 2735b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 27364562236bSHarry Wentland 27374562236bSHarry Wentland } 27383dc780ecSYongqiang Sun 27393dc780ecSYongqiang Sun for (i = 0; i < dc->res_pool->pipe_count; i++) { 27403dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 27413dc780ecSYongqiang Sun struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 27423dc780ecSYongqiang Sun 27433dc780ecSYongqiang Sun if ((stream == pipe_ctx->stream) && 27443dc780ecSYongqiang Sun (!pipe_ctx->top_pipe) && 27453dc780ecSYongqiang Sun (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) 27463dc780ecSYongqiang Sun dc->hwss.pipe_control_lock(dc, pipe_ctx, false); 27473dc780ecSYongqiang Sun } 27484562236bSHarry Wentland } 27494562236bSHarry Wentland 2750e6c258cbSYongqiang Sun static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 27514562236bSHarry Wentland { 2752bc373a89SRoman Li int fe_idx = pipe_ctx->plane_res.mi ? 2753bc373a89SRoman Li pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2754e6c258cbSYongqiang Sun 27557950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 2756608ac7bbSJerry Zuo if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 27574562236bSHarry Wentland return; 27584562236bSHarry Wentland 27594562236bSHarry Wentland dc->hwss.enable_display_power_gating( 2760cfe4645eSDmytro Laktyushkin dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2761cfe4645eSDmytro Laktyushkin 2762cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2763cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]); 27644562236bSHarry Wentland } 27654562236bSHarry Wentland 27666be425f3SEric Yang static void dce110_wait_for_mpcc_disconnect( 2767fb3466a4SBhawanpreet Lakha struct dc *dc, 27686be425f3SEric Yang struct resource_pool *res_pool, 27696be425f3SEric Yang struct pipe_ctx *pipe_ctx) 2770b6762f0cSEric Yang { 2771b6762f0cSEric Yang /* do nothing*/ 2772b6762f0cSEric Yang } 2773b6762f0cSEric Yang 2774bdf9a1a0SYue Hin Lau static void program_csc_matrix(struct pipe_ctx *pipe_ctx, 2775bdf9a1a0SYue Hin Lau enum dc_color_space colorspace, 2776bdf9a1a0SYue Hin Lau uint16_t *matrix) 2777bdf9a1a0SYue Hin Lau { 2778bdf9a1a0SYue Hin Lau int i; 2779bdf9a1a0SYue Hin Lau struct out_csc_color_matrix tbl_entry; 2780bdf9a1a0SYue Hin Lau 2781bdf9a1a0SYue Hin Lau if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 2782bdf9a1a0SYue Hin Lau == true) { 2783bdf9a1a0SYue Hin Lau enum dc_color_space color_space = 2784bdf9a1a0SYue Hin Lau pipe_ctx->stream->output_color_space; 2785bdf9a1a0SYue Hin Lau 2786bdf9a1a0SYue Hin Lau //uint16_t matrix[12]; 2787bdf9a1a0SYue Hin Lau for (i = 0; i < 12; i++) 2788bdf9a1a0SYue Hin Lau tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 2789bdf9a1a0SYue Hin Lau 2790bdf9a1a0SYue Hin Lau tbl_entry.color_space = color_space; 2791bdf9a1a0SYue Hin Lau //tbl_entry.regval = matrix; 279286a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry); 2793bdf9a1a0SYue Hin Lau } 2794bdf9a1a0SYue Hin Lau } 2795bdf9a1a0SYue Hin Lau 279633fd17d9SEric Yang void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 279733fd17d9SEric Yang { 279833fd17d9SEric Yang struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 279933fd17d9SEric Yang struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 280033fd17d9SEric Yang struct mem_input *mi = pipe_ctx->plane_res.mi; 280133fd17d9SEric Yang struct dc_cursor_mi_param param = { 280233fd17d9SEric Yang .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz, 280333fd17d9SEric Yang .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz, 280439a9f4d8SDmytro Laktyushkin .viewport = pipe_ctx->plane_res.scl_data.viewport, 280539a9f4d8SDmytro Laktyushkin .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 280639a9f4d8SDmytro Laktyushkin .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 280739a9f4d8SDmytro Laktyushkin .rotation = pipe_ctx->plane_state->rotation 280833fd17d9SEric Yang }; 280933fd17d9SEric Yang 281033fd17d9SEric Yang if (pipe_ctx->plane_state->address.type 281133fd17d9SEric Yang == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 281233fd17d9SEric Yang pos_cpy.enable = false; 281333fd17d9SEric Yang 281433fd17d9SEric Yang if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 281533fd17d9SEric Yang pos_cpy.enable = false; 281633fd17d9SEric Yang 2817dc75dd70SRoman Li if (ipp->funcs->ipp_cursor_set_position) 281833fd17d9SEric Yang ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2819dc75dd70SRoman Li if (mi->funcs->set_cursor_position) 282033fd17d9SEric Yang mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 282133fd17d9SEric Yang } 282233fd17d9SEric Yang 282333fd17d9SEric Yang void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 282433fd17d9SEric Yang { 282533fd17d9SEric Yang struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 282633fd17d9SEric Yang 2827d1aaad05SHarry Wentland if (pipe_ctx->plane_res.ipp && 2828d1aaad05SHarry Wentland pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 282933fd17d9SEric Yang pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 283033fd17d9SEric Yang pipe_ctx->plane_res.ipp, attributes); 283133fd17d9SEric Yang 2832d1aaad05SHarry Wentland if (pipe_ctx->plane_res.mi && 2833d1aaad05SHarry Wentland pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 283433fd17d9SEric Yang pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 283533fd17d9SEric Yang pipe_ctx->plane_res.mi, attributes); 283633fd17d9SEric Yang 2837d1aaad05SHarry Wentland if (pipe_ctx->plane_res.xfm && 2838d1aaad05SHarry Wentland pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 283933fd17d9SEric Yang pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 284033fd17d9SEric Yang pipe_ctx->plane_res.xfm, attributes); 284133fd17d9SEric Yang } 284233fd17d9SEric Yang 28436bf52028SHersen Wu static void ready_shared_resources(struct dc *dc, struct dc_state *context) {} 284441f97c07SHersen Wu 284541f97c07SHersen Wu static void optimize_shared_resources(struct dc *dc) {} 284641f97c07SHersen Wu 28474562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 28481bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 2849bdf9a1a0SYue Hin Lau .program_csc_matrix = program_csc_matrix, 28504562236bSHarry Wentland .init_hw = init_hw, 28514562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 28524562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 28534562236bSHarry Wentland .update_plane_addr = update_plane_addr, 28544562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 2855d7194cf6SAric Cyr .set_input_transfer_func = dce110_set_input_transfer_func, 285690e508baSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 28574562236bSHarry Wentland .power_down = dce110_power_down, 28584562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 28594562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 2860fa2123dbSMikita Lipski .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 28614562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 28624562236bSHarry Wentland .enable_stream = dce110_enable_stream, 28634562236bSHarry Wentland .disable_stream = dce110_disable_stream, 28644562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 286541b49742SCharlene Liu .blank_stream = dce110_blank_stream, 28661a05873fSAnthony Koo .enable_audio_stream = dce110_enable_audio_stream, 28671a05873fSAnthony Koo .disable_audio_stream = dce110_disable_audio_stream, 28684562236bSHarry Wentland .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 28694562236bSHarry Wentland .enable_display_power_gating = dce110_enable_display_power_gating, 28707f914a62SYongqiang Sun .disable_plane = dce110_power_down_fe, 28714562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 28724562236bSHarry Wentland .set_bandwidth = dce110_set_bandwidth, 28734562236bSHarry Wentland .set_drr = set_drr, 287472ada5f7SEric Cook .get_position = get_position, 28754562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 287654e8695eSDmytro Laktyushkin .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 28773158223eSEric Bernstein .enable_stream_timing = dce110_enable_stream_timing, 287815e17335SCharlene Liu .setup_stereo = NULL, 287915e17335SCharlene Liu .set_avmute = dce110_set_avmute, 288041f97c07SHersen Wu .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 288141f97c07SHersen Wu .ready_shared_resources = ready_shared_resources, 288241f97c07SHersen Wu .optimize_shared_resources = optimize_shared_resources, 2883631aaa0aSHersen Wu .pplib_apply_display_requirements = pplib_apply_display_requirements, 288487401969SAndrew Jiang .edp_backlight_control = hwss_edp_backlight_control, 288587401969SAndrew Jiang .edp_power_control = hwss_edp_power_control, 2886904623eeSYongqiang Sun .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, 288733fd17d9SEric Yang .set_cursor_position = dce110_set_cursor_position, 288833fd17d9SEric Yang .set_cursor_attribute = dce110_set_cursor_attribute 28894562236bSHarry Wentland }; 28904562236bSHarry Wentland 2891c13b408bSDave Airlie void dce110_hw_sequencer_construct(struct dc *dc) 28924562236bSHarry Wentland { 28934562236bSHarry Wentland dc->hwss = dce110_funcs; 28944562236bSHarry Wentland } 28954562236bSHarry Wentland 2896