14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 25c366be54SSam Ravnborg 26c366be54SSam Ravnborg #include <linux/delay.h> 27c366be54SSam Ravnborg 284562236bSHarry Wentland #include "dm_services.h" 294562236bSHarry Wentland #include "dc.h" 304562236bSHarry Wentland #include "dc_bios_types.h" 314562236bSHarry Wentland #include "core_types.h" 324562236bSHarry Wentland #include "core_status.h" 334562236bSHarry Wentland #include "resource.h" 344562236bSHarry Wentland #include "dm_helpers.h" 354562236bSHarry Wentland #include "dce110_timing_generator.h" 3698489c02SLeo (Sunpeng) Li #include "dce/dce_hwseq.h" 3787401969SAndrew Jiang #include "gpio_service_interface.h" 384562236bSHarry Wentland 391663ae1cSBhawanpreet Lakha #include "dce110_compressor.h" 401663ae1cSBhawanpreet Lakha 414562236bSHarry Wentland #include "bios/bios_parser_helper.h" 424562236bSHarry Wentland #include "timing_generator.h" 434562236bSHarry Wentland #include "mem_input.h" 444562236bSHarry Wentland #include "opp.h" 454562236bSHarry Wentland #include "ipp.h" 464562236bSHarry Wentland #include "transform.h" 474562236bSHarry Wentland #include "stream_encoder.h" 484562236bSHarry Wentland #include "link_encoder.h" 4964d283cbSJimmy Kizito #include "link_enc_cfg.h" 5087401969SAndrew Jiang #include "link_hwss.h" 51f9fc6f39SMichael Strauss #include "dc_link_dp.h" 528fe44c08SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 5364b1d0e8SNicholas Kazlauskas #include "dccg.h" 5464b1d0e8SNicholas Kazlauskas #endif 554562236bSHarry Wentland #include "clock_source.h" 56dc88b4a6SEric Yang #include "clk_mgr.h" 575e7773a2SAnthony Koo #include "abm.h" 584562236bSHarry Wentland #include "audio.h" 5908b16886SZeyu Fan #include "reg_helper.h" 60d4caa72eSAnthony Koo #include "panel_cntl.h" 613550d622SLeo (Hanghong) Ma #include "inc/link_dpcd.h" 623550d622SLeo (Hanghong) Ma #include "dpcd_defs.h" 634562236bSHarry Wentland /* include DCE11 register header files */ 644562236bSHarry Wentland #include "dce/dce_11_0_d.h" 654562236bSHarry Wentland #include "dce/dce_11_0_sh_mask.h" 66e266fdf6SVitaly Prosyak #include "custom_float.h" 674562236bSHarry Wentland 684cac1e6dSYongqiang Sun #include "atomfirmware.h" 694cac1e6dSYongqiang Sun 70a76eb7d3SLee Jones #include "dcn10/dcn10_hw_sequencer.h" 716e4a14ccSLee Jones 7264cf26f0SIsabella Basso #include "dce110_hw_sequencer.h" 7364cf26f0SIsabella Basso 7478c77382SAnthony Koo #define GAMMA_HW_POINTS_NUM 256 7578c77382SAnthony Koo 7687401969SAndrew Jiang /* 7787401969SAndrew Jiang * All values are in milliseconds; 7887401969SAndrew Jiang * For eDP, after power-up/power/down, 7987401969SAndrew Jiang * 300/500 msec max. delay from LCDVCC to black video generation 8087401969SAndrew Jiang */ 8187401969SAndrew Jiang #define PANEL_POWER_UP_TIMEOUT 300 8287401969SAndrew Jiang #define PANEL_POWER_DOWN_TIMEOUT 500 8387401969SAndrew Jiang #define HPD_CHECK_INTERVAL 10 8496577cf8SHersen Wu #define OLED_POST_T7_DELAY 100 8596577cf8SHersen Wu #define OLED_PRE_T11_DELAY 150 8687401969SAndrew Jiang 875eefbc40SYue Hin Lau #define CTX \ 885eefbc40SYue Hin Lau hws->ctx 895d4b05ddSBhawanpreet Lakha 905d4b05ddSBhawanpreet Lakha #define DC_LOGGER_INIT() 915d4b05ddSBhawanpreet Lakha 925eefbc40SYue Hin Lau #define REG(reg)\ 935eefbc40SYue Hin Lau hws->regs->reg 945eefbc40SYue Hin Lau 955eefbc40SYue Hin Lau #undef FN 965eefbc40SYue Hin Lau #define FN(reg_name, field_name) \ 975eefbc40SYue Hin Lau hws->shifts->field_name, hws->masks->field_name 985eefbc40SYue Hin Lau 994562236bSHarry Wentland struct dce110_hw_seq_reg_offsets { 1004562236bSHarry Wentland uint32_t crtc; 1014562236bSHarry Wentland }; 1024562236bSHarry Wentland 1034562236bSHarry Wentland static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 1044562236bSHarry Wentland { 1054562236bSHarry Wentland .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1064562236bSHarry Wentland }, 1074562236bSHarry Wentland { 1084562236bSHarry Wentland .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1094562236bSHarry Wentland }, 1104562236bSHarry Wentland { 1114562236bSHarry Wentland .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1124562236bSHarry Wentland }, 1134562236bSHarry Wentland { 1144562236bSHarry Wentland .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 1154562236bSHarry Wentland } 1164562236bSHarry Wentland }; 1174562236bSHarry Wentland 1184562236bSHarry Wentland #define HW_REG_BLND(reg, id)\ 1194562236bSHarry Wentland (reg + reg_offsets[id].blnd) 1204562236bSHarry Wentland 1214562236bSHarry Wentland #define HW_REG_CRTC(reg, id)\ 1224562236bSHarry Wentland (reg + reg_offsets[id].crtc) 1234562236bSHarry Wentland 1244562236bSHarry Wentland #define MAX_WATERMARK 0xFFFF 1254562236bSHarry Wentland #define SAFE_NBP_MARK 0x7FFF 1264562236bSHarry Wentland 1274562236bSHarry Wentland /******************************************************************************* 1284562236bSHarry Wentland * Private definitions 1294562236bSHarry Wentland ******************************************************************************/ 1304562236bSHarry Wentland /***************************PIPE_CONTROL***********************************/ 1314562236bSHarry Wentland static void dce110_init_pte(struct dc_context *ctx) 1324562236bSHarry Wentland { 1334562236bSHarry Wentland uint32_t addr; 1344562236bSHarry Wentland uint32_t value = 0; 1354562236bSHarry Wentland uint32_t chunk_int = 0; 1364562236bSHarry Wentland uint32_t chunk_mul = 0; 1374562236bSHarry Wentland 1384562236bSHarry Wentland addr = mmUNP_DVMM_PTE_CONTROL; 1394562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1404562236bSHarry Wentland 1414562236bSHarry Wentland set_reg_field_value( 1424562236bSHarry Wentland value, 1434562236bSHarry Wentland 0, 1444562236bSHarry Wentland DVMM_PTE_CONTROL, 1454562236bSHarry Wentland DVMM_USE_SINGLE_PTE); 1464562236bSHarry Wentland 1474562236bSHarry Wentland set_reg_field_value( 1484562236bSHarry Wentland value, 1494562236bSHarry Wentland 1, 1504562236bSHarry Wentland DVMM_PTE_CONTROL, 1514562236bSHarry Wentland DVMM_PTE_BUFFER_MODE0); 1524562236bSHarry Wentland 1534562236bSHarry Wentland set_reg_field_value( 1544562236bSHarry Wentland value, 1554562236bSHarry Wentland 1, 1564562236bSHarry Wentland DVMM_PTE_CONTROL, 1574562236bSHarry Wentland DVMM_PTE_BUFFER_MODE1); 1584562236bSHarry Wentland 1594562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1604562236bSHarry Wentland 1614562236bSHarry Wentland addr = mmDVMM_PTE_REQ; 1624562236bSHarry Wentland value = dm_read_reg(ctx, addr); 1634562236bSHarry Wentland 1644562236bSHarry Wentland chunk_int = get_reg_field_value( 1654562236bSHarry Wentland value, 1664562236bSHarry Wentland DVMM_PTE_REQ, 1674562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1684562236bSHarry Wentland 1694562236bSHarry Wentland chunk_mul = get_reg_field_value( 1704562236bSHarry Wentland value, 1714562236bSHarry Wentland DVMM_PTE_REQ, 1724562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1734562236bSHarry Wentland 1744562236bSHarry Wentland if (chunk_int != 0x4 || chunk_mul != 0x4) { 1754562236bSHarry Wentland 1764562236bSHarry Wentland set_reg_field_value( 1774562236bSHarry Wentland value, 1784562236bSHarry Wentland 255, 1794562236bSHarry Wentland DVMM_PTE_REQ, 1804562236bSHarry Wentland MAX_PTEREQ_TO_ISSUE); 1814562236bSHarry Wentland 1824562236bSHarry Wentland set_reg_field_value( 1834562236bSHarry Wentland value, 1844562236bSHarry Wentland 4, 1854562236bSHarry Wentland DVMM_PTE_REQ, 1864562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_INT); 1874562236bSHarry Wentland 1884562236bSHarry Wentland set_reg_field_value( 1894562236bSHarry Wentland value, 1904562236bSHarry Wentland 4, 1914562236bSHarry Wentland DVMM_PTE_REQ, 1924562236bSHarry Wentland HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 1934562236bSHarry Wentland 1944562236bSHarry Wentland dm_write_reg(ctx, addr, value); 1954562236bSHarry Wentland } 1964562236bSHarry Wentland } 1974562236bSHarry Wentland /**************************************************************************/ 1984562236bSHarry Wentland 1994562236bSHarry Wentland static void enable_display_pipe_clock_gating( 2004562236bSHarry Wentland struct dc_context *ctx, 2014562236bSHarry Wentland bool clock_gating) 2024562236bSHarry Wentland { 2034562236bSHarry Wentland /*TODO*/ 2044562236bSHarry Wentland } 2054562236bSHarry Wentland 2064562236bSHarry Wentland static bool dce110_enable_display_power_gating( 207fb3466a4SBhawanpreet Lakha struct dc *dc, 2084562236bSHarry Wentland uint8_t controller_id, 2094562236bSHarry Wentland struct dc_bios *dcb, 2104562236bSHarry Wentland enum pipe_gating_control power_gating) 2114562236bSHarry Wentland { 2124562236bSHarry Wentland enum bp_result bp_result = BP_RESULT_OK; 2134562236bSHarry Wentland enum bp_pipe_control_action cntl; 2144562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 2154562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 2164562236bSHarry Wentland 2174562236bSHarry Wentland if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) 2184562236bSHarry Wentland return true; 2194562236bSHarry Wentland 2204562236bSHarry Wentland if (power_gating == PIPE_GATING_CONTROL_INIT) 2214562236bSHarry Wentland cntl = ASIC_PIPE_INIT; 2224562236bSHarry Wentland else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 2234562236bSHarry Wentland cntl = ASIC_PIPE_ENABLE; 2244562236bSHarry Wentland else 2254562236bSHarry Wentland cntl = ASIC_PIPE_DISABLE; 2264562236bSHarry Wentland 2274562236bSHarry Wentland if (controller_id == underlay_idx) 2284562236bSHarry Wentland controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 2294562236bSHarry Wentland 2304562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ 2314562236bSHarry Wentland 2324562236bSHarry Wentland bp_result = dcb->funcs->enable_disp_power_gating( 2334562236bSHarry Wentland dcb, controller_id + 1, cntl); 2344562236bSHarry Wentland 2354562236bSHarry Wentland /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 2364562236bSHarry Wentland * by default when command table is called 2374562236bSHarry Wentland * 2384562236bSHarry Wentland * Bios parser accepts controller_id = 6 as indicative of 2394562236bSHarry Wentland * underlay pipe in dce110. But we do not support more 2404562236bSHarry Wentland * than 3. 2414562236bSHarry Wentland */ 2424562236bSHarry Wentland if (controller_id < CONTROLLER_ID_MAX - 1) 2434562236bSHarry Wentland dm_write_reg(ctx, 2444562236bSHarry Wentland HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 2454562236bSHarry Wentland 0); 2464562236bSHarry Wentland } 2474562236bSHarry Wentland 2484562236bSHarry Wentland if (power_gating != PIPE_GATING_CONTROL_ENABLE) 2494562236bSHarry Wentland dce110_init_pte(ctx); 2504562236bSHarry Wentland 2514562236bSHarry Wentland if (bp_result == BP_RESULT_OK) 2524562236bSHarry Wentland return true; 2534562236bSHarry Wentland else 2544562236bSHarry Wentland return false; 2554562236bSHarry Wentland } 2564562236bSHarry Wentland 2574562236bSHarry Wentland static void build_prescale_params(struct ipp_prescale_params *prescale_params, 2583be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2594562236bSHarry Wentland { 2604562236bSHarry Wentland prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 2614562236bSHarry Wentland 2623be5262eSHarry Wentland switch (plane_state->format) { 2631352c779SNicholas Kazlauskas case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2641352c779SNicholas Kazlauskas prescale_params->scale = 0x2082; 2651352c779SNicholas Kazlauskas break; 2664562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2678693049aSTony Cheng case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2684562236bSHarry Wentland prescale_params->scale = 0x2020; 2694562236bSHarry Wentland break; 2704562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2714562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2724562236bSHarry Wentland prescale_params->scale = 0x2008; 2734562236bSHarry Wentland break; 2744562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 275050cd3d6SMario Kleiner case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 2764562236bSHarry Wentland case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2774562236bSHarry Wentland prescale_params->scale = 0x2000; 2784562236bSHarry Wentland break; 2794562236bSHarry Wentland default: 2804562236bSHarry Wentland ASSERT(false); 281d7194cf6SAric Cyr break; 2824562236bSHarry Wentland } 2834562236bSHarry Wentland } 2844562236bSHarry Wentland 285a6114e85SHarry Wentland static bool 28678c77382SAnthony Koo dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 2873be5262eSHarry Wentland const struct dc_plane_state *plane_state) 2884562236bSHarry Wentland { 28986a66c4eSHarry Wentland struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 2907b0c470fSLeo (Sunpeng) Li const struct dc_transfer_func *tf = NULL; 29190e508baSAnthony Koo struct ipp_prescale_params prescale_params = { 0 }; 29290e508baSAnthony Koo bool result = true; 29390e508baSAnthony Koo 29490e508baSAnthony Koo if (ipp == NULL) 29590e508baSAnthony Koo return false; 29690e508baSAnthony Koo 2973be5262eSHarry Wentland if (plane_state->in_transfer_func) 2983be5262eSHarry Wentland tf = plane_state->in_transfer_func; 29990e508baSAnthony Koo 3003be5262eSHarry Wentland build_prescale_params(&prescale_params, plane_state); 30190e508baSAnthony Koo ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 30290e508baSAnthony Koo 30384ffa801SLeo (Sunpeng) Li if (plane_state->gamma_correction && 30484ffa801SLeo (Sunpeng) Li !plane_state->gamma_correction->is_identity && 30584ffa801SLeo (Sunpeng) Li dce_use_lut(plane_state->format)) 3063be5262eSHarry Wentland ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); 307d7194cf6SAric Cyr 30890e508baSAnthony Koo if (tf == NULL) { 30990e508baSAnthony Koo /* Default case if no input transfer function specified */ 310a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 3117b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_PREDEFINED) { 3127b0c470fSLeo (Sunpeng) Li switch (tf->tf) { 31390e508baSAnthony Koo case TRANSFER_FUNCTION_SRGB: 314a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 31590e508baSAnthony Koo break; 31690e508baSAnthony Koo case TRANSFER_FUNCTION_BT709: 317a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 31890e508baSAnthony Koo break; 31990e508baSAnthony Koo case TRANSFER_FUNCTION_LINEAR: 320a6114e85SHarry Wentland ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 32190e508baSAnthony Koo break; 32290e508baSAnthony Koo case TRANSFER_FUNCTION_PQ: 32390e508baSAnthony Koo default: 32490e508baSAnthony Koo result = false; 325d7194cf6SAric Cyr break; 32690e508baSAnthony Koo } 3277b0c470fSLeo (Sunpeng) Li } else if (tf->type == TF_TYPE_BYPASS) { 32870063a59SAmy Zhang ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 32990e508baSAnthony Koo } else { 33090e508baSAnthony Koo /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 33190e508baSAnthony Koo result = false; 33290e508baSAnthony Koo } 33390e508baSAnthony Koo 33490e508baSAnthony Koo return result; 33590e508baSAnthony Koo } 33690e508baSAnthony Koo 337bd1be8e8SHarry Wentland static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 338fcd2f4bfSAmy Zhang struct curve_points *arr_points, 339fcd2f4bfSAmy Zhang uint32_t hw_points_num) 340fcd2f4bfSAmy Zhang { 341fcd2f4bfSAmy Zhang struct custom_float_format fmt; 342fcd2f4bfSAmy Zhang 343fcd2f4bfSAmy Zhang struct pwl_result_data *rgb = rgb_resulted; 344fcd2f4bfSAmy Zhang 345fcd2f4bfSAmy Zhang uint32_t i = 0; 346fcd2f4bfSAmy Zhang 347fcd2f4bfSAmy Zhang fmt.exponenta_bits = 6; 348fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 349fcd2f4bfSAmy Zhang fmt.sign = true; 350fcd2f4bfSAmy Zhang 351bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 352fcd2f4bfSAmy Zhang &arr_points[0].custom_float_x)) { 353fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 354fcd2f4bfSAmy Zhang return false; 355fcd2f4bfSAmy Zhang } 356fcd2f4bfSAmy Zhang 357bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 358fcd2f4bfSAmy Zhang &arr_points[0].custom_float_offset)) { 359fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 360fcd2f4bfSAmy Zhang return false; 361fcd2f4bfSAmy Zhang } 362fcd2f4bfSAmy Zhang 363bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 364fcd2f4bfSAmy Zhang &arr_points[0].custom_float_slope)) { 365fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 366fcd2f4bfSAmy Zhang return false; 367fcd2f4bfSAmy Zhang } 368fcd2f4bfSAmy Zhang 369fcd2f4bfSAmy Zhang fmt.mantissa_bits = 10; 370fcd2f4bfSAmy Zhang fmt.sign = false; 371fcd2f4bfSAmy Zhang 372bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 373fcd2f4bfSAmy Zhang &arr_points[1].custom_float_x)) { 374fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 375fcd2f4bfSAmy Zhang return false; 376fcd2f4bfSAmy Zhang } 377fcd2f4bfSAmy Zhang 378bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 379fcd2f4bfSAmy Zhang &arr_points[1].custom_float_y)) { 380fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 381fcd2f4bfSAmy Zhang return false; 382fcd2f4bfSAmy Zhang } 383fcd2f4bfSAmy Zhang 3844d06ccd0SHarry Wentland if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 3854d06ccd0SHarry Wentland &arr_points[1].custom_float_slope)) { 386fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 387fcd2f4bfSAmy Zhang return false; 388fcd2f4bfSAmy Zhang } 389fcd2f4bfSAmy Zhang 390fcd2f4bfSAmy Zhang fmt.mantissa_bits = 12; 391fcd2f4bfSAmy Zhang fmt.sign = true; 392fcd2f4bfSAmy Zhang 393fcd2f4bfSAmy Zhang while (i != hw_points_num) { 394bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->red, &fmt, 395fcd2f4bfSAmy Zhang &rgb->red_reg)) { 396fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 397fcd2f4bfSAmy Zhang return false; 398fcd2f4bfSAmy Zhang } 399fcd2f4bfSAmy Zhang 400bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->green, &fmt, 401fcd2f4bfSAmy Zhang &rgb->green_reg)) { 402fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 403fcd2f4bfSAmy Zhang return false; 404fcd2f4bfSAmy Zhang } 405fcd2f4bfSAmy Zhang 406bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->blue, &fmt, 407fcd2f4bfSAmy Zhang &rgb->blue_reg)) { 408fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 409fcd2f4bfSAmy Zhang return false; 410fcd2f4bfSAmy Zhang } 411fcd2f4bfSAmy Zhang 412bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 413fcd2f4bfSAmy Zhang &rgb->delta_red_reg)) { 414fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 415fcd2f4bfSAmy Zhang return false; 416fcd2f4bfSAmy Zhang } 417fcd2f4bfSAmy Zhang 418bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 419fcd2f4bfSAmy Zhang &rgb->delta_green_reg)) { 420fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 421fcd2f4bfSAmy Zhang return false; 422fcd2f4bfSAmy Zhang } 423fcd2f4bfSAmy Zhang 424bd1be8e8SHarry Wentland if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 425fcd2f4bfSAmy Zhang &rgb->delta_blue_reg)) { 426fcd2f4bfSAmy Zhang BREAK_TO_DEBUGGER(); 427fcd2f4bfSAmy Zhang return false; 428fcd2f4bfSAmy Zhang } 429fcd2f4bfSAmy Zhang 430fcd2f4bfSAmy Zhang ++rgb; 431fcd2f4bfSAmy Zhang ++i; 432fcd2f4bfSAmy Zhang } 433fcd2f4bfSAmy Zhang 434fcd2f4bfSAmy Zhang return true; 435fcd2f4bfSAmy Zhang } 436fcd2f4bfSAmy Zhang 43708616da5SLeo (Sunpeng) Li #define MAX_LOW_POINT 25 4388f8372c7SKrunoslav Kovac #define NUMBER_REGIONS 16 4398f8372c7SKrunoslav Kovac #define NUMBER_SW_SEGMENTS 16 4408f8372c7SKrunoslav Kovac 441b310b081SHarry Wentland static bool 442b310b081SHarry Wentland dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 443b310b081SHarry Wentland struct pwl_params *regamma_params) 444fcd2f4bfSAmy Zhang { 44523ae4f8eSAmy Zhang struct curve_points *arr_points; 44623ae4f8eSAmy Zhang struct pwl_result_data *rgb_resulted; 44723ae4f8eSAmy Zhang struct pwl_result_data *rgb; 44823ae4f8eSAmy Zhang struct pwl_result_data *rgb_plus_1; 449fcd2f4bfSAmy Zhang struct fixed31_32 y_r; 450fcd2f4bfSAmy Zhang struct fixed31_32 y_g; 451fcd2f4bfSAmy Zhang struct fixed31_32 y_b; 452fcd2f4bfSAmy Zhang struct fixed31_32 y1_min; 453fcd2f4bfSAmy Zhang struct fixed31_32 y3_max; 454fcd2f4bfSAmy Zhang 4558f8372c7SKrunoslav Kovac int32_t region_start, region_end; 4568f8372c7SKrunoslav Kovac uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 45723ae4f8eSAmy Zhang 458b310b081SHarry Wentland if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 45923ae4f8eSAmy Zhang return false; 46023ae4f8eSAmy Zhang 46123ae4f8eSAmy Zhang arr_points = regamma_params->arr_points; 46223ae4f8eSAmy Zhang rgb_resulted = regamma_params->rgb_resulted; 46323ae4f8eSAmy Zhang hw_points = 0; 464fcd2f4bfSAmy Zhang 465fcd2f4bfSAmy Zhang memset(regamma_params, 0, sizeof(struct pwl_params)); 466fcd2f4bfSAmy Zhang 467fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 468534db198SAmy Zhang /* 16 segments 469fcd2f4bfSAmy Zhang * segments are from 2^-11 to 2^5 470fcd2f4bfSAmy Zhang */ 47108616da5SLeo (Sunpeng) Li region_start = -11; 47208616da5SLeo (Sunpeng) Li region_end = region_start + NUMBER_REGIONS; 473fcd2f4bfSAmy Zhang 4748f8372c7SKrunoslav Kovac for (i = 0; i < NUMBER_REGIONS; i++) 4758f8372c7SKrunoslav Kovac seg_distr[i] = 4; 476534db198SAmy Zhang 477fcd2f4bfSAmy Zhang } else { 478534db198SAmy Zhang /* 10 segments 479fc6de1c5SLeo (Sunpeng) Li * segment is from 2^-10 to 2^1 480fc6de1c5SLeo (Sunpeng) Li * We include an extra segment for range [2^0, 2^1). This is to 481fc6de1c5SLeo (Sunpeng) Li * ensure that colors with normalized values of 1 don't miss the 482fc6de1c5SLeo (Sunpeng) Li * LUT. 483fcd2f4bfSAmy Zhang */ 4848f8372c7SKrunoslav Kovac region_start = -10; 485fc6de1c5SLeo (Sunpeng) Li region_end = 1; 486534db198SAmy Zhang 4878f8372c7SKrunoslav Kovac seg_distr[0] = 4; 488534db198SAmy Zhang seg_distr[1] = 4; 489534db198SAmy Zhang seg_distr[2] = 4; 490534db198SAmy Zhang seg_distr[3] = 4; 491534db198SAmy Zhang seg_distr[4] = 4; 492534db198SAmy Zhang seg_distr[5] = 4; 493534db198SAmy Zhang seg_distr[6] = 4; 494534db198SAmy Zhang seg_distr[7] = 4; 4958f8372c7SKrunoslav Kovac seg_distr[8] = 4; 4968f8372c7SKrunoslav Kovac seg_distr[9] = 4; 497fc6de1c5SLeo (Sunpeng) Li seg_distr[10] = 0; 498534db198SAmy Zhang seg_distr[11] = -1; 499534db198SAmy Zhang seg_distr[12] = -1; 500534db198SAmy Zhang seg_distr[13] = -1; 501534db198SAmy Zhang seg_distr[14] = -1; 502534db198SAmy Zhang seg_distr[15] = -1; 503fcd2f4bfSAmy Zhang } 504fcd2f4bfSAmy Zhang 505534db198SAmy Zhang for (k = 0; k < 16; k++) { 506534db198SAmy Zhang if (seg_distr[k] != -1) 507534db198SAmy Zhang hw_points += (1 << seg_distr[k]); 508534db198SAmy Zhang } 509534db198SAmy Zhang 510fcd2f4bfSAmy Zhang j = 0; 5118f8372c7SKrunoslav Kovac for (k = 0; k < (region_end - region_start); k++) { 512ec47734aSLeo (Sunpeng) Li increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 5138f8372c7SKrunoslav Kovac start_index = (region_start + k + MAX_LOW_POINT) * 5148f8372c7SKrunoslav Kovac NUMBER_SW_SEGMENTS; 5158f8372c7SKrunoslav Kovac for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 5168f8372c7SKrunoslav Kovac i += increment) { 517534db198SAmy Zhang if (j == hw_points - 1) 518fcd2f4bfSAmy Zhang break; 519fcd2f4bfSAmy Zhang rgb_resulted[j].red = output_tf->tf_pts.red[i]; 520fcd2f4bfSAmy Zhang rgb_resulted[j].green = output_tf->tf_pts.green[i]; 521fcd2f4bfSAmy Zhang rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 522fcd2f4bfSAmy Zhang j++; 523fcd2f4bfSAmy Zhang } 524534db198SAmy Zhang } 525534db198SAmy Zhang 526534db198SAmy Zhang /* last point */ 5278f8372c7SKrunoslav Kovac start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 528b310b081SHarry Wentland rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 529b310b081SHarry Wentland rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 530b310b081SHarry Wentland rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 531fcd2f4bfSAmy Zhang 532eb0e5154SDmytro Laktyushkin arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 533eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_start)); 534eb0e5154SDmytro Laktyushkin arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 535eb0e5154SDmytro Laktyushkin dc_fixpt_from_int(region_end)); 536fcd2f4bfSAmy Zhang 537fcd2f4bfSAmy Zhang y_r = rgb_resulted[0].red; 538fcd2f4bfSAmy Zhang y_g = rgb_resulted[0].green; 539fcd2f4bfSAmy Zhang y_b = rgb_resulted[0].blue; 540fcd2f4bfSAmy Zhang 541eb0e5154SDmytro Laktyushkin y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 542fcd2f4bfSAmy Zhang 543fcd2f4bfSAmy Zhang arr_points[0].y = y1_min; 544eb0e5154SDmytro Laktyushkin arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 545fcd2f4bfSAmy Zhang arr_points[0].x); 546fcd2f4bfSAmy Zhang 547fcd2f4bfSAmy Zhang y_r = rgb_resulted[hw_points - 1].red; 548fcd2f4bfSAmy Zhang y_g = rgb_resulted[hw_points - 1].green; 549fcd2f4bfSAmy Zhang y_b = rgb_resulted[hw_points - 1].blue; 550fcd2f4bfSAmy Zhang 551fcd2f4bfSAmy Zhang /* see comment above, m_arrPoints[1].y should be the Y value for the 552fcd2f4bfSAmy Zhang * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 553fcd2f4bfSAmy Zhang */ 554eb0e5154SDmytro Laktyushkin y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 555fcd2f4bfSAmy Zhang 556fcd2f4bfSAmy Zhang arr_points[1].y = y3_max; 557fcd2f4bfSAmy Zhang 558eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_zero; 559fcd2f4bfSAmy Zhang 560fcd2f4bfSAmy Zhang if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 561fcd2f4bfSAmy Zhang /* for PQ, we want to have a straight line from last HW X point, 562fcd2f4bfSAmy Zhang * and the slope to be such that we hit 1.0 at 10000 nits. 563fcd2f4bfSAmy Zhang */ 564eb0e5154SDmytro Laktyushkin const struct fixed31_32 end_value = dc_fixpt_from_int(125); 565fcd2f4bfSAmy Zhang 566eb0e5154SDmytro Laktyushkin arr_points[1].slope = dc_fixpt_div( 567eb0e5154SDmytro Laktyushkin dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 568eb0e5154SDmytro Laktyushkin dc_fixpt_sub(end_value, arr_points[1].x)); 569fcd2f4bfSAmy Zhang } 570fcd2f4bfSAmy Zhang 571fcd2f4bfSAmy Zhang regamma_params->hw_points_num = hw_points; 572fcd2f4bfSAmy Zhang 57369133b89SAric Cyr k = 0; 57469133b89SAric Cyr for (i = 1; i < 16; i++) { 575534db198SAmy Zhang if (seg_distr[k] != -1) { 576b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 577534db198SAmy Zhang regamma_params->arr_curve_points[i].offset = 578b310b081SHarry Wentland regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 579fcd2f4bfSAmy Zhang } 58069133b89SAric Cyr k++; 581534db198SAmy Zhang } 582534db198SAmy Zhang 583534db198SAmy Zhang if (seg_distr[k] != -1) 584b310b081SHarry Wentland regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 585fcd2f4bfSAmy Zhang 58623ae4f8eSAmy Zhang rgb = rgb_resulted; 58723ae4f8eSAmy Zhang rgb_plus_1 = rgb_resulted + 1; 588fcd2f4bfSAmy Zhang 589fcd2f4bfSAmy Zhang i = 1; 590fcd2f4bfSAmy Zhang 591fcd2f4bfSAmy Zhang while (i != hw_points + 1) { 592eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 593fcd2f4bfSAmy Zhang rgb_plus_1->red = rgb->red; 594eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 595fcd2f4bfSAmy Zhang rgb_plus_1->green = rgb->green; 596eb0e5154SDmytro Laktyushkin if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 597fcd2f4bfSAmy Zhang rgb_plus_1->blue = rgb->blue; 598fcd2f4bfSAmy Zhang 599eb0e5154SDmytro Laktyushkin rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 600eb0e5154SDmytro Laktyushkin rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 601eb0e5154SDmytro Laktyushkin rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 602fcd2f4bfSAmy Zhang 603fcd2f4bfSAmy Zhang ++rgb_plus_1; 604fcd2f4bfSAmy Zhang ++rgb; 605fcd2f4bfSAmy Zhang ++i; 606fcd2f4bfSAmy Zhang } 607fcd2f4bfSAmy Zhang 608fcd2f4bfSAmy Zhang convert_to_custom_float(rgb_resulted, arr_points, hw_points); 609fcd2f4bfSAmy Zhang 610fcd2f4bfSAmy Zhang return true; 611fcd2f4bfSAmy Zhang } 612fcd2f4bfSAmy Zhang 613a6114e85SHarry Wentland static bool 61478c77382SAnthony Koo dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 6150971c40eSHarry Wentland const struct dc_stream_state *stream) 61690e508baSAnthony Koo { 61786a66c4eSHarry Wentland struct transform *xfm = pipe_ctx->plane_res.xfm; 6184562236bSHarry Wentland 6197a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, true); 6207a09f5beSYue Hin Lau xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 6214562236bSHarry Wentland 6224fa086b9SLeo (Sunpeng) Li if (stream->out_transfer_func && 623efd52204SHarry Wentland stream->out_transfer_func->type == TF_TYPE_PREDEFINED && 624efd52204SHarry Wentland stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { 6257a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 626efd52204SHarry Wentland } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, 627efd52204SHarry Wentland &xfm->regamma_params)) { 6287a09f5beSYue Hin Lau xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 6297a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 6304562236bSHarry Wentland } else { 6317a09f5beSYue Hin Lau xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 6324562236bSHarry Wentland } 6334562236bSHarry Wentland 6347a09f5beSYue Hin Lau xfm->funcs->opp_power_on_regamma_lut(xfm, false); 6354562236bSHarry Wentland 636cc0cb445SLeon Elazar return true; 6374562236bSHarry Wentland } 6384562236bSHarry Wentland 6394562236bSHarry Wentland void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 6404562236bSHarry Wentland { 64102553f57SEric Bernstein bool is_hdmi_tmds; 6426f0db2dcSKrunoslav Kovac bool is_dp; 6436f0db2dcSKrunoslav Kovac 64486e2e1beSHersen Wu ASSERT(pipe_ctx->stream); 64586e2e1beSHersen Wu 6468e9c4c8cSHarry Wentland if (pipe_ctx->stream_res.stream_enc == NULL) 64786e2e1beSHersen Wu return; /* this is not root pipe */ 64886e2e1beSHersen Wu 64902553f57SEric Bernstein is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 6506f0db2dcSKrunoslav Kovac is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 6516f0db2dcSKrunoslav Kovac 65202553f57SEric Bernstein if (!is_hdmi_tmds && !is_dp) 6536f0db2dcSKrunoslav Kovac return; 6546f0db2dcSKrunoslav Kovac 65502553f57SEric Bernstein if (is_hdmi_tmds) 6568e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 6578e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 65896c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6596f0db2dcSKrunoslav Kovac else 6608e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 6618e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc, 66296c50c0dSHarry Wentland &pipe_ctx->stream_res.encoder_info_frame); 6634562236bSHarry Wentland } 6644562236bSHarry Wentland 6654562236bSHarry Wentland void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 6664562236bSHarry Wentland { 6674562236bSHarry Wentland enum dc_lane_count lane_count = 668ceb3dbb4SJun Lei pipe_ctx->stream->link->cur_link_settings.lane_count; 6694fa086b9SLeo (Sunpeng) Li struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 670ceb3dbb4SJun Lei struct dc_link *link = pipe_ctx->stream->link; 671f42ea55bSAnthony Koo const struct dc *dc = link->dc; 672f215a57dSEric Yang 6734562236bSHarry Wentland uint32_t active_total_with_borders; 6744562236bSHarry Wentland uint32_t early_control = 0; 6756b670fa9SHarry Wentland struct timing_generator *tg = pipe_ctx->stream_res.tg; 6764562236bSHarry Wentland 677f215a57dSEric Yang /* For MST, there are multiply stream go to only one link. 678f215a57dSEric Yang * connect DIG back_end to front_end while enable_stream and 679f215a57dSEric Yang * disconnect them during disable_stream 680f215a57dSEric Yang * BY this, it is logic clean to separate stream and link */ 681f215a57dSEric Yang link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 682f215a57dSEric Yang pipe_ctx->stream_res.stream_enc->id, true); 683f215a57dSEric Yang 684f42ea55bSAnthony Koo dc->hwss.update_info_frame(pipe_ctx); 685f215a57dSEric Yang 6864562236bSHarry Wentland /* enable early control to avoid corruption on DP monitor*/ 6874562236bSHarry Wentland active_total_with_borders = 6884562236bSHarry Wentland timing->h_addressable 6894562236bSHarry Wentland + timing->h_border_left 6904562236bSHarry Wentland + timing->h_border_right; 6914562236bSHarry Wentland 6924562236bSHarry Wentland if (lane_count != 0) 6934562236bSHarry Wentland early_control = active_total_with_borders % lane_count; 6944562236bSHarry Wentland 6954562236bSHarry Wentland if (early_control == 0) 6964562236bSHarry Wentland early_control = lane_count; 6974562236bSHarry Wentland 6984562236bSHarry Wentland tg->funcs->set_early_control(tg, early_control); 6994562236bSHarry Wentland 7004562236bSHarry Wentland /* enable audio only within mode set */ 701afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio != NULL) { 7024562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 7038e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 7044562236bSHarry Wentland } 7054562236bSHarry Wentland 706f215a57dSEric Yang 707f215a57dSEric Yang 7084562236bSHarry Wentland 7094562236bSHarry Wentland } 7104562236bSHarry Wentland 7115eefbc40SYue Hin Lau static enum bp_result link_transmitter_control( 71287401969SAndrew Jiang struct dc_bios *bios, 7135eefbc40SYue Hin Lau struct bp_transmitter_control *cntl) 7145eefbc40SYue Hin Lau { 7155eefbc40SYue Hin Lau enum bp_result result; 7165eefbc40SYue Hin Lau 71787401969SAndrew Jiang result = bios->funcs->transmitter_control(bios, cntl); 7185eefbc40SYue Hin Lau 7195eefbc40SYue Hin Lau return result; 7205eefbc40SYue Hin Lau } 7215eefbc40SYue Hin Lau 72287401969SAndrew Jiang /* 72387401969SAndrew Jiang * @brief 72487401969SAndrew Jiang * eDP only. 72587401969SAndrew Jiang */ 7268a31820bSMartin Leung void dce110_edp_wait_for_hpd_ready( 727069d418fSAndrew Jiang struct dc_link *link, 72887401969SAndrew Jiang bool power_up) 72987401969SAndrew Jiang { 730069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 731069d418fSAndrew Jiang struct graphics_object_id connector = link->link_enc->connector; 73287401969SAndrew Jiang struct gpio *hpd; 7336798d042SLewis Huang struct dc_sink *sink = link->local_sink; 73487401969SAndrew Jiang bool edp_hpd_high = false; 73587401969SAndrew Jiang uint32_t time_elapsed = 0; 73687401969SAndrew Jiang uint32_t timeout = power_up ? 73787401969SAndrew Jiang PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 73887401969SAndrew Jiang 73987401969SAndrew Jiang if (dal_graphics_object_id_get_connector_id(connector) 74087401969SAndrew Jiang != CONNECTOR_ID_EDP) { 74187401969SAndrew Jiang BREAK_TO_DEBUGGER(); 74287401969SAndrew Jiang return; 74387401969SAndrew Jiang } 74487401969SAndrew Jiang 74587401969SAndrew Jiang if (!power_up) 74687401969SAndrew Jiang /* 74787401969SAndrew Jiang * From KV, we will not HPD low after turning off VCC - 74887401969SAndrew Jiang * instead, we will check the SW timer in power_up(). 74987401969SAndrew Jiang */ 75087401969SAndrew Jiang return; 75187401969SAndrew Jiang 75287401969SAndrew Jiang /* 75387401969SAndrew Jiang * When we power on/off the eDP panel, 75487401969SAndrew Jiang * we need to wait until SENSE bit is high/low. 75587401969SAndrew Jiang */ 75687401969SAndrew Jiang 75787401969SAndrew Jiang /* obtain HPD */ 75887401969SAndrew Jiang /* TODO what to do with this? */ 75987401969SAndrew Jiang hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); 76087401969SAndrew Jiang 76187401969SAndrew Jiang if (!hpd) { 76287401969SAndrew Jiang BREAK_TO_DEBUGGER(); 76387401969SAndrew Jiang return; 76487401969SAndrew Jiang } 76587401969SAndrew Jiang 7666798d042SLewis Huang if (sink != NULL) { 7676798d042SLewis Huang if (sink->edid_caps.panel_patch.extra_t3_ms > 0) { 7686798d042SLewis Huang int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms; 7696798d042SLewis Huang 7706798d042SLewis Huang msleep(extra_t3_in_ms); 7716798d042SLewis Huang } 7726798d042SLewis Huang } 7736798d042SLewis Huang 77487401969SAndrew Jiang dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); 77587401969SAndrew Jiang 77687401969SAndrew Jiang /* wait until timeout or panel detected */ 77787401969SAndrew Jiang 77887401969SAndrew Jiang do { 77987401969SAndrew Jiang uint32_t detected = 0; 78087401969SAndrew Jiang 78187401969SAndrew Jiang dal_gpio_get_value(hpd, &detected); 78287401969SAndrew Jiang 78387401969SAndrew Jiang if (!(detected ^ power_up)) { 78487401969SAndrew Jiang edp_hpd_high = true; 78587401969SAndrew Jiang break; 78687401969SAndrew Jiang } 78787401969SAndrew Jiang 78887401969SAndrew Jiang msleep(HPD_CHECK_INTERVAL); 78987401969SAndrew Jiang 79087401969SAndrew Jiang time_elapsed += HPD_CHECK_INTERVAL; 79187401969SAndrew Jiang } while (time_elapsed < timeout); 79287401969SAndrew Jiang 79387401969SAndrew Jiang dal_gpio_close(hpd); 79487401969SAndrew Jiang 79587401969SAndrew Jiang dal_gpio_destroy_irq(&hpd); 79687401969SAndrew Jiang 79787401969SAndrew Jiang if (false == edp_hpd_high) { 7981296423bSBhawanpreet Lakha DC_LOG_ERROR( 79987401969SAndrew Jiang "%s: wait timed out!\n", __func__); 80087401969SAndrew Jiang } 80187401969SAndrew Jiang } 80287401969SAndrew Jiang 8038a31820bSMartin Leung void dce110_edp_power_control( 804069d418fSAndrew Jiang struct dc_link *link, 80587401969SAndrew Jiang bool power_up) 80687401969SAndrew Jiang { 807069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 80887401969SAndrew Jiang struct bp_transmitter_control cntl = { 0 }; 80987401969SAndrew Jiang enum bp_result bp_result; 81006ddcee4SJake Wang uint8_t panel_instance; 81187401969SAndrew Jiang 81287401969SAndrew Jiang 813069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 81487401969SAndrew Jiang != CONNECTOR_ID_EDP) { 81587401969SAndrew Jiang BREAK_TO_DEBUGGER(); 81687401969SAndrew Jiang return; 81787401969SAndrew Jiang } 81887401969SAndrew Jiang 819ffadb9d6SAnthony Koo if (!link->panel_cntl) 820904fb6e0SAnthony Koo return; 821d4caa72eSAnthony Koo if (power_up != 822d4caa72eSAnthony Koo link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 823172c9b77SAshley Thomas 82478d5d04dSCharlene Liu unsigned long long current_ts = dm_get_timestamp(ctx); 825172c9b77SAshley Thomas unsigned long long time_since_edp_poweroff_ms = 82693ed1814SHugo Hu div64_u64(dm_get_elapse_time_in_ns( 82778d5d04dSCharlene Liu ctx, 82878d5d04dSCharlene Liu current_ts, 82993ed1814SHugo Hu link->link_trace.time_stamp.edp_poweroff), 1000000); 830172c9b77SAshley Thomas unsigned long long time_since_edp_poweron_ms = 831172c9b77SAshley Thomas div64_u64(dm_get_elapse_time_in_ns( 832172c9b77SAshley Thomas ctx, 833172c9b77SAshley Thomas current_ts, 834172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron), 1000000); 835172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 836172c9b77SAshley Thomas "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu", 837172c9b77SAshley Thomas __func__, 838172c9b77SAshley Thomas power_up, 839172c9b77SAshley Thomas current_ts, 840172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweroff, 841172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron, 842172c9b77SAshley Thomas time_since_edp_poweroff_ms, 843172c9b77SAshley Thomas time_since_edp_poweron_ms); 84478d5d04dSCharlene Liu 845172c9b77SAshley Thomas /* Send VBIOS command to prompt eDP panel power */ 846172c9b77SAshley Thomas if (power_up) { 847172c9b77SAshley Thomas /* edp requires a min of 500ms from LCDVDD off to on */ 848172c9b77SAshley Thomas unsigned long long remaining_min_edp_poweroff_time_ms = 500; 849ff587987SHugo Hu 850172c9b77SAshley Thomas /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ 8516c4fff06SYue Hin Lau if (link->local_sink != NULL) 852172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms += 853172c9b77SAshley Thomas link->local_sink->edid_caps.panel_patch.extra_t12_ms; 85478d5d04dSCharlene Liu 855172c9b77SAshley Thomas /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ 856172c9b77SAshley Thomas if (link->link_trace.time_stamp.edp_poweroff != 0) { 857172c9b77SAshley Thomas if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) 858172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms = 859172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; 860172c9b77SAshley Thomas else 861172c9b77SAshley Thomas remaining_min_edp_poweroff_time_ms = 0; 86278d5d04dSCharlene Liu } 86378d5d04dSCharlene Liu 864172c9b77SAshley Thomas if (remaining_min_edp_poweroff_time_ms) { 865172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 866172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", 867172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 868172c9b77SAshley Thomas msleep(remaining_min_edp_poweroff_time_ms); 869172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 870172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", 871172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 872172c9b77SAshley Thomas dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 873172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 874172c9b77SAshley Thomas } else { 875172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 876172c9b77SAshley Thomas "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n", 877172c9b77SAshley Thomas __func__, remaining_min_edp_poweroff_time_ms); 878172c9b77SAshley Thomas } 87978d5d04dSCharlene Liu } 88087401969SAndrew Jiang 8811296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 882172c9b77SAshley Thomas "%s: BEGIN: Panel Power action: %s\n", 88387401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 88487401969SAndrew Jiang 88587401969SAndrew Jiang cntl.action = power_up ? 88687401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_ON : 88787401969SAndrew Jiang TRANSMITTER_CONTROL_POWER_OFF; 888069d418fSAndrew Jiang cntl.transmitter = link->link_enc->transmitter; 889069d418fSAndrew Jiang cntl.connector_obj_id = link->link_enc->connector; 89087401969SAndrew Jiang cntl.coherent = false; 89187401969SAndrew Jiang cntl.lanes_number = LANE_COUNT_FOUR; 892069d418fSAndrew Jiang cntl.hpd_sel = link->link_enc->hpd_source; 89306ddcee4SJake Wang panel_instance = link->panel_cntl->inst; 8948a0e210cSChris Park 8958a0e210cSChris Park if (ctx->dc->ctx->dmub_srv && 8968a0e210cSChris Park ctx->dc->debug.dmub_command_table) { 8978a0e210cSChris Park if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) 8988a0e210cSChris Park bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 89906ddcee4SJake Wang LVTMA_CONTROL_POWER_ON, 90006ddcee4SJake Wang panel_instance); 9018a0e210cSChris Park else 9028a0e210cSChris Park bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 90306ddcee4SJake Wang LVTMA_CONTROL_POWER_OFF, 90406ddcee4SJake Wang panel_instance); 9058a0e210cSChris Park } 9068a0e210cSChris Park 90787401969SAndrew Jiang bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 90887401969SAndrew Jiang 909172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 910172c9b77SAshley Thomas "%s: END: Panel Power action: %s bp_result=%u\n", 911172c9b77SAshley Thomas __func__, (power_up ? "On":"Off"), 912172c9b77SAshley Thomas bp_result); 913172c9b77SAshley Thomas 91478d5d04dSCharlene Liu if (!power_up) 91578d5d04dSCharlene Liu /*save driver power off time stamp*/ 91678d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); 91778d5d04dSCharlene Liu else 91878d5d04dSCharlene Liu link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); 91978d5d04dSCharlene Liu 920172c9b77SAshley Thomas DC_LOG_HW_RESUME_S3( 921172c9b77SAshley Thomas "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n", 922172c9b77SAshley Thomas __func__, 923172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweroff, 924172c9b77SAshley Thomas link->link_trace.time_stamp.edp_poweron); 925172c9b77SAshley Thomas 92687401969SAndrew Jiang if (bp_result != BP_RESULT_OK) 9271296423bSBhawanpreet Lakha DC_LOG_ERROR( 92887401969SAndrew Jiang "%s: Panel Power bp_result: %d\n", 92987401969SAndrew Jiang __func__, bp_result); 93087401969SAndrew Jiang } else { 9311296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 93287401969SAndrew Jiang "%s: Skipping Panel Power action: %s\n", 93387401969SAndrew Jiang __func__, (power_up ? "On":"Off")); 93487401969SAndrew Jiang } 93587401969SAndrew Jiang } 9365eefbc40SYue Hin Lau 937cf3a2627SJun Lei void dce110_edp_wait_for_T12( 938cf3a2627SJun Lei struct dc_link *link) 939cf3a2627SJun Lei { 940cf3a2627SJun Lei struct dc_context *ctx = link->ctx; 941cf3a2627SJun Lei 942cf3a2627SJun Lei if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 943cf3a2627SJun Lei != CONNECTOR_ID_EDP) { 944cf3a2627SJun Lei BREAK_TO_DEBUGGER(); 945cf3a2627SJun Lei return; 946cf3a2627SJun Lei } 947cf3a2627SJun Lei 948cf3a2627SJun Lei if (!link->panel_cntl) 949cf3a2627SJun Lei return; 950cf3a2627SJun Lei 951cf3a2627SJun Lei if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && 952cf3a2627SJun Lei link->link_trace.time_stamp.edp_poweroff != 0) { 953cf3a2627SJun Lei unsigned int t12_duration = 500; // Default T12 as per spec 954cf3a2627SJun Lei unsigned long long current_ts = dm_get_timestamp(ctx); 955cf3a2627SJun Lei unsigned long long time_since_edp_poweroff_ms = 956cf3a2627SJun Lei div64_u64(dm_get_elapse_time_in_ns( 957cf3a2627SJun Lei ctx, 958cf3a2627SJun Lei current_ts, 959cf3a2627SJun Lei link->link_trace.time_stamp.edp_poweroff), 1000000); 960cf3a2627SJun Lei 961cf3a2627SJun Lei t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12 962cf3a2627SJun Lei 963cf3a2627SJun Lei if (time_since_edp_poweroff_ms < t12_duration) 964cf3a2627SJun Lei msleep(t12_duration - time_since_edp_poweroff_ms); 965cf3a2627SJun Lei } 966cf3a2627SJun Lei } 967cf3a2627SJun Lei 9685eefbc40SYue Hin Lau /*todo: cloned in stream enc, fix*/ 9695eefbc40SYue Hin Lau /* 9705eefbc40SYue Hin Lau * @brief 9715eefbc40SYue Hin Lau * eDP only. Control the backlight of the eDP panel 9725eefbc40SYue Hin Lau */ 9738a31820bSMartin Leung void dce110_edp_backlight_control( 9745eefbc40SYue Hin Lau struct dc_link *link, 9755eefbc40SYue Hin Lau bool enable) 9765eefbc40SYue Hin Lau { 977069d418fSAndrew Jiang struct dc_context *ctx = link->ctx; 9785eefbc40SYue Hin Lau struct bp_transmitter_control cntl = { 0 }; 97906ddcee4SJake Wang uint8_t panel_instance; 9805eefbc40SYue Hin Lau 981069d418fSAndrew Jiang if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 9825eefbc40SYue Hin Lau != CONNECTOR_ID_EDP) { 9835eefbc40SYue Hin Lau BREAK_TO_DEBUGGER(); 9845eefbc40SYue Hin Lau return; 9855eefbc40SYue Hin Lau } 9865eefbc40SYue Hin Lau 987014427adSSherry if (link->panel_cntl) { 988014427adSSherry bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); 989014427adSSherry 990014427adSSherry if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { 9911296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 992014427adSSherry "%s: panel already powered up/off. Do nothing.\n", 9935eefbc40SYue Hin Lau __func__); 9945eefbc40SYue Hin Lau return; 9955eefbc40SYue Hin Lau } 996014427adSSherry } 9975eefbc40SYue Hin Lau 9985eefbc40SYue Hin Lau /* Send VBIOS command to control eDP panel backlight */ 9995eefbc40SYue Hin Lau 10001296423bSBhawanpreet Lakha DC_LOG_HW_RESUME_S3( 10015eefbc40SYue Hin Lau "%s: backlight action: %s\n", 10025eefbc40SYue Hin Lau __func__, (enable ? "On":"Off")); 10035eefbc40SYue Hin Lau 10045eefbc40SYue Hin Lau cntl.action = enable ? 10055eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_ON : 10065eefbc40SYue Hin Lau TRANSMITTER_CONTROL_BACKLIGHT_OFF; 100787401969SAndrew Jiang 10085eefbc40SYue Hin Lau /*cntl.engine_id = ctx->engine;*/ 10095eefbc40SYue Hin Lau cntl.transmitter = link->link_enc->transmitter; 10105eefbc40SYue Hin Lau cntl.connector_obj_id = link->link_enc->connector; 10115eefbc40SYue Hin Lau /*todo: unhardcode*/ 10125eefbc40SYue Hin Lau cntl.lanes_number = LANE_COUNT_FOUR; 10135eefbc40SYue Hin Lau cntl.hpd_sel = link->link_enc->hpd_source; 1014cf1835f0SCharlene Liu cntl.signal = SIGNAL_TYPE_EDP; 10155eefbc40SYue Hin Lau 10165eefbc40SYue Hin Lau /* For eDP, the following delays might need to be considered 10175eefbc40SYue Hin Lau * after link training completed: 10185eefbc40SYue Hin Lau * idle period - min. accounts for required BS-Idle pattern, 10195eefbc40SYue Hin Lau * max. allows for source frame synchronization); 10205eefbc40SYue Hin Lau * 50 msec max. delay from valid video data from source 10215eefbc40SYue Hin Lau * to video on dislpay or backlight enable. 10225eefbc40SYue Hin Lau * 10235eefbc40SYue Hin Lau * Disable the delay for now. 10245eefbc40SYue Hin Lau * Enable it in the future if necessary. 10255eefbc40SYue Hin Lau */ 10265eefbc40SYue Hin Lau /* dc_service_sleep_in_milliseconds(50); */ 10275180d4a4SCharlene Liu /*edp 1.2*/ 102806ddcee4SJake Wang panel_instance = link->panel_cntl->inst; 1029a5148245SZhan Liu 1030a5148245SZhan Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { 1031a5148245SZhan Liu if (!link->dc->config.edp_no_power_sequencing) 1032a5148245SZhan Liu /* 1033a5148245SZhan Liu * Sometimes, DP receiver chip power-controlled externally by an 1034a5148245SZhan Liu * Embedded Controller could be treated and used as eDP, 1035a5148245SZhan Liu * if it drives mobile display. In this case, 1036a5148245SZhan Liu * we shouldn't be doing power-sequencing, hence we can skip 1037a5148245SZhan Liu * waiting for T7-ready. 1038a5148245SZhan Liu */ 10395180d4a4SCharlene Liu edp_receiver_ready_T7(link); 1040a5148245SZhan Liu else 1041a5148245SZhan Liu DC_LOG_DC("edp_receiver_ready_T7 skipped\n"); 1042a5148245SZhan Liu } 10438a0e210cSChris Park 10448a0e210cSChris Park if (ctx->dc->ctx->dmub_srv && 10458a0e210cSChris Park ctx->dc->debug.dmub_command_table) { 10468a0e210cSChris Park if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 10478a0e210cSChris Park ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 104806ddcee4SJake Wang LVTMA_CONTROL_LCD_BLON, 104906ddcee4SJake Wang panel_instance); 10508a0e210cSChris Park else 10518a0e210cSChris Park ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 105206ddcee4SJake Wang LVTMA_CONTROL_LCD_BLOFF, 105306ddcee4SJake Wang panel_instance); 10548a0e210cSChris Park } 10558a0e210cSChris Park 1056069d418fSAndrew Jiang link_transmitter_control(ctx->dc_bios, &cntl); 105796577cf8SHersen Wu 105896577cf8SHersen Wu if (enable && link->dpcd_sink_ext_caps.bits.oled) 105996577cf8SHersen Wu msleep(OLED_POST_T7_DELAY); 106096577cf8SHersen Wu 106196577cf8SHersen Wu if (link->dpcd_sink_ext_caps.bits.oled || 106296577cf8SHersen Wu link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 106396577cf8SHersen Wu link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 106496577cf8SHersen Wu dc_link_backlight_enable_aux(link, enable); 106596577cf8SHersen Wu 106669b9723aSCharlene Liu /*edp 1.2*/ 1067a5148245SZhan Liu if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) { 1068a5148245SZhan Liu if (!link->dc->config.edp_no_power_sequencing) 1069a5148245SZhan Liu /* 1070a5148245SZhan Liu * Sometimes, DP receiver chip power-controlled externally by an 1071a5148245SZhan Liu * Embedded Controller could be treated and used as eDP, 1072a5148245SZhan Liu * if it drives mobile display. In this case, 1073a5148245SZhan Liu * we shouldn't be doing power-sequencing, hence we can skip 1074a5148245SZhan Liu * waiting for T9-ready. 1075a5148245SZhan Liu */ 10763a372bedSHugo Hu edp_add_delay_for_T9(link); 1077a5148245SZhan Liu else 1078a5148245SZhan Liu DC_LOG_DC("edp_receiver_ready_T9 skipped\n"); 1079a5148245SZhan Liu } 108096577cf8SHersen Wu 108196577cf8SHersen Wu if (!enable && link->dpcd_sink_ext_caps.bits.oled) 108296577cf8SHersen Wu msleep(OLED_PRE_T11_DELAY); 10835eefbc40SYue Hin Lau } 10845eefbc40SYue Hin Lau 10851a05873fSAnthony Koo void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 10864562236bSHarry Wentland { 10871a05873fSAnthony Koo /* notify audio driver for audio modes of monitor */ 10882b77dcc5SAnthony Koo struct dc *dc; 10891d0610bcSAlvin Lee struct clk_mgr *clk_mgr; 10901a05873fSAnthony Koo unsigned int i, num_audio = 1; 10911a05873fSAnthony Koo 10921d0610bcSAlvin Lee if (!pipe_ctx->stream) 10931d0610bcSAlvin Lee return; 10941d0610bcSAlvin Lee 10952b77dcc5SAnthony Koo dc = pipe_ctx->stream->ctx->dc; 10962b77dcc5SAnthony Koo clk_mgr = dc->clk_mgr; 10971d0610bcSAlvin Lee 10980a32df9cSEryk Brol if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 10990a32df9cSEryk Brol return; 11000a32df9cSEryk Brol 11011a05873fSAnthony Koo if (pipe_ctx->stream_res.audio) { 11021a05873fSAnthony Koo for (i = 0; i < MAX_PIPES; i++) { 11031a05873fSAnthony Koo /*current_state not updated yet*/ 11042b77dcc5SAnthony Koo if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 11051a05873fSAnthony Koo num_audio++; 11061a05873fSAnthony Koo } 11071a05873fSAnthony Koo 11081a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 11091a05873fSAnthony Koo 1110170a2398SSu Sung Chung if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 11111a05873fSAnthony Koo /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1112170a2398SSu Sung Chung clk_mgr->funcs->enable_pme_wa(clk_mgr); 11131a05873fSAnthony Koo /* un-mute audio */ 11141a05873fSAnthony Koo /* TODO: audio should be per stream rather than per link */ 1115f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1116f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1117f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( 1118f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc, false); 1119f01ee019SFangzhi Zuo else 11201a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 11211a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, false); 1122f01ee019SFangzhi Zuo #else 1123f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 1124f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc, false); 1125f01ee019SFangzhi Zuo #endif 11260a32df9cSEryk Brol if (pipe_ctx->stream_res.audio) 11270a32df9cSEryk Brol pipe_ctx->stream_res.audio->enabled = true; 11281a05873fSAnthony Koo } 11293550d622SLeo (Hanghong) Ma 11303550d622SLeo (Hanghong) Ma if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11313550d622SLeo (Hanghong) Ma dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM); 11321a05873fSAnthony Koo } 11331a05873fSAnthony Koo 113457430404SSu Sung Chung void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 11351a05873fSAnthony Koo { 11361d0610bcSAlvin Lee struct dc *dc; 11371d0610bcSAlvin Lee struct clk_mgr *clk_mgr; 11381d0610bcSAlvin Lee 11391d0610bcSAlvin Lee if (!pipe_ctx || !pipe_ctx->stream) 11401d0610bcSAlvin Lee return; 11411d0610bcSAlvin Lee 11421d0610bcSAlvin Lee dc = pipe_ctx->stream->ctx->dc; 11431d0610bcSAlvin Lee clk_mgr = dc->clk_mgr; 11444562236bSHarry Wentland 11450a32df9cSEryk Brol if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 11460a32df9cSEryk Brol return; 11470a32df9cSEryk Brol 1148f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1149f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1150f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->audio_mute_control( 1151f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc, true); 1152f01ee019SFangzhi Zuo else 11532b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 11542b7c97d6SCharlene Liu pipe_ctx->stream_res.stream_enc, true); 1155f01ee019SFangzhi Zuo #else 1156f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( 1157f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc, true); 1158f01ee019SFangzhi Zuo #endif 1159afaacef4SHarry Wentland if (pipe_ctx->stream_res.audio) { 11603f52aa9fSNicholas Kazlauskas pipe_ctx->stream_res.audio->enabled = false; 11613f52aa9fSNicholas Kazlauskas 11624562236bSHarry Wentland if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1163f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1164f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1165f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_disable( 1166f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1167f01ee019SFangzhi Zuo else 11688e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 11698e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 1170f01ee019SFangzhi Zuo #else 1171f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( 1172f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc); 1173f01ee019SFangzhi Zuo #endif 11744562236bSHarry Wentland else 11758e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( 11768e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc); 117757430404SSu Sung Chung 1178170a2398SSu Sung Chung if (clk_mgr->funcs->enable_pme_wa) 1179070fe724SCharlene Liu /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1180170a2398SSu Sung Chung clk_mgr->funcs->enable_pme_wa(clk_mgr); 11814562236bSHarry Wentland 11824562236bSHarry Wentland /* TODO: notify audio driver for if audio modes list changed 11834562236bSHarry Wentland * add audio mode list change flag */ 11844562236bSHarry Wentland /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 11854562236bSHarry Wentland * stream->stream_engine_id); 11864562236bSHarry Wentland */ 11874562236bSHarry Wentland } 11883550d622SLeo (Hanghong) Ma 11893550d622SLeo (Hanghong) Ma if (dc_is_dp_signal(pipe_ctx->stream->signal)) 11903550d622SLeo (Hanghong) Ma dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM); 11911a05873fSAnthony Koo } 11924562236bSHarry Wentland 119357430404SSu Sung Chung void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 11941a05873fSAnthony Koo { 11951a05873fSAnthony Koo struct dc_stream_state *stream = pipe_ctx->stream; 1196ceb3dbb4SJun Lei struct dc_link *link = stream->link; 11971a05873fSAnthony Koo struct dc *dc = pipe_ctx->stream->ctx->dc; 119864d283cbSJimmy Kizito struct link_encoder *link_enc = NULL; 11991a05873fSAnthony Koo 1200ac42fd63SWenjing Liu if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 12011a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 12021a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 1203ac42fd63SWenjing Liu pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1204ac42fd63SWenjing Liu pipe_ctx->stream_res.stream_enc); 1205ac42fd63SWenjing Liu } 12061a05873fSAnthony Koo 1207f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1208f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) { 1209f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets( 1210f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1211f01ee019SFangzhi Zuo } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1212f01ee019SFangzhi Zuo #else 12131a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1214f01ee019SFangzhi Zuo #endif 12151a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 12161a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc); 12171a05873fSAnthony Koo 121857430404SSu Sung Chung dc->hwss.disable_audio_stream(pipe_ctx); 1219904623eeSYongqiang Sun 122064d283cbSJimmy Kizito /* Link encoder may have been dynamically assigned to non-physical display endpoint. */ 122164d283cbSJimmy Kizito if (link->ep_type == DISPLAY_ENDPOINT_PHY) 122264d283cbSJimmy Kizito link_enc = link->link_enc; 122364d283cbSJimmy Kizito else if (dc->res_pool->funcs->link_encs_assign) 12240d4b4253SJimmy Kizito link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link); 122564d283cbSJimmy Kizito ASSERT(link_enc); 122664d283cbSJimmy Kizito 1227f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1228f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) { 1229f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->disable( 1230f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1231f01ee019SFangzhi Zuo setup_dp_hpo_stream(pipe_ctx, false); 1232f01ee019SFangzhi Zuo /* TODO - DP2.0 HW: unmap stream from link encoder here */ 1233f01ee019SFangzhi Zuo } else { 123464d283cbSJimmy Kizito if (link_enc) 123564d283cbSJimmy Kizito link_enc->funcs->connect_dig_be_to_fe( 123664d283cbSJimmy Kizito link_enc, 12378e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->id, 12384562236bSHarry Wentland false); 1239f01ee019SFangzhi Zuo } 1240f01ee019SFangzhi Zuo #else 124164d283cbSJimmy Kizito if (link_enc) 124264d283cbSJimmy Kizito link_enc->funcs->connect_dig_be_to_fe( 1243f01ee019SFangzhi Zuo link->link_enc, 1244f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc->id, 1245f01ee019SFangzhi Zuo false); 1246f01ee019SFangzhi Zuo #endif 12473550d622SLeo (Hanghong) Ma if (dc_is_dp_signal(pipe_ctx->stream->signal)) 12483550d622SLeo (Hanghong) Ma dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE); 12490a068b68SJake Wang 12500a068b68SJake Wang #if defined(CONFIG_DRM_AMD_DC_DCN) 12510a068b68SJake Wang if (dc->hwseq->funcs.setup_hpo_hw_control && is_dp_128b_132b_signal(pipe_ctx)) 12520a068b68SJake Wang dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, false); 12530a068b68SJake Wang #endif 12540a068b68SJake Wang 12554562236bSHarry Wentland } 12564562236bSHarry Wentland 12574562236bSHarry Wentland void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 12584562236bSHarry Wentland struct dc_link_settings *link_settings) 12594562236bSHarry Wentland { 12604562236bSHarry Wentland struct encoder_unblank_param params = { { 0 } }; 126141b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1262ceb3dbb4SJun Lei struct dc_link *link = stream->link; 1263f42ea55bSAnthony Koo struct dce_hwseq *hws = link->dc->hwseq; 12644562236bSHarry Wentland 12654562236bSHarry Wentland /* only 3 items below are used by unblank */ 12667fe538a4SCharlene Liu params.timing = pipe_ctx->stream->timing; 12674562236bSHarry Wentland params.link_settings.link_rate = link_settings->link_rate; 126841b49742SCharlene Liu 126941b49742SCharlene Liu if (dc_is_dp_signal(pipe_ctx->stream->signal)) 12703550d622SLeo (Hanghong) Ma pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 127141b49742SCharlene Liu 127214d6f644SYongqiang Sun if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1273f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(link, true); 127414d6f644SYongqiang Sun } 127541b49742SCharlene Liu } 12762c850b7bSDmytro Laktyushkin 127741b49742SCharlene Liu void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 127841b49742SCharlene Liu { 127941b49742SCharlene Liu struct dc_stream_state *stream = pipe_ctx->stream; 1280ceb3dbb4SJun Lei struct dc_link *link = stream->link; 1281f42ea55bSAnthony Koo struct dce_hwseq *hws = link->dc->hwseq; 128241b49742SCharlene Liu 1283ab892598SRoman Li if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1284f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(link, false); 12853ba01817SYongqiang Sun link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1286ab892598SRoman Li } 128741b49742SCharlene Liu 1288f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1289f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) { 1290f01ee019SFangzhi Zuo /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1291f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank( 1292f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc); 1293f01ee019SFangzhi Zuo } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1294f01ee019SFangzhi Zuo #else 1295eec3303dSAric Cyr if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1296f01ee019SFangzhi Zuo #endif 12973550d622SLeo (Hanghong) Ma pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc); 1298eec3303dSAric Cyr 12993a372bedSHugo Hu if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { 1300eec3303dSAric Cyr /* 1301eec3303dSAric Cyr * After output is idle pattern some sinks need time to recognize the stream 1302eec3303dSAric Cyr * has changed or they enter protection state and hang. 1303eec3303dSAric Cyr */ 1304eec3303dSAric Cyr msleep(60); 13053a372bedSHugo Hu } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) 13063a372bedSHugo Hu edp_receiver_ready_T9(link); 1307eec3303dSAric Cyr } 1308eec3303dSAric Cyr 13094562236bSHarry Wentland } 13104562236bSHarry Wentland 131115e17335SCharlene Liu 131215e17335SCharlene Liu void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 131315e17335SCharlene Liu { 13148e9c4c8cSHarry Wentland if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 13158e9c4c8cSHarry Wentland pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 131615e17335SCharlene Liu } 131715e17335SCharlene Liu 13184562236bSHarry Wentland static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 13194562236bSHarry Wentland { 13204562236bSHarry Wentland switch (crtc_id) { 13214562236bSHarry Wentland case CONTROLLER_ID_D0: 13224562236bSHarry Wentland return DTO_SOURCE_ID0; 13234562236bSHarry Wentland case CONTROLLER_ID_D1: 13244562236bSHarry Wentland return DTO_SOURCE_ID1; 13254562236bSHarry Wentland case CONTROLLER_ID_D2: 13264562236bSHarry Wentland return DTO_SOURCE_ID2; 13274562236bSHarry Wentland case CONTROLLER_ID_D3: 13284562236bSHarry Wentland return DTO_SOURCE_ID3; 13294562236bSHarry Wentland case CONTROLLER_ID_D4: 13304562236bSHarry Wentland return DTO_SOURCE_ID4; 13314562236bSHarry Wentland case CONTROLLER_ID_D5: 13324562236bSHarry Wentland return DTO_SOURCE_ID5; 13334562236bSHarry Wentland default: 13344562236bSHarry Wentland return DTO_SOURCE_UNKNOWN; 13354562236bSHarry Wentland } 13364562236bSHarry Wentland } 13374562236bSHarry Wentland 13384562236bSHarry Wentland static void build_audio_output( 1339ab8db3e1SAndrey Grodzovsky struct dc_state *state, 13404562236bSHarry Wentland const struct pipe_ctx *pipe_ctx, 13414562236bSHarry Wentland struct audio_output *audio_output) 13424562236bSHarry Wentland { 13430971c40eSHarry Wentland const struct dc_stream_state *stream = pipe_ctx->stream; 13448e9c4c8cSHarry Wentland audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 13454562236bSHarry Wentland 13464562236bSHarry Wentland audio_output->signal = pipe_ctx->stream->signal; 13474562236bSHarry Wentland 13484562236bSHarry Wentland /* audio_crtc_info */ 13494562236bSHarry Wentland 13504562236bSHarry Wentland audio_output->crtc_info.h_total = 13514fa086b9SLeo (Sunpeng) Li stream->timing.h_total; 13524562236bSHarry Wentland 13534562236bSHarry Wentland /* 13544562236bSHarry Wentland * Audio packets are sent during actual CRTC blank physical signal, we 13554562236bSHarry Wentland * need to specify actual active signal portion 13564562236bSHarry Wentland */ 13574562236bSHarry Wentland audio_output->crtc_info.h_active = 13584fa086b9SLeo (Sunpeng) Li stream->timing.h_addressable 13594fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_left 13604fa086b9SLeo (Sunpeng) Li + stream->timing.h_border_right; 13614562236bSHarry Wentland 13624562236bSHarry Wentland audio_output->crtc_info.v_active = 13634fa086b9SLeo (Sunpeng) Li stream->timing.v_addressable 13644fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_top 13654fa086b9SLeo (Sunpeng) Li + stream->timing.v_border_bottom; 13664562236bSHarry Wentland 13674562236bSHarry Wentland audio_output->crtc_info.pixel_repetition = 1; 13684562236bSHarry Wentland 13694562236bSHarry Wentland audio_output->crtc_info.interlaced = 13704fa086b9SLeo (Sunpeng) Li stream->timing.flags.INTERLACE; 13714562236bSHarry Wentland 13724562236bSHarry Wentland audio_output->crtc_info.refresh_rate = 137340fd9090SNevenko Stupar (stream->timing.pix_clk_100hz*100)/ 13744fa086b9SLeo (Sunpeng) Li (stream->timing.h_total*stream->timing.v_total); 13754562236bSHarry Wentland 13764562236bSHarry Wentland audio_output->crtc_info.color_depth = 13774fa086b9SLeo (Sunpeng) Li stream->timing.display_color_depth; 13784562236bSHarry Wentland 137940fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz = 138040fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 13814562236bSHarry Wentland 138240fd9090SNevenko Stupar audio_output->crtc_info.calculated_pixel_clock_100Hz = 138340fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 13844562236bSHarry Wentland 138587b58768SCharlene Liu /*for HDMI, audio ACR is with deep color ratio factor*/ 13862166d9fbSCharlene Liu if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && 138740fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz == 138840fd9090SNevenko Stupar (stream->timing.pix_clk_100hz)) { 138910688217SHarry Wentland if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 139040fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz = 139140fd9090SNevenko Stupar audio_output->crtc_info.requested_pixel_clock_100Hz/2; 139240fd9090SNevenko Stupar audio_output->crtc_info.calculated_pixel_clock_100Hz = 139340fd9090SNevenko Stupar pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 139487b58768SCharlene Liu 139587b58768SCharlene Liu } 139687b58768SCharlene Liu } 139787b58768SCharlene Liu 1398ed476602SAhzo if (state->clk_mgr && 1399ed476602SAhzo (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1400ed476602SAhzo pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 14014562236bSHarry Wentland audio_output->pll_info.dp_dto_source_clock_in_khz = 14020de34efcSDmytro Laktyushkin state->clk_mgr->funcs->get_dp_ref_clk_frequency( 14030de34efcSDmytro Laktyushkin state->clk_mgr); 14044562236bSHarry Wentland } 14054562236bSHarry Wentland 14064562236bSHarry Wentland audio_output->pll_info.feed_back_divider = 14074562236bSHarry Wentland pipe_ctx->pll_settings.feedback_divider; 14084562236bSHarry Wentland 14094562236bSHarry Wentland audio_output->pll_info.dto_source = 14104562236bSHarry Wentland translate_to_dto_source( 1411e07f541fSYongqiang Sun pipe_ctx->stream_res.tg->inst + 1); 14124562236bSHarry Wentland 14134562236bSHarry Wentland /* TODO hard code to enable for now. Need get from stream */ 14144562236bSHarry Wentland audio_output->pll_info.ss_enabled = true; 14154562236bSHarry Wentland 14164562236bSHarry Wentland audio_output->pll_info.ss_percentage = 14174562236bSHarry Wentland pipe_ctx->pll_settings.ss_percentage; 14184562236bSHarry Wentland } 14194562236bSHarry Wentland 1420fb3466a4SBhawanpreet Lakha static void program_scaler(const struct dc *dc, 14214562236bSHarry Wentland const struct pipe_ctx *pipe_ctx) 14224562236bSHarry Wentland { 14234562236bSHarry Wentland struct tg_color color = {0}; 14244562236bSHarry Wentland 1425b86a1aa3SBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC_DCN) 1426ff5ef992SAlex Deucher /* TOFPGA */ 142786a66c4eSHarry Wentland if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1428ff5ef992SAlex Deucher return; 1429ff5ef992SAlex Deucher #endif 1430ff5ef992SAlex Deucher 1431bf53769dSGloria Li if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 14324562236bSHarry Wentland get_surface_visual_confirm_color(pipe_ctx, &color); 14334562236bSHarry Wentland else 14344562236bSHarry Wentland color_space_to_black_color(dc, 14354fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space, 14364562236bSHarry Wentland &color); 14374562236bSHarry Wentland 143886a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 143986a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, 14406702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.depth, 14414562236bSHarry Wentland &pipe_ctx->stream->bit_depth_params); 14424562236bSHarry Wentland 144312750d16SEric Yang if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 144412750d16SEric Yang /* 144512750d16SEric Yang * The way 420 is packed, 2 channels carry Y component, 1 channel 144612750d16SEric Yang * alternate between Cb and Cr, so both channels need the pixel 144712750d16SEric Yang * value for Y 144812750d16SEric Yang */ 144912750d16SEric Yang if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 145012750d16SEric Yang color.color_r_cr = color.color_g_y; 145112750d16SEric Yang 14526b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 14536b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14544562236bSHarry Wentland &color); 145512750d16SEric Yang } 14564562236bSHarry Wentland 145786a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 14586702a9acSHarry Wentland &pipe_ctx->plane_res.scl_data); 14594562236bSHarry Wentland } 14604562236bSHarry Wentland 14613158223eSEric Bernstein static enum dc_status dce110_enable_stream_timing( 14624562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1463608ac7bbSJerry Zuo struct dc_state *context, 1464fb3466a4SBhawanpreet Lakha struct dc *dc) 14654562236bSHarry Wentland { 14660971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 1467608ac7bbSJerry Zuo struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 14684562236bSHarry Wentland pipe_ctx[pipe_ctx->pipe_idx]; 14694562236bSHarry Wentland struct tg_color black_color = {0}; 14704562236bSHarry Wentland 14714562236bSHarry Wentland if (!pipe_ctx_old->stream) { 14724562236bSHarry Wentland 14734562236bSHarry Wentland /* program blank color */ 14744562236bSHarry Wentland color_space_to_black_color(dc, 14754fa086b9SLeo (Sunpeng) Li stream->output_color_space, &black_color); 14766b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank_color( 14776b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14784562236bSHarry Wentland &black_color); 14794b5e7d62SHersen Wu 14804562236bSHarry Wentland /* 14814562236bSHarry Wentland * Must blank CRTC after disabling power gating and before any 14824562236bSHarry Wentland * programming, otherwise CRTC will be hung in bad state 14834562236bSHarry Wentland */ 14846b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 14854562236bSHarry Wentland 14864562236bSHarry Wentland if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 14874562236bSHarry Wentland pipe_ctx->clock_source, 148810688217SHarry Wentland &pipe_ctx->stream_res.pix_clk_params, 14894562236bSHarry Wentland &pipe_ctx->pll_settings)) { 14904562236bSHarry Wentland BREAK_TO_DEBUGGER(); 14914562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 14924562236bSHarry Wentland } 14934562236bSHarry Wentland 14946b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->program_timing( 14956b670fa9SHarry Wentland pipe_ctx->stream_res.tg, 14964fa086b9SLeo (Sunpeng) Li &stream->timing, 1497e7e10c46SDmytro Laktyushkin 0, 1498e7e10c46SDmytro Laktyushkin 0, 1499e7e10c46SDmytro Laktyushkin 0, 1500e7e10c46SDmytro Laktyushkin 0, 1501e7e10c46SDmytro Laktyushkin pipe_ctx->stream->signal, 15024562236bSHarry Wentland true); 15034562236bSHarry Wentland } 15044562236bSHarry Wentland 15054562236bSHarry Wentland if (!pipe_ctx_old->stream) { 15066b670fa9SHarry Wentland if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 15076b670fa9SHarry Wentland pipe_ctx->stream_res.tg)) { 15084562236bSHarry Wentland BREAK_TO_DEBUGGER(); 15094562236bSHarry Wentland return DC_ERROR_UNEXPECTED; 15104562236bSHarry Wentland } 15114562236bSHarry Wentland } 15124562236bSHarry Wentland 15134562236bSHarry Wentland return DC_OK; 15144562236bSHarry Wentland } 15154562236bSHarry Wentland 15164562236bSHarry Wentland static enum dc_status apply_single_controller_ctx_to_hw( 15174562236bSHarry Wentland struct pipe_ctx *pipe_ctx, 1518608ac7bbSJerry Zuo struct dc_state *context, 1519fb3466a4SBhawanpreet Lakha struct dc *dc) 15204562236bSHarry Wentland { 15210971c40eSHarry Wentland struct dc_stream_state *stream = pipe_ctx->stream; 15223550d622SLeo (Hanghong) Ma struct dc_link *link = stream->link; 15239c0fb8d4SAnthony Koo struct drr_params params = {0}; 15249c0fb8d4SAnthony Koo unsigned int event_triggers = 0; 1525b1f6d01cSDmytro Laktyushkin struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1526f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 15274562236bSHarry Wentland 1528f42ea55bSAnthony Koo if (hws->funcs.disable_stream_gating) { 1529f42ea55bSAnthony Koo hws->funcs.disable_stream_gating(dc, pipe_ctx); 1530240d09d0SGary Kattan } 1531240d09d0SGary Kattan 15321a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 15331a05873fSAnthony Koo struct audio_output audio_output; 15341a05873fSAnthony Koo 15351a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 15361a05873fSAnthony Koo 15371a05873fSAnthony Koo if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1538f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1539f01ee019SFangzhi Zuo if (is_dp_128b_132b_signal(pipe_ctx)) 1540f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( 1541f01ee019SFangzhi Zuo pipe_ctx->stream_res.hpo_dp_stream_enc, 1542f01ee019SFangzhi Zuo pipe_ctx->stream_res.audio->inst, 1543f01ee019SFangzhi Zuo &pipe_ctx->stream->audio_info); 1544f01ee019SFangzhi Zuo else 15451a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 15461a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 15471a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 15481a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 1549f01ee019SFangzhi Zuo #else 1550f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( 1551f01ee019SFangzhi Zuo pipe_ctx->stream_res.stream_enc, 1552f01ee019SFangzhi Zuo pipe_ctx->stream_res.audio->inst, 1553f01ee019SFangzhi Zuo &pipe_ctx->stream->audio_info); 1554f01ee019SFangzhi Zuo #endif 15551a05873fSAnthony Koo else 15561a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( 15571a05873fSAnthony Koo pipe_ctx->stream_res.stream_enc, 15581a05873fSAnthony Koo pipe_ctx->stream_res.audio->inst, 15591a05873fSAnthony Koo &pipe_ctx->stream->audio_info, 15601a05873fSAnthony Koo &audio_output.crtc_info); 15611a05873fSAnthony Koo 15621a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->az_configure( 15631a05873fSAnthony Koo pipe_ctx->stream_res.audio, 15641a05873fSAnthony Koo pipe_ctx->stream->signal, 15651a05873fSAnthony Koo &audio_output.crtc_info, 15661a05873fSAnthony Koo &pipe_ctx->stream->audio_info); 15671a05873fSAnthony Koo } 15681a05873fSAnthony Koo 1569a896f870SMeenakshikumar Somasundaram /* make sure no pipes syncd to the pipe being enabled */ 1570a896f870SMeenakshikumar Somasundaram if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic) 1571a896f870SMeenakshikumar Somasundaram check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); 1572a896f870SMeenakshikumar Somasundaram 1573f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1574f01ee019SFangzhi Zuo /* DCN3.1 FPGA Workaround 1575f01ee019SFangzhi Zuo * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1576f01ee019SFangzhi Zuo * To do so, move calling function enable_stream_timing to only be done AFTER calling 1577f01ee019SFangzhi Zuo * function core_link_enable_stream 1578f01ee019SFangzhi Zuo */ 1579f01ee019SFangzhi Zuo if (!(hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx))) 1580f01ee019SFangzhi Zuo #endif 15814562236bSHarry Wentland /* */ 1582d2d7885fSAnthony Koo /* Do not touch stream timing on seamless boot optimization. */ 1583d2d7885fSAnthony Koo if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1584f42ea55bSAnthony Koo hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 15854562236bSHarry Wentland 1586f42ea55bSAnthony Koo if (hws->funcs.setup_vupdate_interrupt) 1587f42ea55bSAnthony Koo hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1588a122b62dSAnthony Koo 15899c0fb8d4SAnthony Koo params.vertical_total_min = stream->adjust.v_total_min; 15909c0fb8d4SAnthony Koo params.vertical_total_max = stream->adjust.v_total_max; 15919c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_drr) 15929c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_drr( 15939c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg, ¶ms); 15949c0fb8d4SAnthony Koo 15959c0fb8d4SAnthony Koo // DRR should set trigger event to monitor surface update event 15969c0fb8d4SAnthony Koo if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 15979c0fb8d4SAnthony Koo event_triggers = 0x80; 15985b5abe95SAnthony Koo /* Event triggers and num frames initialized for DRR, but can be 15995b5abe95SAnthony Koo * later updated for PSR use. Note DRR trigger events are generated 16005b5abe95SAnthony Koo * regardless of whether num frames met. 16015b5abe95SAnthony Koo */ 16029c0fb8d4SAnthony Koo if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 16039c0fb8d4SAnthony Koo pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 16045b5abe95SAnthony Koo pipe_ctx->stream_res.tg, event_triggers, 2); 16059c0fb8d4SAnthony Koo 1606248cbed6SEric Bernstein if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) 1607d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1608d2c460e7Shersen wu pipe_ctx->stream_res.stream_enc, 1609d2c460e7Shersen wu pipe_ctx->stream_res.tg->inst); 1610aa9c4abeSNikola Cornij 1611430bb83dSXu, Jinze if (dc_is_dp_signal(pipe_ctx->stream->signal) && 1612430bb83dSXu, Jinze pipe_ctx->stream_res.stream_enc->funcs->reset_fifo) 1613430bb83dSXu, Jinze pipe_ctx->stream_res.stream_enc->funcs->reset_fifo( 1614430bb83dSXu, Jinze pipe_ctx->stream_res.stream_enc); 1615430bb83dSXu, Jinze 16163550d622SLeo (Hanghong) Ma if (dc_is_dp_signal(pipe_ctx->stream->signal)) 16173550d622SLeo (Hanghong) Ma dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG); 16183550d622SLeo (Hanghong) Ma 1619f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1620f0c4d997SCorbin McElhanney pipe_ctx->stream_res.opp, 1621f0c4d997SCorbin McElhanney COLOR_SPACE_YCBCR601, 1622f0c4d997SCorbin McElhanney stream->timing.display_color_depth, 1623661a8cd9SDmytro Laktyushkin stream->signal); 16244562236bSHarry Wentland 1625a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1626a6a6cb34SHarry Wentland pipe_ctx->stream_res.opp, 1627181a888fSCharlene Liu &stream->bit_depth_params, 1628181a888fSCharlene Liu &stream->clamping); 1629b1f6d01cSDmytro Laktyushkin while (odm_pipe) { 16307ed4e635SHarry Wentland odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 16317ed4e635SHarry Wentland odm_pipe->stream_res.opp, 16327ed4e635SHarry Wentland COLOR_SPACE_YCBCR601, 16337ed4e635SHarry Wentland stream->timing.display_color_depth, 16347ed4e635SHarry Wentland stream->signal); 16357ed4e635SHarry Wentland 16367ed4e635SHarry Wentland odm_pipe->stream_res.opp->funcs->opp_program_fmt( 16377ed4e635SHarry Wentland odm_pipe->stream_res.opp, 16387ed4e635SHarry Wentland &stream->bit_depth_params, 16397ed4e635SHarry Wentland &stream->clamping); 1640b1f6d01cSDmytro Laktyushkin odm_pipe = odm_pipe->next_odm_pipe; 16417ed4e635SHarry Wentland } 1642603767f9STony Cheng 16431e7e86c4SSamson Tam if (!stream->dpms_off) 1644ab8db3e1SAndrey Grodzovsky core_link_enable_stream(context, pipe_ctx); 16454562236bSHarry Wentland 1646f01ee019SFangzhi Zuo #if defined(CONFIG_DRM_AMD_DC_DCN) 1647f01ee019SFangzhi Zuo /* DCN3.1 FPGA Workaround 1648f01ee019SFangzhi Zuo * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1649f01ee019SFangzhi Zuo * To do so, move calling function enable_stream_timing to only be done AFTER calling 1650f01ee019SFangzhi Zuo * function core_link_enable_stream 1651f01ee019SFangzhi Zuo */ 1652f01ee019SFangzhi Zuo if (hws->wa.dp_hpo_and_otg_sequence && is_dp_128b_132b_signal(pipe_ctx)) { 1653f01ee019SFangzhi Zuo if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1654f01ee019SFangzhi Zuo hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1655f01ee019SFangzhi Zuo } 1656f01ee019SFangzhi Zuo #endif 1657f01ee019SFangzhi Zuo 16586702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 16594562236bSHarry Wentland 1660d1ebfdd8SWyatt Wood pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 166194267b3dSSylvia Tsai 16624562236bSHarry Wentland return DC_OK; 16634562236bSHarry Wentland } 16644562236bSHarry Wentland 16654562236bSHarry Wentland /******************************************************************************/ 16664562236bSHarry Wentland 1667fb3466a4SBhawanpreet Lakha static void power_down_encoders(struct dc *dc) 16684562236bSHarry Wentland { 1669ebd1e719SLeo (Hanghong) Ma int i; 1670b9b171ffSHersen Wu 16714562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 1672d4c2a96fSLewis Huang enum signal_type signal = dc->links[i]->connector_signal; 1673a0c38ebaSCharlene Liu 1674ebd1e719SLeo (Hanghong) Ma dc_link_blank_dp_stream(dc->links[i], false); 1675c494e579SAgustin Gutierrez 16764338ffa8SSung Lee if (signal != SIGNAL_TYPE_EDP) 16774338ffa8SSung Lee signal = SIGNAL_TYPE_NONE; 16784338ffa8SSung Lee 167964d283cbSJimmy Kizito if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY) 16804562236bSHarry Wentland dc->links[i]->link_enc->funcs->disable_output( 1681069d418fSAndrew Jiang dc->links[i]->link_enc, signal); 1682b56e90eaSPaul Hsieh 1683b56e90eaSPaul Hsieh dc->links[i]->link_status.link_active = false; 168407920450SJoshua Aberback memset(&dc->links[i]->cur_link_settings, 0, 168507920450SJoshua Aberback sizeof(dc->links[i]->cur_link_settings)); 16864562236bSHarry Wentland } 16874562236bSHarry Wentland } 16884562236bSHarry Wentland 1689fb3466a4SBhawanpreet Lakha static void power_down_controllers(struct dc *dc) 16904562236bSHarry Wentland { 16914562236bSHarry Wentland int i; 16924562236bSHarry Wentland 16937f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 16944562236bSHarry Wentland dc->res_pool->timing_generators[i]->funcs->disable_crtc( 16954562236bSHarry Wentland dc->res_pool->timing_generators[i]); 16964562236bSHarry Wentland } 16974562236bSHarry Wentland } 16984562236bSHarry Wentland 1699fb3466a4SBhawanpreet Lakha static void power_down_clock_sources(struct dc *dc) 17004562236bSHarry Wentland { 17014562236bSHarry Wentland int i; 17024562236bSHarry Wentland 17034562236bSHarry Wentland if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 17044562236bSHarry Wentland dc->res_pool->dp_clock_source) == false) 17054562236bSHarry Wentland dm_error("Failed to power down pll! (dp clk src)\n"); 17064562236bSHarry Wentland 17074562236bSHarry Wentland for (i = 0; i < dc->res_pool->clk_src_count; i++) { 17084562236bSHarry Wentland if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 17094562236bSHarry Wentland dc->res_pool->clock_sources[i]) == false) 17104562236bSHarry Wentland dm_error("Failed to power down pll! (clk src index=%d)\n", i); 17114562236bSHarry Wentland } 17124562236bSHarry Wentland } 17134562236bSHarry Wentland 1714fb3466a4SBhawanpreet Lakha static void power_down_all_hw_blocks(struct dc *dc) 17154562236bSHarry Wentland { 17164562236bSHarry Wentland power_down_encoders(dc); 17174562236bSHarry Wentland 17184562236bSHarry Wentland power_down_controllers(dc); 17194562236bSHarry Wentland 17204562236bSHarry Wentland power_down_clock_sources(dc); 17211663ae1cSBhawanpreet Lakha 17222f3bfb27SRoman Li if (dc->fbc_compressor) 17231663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 17244562236bSHarry Wentland } 17254562236bSHarry Wentland 17264562236bSHarry Wentland static void disable_vga_and_power_gate_all_controllers( 1727fb3466a4SBhawanpreet Lakha struct dc *dc) 17284562236bSHarry Wentland { 17294562236bSHarry Wentland int i; 17304562236bSHarry Wentland struct timing_generator *tg; 17314562236bSHarry Wentland struct dc_context *ctx = dc->ctx; 17324562236bSHarry Wentland 17337f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 17344562236bSHarry Wentland tg = dc->res_pool->timing_generators[i]; 17354562236bSHarry Wentland 17360a87425aSTony Cheng if (tg->funcs->disable_vga) 17374562236bSHarry Wentland tg->funcs->disable_vga(tg); 17387f93c1deSCharlene Liu } 17397f93c1deSCharlene Liu for (i = 0; i < dc->res_pool->pipe_count; i++) { 17404562236bSHarry Wentland /* Enable CLOCK gating for each pipe BEFORE controller 17414562236bSHarry Wentland * powergating. */ 17424562236bSHarry Wentland enable_display_pipe_clock_gating(ctx, 17434562236bSHarry Wentland true); 17444562236bSHarry Wentland 1745e6c258cbSYongqiang Sun dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 17467f914a62SYongqiang Sun dc->hwss.disable_plane(dc, 1747e6c258cbSYongqiang Sun &dc->current_state->res_ctx.pipe_ctx[i]); 17484562236bSHarry Wentland } 17494562236bSHarry Wentland } 17504562236bSHarry Wentland 17513de5aa81SSivapiriyanKumarasamy 175245a1261bSJake Wang static void get_edp_streams(struct dc_state *context, 175345a1261bSJake Wang struct dc_stream_state **edp_streams, 175445a1261bSJake Wang int *edp_stream_num) 17553de5aa81SSivapiriyanKumarasamy { 17563de5aa81SSivapiriyanKumarasamy int i; 17573de5aa81SSivapiriyanKumarasamy 175845a1261bSJake Wang *edp_stream_num = 0; 17593de5aa81SSivapiriyanKumarasamy for (i = 0; i < context->stream_count; i++) { 176045a1261bSJake Wang if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { 176145a1261bSJake Wang edp_streams[*edp_stream_num] = context->streams[i]; 176245a1261bSJake Wang if (++(*edp_stream_num) == MAX_NUM_EDP) 176345a1261bSJake Wang return; 17643de5aa81SSivapiriyanKumarasamy } 176545a1261bSJake Wang } 17663de5aa81SSivapiriyanKumarasamy } 17673de5aa81SSivapiriyanKumarasamy 176845a1261bSJake Wang static void get_edp_links_with_sink( 176925292028SYongqiang Sun struct dc *dc, 177045a1261bSJake Wang struct dc_link **edp_links_with_sink, 177145a1261bSJake Wang int *edp_with_sink_num) 177225292028SYongqiang Sun { 177325292028SYongqiang Sun int i; 177425292028SYongqiang Sun 177525292028SYongqiang Sun /* check if there is an eDP panel not in use */ 177645a1261bSJake Wang *edp_with_sink_num = 0; 177725292028SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 177825292028SYongqiang Sun if (dc->links[i]->local_sink && 177925292028SYongqiang Sun dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 178045a1261bSJake Wang edp_links_with_sink[*edp_with_sink_num] = dc->links[i]; 178145a1261bSJake Wang if (++(*edp_with_sink_num) == MAX_NUM_EDP) 178245a1261bSJake Wang return; 178325292028SYongqiang Sun } 178425292028SYongqiang Sun } 178525292028SYongqiang Sun } 178625292028SYongqiang Sun 17871c17952eSLee Jones /* 17884562236bSHarry Wentland * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 17894562236bSHarry Wentland * 1. Power down all DC HW blocks 17904562236bSHarry Wentland * 2. Disable VGA engine on all controllers 17914562236bSHarry Wentland * 3. Enable power gating for controller 17924562236bSHarry Wentland * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 17934562236bSHarry Wentland */ 179425292028SYongqiang Sun void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 17954562236bSHarry Wentland { 179645a1261bSJake Wang struct dc_link *edp_links_with_sink[MAX_NUM_EDP]; 179745a1261bSJake Wang struct dc_link *edp_links[MAX_NUM_EDP]; 179845a1261bSJake Wang struct dc_stream_state *edp_streams[MAX_NUM_EDP]; 179945a1261bSJake Wang struct dc_link *edp_link_with_sink = NULL; 180045a1261bSJake Wang struct dc_link *edp_link = NULL; 180145a1261bSJake Wang struct dce_hwseq *hws = dc->hwseq; 180245a1261bSJake Wang int edp_with_sink_num; 180345a1261bSJake Wang int edp_num; 180445a1261bSJake Wang int edp_stream_num; 180545a1261bSJake Wang int i; 1806be4b289fSSivapiriyanKumarasamy bool can_apply_edp_fast_boot = false; 1807ce72741bSAnthony Koo bool can_apply_seamless_boot = false; 18083de5aa81SSivapiriyanKumarasamy bool keep_edp_vdd_on = false; 18090eda55caSMichael Strauss DC_LOGGER_INIT(); 18100eda55caSMichael Strauss 181145a1261bSJake Wang 181245a1261bSJake Wang get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); 181345a1261bSJake Wang get_edp_links(dc, edp_links, &edp_num); 1814ce72741bSAnthony Koo 1815f42ea55bSAnthony Koo if (hws->funcs.init_pipes) 1816f42ea55bSAnthony Koo hws->funcs.init_pipes(dc, context); 1817be4b289fSSivapiriyanKumarasamy 181845a1261bSJake Wang get_edp_streams(context, edp_streams, &edp_stream_num); 18193de5aa81SSivapiriyanKumarasamy 1820be4b289fSSivapiriyanKumarasamy // Check fastboot support, disable on DCE8 because of blank screens 1821b9957475SBrandon Syu if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 && 1822be4b289fSSivapiriyanKumarasamy dc->ctx->dce_version != DCE_VERSION_8_1 && 1823be4b289fSSivapiriyanKumarasamy dc->ctx->dce_version != DCE_VERSION_8_3) { 182445a1261bSJake Wang for (i = 0; i < edp_num; i++) { 182545a1261bSJake Wang edp_link = edp_links[i]; 1826b9957475SBrandon Syu if (edp_link != edp_streams[0]->link) 1827b9957475SBrandon Syu continue; 1828be4b289fSSivapiriyanKumarasamy // enable fastboot if backend is enabled on eDP 18294fe38194SMario Limonciello if (edp_link->link_enc->funcs->is_dig_enabled && 18304fe38194SMario Limonciello edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 18314fe38194SMario Limonciello edp_link->link_status.link_active) { 1832*2b36afc6SMario Limonciello struct dc_stream_state *edp_stream = edp_streams[0]; 1833*2b36afc6SMario Limonciello 1834f9fc6f39SMichael Strauss can_apply_edp_fast_boot = !is_edp_ilr_optimization_required(edp_stream->link, &edp_stream->timing); 1835f9fc6f39SMichael Strauss edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot; 18360eda55caSMichael Strauss if (can_apply_edp_fast_boot) 18370eda55caSMichael Strauss DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n"); 1838f9fc6f39SMichael Strauss 183945a1261bSJake Wang break; 1840be4b289fSSivapiriyanKumarasamy } 1841be4b289fSSivapiriyanKumarasamy } 18423de5aa81SSivapiriyanKumarasamy // We are trying to enable eDP, don't power down VDD 1843b9957475SBrandon Syu if (can_apply_edp_fast_boot) 18443de5aa81SSivapiriyanKumarasamy keep_edp_vdd_on = true; 1845be4b289fSSivapiriyanKumarasamy } 1846be4b289fSSivapiriyanKumarasamy 1847be4b289fSSivapiriyanKumarasamy // Check seamless boot support 1848ce72741bSAnthony Koo for (i = 0; i < context->stream_count; i++) { 1849ce72741bSAnthony Koo if (context->streams[i]->apply_seamless_boot_optimization) { 1850ce72741bSAnthony Koo can_apply_seamless_boot = true; 1851ce72741bSAnthony Koo break; 1852ce72741bSAnthony Koo } 1853ce72741bSAnthony Koo } 18544cac1e6dSYongqiang Sun 1855be4b289fSSivapiriyanKumarasamy /* eDP should not have stream in resume from S4 and so even with VBios post 1856be4b289fSSivapiriyanKumarasamy * it should get turned off 18572c37e49aSYongqiang Sun */ 185845a1261bSJake Wang if (edp_with_sink_num) 185945a1261bSJake Wang edp_link_with_sink = edp_links_with_sink[0]; 186045a1261bSJake Wang 1861be4b289fSSivapiriyanKumarasamy if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 18623de5aa81SSivapiriyanKumarasamy if (edp_link_with_sink && !keep_edp_vdd_on) { 18634cac1e6dSYongqiang Sun /*turn off backlight before DP_blank and encoder powered down*/ 1864f42ea55bSAnthony Koo hws->funcs.edp_backlight_control(edp_link_with_sink, false); 1865c5fc7f59SCharlene Liu } 1866c5fc7f59SCharlene Liu /*resume from S3, no vbios posting, no need to power down again*/ 186725292028SYongqiang Sun power_down_all_hw_blocks(dc); 18684562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 18693de5aa81SSivapiriyanKumarasamy if (edp_link_with_sink && !keep_edp_vdd_on) 1870be4b289fSSivapiriyanKumarasamy dc->hwss.edp_power_control(edp_link_with_sink, false); 1871c5fc7f59SCharlene Liu } 18721c5ea40cSYao Wang1 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); 18734562236bSHarry Wentland } 18744562236bSHarry Wentland 18754562236bSHarry Wentland static uint32_t compute_pstate_blackout_duration( 18764562236bSHarry Wentland struct bw_fixed blackout_duration, 18770971c40eSHarry Wentland const struct dc_stream_state *stream) 18784562236bSHarry Wentland { 18794562236bSHarry Wentland uint32_t total_dest_line_time_ns; 18804562236bSHarry Wentland uint32_t pstate_blackout_duration_ns; 18814562236bSHarry Wentland 18824562236bSHarry Wentland pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; 18834562236bSHarry Wentland 18844562236bSHarry Wentland total_dest_line_time_ns = 1000000UL * 1885380604e2SKen Chalmers (stream->timing.h_total * 10) / 1886380604e2SKen Chalmers stream->timing.pix_clk_100hz + 18874562236bSHarry Wentland pstate_blackout_duration_ns; 18884562236bSHarry Wentland 18894562236bSHarry Wentland return total_dest_line_time_ns; 18904562236bSHarry Wentland } 18914562236bSHarry Wentland 1892f774b339SEric Yang static void dce110_set_displaymarks( 1893fb3466a4SBhawanpreet Lakha const struct dc *dc, 1894608ac7bbSJerry Zuo struct dc_state *context) 18954562236bSHarry Wentland { 18964562236bSHarry Wentland uint8_t i, num_pipes; 18974562236bSHarry Wentland unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 18984562236bSHarry Wentland 18994562236bSHarry Wentland for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 19004562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 19014562236bSHarry Wentland uint32_t total_dest_line_time_ns; 19024562236bSHarry Wentland 19034562236bSHarry Wentland if (pipe_ctx->stream == NULL) 19044562236bSHarry Wentland continue; 19054562236bSHarry Wentland 19064562236bSHarry Wentland total_dest_line_time_ns = compute_pstate_blackout_duration( 190777a4ea53SBhawanpreet Lakha dc->bw_vbios->blackout_duration, pipe_ctx->stream); 190886a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 190986a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 1910813d20dcSAidan Wood context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1911813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1912813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 1913813d20dcSAidan Wood context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 19144562236bSHarry Wentland total_dest_line_time_ns); 19154562236bSHarry Wentland if (i == underlay_idx) { 19164562236bSHarry Wentland num_pipes++; 191786a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 191886a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 1919813d20dcSAidan Wood context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 1920813d20dcSAidan Wood context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 1921813d20dcSAidan Wood context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 19224562236bSHarry Wentland total_dest_line_time_ns); 19234562236bSHarry Wentland } 19244562236bSHarry Wentland num_pipes++; 19254562236bSHarry Wentland } 19264562236bSHarry Wentland } 19274562236bSHarry Wentland 1928fab55d61SDmytro Laktyushkin void dce110_set_safe_displaymarks( 1929a2b8659dSTony Cheng struct resource_context *res_ctx, 1930a2b8659dSTony Cheng const struct resource_pool *pool) 19314562236bSHarry Wentland { 19324562236bSHarry Wentland int i; 1933a2b8659dSTony Cheng int underlay_idx = pool->underlay_pipe_index; 19349037d802SDmytro Laktyushkin struct dce_watermarks max_marks = { 19354562236bSHarry Wentland MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 19369037d802SDmytro Laktyushkin struct dce_watermarks nbp_marks = { 19374562236bSHarry Wentland SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 19383722c794SMikita Lipski struct dce_watermarks min_marks = { 0, 0, 0, 0}; 19394562236bSHarry Wentland 19404562236bSHarry Wentland for (i = 0; i < MAX_PIPES; i++) { 19418feabd03SYue Hin Lau if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 19424562236bSHarry Wentland continue; 19434562236bSHarry Wentland 194486a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 194586a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 19464562236bSHarry Wentland nbp_marks, 19474562236bSHarry Wentland max_marks, 19483722c794SMikita Lipski min_marks, 19494562236bSHarry Wentland max_marks, 19504562236bSHarry Wentland MAX_WATERMARK); 19518feabd03SYue Hin Lau 19524562236bSHarry Wentland if (i == underlay_idx) 195386a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 195486a66c4eSHarry Wentland res_ctx->pipe_ctx[i].plane_res.mi, 19554562236bSHarry Wentland nbp_marks, 19564562236bSHarry Wentland max_marks, 19574562236bSHarry Wentland max_marks, 19584562236bSHarry Wentland MAX_WATERMARK); 19598feabd03SYue Hin Lau 19604562236bSHarry Wentland } 19614562236bSHarry Wentland } 19624562236bSHarry Wentland 19634562236bSHarry Wentland /******************************************************************************* 19644562236bSHarry Wentland * Public functions 19654562236bSHarry Wentland ******************************************************************************/ 19664562236bSHarry Wentland 19674562236bSHarry Wentland static void set_drr(struct pipe_ctx **pipe_ctx, 196849c70eceSAlvin Lee int num_pipes, struct dc_crtc_timing_adjust adjust) 19694562236bSHarry Wentland { 19704562236bSHarry Wentland int i = 0; 19714562236bSHarry Wentland struct drr_params params = {0}; 197298e6436dSAnthony Koo // DRR should set trigger event to monitor surface update event 197398e6436dSAnthony Koo unsigned int event_triggers = 0x80; 19745b5abe95SAnthony Koo // Note DRR trigger events are generated regardless of whether num frames met. 19755b5abe95SAnthony Koo unsigned int num_frames = 2; 19764562236bSHarry Wentland 197749c70eceSAlvin Lee params.vertical_total_max = adjust.v_total_max; 197849c70eceSAlvin Lee params.vertical_total_min = adjust.v_total_min; 19794562236bSHarry Wentland 19804562236bSHarry Wentland /* TODO: If multiple pipes are to be supported, you need 198198e6436dSAnthony Koo * some GSL stuff. Static screen triggers may be programmed differently 198298e6436dSAnthony Koo * as well. 19834562236bSHarry Wentland */ 19844562236bSHarry Wentland for (i = 0; i < num_pipes; i++) { 198598e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_drr( 198698e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, ¶ms); 198798e6436dSAnthony Koo 198849c70eceSAlvin Lee if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 198998e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( 199098e6436dSAnthony Koo pipe_ctx[i]->stream_res.tg, 19915b5abe95SAnthony Koo event_triggers, num_frames); 19924562236bSHarry Wentland } 19934562236bSHarry Wentland } 19944562236bSHarry Wentland 199572ada5f7SEric Cook static void get_position(struct pipe_ctx **pipe_ctx, 199672ada5f7SEric Cook int num_pipes, 199772ada5f7SEric Cook struct crtc_position *position) 199872ada5f7SEric Cook { 199972ada5f7SEric Cook int i = 0; 200072ada5f7SEric Cook 200172ada5f7SEric Cook /* TODO: handle pipes > 1 200272ada5f7SEric Cook */ 200372ada5f7SEric Cook for (i = 0; i < num_pipes; i++) 20046b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 200572ada5f7SEric Cook } 200672ada5f7SEric Cook 20074562236bSHarry Wentland static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 20085b5abe95SAnthony Koo int num_pipes, const struct dc_static_screen_params *params) 20094562236bSHarry Wentland { 20104562236bSHarry Wentland unsigned int i; 20115b5abe95SAnthony Koo unsigned int triggers = 0; 201294267b3dSSylvia Tsai 20135b5abe95SAnthony Koo if (params->triggers.overlay_update) 20145b5abe95SAnthony Koo triggers |= 0x100; 20155b5abe95SAnthony Koo if (params->triggers.surface_update) 20165b5abe95SAnthony Koo triggers |= 0x80; 20175b5abe95SAnthony Koo if (params->triggers.cursor_update) 20185b5abe95SAnthony Koo triggers |= 0x2; 20195b5abe95SAnthony Koo if (params->triggers.force_trigger) 20205b5abe95SAnthony Koo triggers |= 0x1; 20214562236bSHarry Wentland 2022593f79a2SAlex Deucher if (num_pipes) { 2023593f79a2SAlex Deucher struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 2024593f79a2SAlex Deucher 2025593f79a2SAlex Deucher if (dc->fbc_compressor) 20265b5abe95SAnthony Koo triggers |= 0x84; 2027593f79a2SAlex Deucher } 2028c3aa1d67SBhawanpreet Lakha 20294562236bSHarry Wentland for (i = 0; i < num_pipes; i++) 20306b670fa9SHarry Wentland pipe_ctx[i]->stream_res.tg->funcs-> 20315b5abe95SAnthony Koo set_static_screen_control(pipe_ctx[i]->stream_res.tg, 20325b5abe95SAnthony Koo triggers, params->num_frames); 20334562236bSHarry Wentland } 20344562236bSHarry Wentland 2035f6baff4dSHarry Wentland /* 2036690b5e39SRoman Li * Check if FBC can be enabled 2037690b5e39SRoman Li */ 20389c6569deSHarry Wentland static bool should_enable_fbc(struct dc *dc, 20393bc4aaa9SRoman Li struct dc_state *context, 20403bc4aaa9SRoman Li uint32_t *pipe_idx) 2041690b5e39SRoman Li { 20423bc4aaa9SRoman Li uint32_t i; 20433bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = NULL; 20443bc4aaa9SRoman Li struct resource_context *res_ctx = &context->res_ctx; 204565d38262Shersen wu unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 20463bc4aaa9SRoman Li 2047690b5e39SRoman Li 2048690b5e39SRoman Li ASSERT(dc->fbc_compressor); 2049690b5e39SRoman Li 2050690b5e39SRoman Li /* FBC memory should be allocated */ 2051690b5e39SRoman Li if (!dc->ctx->fbc_gpu_addr) 20529c6569deSHarry Wentland return false; 2053690b5e39SRoman Li 2054690b5e39SRoman Li /* Only supports single display */ 2055690b5e39SRoman Li if (context->stream_count != 1) 20569c6569deSHarry Wentland return false; 2057690b5e39SRoman Li 20583bc4aaa9SRoman Li for (i = 0; i < dc->res_pool->pipe_count; i++) { 20593bc4aaa9SRoman Li if (res_ctx->pipe_ctx[i].stream) { 206065d38262Shersen wu 20613bc4aaa9SRoman Li pipe_ctx = &res_ctx->pipe_ctx[i]; 206265d38262Shersen wu 206365d38262Shersen wu if (!pipe_ctx) 206465d38262Shersen wu continue; 206565d38262Shersen wu 206665d38262Shersen wu /* fbc not applicable on underlay pipe */ 206765d38262Shersen wu if (pipe_ctx->pipe_idx != underlay_idx) { 20683bc4aaa9SRoman Li *pipe_idx = i; 20693bc4aaa9SRoman Li break; 20703bc4aaa9SRoman Li } 20713bc4aaa9SRoman Li } 207265d38262Shersen wu } 20733bc4aaa9SRoman Li 207465d38262Shersen wu if (i == dc->res_pool->pipe_count) 207565d38262Shersen wu return false; 207665d38262Shersen wu 2077ceb3dbb4SJun Lei if (!pipe_ctx->stream->link) 207865d38262Shersen wu return false; 20797a840773SRoman Li 2080690b5e39SRoman Li /* Only supports eDP */ 2081ceb3dbb4SJun Lei if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 20829c6569deSHarry Wentland return false; 2083690b5e39SRoman Li 2084690b5e39SRoman Li /* PSR should not be enabled */ 2085d1ebfdd8SWyatt Wood if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 20869c6569deSHarry Wentland return false; 2087690b5e39SRoman Li 208893984bbcSShirish S /* Nothing to compress */ 208993984bbcSShirish S if (!pipe_ctx->plane_state) 20909c6569deSHarry Wentland return false; 209193984bbcSShirish S 209205230fa9SRoman Li /* Only for non-linear tiling */ 209305230fa9SRoman Li if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 20949c6569deSHarry Wentland return false; 209505230fa9SRoman Li 20969c6569deSHarry Wentland return true; 2097690b5e39SRoman Li } 2098690b5e39SRoman Li 2099690b5e39SRoman Li /* 2100690b5e39SRoman Li * Enable FBC 2101690b5e39SRoman Li */ 210265d38262Shersen wu static void enable_fbc( 210365d38262Shersen wu struct dc *dc, 2104608ac7bbSJerry Zuo struct dc_state *context) 2105690b5e39SRoman Li { 21063bc4aaa9SRoman Li uint32_t pipe_idx = 0; 21073bc4aaa9SRoman Li 21083bc4aaa9SRoman Li if (should_enable_fbc(dc, context, &pipe_idx)) { 2109690b5e39SRoman Li /* Program GRPH COMPRESSED ADDRESS and PITCH */ 2110690b5e39SRoman Li struct compr_addr_and_pitch_params params = {0, 0, 0}; 2111690b5e39SRoman Li struct compressor *compr = dc->fbc_compressor; 21123bc4aaa9SRoman Li struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 21133bc4aaa9SRoman Li 21149c6569deSHarry Wentland params.source_view_width = pipe_ctx->stream->timing.h_addressable; 21159c6569deSHarry Wentland params.source_view_height = pipe_ctx->stream->timing.v_addressable; 211665d38262Shersen wu params.inst = pipe_ctx->stream_res.tg->inst; 2117690b5e39SRoman Li compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 2118690b5e39SRoman Li 2119690b5e39SRoman Li compr->funcs->surface_address_and_pitch(compr, ¶ms); 2120690b5e39SRoman Li compr->funcs->set_fbc_invalidation_triggers(compr, 1); 2121690b5e39SRoman Li 2122690b5e39SRoman Li compr->funcs->enable_fbc(compr, ¶ms); 2123690b5e39SRoman Li } 2124690b5e39SRoman Li } 2125690b5e39SRoman Li 212654e8695eSDmytro Laktyushkin static void dce110_reset_hw_ctx_wrap( 2127fb3466a4SBhawanpreet Lakha struct dc *dc, 2128608ac7bbSJerry Zuo struct dc_state *context) 21294562236bSHarry Wentland { 21304562236bSHarry Wentland int i; 21314562236bSHarry Wentland 21324562236bSHarry Wentland /* Reset old context */ 21334562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 2134a2b8659dSTony Cheng for (i = 0; i < MAX_PIPES; i++) { 21354562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2136608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 21374562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 21384562236bSHarry Wentland 21394562236bSHarry Wentland /* Note: We need to disable output if clock sources change, 21404562236bSHarry Wentland * since bios does optimization and doesn't apply if changing 21414562236bSHarry Wentland * PHY when not already disabled. 21424562236bSHarry Wentland */ 21434562236bSHarry Wentland 21444562236bSHarry Wentland /* Skip underlay pipe since it will be handled in commit surface*/ 21454562236bSHarry Wentland if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 21464562236bSHarry Wentland continue; 21474562236bSHarry Wentland 21484562236bSHarry Wentland if (!pipe_ctx->stream || 214954e8695eSDmytro Laktyushkin pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 215021e67d4dSHarry Wentland struct clock_source *old_clk = pipe_ctx_old->clock_source; 215121e67d4dSHarry Wentland 2152827f11e9SLeo (Sunpeng) Li /* Disable if new stream is null. O/w, if stream is 2153827f11e9SLeo (Sunpeng) Li * disabled already, no need to disable again. 2154827f11e9SLeo (Sunpeng) Li */ 215557430404SSu Sung Chung if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 215657430404SSu Sung Chung core_link_disable_stream(pipe_ctx_old); 215757430404SSu Sung Chung 215857430404SSu Sung Chung /* free acquired resources*/ 215957430404SSu Sung Chung if (pipe_ctx_old->stream_res.audio) { 216057430404SSu Sung Chung /*disable az_endpoint*/ 216157430404SSu Sung Chung pipe_ctx_old->stream_res.audio->funcs-> 216257430404SSu Sung Chung az_disable(pipe_ctx_old->stream_res.audio); 216357430404SSu Sung Chung 216457430404SSu Sung Chung /*free audio*/ 216557430404SSu Sung Chung if (dc->caps.dynamic_audio == true) { 216657430404SSu Sung Chung /*we have to dynamic arbitrate the audio endpoints*/ 216757430404SSu Sung Chung /*we free the resource, need reset is_audio_acquired*/ 216857430404SSu Sung Chung update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 216957430404SSu Sung Chung pipe_ctx_old->stream_res.audio, false); 217057430404SSu Sung Chung pipe_ctx_old->stream_res.audio = NULL; 217157430404SSu Sung Chung } 217257430404SSu Sung Chung } 217357430404SSu Sung Chung } 2174d050f8edSHersen Wu 21756b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 21766b670fa9SHarry Wentland if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 217754e8695eSDmytro Laktyushkin dm_error("DC: failed to blank crtc!\n"); 217854e8695eSDmytro Laktyushkin BREAK_TO_DEBUGGER(); 217954e8695eSDmytro Laktyushkin } 21806b670fa9SHarry Wentland pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 218186a66c4eSHarry Wentland pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 2182608ac7bbSJerry Zuo pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 218354e8695eSDmytro Laktyushkin 2184ad8960a6SMikita Lipski if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 2185ad8960a6SMikita Lipski dc->res_pool, 2186ad8960a6SMikita Lipski old_clk)) 218721e67d4dSHarry Wentland old_clk->funcs->cs_power_down(old_clk); 218821e67d4dSHarry Wentland 21897f914a62SYongqiang Sun dc->hwss.disable_plane(dc, pipe_ctx_old); 219054e8695eSDmytro Laktyushkin 219154e8695eSDmytro Laktyushkin pipe_ctx_old->stream = NULL; 219254e8695eSDmytro Laktyushkin } 21934562236bSHarry Wentland } 21944562236bSHarry Wentland } 21954562236bSHarry Wentland 21961a05873fSAnthony Koo static void dce110_setup_audio_dto( 21971a05873fSAnthony Koo struct dc *dc, 21981a05873fSAnthony Koo struct dc_state *context) 21991a05873fSAnthony Koo { 22001a05873fSAnthony Koo int i; 22011a05873fSAnthony Koo 22021a05873fSAnthony Koo /* program audio wall clock. use HDMI as clock source if HDMI 22031a05873fSAnthony Koo * audio active. Otherwise, use DP as clock source 22041a05873fSAnthony Koo * first, loop to find any HDMI audio, if not, loop find DP audio 22051a05873fSAnthony Koo */ 22061a05873fSAnthony Koo /* Setup audio rate clock source */ 22071a05873fSAnthony Koo /* Issue: 22081a05873fSAnthony Koo * Audio lag happened on DP monitor when unplug a HDMI monitor 22091a05873fSAnthony Koo * 22101a05873fSAnthony Koo * Cause: 22111a05873fSAnthony Koo * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 22121a05873fSAnthony Koo * is set to either dto0 or dto1, audio should work fine. 22131a05873fSAnthony Koo * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 22141a05873fSAnthony Koo * set to dto0 will cause audio lag. 22151a05873fSAnthony Koo * 22161a05873fSAnthony Koo * Solution: 22171a05873fSAnthony Koo * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 22181a05873fSAnthony Koo * find first available pipe with audio, setup audio wall DTO per topology 22191a05873fSAnthony Koo * instead of per pipe. 22201a05873fSAnthony Koo */ 22211a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 22221a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 22231a05873fSAnthony Koo 22241a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 22251a05873fSAnthony Koo continue; 22261a05873fSAnthony Koo 22271a05873fSAnthony Koo if (pipe_ctx->top_pipe) 22281a05873fSAnthony Koo continue; 22291a05873fSAnthony Koo if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) 22301a05873fSAnthony Koo continue; 22311a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 22321a05873fSAnthony Koo struct audio_output audio_output; 22331a05873fSAnthony Koo 22341a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 22351a05873fSAnthony Koo 22368fe44c08SAlex Deucher #if defined(CONFIG_DRM_AMD_DC_DCN) 223764b1d0e8SNicholas Kazlauskas /* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */ 223864b1d0e8SNicholas Kazlauskas if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { 223964b1d0e8SNicholas Kazlauskas /* disable audio DTBCLK DTO */ 224064b1d0e8SNicholas Kazlauskas dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 224164b1d0e8SNicholas Kazlauskas dc->res_pool->dccg, 0); 224264b1d0e8SNicholas Kazlauskas 22431a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 22441a05873fSAnthony Koo pipe_ctx->stream_res.audio, 22451a05873fSAnthony Koo pipe_ctx->stream->signal, 22461a05873fSAnthony Koo &audio_output.crtc_info, 22471a05873fSAnthony Koo &audio_output.pll_info); 224864b1d0e8SNicholas Kazlauskas } else 224964b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 225064b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio, 225164b1d0e8SNicholas Kazlauskas pipe_ctx->stream->signal, 225264b1d0e8SNicholas Kazlauskas &audio_output.crtc_info, 225364b1d0e8SNicholas Kazlauskas &audio_output.pll_info); 225464b1d0e8SNicholas Kazlauskas #else 225564b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 225664b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio, 225764b1d0e8SNicholas Kazlauskas pipe_ctx->stream->signal, 225864b1d0e8SNicholas Kazlauskas &audio_output.crtc_info, 225964b1d0e8SNicholas Kazlauskas &audio_output.pll_info); 226064b1d0e8SNicholas Kazlauskas #endif 22611a05873fSAnthony Koo break; 22621a05873fSAnthony Koo } 22631a05873fSAnthony Koo } 22641a05873fSAnthony Koo 22651a05873fSAnthony Koo /* no HDMI audio is found, try DP audio */ 22661a05873fSAnthony Koo if (i == dc->res_pool->pipe_count) { 22671a05873fSAnthony Koo for (i = 0; i < dc->res_pool->pipe_count; i++) { 22681a05873fSAnthony Koo struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 22691a05873fSAnthony Koo 22701a05873fSAnthony Koo if (pipe_ctx->stream == NULL) 22711a05873fSAnthony Koo continue; 22721a05873fSAnthony Koo 22731a05873fSAnthony Koo if (pipe_ctx->top_pipe) 22741a05873fSAnthony Koo continue; 22751a05873fSAnthony Koo 22761a05873fSAnthony Koo if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 22771a05873fSAnthony Koo continue; 22781a05873fSAnthony Koo 22791a05873fSAnthony Koo if (pipe_ctx->stream_res.audio != NULL) { 22801a05873fSAnthony Koo struct audio_output audio_output; 22811a05873fSAnthony Koo 22821a05873fSAnthony Koo build_audio_output(context, pipe_ctx, &audio_output); 22831a05873fSAnthony Koo 22841a05873fSAnthony Koo pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 22851a05873fSAnthony Koo pipe_ctx->stream_res.audio, 22861a05873fSAnthony Koo pipe_ctx->stream->signal, 22871a05873fSAnthony Koo &audio_output.crtc_info, 22881a05873fSAnthony Koo &audio_output.pll_info); 22891a05873fSAnthony Koo break; 22901a05873fSAnthony Koo } 22911a05873fSAnthony Koo } 22921a05873fSAnthony Koo } 22931a05873fSAnthony Koo } 2294cf437593SDmytro Laktyushkin 22954562236bSHarry Wentland enum dc_status dce110_apply_ctx_to_hw( 2296fb3466a4SBhawanpreet Lakha struct dc *dc, 2297608ac7bbSJerry Zuo struct dc_state *context) 22984562236bSHarry Wentland { 2299f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 23004562236bSHarry Wentland struct dc_bios *dcb = dc->ctx->dc_bios; 23014562236bSHarry Wentland enum dc_status status; 23024562236bSHarry Wentland int i; 23034562236bSHarry Wentland 2304a896f870SMeenakshikumar Somasundaram /* reset syncd pipes from disabled pipes */ 2305a896f870SMeenakshikumar Somasundaram if (dc->config.use_pipe_ctx_sync_logic) 2306a896f870SMeenakshikumar Somasundaram reset_syncd_pipes_from_disabled_pipes(dc, context); 2307a896f870SMeenakshikumar Somasundaram 23084562236bSHarry Wentland /* Reset old context */ 23094562236bSHarry Wentland /* look up the targets that have been removed since last commit */ 2310f42ea55bSAnthony Koo hws->funcs.reset_hw_ctx_wrap(dc, context); 23114562236bSHarry Wentland 23124562236bSHarry Wentland /* Skip applying if no targets */ 2313ab2541b6SAric Cyr if (context->stream_count <= 0) 23144562236bSHarry Wentland return DC_OK; 23154562236bSHarry Wentland 23164562236bSHarry Wentland /* Apply new context */ 23174562236bSHarry Wentland dcb->funcs->set_scratch_critical_state(dcb, true); 23184562236bSHarry Wentland 23194562236bSHarry Wentland /* below is for real asic only */ 2320a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 23214562236bSHarry Wentland struct pipe_ctx *pipe_ctx_old = 2322608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 23234562236bSHarry Wentland struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 23244562236bSHarry Wentland 23254562236bSHarry Wentland if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 23264562236bSHarry Wentland continue; 23274562236bSHarry Wentland 23284562236bSHarry Wentland if (pipe_ctx->stream == pipe_ctx_old->stream) { 23294562236bSHarry Wentland if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 23304562236bSHarry Wentland dce_crtc_switch_to_clk_src(dc->hwseq, 23314562236bSHarry Wentland pipe_ctx->clock_source, i); 23324562236bSHarry Wentland continue; 23334562236bSHarry Wentland } 23344562236bSHarry Wentland 2335f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 23364562236bSHarry Wentland dc, i, dc->ctx->dc_bios, 23374562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 23384562236bSHarry Wentland } 23394562236bSHarry Wentland 23402f3bfb27SRoman Li if (dc->fbc_compressor) 23411663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 23425099114bSAlex Deucher 23431a05873fSAnthony Koo dce110_setup_audio_dto(dc, context); 2344ab8812a3SHersen Wu 2345a2b8659dSTony Cheng for (i = 0; i < dc->res_pool->pipe_count; i++) { 2346ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx_old = 2347608ac7bbSJerry Zuo &dc->current_state->res_ctx.pipe_ctx[i]; 2348ab8812a3SHersen Wu struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2349ab8812a3SHersen Wu 2350ab8812a3SHersen Wu if (pipe_ctx->stream == NULL) 2351ab8812a3SHersen Wu continue; 2352ab8812a3SHersen Wu 2353eed928dcSCharlene Liu if (pipe_ctx->stream == pipe_ctx_old->stream && 2354eed928dcSCharlene Liu pipe_ctx->stream->link->link_state_valid) { 2355ab8812a3SHersen Wu continue; 2356eed928dcSCharlene Liu } 2357ab8812a3SHersen Wu 23585b92d9d4SHarry Wentland if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2359313bf4ffSYongqiang Sun continue; 2360313bf4ffSYongqiang Sun 2361b1f6d01cSDmytro Laktyushkin if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2362ab8812a3SHersen Wu continue; 2363ab8812a3SHersen Wu 23644562236bSHarry Wentland status = apply_single_controller_ctx_to_hw( 23654562236bSHarry Wentland pipe_ctx, 23664562236bSHarry Wentland context, 23674562236bSHarry Wentland dc); 23684562236bSHarry Wentland 23694562236bSHarry Wentland if (DC_OK != status) 23704562236bSHarry Wentland return status; 23714562236bSHarry Wentland } 23724562236bSHarry Wentland 2373690b5e39SRoman Li if (dc->fbc_compressor) 237465d38262Shersen wu enable_fbc(dc, dc->current_state); 237565d38262Shersen wu 237665d38262Shersen wu dcb->funcs->set_scratch_critical_state(dcb, false); 2377690b5e39SRoman Li 23784562236bSHarry Wentland return DC_OK; 23794562236bSHarry Wentland } 23804562236bSHarry Wentland 23814562236bSHarry Wentland /******************************************************************************* 23824562236bSHarry Wentland * Front End programming 23834562236bSHarry Wentland ******************************************************************************/ 23844562236bSHarry Wentland static void set_default_colors(struct pipe_ctx *pipe_ctx) 23854562236bSHarry Wentland { 23864562236bSHarry Wentland struct default_adjustment default_adjust = { 0 }; 23874562236bSHarry Wentland 23884562236bSHarry Wentland default_adjust.force_hw_default = false; 238934996173SHarry Wentland default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 239034996173SHarry Wentland default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 23914562236bSHarry Wentland default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 23926702a9acSHarry Wentland default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 23934562236bSHarry Wentland 23944562236bSHarry Wentland /* display color depth */ 23954562236bSHarry Wentland default_adjust.color_depth = 23964fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->timing.display_color_depth; 23974562236bSHarry Wentland 23984562236bSHarry Wentland /* Lb color depth */ 23996702a9acSHarry Wentland default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 24004562236bSHarry Wentland 240186a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 240286a66c4eSHarry Wentland pipe_ctx->plane_res.xfm, &default_adjust); 24034562236bSHarry Wentland } 24044562236bSHarry Wentland 2405b06b7680SLeon Elazar 2406b06b7680SLeon Elazar /******************************************************************************* 2407b06b7680SLeon Elazar * In order to turn on/off specific surface we will program 2408b06b7680SLeon Elazar * Blender + CRTC 2409b06b7680SLeon Elazar * 2410b06b7680SLeon Elazar * In case that we have two surfaces and they have a different visibility 2411b06b7680SLeon Elazar * we can't turn off the CRTC since it will turn off the entire display 2412b06b7680SLeon Elazar * 2413b06b7680SLeon Elazar * |----------------------------------------------- | 2414b06b7680SLeon Elazar * |bottom pipe|curr pipe | | | 2415b06b7680SLeon Elazar * |Surface |Surface | Blender | CRCT | 2416b06b7680SLeon Elazar * |visibility |visibility | Configuration| | 2417b06b7680SLeon Elazar * |------------------------------------------------| 2418b06b7680SLeon Elazar * | off | off | CURRENT_PIPE | blank | 2419b06b7680SLeon Elazar * | off | on | CURRENT_PIPE | unblank | 2420b06b7680SLeon Elazar * | on | off | OTHER_PIPE | unblank | 2421b06b7680SLeon Elazar * | on | on | BLENDING | unblank | 2422b06b7680SLeon Elazar * -------------------------------------------------| 2423b06b7680SLeon Elazar * 2424b06b7680SLeon Elazar ******************************************************************************/ 2425fb3466a4SBhawanpreet Lakha static void program_surface_visibility(const struct dc *dc, 24264562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 24274562236bSHarry Wentland { 24284562236bSHarry Wentland enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2429b06b7680SLeon Elazar bool blank_target = false; 24304562236bSHarry Wentland 24314562236bSHarry Wentland if (pipe_ctx->bottom_pipe) { 2432b06b7680SLeon Elazar 2433b06b7680SLeon Elazar /* For now we are supporting only two pipes */ 2434b06b7680SLeon Elazar ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2435b06b7680SLeon Elazar 24363be5262eSHarry Wentland if (pipe_ctx->bottom_pipe->plane_state->visible) { 24373be5262eSHarry Wentland if (pipe_ctx->plane_state->visible) 24384562236bSHarry Wentland blender_mode = BLND_MODE_BLENDING; 24394562236bSHarry Wentland else 24404562236bSHarry Wentland blender_mode = BLND_MODE_OTHER_PIPE; 2441b06b7680SLeon Elazar 24423be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2443b06b7680SLeon Elazar blank_target = true; 2444b06b7680SLeon Elazar 24453be5262eSHarry Wentland } else if (!pipe_ctx->plane_state->visible) 2446b06b7680SLeon Elazar blank_target = true; 2447b06b7680SLeon Elazar 2448e07f541fSYongqiang Sun dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 24496b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2450b06b7680SLeon Elazar 24514562236bSHarry Wentland } 24524562236bSHarry Wentland 24531bf56e62SZeyu Fan static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 24541bf56e62SZeyu Fan { 2455146a9f63SKrunoslav Kovac int i = 0; 24561bf56e62SZeyu Fan struct xfm_grph_csc_adjustment adjust; 24571bf56e62SZeyu Fan memset(&adjust, 0, sizeof(adjust)); 24581bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 24591bf56e62SZeyu Fan 24601bf56e62SZeyu Fan 24614fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 24621bf56e62SZeyu Fan adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2463146a9f63SKrunoslav Kovac 2464146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2465146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2466146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 24671bf56e62SZeyu Fan } 24681bf56e62SZeyu Fan 246986a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 24701bf56e62SZeyu Fan } 2471fb3466a4SBhawanpreet Lakha static void update_plane_addr(const struct dc *dc, 24724562236bSHarry Wentland struct pipe_ctx *pipe_ctx) 24734562236bSHarry Wentland { 24743be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 24754562236bSHarry Wentland 24763be5262eSHarry Wentland if (plane_state == NULL) 24774562236bSHarry Wentland return; 24784562236bSHarry Wentland 247986a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 248086a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 24813be5262eSHarry Wentland &plane_state->address, 24823be5262eSHarry Wentland plane_state->flip_immediate); 24834562236bSHarry Wentland 24843be5262eSHarry Wentland plane_state->status.requested_address = plane_state->address; 24854562236bSHarry Wentland } 24864562236bSHarry Wentland 2487f774b339SEric Yang static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 24884562236bSHarry Wentland { 24893be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 24904562236bSHarry Wentland 24913be5262eSHarry Wentland if (plane_state == NULL) 24924562236bSHarry Wentland return; 24934562236bSHarry Wentland 24943be5262eSHarry Wentland plane_state->status.is_flip_pending = 249586a66c4eSHarry Wentland pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 249686a66c4eSHarry Wentland pipe_ctx->plane_res.mi); 24974562236bSHarry Wentland 24983be5262eSHarry Wentland if (plane_state->status.is_flip_pending && !plane_state->visible) 249986a66c4eSHarry Wentland pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 25004562236bSHarry Wentland 250186a66c4eSHarry Wentland plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 250286a66c4eSHarry Wentland if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 25036b670fa9SHarry Wentland pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 25043be5262eSHarry Wentland plane_state->status.is_right_eye =\ 25056b670fa9SHarry Wentland !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 25067f5c22d1SVitaly Prosyak } 25074562236bSHarry Wentland } 25084562236bSHarry Wentland 2509fb3466a4SBhawanpreet Lakha void dce110_power_down(struct dc *dc) 25104562236bSHarry Wentland { 25114562236bSHarry Wentland power_down_all_hw_blocks(dc); 25124562236bSHarry Wentland disable_vga_and_power_gate_all_controllers(dc); 25134562236bSHarry Wentland } 25144562236bSHarry Wentland 25154562236bSHarry Wentland static bool wait_for_reset_trigger_to_occur( 25164562236bSHarry Wentland struct dc_context *dc_ctx, 25174562236bSHarry Wentland struct timing_generator *tg) 25184562236bSHarry Wentland { 25194562236bSHarry Wentland bool rc = false; 25204562236bSHarry Wentland 25214562236bSHarry Wentland /* To avoid endless loop we wait at most 25224562236bSHarry Wentland * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 25234562236bSHarry Wentland const uint32_t frames_to_wait_on_triggered_reset = 10; 25244562236bSHarry Wentland uint32_t i; 25254562236bSHarry Wentland 25264562236bSHarry Wentland for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 25274562236bSHarry Wentland 25284562236bSHarry Wentland if (!tg->funcs->is_counter_moving(tg)) { 25294562236bSHarry Wentland DC_ERROR("TG counter is not moving!\n"); 25304562236bSHarry Wentland break; 25314562236bSHarry Wentland } 25324562236bSHarry Wentland 25334562236bSHarry Wentland if (tg->funcs->did_triggered_reset_occur(tg)) { 25344562236bSHarry Wentland rc = true; 25354562236bSHarry Wentland /* usually occurs at i=1 */ 25364562236bSHarry Wentland DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 25374562236bSHarry Wentland i); 25384562236bSHarry Wentland break; 25394562236bSHarry Wentland } 25404562236bSHarry Wentland 25414562236bSHarry Wentland /* Wait for one frame. */ 25424562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 25434562236bSHarry Wentland tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 25444562236bSHarry Wentland } 25454562236bSHarry Wentland 25464562236bSHarry Wentland if (false == rc) 25474562236bSHarry Wentland DC_ERROR("GSL: Timeout on reset trigger!\n"); 25484562236bSHarry Wentland 25494562236bSHarry Wentland return rc; 25504562236bSHarry Wentland } 25514562236bSHarry Wentland 25524562236bSHarry Wentland /* Enable timing synchronization for a group of Timing Generators. */ 25534562236bSHarry Wentland static void dce110_enable_timing_synchronization( 2554fb3466a4SBhawanpreet Lakha struct dc *dc, 25554562236bSHarry Wentland int group_index, 25564562236bSHarry Wentland int group_size, 25574562236bSHarry Wentland struct pipe_ctx *grouped_pipes[]) 25584562236bSHarry Wentland { 25594562236bSHarry Wentland struct dc_context *dc_ctx = dc->ctx; 25604562236bSHarry Wentland struct dcp_gsl_params gsl_params = { 0 }; 25614562236bSHarry Wentland int i; 25624562236bSHarry Wentland 25634562236bSHarry Wentland DC_SYNC_INFO("GSL: Setting-up...\n"); 25644562236bSHarry Wentland 25654562236bSHarry Wentland /* Designate a single TG in the group as a master. 25664562236bSHarry Wentland * Since HW doesn't care which one, we always assign 25674562236bSHarry Wentland * the 1st one in the group. */ 25684562236bSHarry Wentland gsl_params.gsl_group = 0; 25696b670fa9SHarry Wentland gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 25704562236bSHarry Wentland 25714562236bSHarry Wentland for (i = 0; i < group_size; i++) 25726b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 25736b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg, &gsl_params); 25744562236bSHarry Wentland 25754562236bSHarry Wentland /* Reset slave controllers on master VSync */ 25764562236bSHarry Wentland DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 25774562236bSHarry Wentland 25784562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) 25796b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2580fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2581fa2123dbSMikita Lipski gsl_params.gsl_group); 25824562236bSHarry Wentland 25834562236bSHarry Wentland for (i = 1 /* skip the master */; i < group_size; i++) { 25844562236bSHarry Wentland DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 25856b670fa9SHarry Wentland wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2586fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2587fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg); 25884562236bSHarry Wentland } 25894562236bSHarry Wentland 25904562236bSHarry Wentland /* GSL Vblank synchronization is a one time sync mechanism, assumption 25914562236bSHarry Wentland * is that the sync'ed displays will not drift out of sync over time*/ 25924562236bSHarry Wentland DC_SYNC_INFO("GSL: Restoring register states.\n"); 25934562236bSHarry Wentland for (i = 0; i < group_size; i++) 25946b670fa9SHarry Wentland grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 25954562236bSHarry Wentland 25964562236bSHarry Wentland DC_SYNC_INFO("GSL: Set-up complete.\n"); 25974562236bSHarry Wentland } 25984562236bSHarry Wentland 2599fa2123dbSMikita Lipski static void dce110_enable_per_frame_crtc_position_reset( 2600fa2123dbSMikita Lipski struct dc *dc, 2601fa2123dbSMikita Lipski int group_size, 2602fa2123dbSMikita Lipski struct pipe_ctx *grouped_pipes[]) 2603fa2123dbSMikita Lipski { 2604fa2123dbSMikita Lipski struct dc_context *dc_ctx = dc->ctx; 2605fa2123dbSMikita Lipski struct dcp_gsl_params gsl_params = { 0 }; 2606fa2123dbSMikita Lipski int i; 2607fa2123dbSMikita Lipski 2608fa2123dbSMikita Lipski gsl_params.gsl_group = 0; 260937cd85ceSDavid Francis gsl_params.gsl_master = 0; 2610fa2123dbSMikita Lipski 2611fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2612fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2613fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, &gsl_params); 2614fa2123dbSMikita Lipski 2615fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2616fa2123dbSMikita Lipski 2617fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2618fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2619fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg, 2620fa2123dbSMikita Lipski gsl_params.gsl_master, 2621fa2123dbSMikita Lipski &grouped_pipes[i]->stream->triggered_crtc_reset); 2622fa2123dbSMikita Lipski 2623fa2123dbSMikita Lipski DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2624fa2123dbSMikita Lipski for (i = 1; i < group_size; i++) 2625fa2123dbSMikita Lipski wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2626fa2123dbSMikita Lipski 2627fa2123dbSMikita Lipski for (i = 0; i < group_size; i++) 2628fa2123dbSMikita Lipski grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2629fa2123dbSMikita Lipski 2630fa2123dbSMikita Lipski } 2631fa2123dbSMikita Lipski 2632fb55546eSAnthony Koo static void init_pipes(struct dc *dc, struct dc_state *context) 2633fb55546eSAnthony Koo { 2634fb55546eSAnthony Koo // Do nothing 2635fb55546eSAnthony Koo } 2636fb55546eSAnthony Koo 2637fb3466a4SBhawanpreet Lakha static void init_hw(struct dc *dc) 26384562236bSHarry Wentland { 26394562236bSHarry Wentland int i; 26404562236bSHarry Wentland struct dc_bios *bp; 26414562236bSHarry Wentland struct transform *xfm; 26425e7773a2SAnthony Koo struct abm *abm; 264370d9e8cbSPaul Hsieh struct dmcu *dmcu; 2644f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 26453ba01817SYongqiang Sun uint32_t backlight = MAX_BACKLIGHT_LEVEL; 26464562236bSHarry Wentland 26474562236bSHarry Wentland bp = dc->ctx->dc_bios; 26484562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 26494562236bSHarry Wentland xfm = dc->res_pool->transforms[i]; 26504562236bSHarry Wentland xfm->funcs->transform_reset(xfm); 26514562236bSHarry Wentland 2652f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 26534562236bSHarry Wentland dc, i, bp, 26544562236bSHarry Wentland PIPE_GATING_CONTROL_INIT); 2655f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 26564562236bSHarry Wentland dc, i, bp, 26574562236bSHarry Wentland PIPE_GATING_CONTROL_DISABLE); 2658f42ea55bSAnthony Koo hws->funcs.enable_display_pipe_clock_gating( 26594562236bSHarry Wentland dc->ctx, 26604562236bSHarry Wentland true); 26614562236bSHarry Wentland } 26624562236bSHarry Wentland 2663e166ad43SJulia Lawall dce_clock_gating_power_up(dc->hwseq, false); 26644562236bSHarry Wentland /***************************************/ 26654562236bSHarry Wentland 26664562236bSHarry Wentland for (i = 0; i < dc->link_count; i++) { 26674562236bSHarry Wentland /****************************************/ 26684562236bSHarry Wentland /* Power up AND update implementation according to the 26694562236bSHarry Wentland * required signal (which may be different from the 26704562236bSHarry Wentland * default signal on connector). */ 2671d0778ebfSHarry Wentland struct dc_link *link = dc->links[i]; 2672069d418fSAndrew Jiang 26734562236bSHarry Wentland link->link_enc->funcs->hw_init(link->link_enc); 26744562236bSHarry Wentland } 26754562236bSHarry Wentland 26764562236bSHarry Wentland for (i = 0; i < dc->res_pool->pipe_count; i++) { 26774562236bSHarry Wentland struct timing_generator *tg = dc->res_pool->timing_generators[i]; 26784562236bSHarry Wentland 26794562236bSHarry Wentland tg->funcs->disable_vga(tg); 26804562236bSHarry Wentland 26814562236bSHarry Wentland /* Blank controller using driver code instead of 26824562236bSHarry Wentland * command table. */ 26834562236bSHarry Wentland tg->funcs->set_blank(tg, true); 26844b5e7d62SHersen Wu hwss_wait_for_blank_complete(tg); 26854562236bSHarry Wentland } 26864562236bSHarry Wentland 26874562236bSHarry Wentland for (i = 0; i < dc->res_pool->audio_count; i++) { 26884562236bSHarry Wentland struct audio *audio = dc->res_pool->audios[i]; 26894562236bSHarry Wentland audio->funcs->hw_init(audio); 26904562236bSHarry Wentland } 26915e7773a2SAnthony Koo 26923ba01817SYongqiang Sun for (i = 0; i < dc->link_count; i++) { 26933ba01817SYongqiang Sun struct dc_link *link = dc->links[i]; 26943ba01817SYongqiang Sun 26953ba01817SYongqiang Sun if (link->panel_cntl) 26963ba01817SYongqiang Sun backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 26974562236bSHarry Wentland } 26985099114bSAlex Deucher 26993ba01817SYongqiang Sun abm = dc->res_pool->abm; 27003ba01817SYongqiang Sun if (abm != NULL) 27013ba01817SYongqiang Sun abm->funcs->abm_init(abm, backlight); 27023ba01817SYongqiang Sun 270370d9e8cbSPaul Hsieh dmcu = dc->res_pool->dmcu; 270470d9e8cbSPaul Hsieh if (dmcu != NULL && abm != NULL) 270570d9e8cbSPaul Hsieh abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 270670d9e8cbSPaul Hsieh 27072f3bfb27SRoman Li if (dc->fbc_compressor) 27081663ae1cSBhawanpreet Lakha dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 2709690b5e39SRoman Li 27106728b30cSAnthony Koo } 27114562236bSHarry Wentland 27129566b675SDmytro Laktyushkin 27139566b675SDmytro Laktyushkin void dce110_prepare_bandwidth( 2714fb3466a4SBhawanpreet Lakha struct dc *dc, 27159566b675SDmytro Laktyushkin struct dc_state *context) 2716cf437593SDmytro Laktyushkin { 2717dc88b4a6SEric Yang struct clk_mgr *dccg = dc->clk_mgr; 2718fab55d61SDmytro Laktyushkin 2719fab55d61SDmytro Laktyushkin dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 2720cf437593SDmytro Laktyushkin 27215a83c932SNicholas Kazlauskas dccg->funcs->update_clocks( 27225a83c932SNicholas Kazlauskas dccg, 272324f7dd7eSDmytro Laktyushkin context, 27249566b675SDmytro Laktyushkin false); 27259566b675SDmytro Laktyushkin } 27269566b675SDmytro Laktyushkin 27279566b675SDmytro Laktyushkin void dce110_optimize_bandwidth( 27289566b675SDmytro Laktyushkin struct dc *dc, 27299566b675SDmytro Laktyushkin struct dc_state *context) 27309566b675SDmytro Laktyushkin { 2731dc88b4a6SEric Yang struct clk_mgr *dccg = dc->clk_mgr; 27329566b675SDmytro Laktyushkin 27339566b675SDmytro Laktyushkin dce110_set_displaymarks(dc, context); 27349566b675SDmytro Laktyushkin 27359566b675SDmytro Laktyushkin dccg->funcs->update_clocks( 27369566b675SDmytro Laktyushkin dccg, 27379566b675SDmytro Laktyushkin context, 27389566b675SDmytro Laktyushkin true); 27394562236bSHarry Wentland } 27404562236bSHarry Wentland 27414562236bSHarry Wentland static void dce110_program_front_end_for_pipe( 2742fb3466a4SBhawanpreet Lakha struct dc *dc, struct pipe_ctx *pipe_ctx) 27434562236bSHarry Wentland { 274486a66c4eSHarry Wentland struct mem_input *mi = pipe_ctx->plane_res.mi; 27453be5262eSHarry Wentland struct dc_plane_state *plane_state = pipe_ctx->plane_state; 27464562236bSHarry Wentland struct xfm_grph_csc_adjustment adjust; 27474562236bSHarry Wentland struct out_csc_color_matrix tbl_entry; 27484562236bSHarry Wentland unsigned int i; 2749f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 2750f42ea55bSAnthony Koo 27515d4b05ddSBhawanpreet Lakha DC_LOGGER_INIT(); 27524562236bSHarry Wentland memset(&tbl_entry, 0, sizeof(tbl_entry)); 27534562236bSHarry Wentland 27544562236bSHarry Wentland memset(&adjust, 0, sizeof(adjust)); 27554562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 27564562236bSHarry Wentland 2757e07f541fSYongqiang Sun dce_enable_fe_clock(dc->hwseq, mi->inst, true); 27584562236bSHarry Wentland 27594562236bSHarry Wentland set_default_colors(pipe_ctx); 27604fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 27614562236bSHarry Wentland == true) { 27624562236bSHarry Wentland tbl_entry.color_space = 27634fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->output_color_space; 27644562236bSHarry Wentland 27654562236bSHarry Wentland for (i = 0; i < 12; i++) 27664562236bSHarry Wentland tbl_entry.regval[i] = 27674fa086b9SLeo (Sunpeng) Li pipe_ctx->stream->csc_color_matrix.matrix[i]; 27684562236bSHarry Wentland 276986a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 277086a66c4eSHarry Wentland (pipe_ctx->plane_res.xfm, &tbl_entry); 27714562236bSHarry Wentland } 27724562236bSHarry Wentland 27734fa086b9SLeo (Sunpeng) Li if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 27744562236bSHarry Wentland adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2775146a9f63SKrunoslav Kovac 2776146a9f63SKrunoslav Kovac for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2777146a9f63SKrunoslav Kovac adjust.temperature_matrix[i] = 2778146a9f63SKrunoslav Kovac pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 27794562236bSHarry Wentland } 27804562236bSHarry Wentland 278186a66c4eSHarry Wentland pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 27824562236bSHarry Wentland 27836702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; 2784c1473558SAndrey Grodzovsky 27854562236bSHarry Wentland program_scaler(dc, pipe_ctx); 27864562236bSHarry Wentland 27874562236bSHarry Wentland mi->funcs->mem_input_program_surface_config( 27884562236bSHarry Wentland mi, 27893be5262eSHarry Wentland plane_state->format, 27903be5262eSHarry Wentland &plane_state->tiling_info, 27913be5262eSHarry Wentland &plane_state->plane_size, 27923be5262eSHarry Wentland plane_state->rotation, 2793624d7c47SYongqiang Sun NULL, 27944b28b76bSDmytro Laktyushkin false); 27954b28b76bSDmytro Laktyushkin if (mi->funcs->set_blank) 27963be5262eSHarry Wentland mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 27974562236bSHarry Wentland 2798fb3466a4SBhawanpreet Lakha if (dc->config.gpu_vm_support) 27994562236bSHarry Wentland mi->funcs->mem_input_program_pte_vm( 280086a66c4eSHarry Wentland pipe_ctx->plane_res.mi, 28013be5262eSHarry Wentland plane_state->format, 28023be5262eSHarry Wentland &plane_state->tiling_info, 28033be5262eSHarry Wentland plane_state->rotation); 28044562236bSHarry Wentland 2805067c878aSYongqiang Sun /* Moved programming gamma from dc to hwss */ 2806405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update || 2807405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 2808405c50a0SAndrew Jiang pipe_ctx->plane_state->update_flags.bits.gamma_change) 2809f42ea55bSAnthony Koo hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 2810405c50a0SAndrew Jiang 2811405c50a0SAndrew Jiang if (pipe_ctx->plane_state->update_flags.bits.full_update) 2812f42ea55bSAnthony Koo hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 2813067c878aSYongqiang Sun 28141296423bSBhawanpreet Lakha DC_LOG_SURFACE( 28153032deb5SBhawanpreet Lakha "Pipe:%d %p: addr hi:0x%x, " 28164562236bSHarry Wentland "addr low:0x%x, " 28174562236bSHarry Wentland "src: %d, %d, %d," 28184562236bSHarry Wentland " %d; dst: %d, %d, %d, %d;" 28194562236bSHarry Wentland "clip: %d, %d, %d, %d\n", 28204562236bSHarry Wentland pipe_ctx->pipe_idx, 28213032deb5SBhawanpreet Lakha (void *) pipe_ctx->plane_state, 28223be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.high_part, 28233be5262eSHarry Wentland pipe_ctx->plane_state->address.grph.addr.low_part, 28243be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.x, 28253be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.y, 28263be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.width, 28273be5262eSHarry Wentland pipe_ctx->plane_state->src_rect.height, 28283be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.x, 28293be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.y, 28303be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.width, 28313be5262eSHarry Wentland pipe_ctx->plane_state->dst_rect.height, 28323be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.x, 28333be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.y, 28343be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.width, 28353be5262eSHarry Wentland pipe_ctx->plane_state->clip_rect.height); 28364562236bSHarry Wentland 28371296423bSBhawanpreet Lakha DC_LOG_SURFACE( 28384562236bSHarry Wentland "Pipe %d: width, height, x, y\n" 28394562236bSHarry Wentland "viewport:%d, %d, %d, %d\n" 28404562236bSHarry Wentland "recout: %d, %d, %d, %d\n", 28414562236bSHarry Wentland pipe_ctx->pipe_idx, 28426702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.width, 28436702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.height, 28446702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.x, 28456702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.viewport.y, 28466702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.width, 28476702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.height, 28486702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.x, 28496702a9acSHarry Wentland pipe_ctx->plane_res.scl_data.recout.y); 28504562236bSHarry Wentland } 28514562236bSHarry Wentland 28524562236bSHarry Wentland static void dce110_apply_ctx_for_surface( 2853fb3466a4SBhawanpreet Lakha struct dc *dc, 28543e9ad616SEric Yang const struct dc_stream_state *stream, 28553e9ad616SEric Yang int num_planes, 2856608ac7bbSJerry Zuo struct dc_state *context) 28574562236bSHarry Wentland { 28582194e3aeSRoman Li int i; 28594562236bSHarry Wentland 28603e9ad616SEric Yang if (num_planes == 0) 28614562236bSHarry Wentland return; 28624562236bSHarry Wentland 286365d38262Shersen wu if (dc->fbc_compressor) 286465d38262Shersen wu dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 286565d38262Shersen wu 28663e9ad616SEric Yang for (i = 0; i < dc->res_pool->pipe_count; i++) { 28673dc780ecSYongqiang Sun struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 28684562236bSHarry Wentland 2869a2607aefSHarry Wentland if (pipe_ctx->stream != stream) 28704562236bSHarry Wentland continue; 28714562236bSHarry Wentland 28723b21b6d2SJerry Zuo /* Need to allocate mem before program front end for Fiji */ 28733b21b6d2SJerry Zuo pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 28743b21b6d2SJerry Zuo pipe_ctx->plane_res.mi, 28753b21b6d2SJerry Zuo pipe_ctx->stream->timing.h_total, 28763b21b6d2SJerry Zuo pipe_ctx->stream->timing.v_total, 2877380604e2SKen Chalmers pipe_ctx->stream->timing.pix_clk_100hz / 10, 28783b21b6d2SJerry Zuo context->stream_count); 28793b21b6d2SJerry Zuo 28804562236bSHarry Wentland dce110_program_front_end_for_pipe(dc, pipe_ctx); 28814f804817SYongqiang Sun 28824f804817SYongqiang Sun dc->hwss.update_plane_addr(dc, pipe_ctx); 28834f804817SYongqiang Sun 2884b06b7680SLeon Elazar program_surface_visibility(dc, pipe_ctx); 28854562236bSHarry Wentland 28864562236bSHarry Wentland } 28873dc780ecSYongqiang Sun 288865d38262Shersen wu if (dc->fbc_compressor) 288912a8bd88SShirish S enable_fbc(dc, context); 28904562236bSHarry Wentland } 28914562236bSHarry Wentland 2892bbf5f6c3SAnthony Koo static void dce110_post_unlock_program_front_end( 2893bbf5f6c3SAnthony Koo struct dc *dc, 2894bbf5f6c3SAnthony Koo struct dc_state *context) 2895bbf5f6c3SAnthony Koo { 2896bbf5f6c3SAnthony Koo } 2897009114f6SAnthony Koo 2898e6c258cbSYongqiang Sun static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) 28994562236bSHarry Wentland { 2900f42ea55bSAnthony Koo struct dce_hwseq *hws = dc->hwseq; 2901bc373a89SRoman Li int fe_idx = pipe_ctx->plane_res.mi ? 2902bc373a89SRoman Li pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 2903e6c258cbSYongqiang Sun 29047950f0f9SDmytro Laktyushkin /* Do not power down fe when stream is active on dce*/ 2905608ac7bbSJerry Zuo if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 29064562236bSHarry Wentland return; 29074562236bSHarry Wentland 2908f42ea55bSAnthony Koo hws->funcs.enable_display_power_gating( 2909cfe4645eSDmytro Laktyushkin dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 2910cfe4645eSDmytro Laktyushkin 2911cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 2912cfe4645eSDmytro Laktyushkin dc->res_pool->transforms[fe_idx]); 29134562236bSHarry Wentland } 29144562236bSHarry Wentland 29156be425f3SEric Yang static void dce110_wait_for_mpcc_disconnect( 2916fb3466a4SBhawanpreet Lakha struct dc *dc, 29176be425f3SEric Yang struct resource_pool *res_pool, 29186be425f3SEric Yang struct pipe_ctx *pipe_ctx) 2919b6762f0cSEric Yang { 2920b6762f0cSEric Yang /* do nothing*/ 2921b6762f0cSEric Yang } 2922b6762f0cSEric Yang 29234bd0dc68SJoshua Aberback static void program_output_csc(struct dc *dc, 29244bd0dc68SJoshua Aberback struct pipe_ctx *pipe_ctx, 29254bd0dc68SJoshua Aberback enum dc_color_space colorspace, 29264bd0dc68SJoshua Aberback uint16_t *matrix, 29274bd0dc68SJoshua Aberback int opp_id) 29284bd0dc68SJoshua Aberback { 29294bd0dc68SJoshua Aberback int i; 29304bd0dc68SJoshua Aberback struct out_csc_color_matrix tbl_entry; 29314bd0dc68SJoshua Aberback 29324bd0dc68SJoshua Aberback if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 29334bd0dc68SJoshua Aberback enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 29344bd0dc68SJoshua Aberback 29354bd0dc68SJoshua Aberback for (i = 0; i < 12; i++) 29364bd0dc68SJoshua Aberback tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 29374bd0dc68SJoshua Aberback 29384bd0dc68SJoshua Aberback tbl_entry.color_space = color_space; 29394bd0dc68SJoshua Aberback 29404bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 29414bd0dc68SJoshua Aberback pipe_ctx->plane_res.xfm, &tbl_entry); 29424bd0dc68SJoshua Aberback } 29434bd0dc68SJoshua Aberback } 29444bd0dc68SJoshua Aberback 2945faf0389fSJason Yan static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 294633fd17d9SEric Yang { 294733fd17d9SEric Yang struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 294833fd17d9SEric Yang struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 294933fd17d9SEric Yang struct mem_input *mi = pipe_ctx->plane_res.mi; 295033fd17d9SEric Yang struct dc_cursor_mi_param param = { 2951380604e2SKen Chalmers .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 295233d7598dSJun Lei .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 295339a9f4d8SDmytro Laktyushkin .viewport = pipe_ctx->plane_res.scl_data.viewport, 295439a9f4d8SDmytro Laktyushkin .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 295539a9f4d8SDmytro Laktyushkin .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 295608ed681cSDmytro Laktyushkin .rotation = pipe_ctx->plane_state->rotation, 295708ed681cSDmytro Laktyushkin .mirror = pipe_ctx->plane_state->horizontal_mirror 295833fd17d9SEric Yang }; 295933fd17d9SEric Yang 296003a4059bSNicholas Kazlauskas /** 296103a4059bSNicholas Kazlauskas * If the cursor's source viewport is clipped then we need to 296203a4059bSNicholas Kazlauskas * translate the cursor to appear in the correct position on 296303a4059bSNicholas Kazlauskas * the screen. 296403a4059bSNicholas Kazlauskas * 296503a4059bSNicholas Kazlauskas * This translation isn't affected by scaling so it needs to be 296603a4059bSNicholas Kazlauskas * done *after* we adjust the position for the scale factor. 2967033baeeeSNicholas Kazlauskas * 2968033baeeeSNicholas Kazlauskas * This is only done by opt-in for now since there are still 2969033baeeeSNicholas Kazlauskas * some usecases like tiled display that might enable the 2970033baeeeSNicholas Kazlauskas * cursor on both streams while expecting dc to clip it. 297103a4059bSNicholas Kazlauskas */ 2972033baeeeSNicholas Kazlauskas if (pos_cpy.translate_by_source) { 297303a4059bSNicholas Kazlauskas pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 297403a4059bSNicholas Kazlauskas pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 2975033baeeeSNicholas Kazlauskas } 297603a4059bSNicholas Kazlauskas 297733fd17d9SEric Yang if (pipe_ctx->plane_state->address.type 297833fd17d9SEric Yang == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 297933fd17d9SEric Yang pos_cpy.enable = false; 298033fd17d9SEric Yang 298133fd17d9SEric Yang if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 298233fd17d9SEric Yang pos_cpy.enable = false; 298333fd17d9SEric Yang 2984dc75dd70SRoman Li if (ipp->funcs->ipp_cursor_set_position) 298533fd17d9SEric Yang ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 2986dc75dd70SRoman Li if (mi->funcs->set_cursor_position) 298733fd17d9SEric Yang mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 298833fd17d9SEric Yang } 298933fd17d9SEric Yang 2990faf0389fSJason Yan static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 299133fd17d9SEric Yang { 299233fd17d9SEric Yang struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 299333fd17d9SEric Yang 2994d1aaad05SHarry Wentland if (pipe_ctx->plane_res.ipp && 2995d1aaad05SHarry Wentland pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 299633fd17d9SEric Yang pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 299733fd17d9SEric Yang pipe_ctx->plane_res.ipp, attributes); 299833fd17d9SEric Yang 2999d1aaad05SHarry Wentland if (pipe_ctx->plane_res.mi && 3000d1aaad05SHarry Wentland pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 300133fd17d9SEric Yang pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 300233fd17d9SEric Yang pipe_ctx->plane_res.mi, attributes); 300333fd17d9SEric Yang 3004d1aaad05SHarry Wentland if (pipe_ctx->plane_res.xfm && 3005d1aaad05SHarry Wentland pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 300633fd17d9SEric Yang pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 300733fd17d9SEric Yang pipe_ctx->plane_res.xfm, attributes); 300833fd17d9SEric Yang } 300933fd17d9SEric Yang 30104b0e95d1SYongqiang Sun bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 30114b0e95d1SYongqiang Sun uint32_t backlight_pwm_u16_16, 30124b0e95d1SYongqiang Sun uint32_t frame_ramp) 30134b0e95d1SYongqiang Sun { 30144b0e95d1SYongqiang Sun struct dc_link *link = pipe_ctx->stream->link; 30154b0e95d1SYongqiang Sun struct dc *dc = link->ctx->dc; 30164b0e95d1SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 30173ba01817SYongqiang Sun struct panel_cntl *panel_cntl = link->panel_cntl; 30184b0e95d1SYongqiang Sun struct dmcu *dmcu = dc->res_pool->dmcu; 30194b0e95d1SYongqiang Sun bool fw_set_brightness = true; 30204b0e95d1SYongqiang Sun /* DMCU -1 for all controller id values, 30214b0e95d1SYongqiang Sun * therefore +1 here 30224b0e95d1SYongqiang Sun */ 30234b0e95d1SYongqiang Sun uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 30244b0e95d1SYongqiang Sun 30253ba01817SYongqiang Sun if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 30264b0e95d1SYongqiang Sun return false; 30274b0e95d1SYongqiang Sun 30284b0e95d1SYongqiang Sun if (dmcu) 30294b0e95d1SYongqiang Sun fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 30304b0e95d1SYongqiang Sun 30313ba01817SYongqiang Sun if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 30323ba01817SYongqiang Sun panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 30333ba01817SYongqiang Sun else 30344b0e95d1SYongqiang Sun abm->funcs->set_backlight_level_pwm( 30354b0e95d1SYongqiang Sun abm, 30364b0e95d1SYongqiang Sun backlight_pwm_u16_16, 30374b0e95d1SYongqiang Sun frame_ramp, 30384b0e95d1SYongqiang Sun controller_id, 30393ba01817SYongqiang Sun link->panel_cntl->inst); 30404b0e95d1SYongqiang Sun 30414b0e95d1SYongqiang Sun return true; 30424b0e95d1SYongqiang Sun } 30434b0e95d1SYongqiang Sun 30443ba01817SYongqiang Sun void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 30453ba01817SYongqiang Sun { 30463ba01817SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 30473ba01817SYongqiang Sun struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 30483ba01817SYongqiang Sun 30493ba01817SYongqiang Sun if (abm) 30503ba01817SYongqiang Sun abm->funcs->set_abm_immediate_disable(abm, 30513ba01817SYongqiang Sun pipe_ctx->stream->link->panel_cntl->inst); 30523ba01817SYongqiang Sun 30533ba01817SYongqiang Sun if (panel_cntl) 30543ba01817SYongqiang Sun panel_cntl->funcs->store_backlight_level(panel_cntl); 30553ba01817SYongqiang Sun } 30563ba01817SYongqiang Sun 3057474ac4a8SYongqiang Sun void dce110_set_pipe(struct pipe_ctx *pipe_ctx) 3058474ac4a8SYongqiang Sun { 3059474ac4a8SYongqiang Sun struct abm *abm = pipe_ctx->stream_res.abm; 3060474ac4a8SYongqiang Sun struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 3061474ac4a8SYongqiang Sun uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; 3062474ac4a8SYongqiang Sun 3063474ac4a8SYongqiang Sun if (abm && panel_cntl) 3064474ac4a8SYongqiang Sun abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); 3065474ac4a8SYongqiang Sun } 3066474ac4a8SYongqiang Sun 30674562236bSHarry Wentland static const struct hw_sequencer_funcs dce110_funcs = { 30681bf56e62SZeyu Fan .program_gamut_remap = program_gamut_remap, 30694bd0dc68SJoshua Aberback .program_output_csc = program_output_csc, 30704562236bSHarry Wentland .init_hw = init_hw, 30714562236bSHarry Wentland .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 30724562236bSHarry Wentland .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 3073bbf5f6c3SAnthony Koo .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 30744562236bSHarry Wentland .update_plane_addr = update_plane_addr, 30754562236bSHarry Wentland .update_pending_status = dce110_update_pending_status, 30764562236bSHarry Wentland .enable_accelerated_mode = dce110_enable_accelerated_mode, 30774562236bSHarry Wentland .enable_timing_synchronization = dce110_enable_timing_synchronization, 3078fa2123dbSMikita Lipski .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 30794562236bSHarry Wentland .update_info_frame = dce110_update_info_frame, 30804562236bSHarry Wentland .enable_stream = dce110_enable_stream, 30814562236bSHarry Wentland .disable_stream = dce110_disable_stream, 30824562236bSHarry Wentland .unblank_stream = dce110_unblank_stream, 308341b49742SCharlene Liu .blank_stream = dce110_blank_stream, 30841a05873fSAnthony Koo .enable_audio_stream = dce110_enable_audio_stream, 30851a05873fSAnthony Koo .disable_audio_stream = dce110_disable_audio_stream, 30867f914a62SYongqiang Sun .disable_plane = dce110_power_down_fe, 30874562236bSHarry Wentland .pipe_control_lock = dce_pipe_control_lock, 3088009114f6SAnthony Koo .interdependent_update_lock = NULL, 30891e461c37SAric Cyr .cursor_lock = dce_pipe_control_lock, 30909566b675SDmytro Laktyushkin .prepare_bandwidth = dce110_prepare_bandwidth, 30919566b675SDmytro Laktyushkin .optimize_bandwidth = dce110_optimize_bandwidth, 30924562236bSHarry Wentland .set_drr = set_drr, 309372ada5f7SEric Cook .get_position = get_position, 30944562236bSHarry Wentland .set_static_screen_control = set_static_screen_control, 309515e17335SCharlene Liu .setup_stereo = NULL, 309615e17335SCharlene Liu .set_avmute = dce110_set_avmute, 309741f97c07SHersen Wu .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 3098099303e9SPeikang Zhang .edp_backlight_control = dce110_edp_backlight_control, 30998a31820bSMartin Leung .edp_power_control = dce110_edp_power_control, 31008a31820bSMartin Leung .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 310133fd17d9SEric Yang .set_cursor_position = dce110_set_cursor_position, 31024b0e95d1SYongqiang Sun .set_cursor_attribute = dce110_set_cursor_attribute, 31034b0e95d1SYongqiang Sun .set_backlight_level = dce110_set_backlight_level, 31043ba01817SYongqiang Sun .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 3105474ac4a8SYongqiang Sun .set_pipe = dce110_set_pipe, 31064562236bSHarry Wentland }; 31074562236bSHarry Wentland 3108f42ea55bSAnthony Koo static const struct hwseq_private_funcs dce110_private_funcs = { 3109f42ea55bSAnthony Koo .init_pipes = init_pipes, 3110f42ea55bSAnthony Koo .update_plane_addr = update_plane_addr, 3111f42ea55bSAnthony Koo .set_input_transfer_func = dce110_set_input_transfer_func, 3112f42ea55bSAnthony Koo .set_output_transfer_func = dce110_set_output_transfer_func, 3113f42ea55bSAnthony Koo .power_down = dce110_power_down, 3114f42ea55bSAnthony Koo .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 3115f42ea55bSAnthony Koo .enable_display_power_gating = dce110_enable_display_power_gating, 3116f42ea55bSAnthony Koo .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 3117f42ea55bSAnthony Koo .enable_stream_timing = dce110_enable_stream_timing, 3118f42ea55bSAnthony Koo .disable_stream_gating = NULL, 3119f42ea55bSAnthony Koo .enable_stream_gating = NULL, 3120f42ea55bSAnthony Koo .edp_backlight_control = dce110_edp_backlight_control, 3121f42ea55bSAnthony Koo }; 3122f42ea55bSAnthony Koo 3123c13b408bSDave Airlie void dce110_hw_sequencer_construct(struct dc *dc) 31244562236bSHarry Wentland { 31254562236bSHarry Wentland dc->hwss = dce110_funcs; 3126f42ea55bSAnthony Koo dc->hwseq->funcs = dce110_private_funcs; 31274562236bSHarry Wentland } 31284562236bSHarry Wentland 3129