1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "link_encoder.h" 33 #include "stream_encoder.h" 34 #include "opp.h" 35 #include "timing_generator.h" 36 #include "transform.h" 37 #include "dccg.h" 38 #include "dchubbub.h" 39 #include "dpp.h" 40 #include "core_types.h" 41 #include "set_mode_types.h" 42 #include "virtual/virtual_stream_encoder.h" 43 #include "dpcd_defs.h" 44 #include "link_enc_cfg.h" 45 #include "dc_link_dp.h" 46 #include "virtual/virtual_link_hwss.h" 47 #include "link/link_hwss_dio.h" 48 #include "link/link_hwss_dpia.h" 49 #include "link/link_hwss_hpo_dp.h" 50 51 #if defined(CONFIG_DRM_AMD_DC_SI) 52 #include "dce60/dce60_resource.h" 53 #endif 54 #include "dce80/dce80_resource.h" 55 #include "dce100/dce100_resource.h" 56 #include "dce110/dce110_resource.h" 57 #include "dce112/dce112_resource.h" 58 #include "dce120/dce120_resource.h" 59 #if defined(CONFIG_DRM_AMD_DC_DCN) 60 #include "dcn10/dcn10_resource.h" 61 #include "dcn20/dcn20_resource.h" 62 #include "dcn21/dcn21_resource.h" 63 #include "dcn201/dcn201_resource.h" 64 #include "dcn30/dcn30_resource.h" 65 #include "dcn301/dcn301_resource.h" 66 #include "dcn302/dcn302_resource.h" 67 #include "dcn303/dcn303_resource.h" 68 #include "dcn31/dcn31_resource.h" 69 #include "dcn315/dcn315_resource.h" 70 #include "dcn316/dcn316_resource.h" 71 #endif 72 73 #define DC_LOGGER_INIT(logger) 74 75 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 76 { 77 enum dce_version dc_version = DCE_VERSION_UNKNOWN; 78 switch (asic_id.chip_family) { 79 80 #if defined(CONFIG_DRM_AMD_DC_SI) 81 case FAMILY_SI: 82 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) || 83 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) || 84 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev)) 85 dc_version = DCE_VERSION_6_0; 86 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev)) 87 dc_version = DCE_VERSION_6_4; 88 else 89 dc_version = DCE_VERSION_6_1; 90 break; 91 #endif 92 case FAMILY_CI: 93 dc_version = DCE_VERSION_8_0; 94 break; 95 case FAMILY_KV: 96 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) || 97 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) || 98 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev)) 99 dc_version = DCE_VERSION_8_3; 100 else 101 dc_version = DCE_VERSION_8_1; 102 break; 103 case FAMILY_CZ: 104 dc_version = DCE_VERSION_11_0; 105 break; 106 107 case FAMILY_VI: 108 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || 109 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { 110 dc_version = DCE_VERSION_10_0; 111 break; 112 } 113 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || 114 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || 115 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { 116 dc_version = DCE_VERSION_11_2; 117 } 118 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) 119 dc_version = DCE_VERSION_11_22; 120 break; 121 case FAMILY_AI: 122 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev)) 123 dc_version = DCE_VERSION_12_1; 124 else 125 dc_version = DCE_VERSION_12_0; 126 break; 127 #if defined(CONFIG_DRM_AMD_DC_DCN) 128 case FAMILY_RV: 129 dc_version = DCN_VERSION_1_0; 130 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) 131 dc_version = DCN_VERSION_1_01; 132 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) 133 dc_version = DCN_VERSION_2_1; 134 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) 135 dc_version = DCN_VERSION_2_1; 136 break; 137 138 case FAMILY_NV: 139 dc_version = DCN_VERSION_2_0; 140 if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) { 141 dc_version = DCN_VERSION_2_01; 142 break; 143 } 144 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) 145 dc_version = DCN_VERSION_3_0; 146 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) 147 dc_version = DCN_VERSION_3_02; 148 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) 149 dc_version = DCN_VERSION_3_03; 150 break; 151 152 case FAMILY_VGH: 153 dc_version = DCN_VERSION_3_01; 154 break; 155 156 case FAMILY_YELLOW_CARP: 157 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) 158 dc_version = DCN_VERSION_3_1; 159 break; 160 case AMDGPU_FAMILY_GC_10_3_6: 161 if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev)) 162 dc_version = DCN_VERSION_3_15; 163 break; 164 case AMDGPU_FAMILY_GC_10_3_7: 165 if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev)) 166 dc_version = DCN_VERSION_3_16; 167 break; 168 #endif 169 170 default: 171 dc_version = DCE_VERSION_UNKNOWN; 172 break; 173 } 174 return dc_version; 175 } 176 177 struct resource_pool *dc_create_resource_pool(struct dc *dc, 178 const struct dc_init_data *init_data, 179 enum dce_version dc_version) 180 { 181 struct resource_pool *res_pool = NULL; 182 183 switch (dc_version) { 184 #if defined(CONFIG_DRM_AMD_DC_SI) 185 case DCE_VERSION_6_0: 186 res_pool = dce60_create_resource_pool( 187 init_data->num_virtual_links, dc); 188 break; 189 case DCE_VERSION_6_1: 190 res_pool = dce61_create_resource_pool( 191 init_data->num_virtual_links, dc); 192 break; 193 case DCE_VERSION_6_4: 194 res_pool = dce64_create_resource_pool( 195 init_data->num_virtual_links, dc); 196 break; 197 #endif 198 case DCE_VERSION_8_0: 199 res_pool = dce80_create_resource_pool( 200 init_data->num_virtual_links, dc); 201 break; 202 case DCE_VERSION_8_1: 203 res_pool = dce81_create_resource_pool( 204 init_data->num_virtual_links, dc); 205 break; 206 case DCE_VERSION_8_3: 207 res_pool = dce83_create_resource_pool( 208 init_data->num_virtual_links, dc); 209 break; 210 case DCE_VERSION_10_0: 211 res_pool = dce100_create_resource_pool( 212 init_data->num_virtual_links, dc); 213 break; 214 case DCE_VERSION_11_0: 215 res_pool = dce110_create_resource_pool( 216 init_data->num_virtual_links, dc, 217 init_data->asic_id); 218 break; 219 case DCE_VERSION_11_2: 220 case DCE_VERSION_11_22: 221 res_pool = dce112_create_resource_pool( 222 init_data->num_virtual_links, dc); 223 break; 224 case DCE_VERSION_12_0: 225 case DCE_VERSION_12_1: 226 res_pool = dce120_create_resource_pool( 227 init_data->num_virtual_links, dc); 228 break; 229 230 #if defined(CONFIG_DRM_AMD_DC_DCN) 231 case DCN_VERSION_1_0: 232 case DCN_VERSION_1_01: 233 res_pool = dcn10_create_resource_pool(init_data, dc); 234 break; 235 case DCN_VERSION_2_0: 236 res_pool = dcn20_create_resource_pool(init_data, dc); 237 break; 238 case DCN_VERSION_2_1: 239 res_pool = dcn21_create_resource_pool(init_data, dc); 240 break; 241 case DCN_VERSION_2_01: 242 res_pool = dcn201_create_resource_pool(init_data, dc); 243 break; 244 case DCN_VERSION_3_0: 245 res_pool = dcn30_create_resource_pool(init_data, dc); 246 break; 247 case DCN_VERSION_3_01: 248 res_pool = dcn301_create_resource_pool(init_data, dc); 249 break; 250 case DCN_VERSION_3_02: 251 res_pool = dcn302_create_resource_pool(init_data, dc); 252 break; 253 case DCN_VERSION_3_03: 254 res_pool = dcn303_create_resource_pool(init_data, dc); 255 break; 256 case DCN_VERSION_3_1: 257 res_pool = dcn31_create_resource_pool(init_data, dc); 258 break; 259 case DCN_VERSION_3_15: 260 res_pool = dcn315_create_resource_pool(init_data, dc); 261 break; 262 case DCN_VERSION_3_16: 263 res_pool = dcn316_create_resource_pool(init_data, dc); 264 break; 265 #endif 266 default: 267 break; 268 } 269 270 if (res_pool != NULL) { 271 if (dc->ctx->dc_bios->fw_info_valid) { 272 res_pool->ref_clocks.xtalin_clock_inKhz = 273 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 274 /* initialize with firmware data first, no all 275 * ASIC have DCCG SW component. FPGA or 276 * simulation need initialization of 277 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz 278 * with xtalin_clock_inKhz 279 */ 280 res_pool->ref_clocks.dccg_ref_clock_inKhz = 281 res_pool->ref_clocks.xtalin_clock_inKhz; 282 res_pool->ref_clocks.dchub_ref_clock_inKhz = 283 res_pool->ref_clocks.xtalin_clock_inKhz; 284 } else 285 ASSERT_CRITICAL(false); 286 } 287 288 return res_pool; 289 } 290 291 void dc_destroy_resource_pool(struct dc *dc) 292 { 293 if (dc) { 294 if (dc->res_pool) 295 dc->res_pool->funcs->destroy(&dc->res_pool); 296 297 kfree(dc->hwseq); 298 } 299 } 300 301 static void update_num_audio( 302 const struct resource_straps *straps, 303 unsigned int *num_audio, 304 struct audio_support *aud_support) 305 { 306 aud_support->dp_audio = true; 307 aud_support->hdmi_audio_native = false; 308 aud_support->hdmi_audio_on_dongle = false; 309 310 if (straps->hdmi_disable == 0) { 311 if (straps->dc_pinstraps_audio & 0x2) { 312 aud_support->hdmi_audio_on_dongle = true; 313 aud_support->hdmi_audio_native = true; 314 } 315 } 316 317 switch (straps->audio_stream_number) { 318 case 0: /* multi streams supported */ 319 break; 320 case 1: /* multi streams not supported */ 321 *num_audio = 1; 322 break; 323 default: 324 DC_ERR("DC: unexpected audio fuse!\n"); 325 } 326 } 327 328 bool resource_construct( 329 unsigned int num_virtual_links, 330 struct dc *dc, 331 struct resource_pool *pool, 332 const struct resource_create_funcs *create_funcs) 333 { 334 struct dc_context *ctx = dc->ctx; 335 const struct resource_caps *caps = pool->res_cap; 336 int i; 337 unsigned int num_audio = caps->num_audio; 338 struct resource_straps straps = {0}; 339 340 if (create_funcs->read_dce_straps) 341 create_funcs->read_dce_straps(dc->ctx, &straps); 342 343 pool->audio_count = 0; 344 if (create_funcs->create_audio) { 345 /* find the total number of streams available via the 346 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 347 * registers (one for each pin) starting from pin 1 348 * up to the max number of audio pins. 349 * We stop on the first pin where 350 * PORT_CONNECTIVITY == 1 (as instructed by HW team). 351 */ 352 update_num_audio(&straps, &num_audio, &pool->audio_support); 353 for (i = 0; i < caps->num_audio; i++) { 354 struct audio *aud = create_funcs->create_audio(ctx, i); 355 356 if (aud == NULL) { 357 DC_ERR("DC: failed to create audio!\n"); 358 return false; 359 } 360 if (!aud->funcs->endpoint_valid(aud)) { 361 aud->funcs->destroy(&aud); 362 break; 363 } 364 pool->audios[i] = aud; 365 pool->audio_count++; 366 } 367 } 368 369 pool->stream_enc_count = 0; 370 if (create_funcs->create_stream_encoder) { 371 for (i = 0; i < caps->num_stream_encoder; i++) { 372 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); 373 if (pool->stream_enc[i] == NULL) 374 DC_ERR("DC: failed to create stream_encoder!\n"); 375 pool->stream_enc_count++; 376 } 377 } 378 379 pool->hpo_dp_stream_enc_count = 0; 380 if (create_funcs->create_hpo_dp_stream_encoder) { 381 for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) { 382 pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx); 383 if (pool->hpo_dp_stream_enc[i] == NULL) 384 DC_ERR("DC: failed to create HPO DP stream encoder!\n"); 385 pool->hpo_dp_stream_enc_count++; 386 387 } 388 } 389 390 pool->hpo_dp_link_enc_count = 0; 391 if (create_funcs->create_hpo_dp_link_encoder) { 392 for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) { 393 pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx); 394 if (pool->hpo_dp_link_enc[i] == NULL) 395 DC_ERR("DC: failed to create HPO DP link encoder!\n"); 396 pool->hpo_dp_link_enc_count++; 397 } 398 } 399 400 #if defined(CONFIG_DRM_AMD_DC_DCN) 401 for (i = 0; i < caps->num_mpc_3dlut; i++) { 402 pool->mpc_lut[i] = dc_create_3dlut_func(); 403 if (pool->mpc_lut[i] == NULL) 404 DC_ERR("DC: failed to create MPC 3dlut!\n"); 405 pool->mpc_shaper[i] = dc_create_transfer_func(); 406 if (pool->mpc_shaper[i] == NULL) 407 DC_ERR("DC: failed to create MPC shaper!\n"); 408 } 409 #endif 410 dc->caps.dynamic_audio = false; 411 if (pool->audio_count < pool->stream_enc_count) { 412 dc->caps.dynamic_audio = true; 413 } 414 for (i = 0; i < num_virtual_links; i++) { 415 pool->stream_enc[pool->stream_enc_count] = 416 virtual_stream_encoder_create( 417 ctx, ctx->dc_bios); 418 if (pool->stream_enc[pool->stream_enc_count] == NULL) { 419 DC_ERR("DC: failed to create stream_encoder!\n"); 420 return false; 421 } 422 pool->stream_enc_count++; 423 } 424 425 dc->hwseq = create_funcs->create_hwseq(ctx); 426 427 return true; 428 } 429 static int find_matching_clock_source( 430 const struct resource_pool *pool, 431 struct clock_source *clock_source) 432 { 433 434 int i; 435 436 for (i = 0; i < pool->clk_src_count; i++) { 437 if (pool->clock_sources[i] == clock_source) 438 return i; 439 } 440 return -1; 441 } 442 443 void resource_unreference_clock_source( 444 struct resource_context *res_ctx, 445 const struct resource_pool *pool, 446 struct clock_source *clock_source) 447 { 448 int i = find_matching_clock_source(pool, clock_source); 449 450 if (i > -1) 451 res_ctx->clock_source_ref_count[i]--; 452 453 if (pool->dp_clock_source == clock_source) 454 res_ctx->dp_clock_source_ref_count--; 455 } 456 457 void resource_reference_clock_source( 458 struct resource_context *res_ctx, 459 const struct resource_pool *pool, 460 struct clock_source *clock_source) 461 { 462 int i = find_matching_clock_source(pool, clock_source); 463 464 if (i > -1) 465 res_ctx->clock_source_ref_count[i]++; 466 467 if (pool->dp_clock_source == clock_source) 468 res_ctx->dp_clock_source_ref_count++; 469 } 470 471 int resource_get_clock_source_reference( 472 struct resource_context *res_ctx, 473 const struct resource_pool *pool, 474 struct clock_source *clock_source) 475 { 476 int i = find_matching_clock_source(pool, clock_source); 477 478 if (i > -1) 479 return res_ctx->clock_source_ref_count[i]; 480 481 if (pool->dp_clock_source == clock_source) 482 return res_ctx->dp_clock_source_ref_count; 483 484 return -1; 485 } 486 487 bool resource_are_vblanks_synchronizable( 488 struct dc_stream_state *stream1, 489 struct dc_stream_state *stream2) 490 { 491 uint32_t base60_refresh_rates[] = {10, 20, 5}; 492 uint8_t i; 493 uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates); 494 uint64_t frame_time_diff; 495 496 if (stream1->ctx->dc->config.vblank_alignment_dto_params && 497 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 && 498 dc_is_dp_signal(stream1->signal) && 499 dc_is_dp_signal(stream2->signal) && 500 false == stream1->has_non_synchronizable_pclk && 501 false == stream2->has_non_synchronizable_pclk && 502 stream1->timing.flags.VBLANK_SYNCHRONIZABLE && 503 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) { 504 /* disable refresh rates higher than 60Hz for now */ 505 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/ 506 stream1->timing.v_total > 60) 507 return false; 508 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/ 509 stream2->timing.v_total > 60) 510 return false; 511 frame_time_diff = (uint64_t)10000 * 512 stream1->timing.h_total * 513 stream1->timing.v_total * 514 stream2->timing.pix_clk_100hz; 515 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz); 516 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total); 517 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total); 518 for (i = 0; i < rr_count; i++) { 519 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000; 520 521 if (diff < 0) 522 diff = -diff; 523 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff) 524 return true; 525 } 526 } 527 return false; 528 } 529 530 bool resource_are_streams_timing_synchronizable( 531 struct dc_stream_state *stream1, 532 struct dc_stream_state *stream2) 533 { 534 if (stream1->timing.h_total != stream2->timing.h_total) 535 return false; 536 537 if (stream1->timing.v_total != stream2->timing.v_total) 538 return false; 539 540 if (stream1->timing.h_addressable 541 != stream2->timing.h_addressable) 542 return false; 543 544 if (stream1->timing.v_addressable 545 != stream2->timing.v_addressable) 546 return false; 547 548 if (stream1->timing.v_front_porch 549 != stream2->timing.v_front_porch) 550 return false; 551 552 if (stream1->timing.pix_clk_100hz 553 != stream2->timing.pix_clk_100hz) 554 return false; 555 556 if (stream1->clamping.c_depth != stream2->clamping.c_depth) 557 return false; 558 559 if (stream1->phy_pix_clk != stream2->phy_pix_clk 560 && (!dc_is_dp_signal(stream1->signal) 561 || !dc_is_dp_signal(stream2->signal))) 562 return false; 563 564 if (stream1->view_format != stream2->view_format) 565 return false; 566 567 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param) 568 return false; 569 570 return true; 571 } 572 static bool is_dp_and_hdmi_sharable( 573 struct dc_stream_state *stream1, 574 struct dc_stream_state *stream2) 575 { 576 if (stream1->ctx->dc->caps.disable_dp_clk_share) 577 return false; 578 579 if (stream1->clamping.c_depth != COLOR_DEPTH_888 || 580 stream2->clamping.c_depth != COLOR_DEPTH_888) 581 return false; 582 583 return true; 584 585 } 586 587 static bool is_sharable_clk_src( 588 const struct pipe_ctx *pipe_with_clk_src, 589 const struct pipe_ctx *pipe) 590 { 591 if (pipe_with_clk_src->clock_source == NULL) 592 return false; 593 594 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) 595 return false; 596 597 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) || 598 (dc_is_dp_signal(pipe->stream->signal) && 599 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream, 600 pipe->stream))) 601 return false; 602 603 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) 604 && dc_is_dual_link_signal(pipe->stream->signal)) 605 return false; 606 607 if (dc_is_hdmi_signal(pipe->stream->signal) 608 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal)) 609 return false; 610 611 if (!resource_are_streams_timing_synchronizable( 612 pipe_with_clk_src->stream, pipe->stream)) 613 return false; 614 615 return true; 616 } 617 618 struct clock_source *resource_find_used_clk_src_for_sharing( 619 struct resource_context *res_ctx, 620 struct pipe_ctx *pipe_ctx) 621 { 622 int i; 623 624 for (i = 0; i < MAX_PIPES; i++) { 625 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) 626 return res_ctx->pipe_ctx[i].clock_source; 627 } 628 629 return NULL; 630 } 631 632 static enum pixel_format convert_pixel_format_to_dalsurface( 633 enum surface_pixel_format surface_pixel_format) 634 { 635 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 636 637 switch (surface_pixel_format) { 638 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 639 dal_pixel_format = PIXEL_FORMAT_INDEX8; 640 break; 641 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 642 dal_pixel_format = PIXEL_FORMAT_RGB565; 643 break; 644 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 645 dal_pixel_format = PIXEL_FORMAT_RGB565; 646 break; 647 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 648 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 649 break; 650 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 651 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 652 break; 653 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 654 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 655 break; 656 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 657 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 658 break; 659 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 660 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS; 661 break; 662 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 663 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 664 dal_pixel_format = PIXEL_FORMAT_FP16; 665 break; 666 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 667 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 668 dal_pixel_format = PIXEL_FORMAT_420BPP8; 669 break; 670 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 671 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 672 dal_pixel_format = PIXEL_FORMAT_420BPP10; 673 break; 674 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 675 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 676 default: 677 dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 678 break; 679 } 680 return dal_pixel_format; 681 } 682 683 static inline void get_vp_scan_direction( 684 enum dc_rotation_angle rotation, 685 bool horizontal_mirror, 686 bool *orthogonal_rotation, 687 bool *flip_vert_scan_dir, 688 bool *flip_horz_scan_dir) 689 { 690 *orthogonal_rotation = false; 691 *flip_vert_scan_dir = false; 692 *flip_horz_scan_dir = false; 693 if (rotation == ROTATION_ANGLE_180) { 694 *flip_vert_scan_dir = true; 695 *flip_horz_scan_dir = true; 696 } else if (rotation == ROTATION_ANGLE_90) { 697 *orthogonal_rotation = true; 698 *flip_horz_scan_dir = true; 699 } else if (rotation == ROTATION_ANGLE_270) { 700 *orthogonal_rotation = true; 701 *flip_vert_scan_dir = true; 702 } 703 704 if (horizontal_mirror) 705 *flip_horz_scan_dir = !*flip_horz_scan_dir; 706 } 707 708 int get_num_mpc_splits(struct pipe_ctx *pipe) 709 { 710 int mpc_split_count = 0; 711 struct pipe_ctx *other_pipe = pipe->bottom_pipe; 712 713 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 714 mpc_split_count++; 715 other_pipe = other_pipe->bottom_pipe; 716 } 717 other_pipe = pipe->top_pipe; 718 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 719 mpc_split_count++; 720 other_pipe = other_pipe->top_pipe; 721 } 722 723 return mpc_split_count; 724 } 725 726 int get_num_odm_splits(struct pipe_ctx *pipe) 727 { 728 int odm_split_count = 0; 729 struct pipe_ctx *next_pipe = pipe->next_odm_pipe; 730 while (next_pipe) { 731 odm_split_count++; 732 next_pipe = next_pipe->next_odm_pipe; 733 } 734 pipe = pipe->prev_odm_pipe; 735 while (pipe) { 736 odm_split_count++; 737 pipe = pipe->prev_odm_pipe; 738 } 739 return odm_split_count; 740 } 741 742 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx) 743 { 744 *split_count = get_num_odm_splits(pipe_ctx); 745 *split_idx = 0; 746 if (*split_count == 0) { 747 /*Check for mpc split*/ 748 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe; 749 750 *split_count = get_num_mpc_splits(pipe_ctx); 751 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) { 752 (*split_idx)++; 753 split_pipe = split_pipe->top_pipe; 754 } 755 } else { 756 /*Get odm split index*/ 757 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe; 758 759 while (split_pipe) { 760 (*split_idx)++; 761 split_pipe = split_pipe->prev_odm_pipe; 762 } 763 } 764 } 765 766 /* 767 * This is a preliminary vp size calculation to allow us to check taps support. 768 * The result is completely overridden afterwards. 769 */ 770 static void calculate_viewport_size(struct pipe_ctx *pipe_ctx) 771 { 772 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 773 774 data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width)); 775 data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height)); 776 data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width)); 777 data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height)); 778 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 779 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { 780 swap(data->viewport.width, data->viewport.height); 781 swap(data->viewport_c.width, data->viewport_c.height); 782 } 783 } 784 785 static void calculate_recout(struct pipe_ctx *pipe_ctx) 786 { 787 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 788 const struct dc_stream_state *stream = pipe_ctx->stream; 789 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 790 struct rect surf_clip = plane_state->clip_rect; 791 bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; 792 int split_count, split_idx; 793 794 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 795 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 796 split_idx = 0; 797 798 /* 799 * Only the leftmost ODM pipe should be offset by a nonzero distance 800 */ 801 if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) { 802 data->recout.x = stream->dst.x; 803 if (stream->src.x < surf_clip.x) 804 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width 805 / stream->src.width; 806 } else 807 data->recout.x = 0; 808 809 if (stream->src.x > surf_clip.x) 810 surf_clip.width -= stream->src.x - surf_clip.x; 811 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width; 812 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width) 813 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x; 814 815 data->recout.y = stream->dst.y; 816 if (stream->src.y < surf_clip.y) 817 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height 818 / stream->src.height; 819 else if (stream->src.y > surf_clip.y) 820 surf_clip.height -= stream->src.y - surf_clip.y; 821 822 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height; 823 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height) 824 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y; 825 826 /* Handle h & v split */ 827 if (split_tb) { 828 ASSERT(data->recout.height % 2 == 0); 829 data->recout.height /= 2; 830 } else if (split_count) { 831 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) { 832 /* extra pixels in the division remainder need to go to pipes after 833 * the extra pixel index minus one(epimo) defined here as: 834 */ 835 int epimo = split_count - data->recout.width % (split_count + 1); 836 837 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx; 838 if (split_idx > epimo) 839 data->recout.x += split_idx - epimo - 1; 840 ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0); 841 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0); 842 } else { 843 /* odm */ 844 if (split_idx == split_count) { 845 /* rightmost pipe is the remainder recout */ 846 data->recout.width -= data->h_active * split_count - data->recout.x; 847 848 /* ODM combine cases with MPO we can get negative widths */ 849 if (data->recout.width < 0) 850 data->recout.width = 0; 851 852 data->recout.x = 0; 853 } else 854 data->recout.width = data->h_active - data->recout.x; 855 } 856 } 857 } 858 859 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) 860 { 861 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 862 const struct dc_stream_state *stream = pipe_ctx->stream; 863 struct rect surf_src = plane_state->src_rect; 864 const int in_w = stream->src.width; 865 const int in_h = stream->src.height; 866 const int out_w = stream->dst.width; 867 const int out_h = stream->dst.height; 868 869 /*Swap surf_src height and width since scaling ratios are in recout rotation*/ 870 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 871 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 872 swap(surf_src.height, surf_src.width); 873 874 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( 875 surf_src.width, 876 plane_state->dst_rect.width); 877 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( 878 surf_src.height, 879 plane_state->dst_rect.height); 880 881 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 882 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; 883 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 884 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; 885 886 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( 887 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); 888 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( 889 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); 890 891 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; 892 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; 893 894 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 895 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { 896 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; 897 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; 898 } 899 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate( 900 pipe_ctx->plane_res.scl_data.ratios.horz, 19); 901 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( 902 pipe_ctx->plane_res.scl_data.ratios.vert, 19); 903 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate( 904 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19); 905 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate( 906 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); 907 } 908 909 910 /* 911 * We completely calculate vp offset, size and inits here based entirely on scaling 912 * ratios and recout for pixel perfect pipe combine. 913 */ 914 static void calculate_init_and_vp( 915 bool flip_scan_dir, 916 int recout_offset_within_recout_full, 917 int recout_size, 918 int src_size, 919 int taps, 920 struct fixed31_32 ratio, 921 struct fixed31_32 *init, 922 int *vp_offset, 923 int *vp_size) 924 { 925 struct fixed31_32 temp; 926 int int_part; 927 928 /* 929 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout 930 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on. 931 * All following calculations are based on this logic. 932 * 933 * Init calculated according to formula: 934 * init = (scaling_ratio + number_of_taps + 1) / 2 935 * init_bot = init + scaling_ratio 936 * to get pixel perfect combine add the fraction from calculating vp offset 937 */ 938 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full); 939 *vp_offset = dc_fixpt_floor(temp); 940 temp.value &= 0xffffffff; 941 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int( 942 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19); 943 /* 944 * If viewport has non 0 offset and there are more taps than covered by init then 945 * we should decrease the offset and increase init so we are never sampling 946 * outside of viewport. 947 */ 948 int_part = dc_fixpt_floor(*init); 949 if (int_part < taps) { 950 int_part = taps - int_part; 951 if (int_part > *vp_offset) 952 int_part = *vp_offset; 953 *vp_offset -= int_part; 954 *init = dc_fixpt_add_int(*init, int_part); 955 } 956 /* 957 * If taps are sampling outside of viewport at end of recout and there are more pixels 958 * available in the surface we should increase the viewport size, regardless set vp to 959 * only what is used. 960 */ 961 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1)); 962 *vp_size = dc_fixpt_floor(temp); 963 if (*vp_size + *vp_offset > src_size) 964 *vp_size = src_size - *vp_offset; 965 966 /* We did all the math assuming we are scanning same direction as display does, 967 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction 968 * is flipped we simply need to calculate offset from the other side of plane. 969 * Note that outside of viewport all scaling hardware works in recout space. 970 */ 971 if (flip_scan_dir) 972 *vp_offset = src_size - *vp_offset - *vp_size; 973 } 974 975 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx) 976 { 977 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 978 const struct dc_stream_state *stream = pipe_ctx->stream; 979 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 980 struct rect src = plane_state->src_rect; 981 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 982 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 983 int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y; 984 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; 985 986 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 987 /* 988 * recout full is what the recout would have been if we didnt clip 989 * the source plane at all. We only care about left(ro_lb) and top(ro_tb) 990 * offsets of recout within recout full because those are the directions 991 * we scan from and therefore the only ones that affect inits. 992 */ 993 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) 994 * stream->dst.width / stream->src.width; 995 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) 996 * stream->dst.height / stream->src.height; 997 if (pipe_ctx->prev_odm_pipe && split_idx) 998 ro_lb = data->h_active * split_idx - recout_full_x; 999 else 1000 ro_lb = data->recout.x - recout_full_x; 1001 ro_tb = data->recout.y - recout_full_y; 1002 ASSERT(ro_lb >= 0 && ro_tb >= 0); 1003 1004 /* 1005 * Work in recout rotation since that requires less transformations 1006 */ 1007 get_vp_scan_direction( 1008 plane_state->rotation, 1009 plane_state->horizontal_mirror, 1010 &orthogonal_rotation, 1011 &flip_vert_scan_dir, 1012 &flip_horz_scan_dir); 1013 1014 if (orthogonal_rotation) { 1015 swap(src.width, src.height); 1016 swap(flip_vert_scan_dir, flip_horz_scan_dir); 1017 } 1018 1019 calculate_init_and_vp( 1020 flip_horz_scan_dir, 1021 ro_lb, 1022 data->recout.width, 1023 src.width, 1024 data->taps.h_taps, 1025 data->ratios.horz, 1026 &data->inits.h, 1027 &data->viewport.x, 1028 &data->viewport.width); 1029 calculate_init_and_vp( 1030 flip_horz_scan_dir, 1031 ro_lb, 1032 data->recout.width, 1033 src.width / vpc_div, 1034 data->taps.h_taps_c, 1035 data->ratios.horz_c, 1036 &data->inits.h_c, 1037 &data->viewport_c.x, 1038 &data->viewport_c.width); 1039 calculate_init_and_vp( 1040 flip_vert_scan_dir, 1041 ro_tb, 1042 data->recout.height, 1043 src.height, 1044 data->taps.v_taps, 1045 data->ratios.vert, 1046 &data->inits.v, 1047 &data->viewport.y, 1048 &data->viewport.height); 1049 calculate_init_and_vp( 1050 flip_vert_scan_dir, 1051 ro_tb, 1052 data->recout.height, 1053 src.height / vpc_div, 1054 data->taps.v_taps_c, 1055 data->ratios.vert_c, 1056 &data->inits.v_c, 1057 &data->viewport_c.y, 1058 &data->viewport_c.height); 1059 if (orthogonal_rotation) { 1060 swap(data->viewport.x, data->viewport.y); 1061 swap(data->viewport.width, data->viewport.height); 1062 swap(data->viewport_c.x, data->viewport_c.y); 1063 swap(data->viewport_c.width, data->viewport_c.height); 1064 } 1065 data->viewport.x += src.x; 1066 data->viewport.y += src.y; 1067 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); 1068 data->viewport_c.x += src.x / vpc_div; 1069 data->viewport_c.y += src.y / vpc_div; 1070 } 1071 1072 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 1073 { 1074 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1075 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 1076 bool res = false; 1077 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 1078 1079 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( 1080 pipe_ctx->plane_state->format); 1081 1082 /* Timing borders are part of vactive that we are also supposed to skip in addition 1083 * to any stream dst offset. Since dm logic assumes dst is in addressable 1084 * space we need to add the left and top borders to dst offsets temporarily. 1085 * TODO: fix in DM, stream dst is supposed to be in vactive 1086 */ 1087 pipe_ctx->stream->dst.x += timing->h_border_left; 1088 pipe_ctx->stream->dst.y += timing->v_border_top; 1089 1090 /* Calculate H and V active size */ 1091 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + 1092 timing->h_border_left + timing->h_border_right; 1093 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + 1094 timing->v_border_top + timing->v_border_bottom; 1095 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe) 1096 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1; 1097 1098 /* depends on h_active */ 1099 calculate_recout(pipe_ctx); 1100 /* depends on pixel format */ 1101 calculate_scaling_ratios(pipe_ctx); 1102 /* depends on scaling ratios and recout, does not calculate offset yet */ 1103 calculate_viewport_size(pipe_ctx); 1104 1105 /* Stopgap for validation of ODM + MPO on one side of screen case */ 1106 if (pipe_ctx->plane_res.scl_data.viewport.height < 1 || 1107 pipe_ctx->plane_res.scl_data.viewport.width < 1) 1108 return false; 1109 1110 /* 1111 * LB calculations depend on vp size, h/v_active and scaling ratios 1112 * Setting line buffer pixel depth to 24bpp yields banding 1113 * on certain displays, such as the Sharp 4k. 36bpp is needed 1114 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and 1115 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc 1116 * precision on at least DCN display engines. However, at least 1117 * Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth, 1118 * so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3 1119 * did not show such problems, so this seems to be the exception. 1120 */ 1121 if (plane_state->ctx->dce_version > DCE_VERSION_11_0) 1122 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; 1123 else 1124 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; 1125 1126 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; 1127 1128 if (pipe_ctx->plane_res.xfm != NULL) 1129 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1130 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1131 1132 if (pipe_ctx->plane_res.dpp != NULL) 1133 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1134 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1135 1136 1137 if (!res) { 1138 /* Try 24 bpp linebuffer */ 1139 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; 1140 1141 if (pipe_ctx->plane_res.xfm != NULL) 1142 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1143 pipe_ctx->plane_res.xfm, 1144 &pipe_ctx->plane_res.scl_data, 1145 &plane_state->scaling_quality); 1146 1147 if (pipe_ctx->plane_res.dpp != NULL) 1148 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1149 pipe_ctx->plane_res.dpp, 1150 &pipe_ctx->plane_res.scl_data, 1151 &plane_state->scaling_quality); 1152 } 1153 1154 /* 1155 * Depends on recout, scaling ratios, h_active and taps 1156 * May need to re-check lb size after this in some obscure scenario 1157 */ 1158 if (res) 1159 calculate_inits_and_viewports(pipe_ctx); 1160 1161 /* 1162 * Handle side by side and top bottom 3d recout offsets after vp calculation 1163 * since 3d is special and needs to calculate vp as if there is no recout offset 1164 * This may break with rotation, good thing we aren't mixing hw rotation and 3d 1165 */ 1166 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) { 1167 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 || 1168 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM && 1169 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE)); 1170 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 1171 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; 1172 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 1173 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; 1174 } 1175 1176 if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) { 1177 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE || 1178 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) 1179 res = false; 1180 } else { 1181 /* Clamp minimum viewport size */ 1182 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE) 1183 pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE; 1184 if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) 1185 pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE; 1186 } 1187 1188 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n" 1189 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n", 1190 __func__, 1191 pipe_ctx->pipe_idx, 1192 pipe_ctx->plane_res.scl_data.viewport.height, 1193 pipe_ctx->plane_res.scl_data.viewport.width, 1194 pipe_ctx->plane_res.scl_data.viewport.x, 1195 pipe_ctx->plane_res.scl_data.viewport.y, 1196 pipe_ctx->plane_res.scl_data.recout.height, 1197 pipe_ctx->plane_res.scl_data.recout.width, 1198 pipe_ctx->plane_res.scl_data.recout.x, 1199 pipe_ctx->plane_res.scl_data.recout.y, 1200 pipe_ctx->plane_res.scl_data.h_active, 1201 pipe_ctx->plane_res.scl_data.v_active, 1202 plane_state->src_rect.height, 1203 plane_state->src_rect.width, 1204 plane_state->src_rect.x, 1205 plane_state->src_rect.y, 1206 plane_state->dst_rect.height, 1207 plane_state->dst_rect.width, 1208 plane_state->dst_rect.x, 1209 plane_state->dst_rect.y, 1210 plane_state->clip_rect.height, 1211 plane_state->clip_rect.width, 1212 plane_state->clip_rect.x, 1213 plane_state->clip_rect.y); 1214 1215 pipe_ctx->stream->dst.x -= timing->h_border_left; 1216 pipe_ctx->stream->dst.y -= timing->v_border_top; 1217 1218 return res; 1219 } 1220 1221 1222 enum dc_status resource_build_scaling_params_for_context( 1223 const struct dc *dc, 1224 struct dc_state *context) 1225 { 1226 int i; 1227 1228 for (i = 0; i < MAX_PIPES; i++) { 1229 if (context->res_ctx.pipe_ctx[i].plane_state != NULL && 1230 context->res_ctx.pipe_ctx[i].stream != NULL) 1231 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) 1232 return DC_FAIL_SCALING; 1233 } 1234 1235 return DC_OK; 1236 } 1237 1238 struct pipe_ctx *find_idle_secondary_pipe( 1239 struct resource_context *res_ctx, 1240 const struct resource_pool *pool, 1241 const struct pipe_ctx *primary_pipe) 1242 { 1243 int i; 1244 struct pipe_ctx *secondary_pipe = NULL; 1245 1246 /* 1247 * We add a preferred pipe mapping to avoid the chance that 1248 * MPCCs already in use will need to be reassigned to other trees. 1249 * For example, if we went with the strict, assign backwards logic: 1250 * 1251 * (State 1) 1252 * Display A on, no surface, top pipe = 0 1253 * Display B on, no surface, top pipe = 1 1254 * 1255 * (State 2) 1256 * Display A on, no surface, top pipe = 0 1257 * Display B on, surface enable, top pipe = 1, bottom pipe = 5 1258 * 1259 * (State 3) 1260 * Display A on, surface enable, top pipe = 0, bottom pipe = 5 1261 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1262 * 1263 * The state 2->3 transition requires remapping MPCC 5 from display B 1264 * to display A. 1265 * 1266 * However, with the preferred pipe logic, state 2 would look like: 1267 * 1268 * (State 2) 1269 * Display A on, no surface, top pipe = 0 1270 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1271 * 1272 * This would then cause 2->3 to not require remapping any MPCCs. 1273 */ 1274 if (primary_pipe) { 1275 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 1276 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1277 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1278 secondary_pipe->pipe_idx = preferred_pipe_idx; 1279 } 1280 } 1281 1282 /* 1283 * search backwards for the second pipe to keep pipe 1284 * assignment more consistent 1285 */ 1286 if (!secondary_pipe) 1287 for (i = pool->pipe_count - 1; i >= 0; i--) { 1288 if (res_ctx->pipe_ctx[i].stream == NULL) { 1289 secondary_pipe = &res_ctx->pipe_ctx[i]; 1290 secondary_pipe->pipe_idx = i; 1291 break; 1292 } 1293 } 1294 1295 return secondary_pipe; 1296 } 1297 1298 struct pipe_ctx *resource_get_head_pipe_for_stream( 1299 struct resource_context *res_ctx, 1300 struct dc_stream_state *stream) 1301 { 1302 int i; 1303 1304 for (i = 0; i < MAX_PIPES; i++) { 1305 if (res_ctx->pipe_ctx[i].stream == stream 1306 && !res_ctx->pipe_ctx[i].top_pipe 1307 && !res_ctx->pipe_ctx[i].prev_odm_pipe) 1308 return &res_ctx->pipe_ctx[i]; 1309 } 1310 return NULL; 1311 } 1312 1313 static struct pipe_ctx *resource_get_tail_pipe( 1314 struct resource_context *res_ctx, 1315 struct pipe_ctx *head_pipe) 1316 { 1317 struct pipe_ctx *tail_pipe; 1318 1319 tail_pipe = head_pipe->bottom_pipe; 1320 1321 while (tail_pipe) { 1322 head_pipe = tail_pipe; 1323 tail_pipe = tail_pipe->bottom_pipe; 1324 } 1325 1326 return head_pipe; 1327 } 1328 1329 /* 1330 * A free_pipe for a stream is defined here as a pipe 1331 * that has no surface attached yet 1332 */ 1333 static struct pipe_ctx *acquire_free_pipe_for_head( 1334 struct dc_state *context, 1335 const struct resource_pool *pool, 1336 struct pipe_ctx *head_pipe) 1337 { 1338 int i; 1339 struct resource_context *res_ctx = &context->res_ctx; 1340 1341 if (!head_pipe->plane_state) 1342 return head_pipe; 1343 1344 /* Re-use pipe already acquired for this stream if available*/ 1345 for (i = pool->pipe_count - 1; i >= 0; i--) { 1346 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream && 1347 !res_ctx->pipe_ctx[i].plane_state) { 1348 return &res_ctx->pipe_ctx[i]; 1349 } 1350 } 1351 1352 /* 1353 * At this point we have no re-useable pipe for this stream and we need 1354 * to acquire an idle one to satisfy the request 1355 */ 1356 1357 if (!pool->funcs->acquire_idle_pipe_for_layer) 1358 return NULL; 1359 1360 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream); 1361 } 1362 1363 #if defined(CONFIG_DRM_AMD_DC_DCN) 1364 static int acquire_first_split_pipe( 1365 struct resource_context *res_ctx, 1366 const struct resource_pool *pool, 1367 struct dc_stream_state *stream) 1368 { 1369 int i; 1370 1371 for (i = 0; i < pool->pipe_count; i++) { 1372 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; 1373 1374 if (split_pipe->top_pipe && 1375 split_pipe->top_pipe->plane_state == split_pipe->plane_state) { 1376 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; 1377 if (split_pipe->bottom_pipe) 1378 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; 1379 1380 if (split_pipe->top_pipe->plane_state) 1381 resource_build_scaling_params(split_pipe->top_pipe); 1382 1383 memset(split_pipe, 0, sizeof(*split_pipe)); 1384 split_pipe->stream_res.tg = pool->timing_generators[i]; 1385 split_pipe->plane_res.hubp = pool->hubps[i]; 1386 split_pipe->plane_res.ipp = pool->ipps[i]; 1387 split_pipe->plane_res.dpp = pool->dpps[i]; 1388 split_pipe->stream_res.opp = pool->opps[i]; 1389 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; 1390 split_pipe->pipe_idx = i; 1391 1392 split_pipe->stream = stream; 1393 return i; 1394 } 1395 } 1396 return -1; 1397 } 1398 #endif 1399 1400 bool dc_add_plane_to_context( 1401 const struct dc *dc, 1402 struct dc_stream_state *stream, 1403 struct dc_plane_state *plane_state, 1404 struct dc_state *context) 1405 { 1406 int i; 1407 struct resource_pool *pool = dc->res_pool; 1408 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; 1409 struct dc_stream_status *stream_status = NULL; 1410 1411 for (i = 0; i < context->stream_count; i++) 1412 if (context->streams[i] == stream) { 1413 stream_status = &context->stream_status[i]; 1414 break; 1415 } 1416 if (stream_status == NULL) { 1417 dm_error("Existing stream not found; failed to attach surface!\n"); 1418 return false; 1419 } 1420 1421 1422 if (stream_status->plane_count == MAX_SURFACE_NUM) { 1423 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", 1424 plane_state, MAX_SURFACE_NUM); 1425 return false; 1426 } 1427 1428 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1429 1430 if (!head_pipe) { 1431 dm_error("Head pipe not found for stream_state %p !\n", stream); 1432 return false; 1433 } 1434 1435 /* retain new surface, but only once per stream */ 1436 dc_plane_state_retain(plane_state); 1437 1438 while (head_pipe) { 1439 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe); 1440 1441 #if defined(CONFIG_DRM_AMD_DC_DCN) 1442 if (!free_pipe) { 1443 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 1444 if (pipe_idx >= 0) 1445 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; 1446 } 1447 #endif 1448 if (!free_pipe) { 1449 dc_plane_state_release(plane_state); 1450 return false; 1451 } 1452 1453 free_pipe->plane_state = plane_state; 1454 1455 if (head_pipe != free_pipe) { 1456 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe); 1457 ASSERT(tail_pipe); 1458 free_pipe->stream_res.tg = tail_pipe->stream_res.tg; 1459 free_pipe->stream_res.abm = tail_pipe->stream_res.abm; 1460 free_pipe->stream_res.opp = tail_pipe->stream_res.opp; 1461 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; 1462 free_pipe->stream_res.audio = tail_pipe->stream_res.audio; 1463 free_pipe->clock_source = tail_pipe->clock_source; 1464 free_pipe->top_pipe = tail_pipe; 1465 tail_pipe->bottom_pipe = free_pipe; 1466 if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) { 1467 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe; 1468 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe; 1469 } 1470 if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) { 1471 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe; 1472 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe; 1473 } 1474 } 1475 head_pipe = head_pipe->next_odm_pipe; 1476 } 1477 /* assign new surfaces*/ 1478 stream_status->plane_states[stream_status->plane_count] = plane_state; 1479 1480 stream_status->plane_count++; 1481 1482 return true; 1483 } 1484 1485 bool dc_remove_plane_from_context( 1486 const struct dc *dc, 1487 struct dc_stream_state *stream, 1488 struct dc_plane_state *plane_state, 1489 struct dc_state *context) 1490 { 1491 int i; 1492 struct dc_stream_status *stream_status = NULL; 1493 struct resource_pool *pool = dc->res_pool; 1494 1495 for (i = 0; i < context->stream_count; i++) 1496 if (context->streams[i] == stream) { 1497 stream_status = &context->stream_status[i]; 1498 break; 1499 } 1500 1501 if (stream_status == NULL) { 1502 dm_error("Existing stream not found; failed to remove plane.\n"); 1503 return false; 1504 } 1505 1506 /* release pipe for plane*/ 1507 for (i = pool->pipe_count - 1; i >= 0; i--) { 1508 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1509 1510 if (pipe_ctx->plane_state == plane_state) { 1511 if (pipe_ctx->top_pipe) 1512 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1513 1514 /* Second condition is to avoid setting NULL to top pipe 1515 * of tail pipe making it look like head pipe in subsequent 1516 * deletes 1517 */ 1518 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) 1519 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1520 1521 /* 1522 * For head pipe detach surfaces from pipe for tail 1523 * pipe just zero it out 1524 */ 1525 if (!pipe_ctx->top_pipe) 1526 pipe_ctx->plane_state = NULL; 1527 else 1528 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1529 } 1530 } 1531 1532 1533 for (i = 0; i < stream_status->plane_count; i++) { 1534 if (stream_status->plane_states[i] == plane_state) { 1535 1536 dc_plane_state_release(stream_status->plane_states[i]); 1537 break; 1538 } 1539 } 1540 1541 if (i == stream_status->plane_count) { 1542 dm_error("Existing plane_state not found; failed to detach it!\n"); 1543 return false; 1544 } 1545 1546 stream_status->plane_count--; 1547 1548 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */ 1549 for (; i < stream_status->plane_count; i++) 1550 stream_status->plane_states[i] = stream_status->plane_states[i + 1]; 1551 1552 stream_status->plane_states[stream_status->plane_count] = NULL; 1553 1554 return true; 1555 } 1556 1557 bool dc_rem_all_planes_for_stream( 1558 const struct dc *dc, 1559 struct dc_stream_state *stream, 1560 struct dc_state *context) 1561 { 1562 int i, old_plane_count; 1563 struct dc_stream_status *stream_status = NULL; 1564 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; 1565 1566 for (i = 0; i < context->stream_count; i++) 1567 if (context->streams[i] == stream) { 1568 stream_status = &context->stream_status[i]; 1569 break; 1570 } 1571 1572 if (stream_status == NULL) { 1573 dm_error("Existing stream %p not found!\n", stream); 1574 return false; 1575 } 1576 1577 old_plane_count = stream_status->plane_count; 1578 1579 for (i = 0; i < old_plane_count; i++) 1580 del_planes[i] = stream_status->plane_states[i]; 1581 1582 for (i = 0; i < old_plane_count; i++) 1583 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) 1584 return false; 1585 1586 return true; 1587 } 1588 1589 static bool add_all_planes_for_stream( 1590 const struct dc *dc, 1591 struct dc_stream_state *stream, 1592 const struct dc_validation_set set[], 1593 int set_count, 1594 struct dc_state *context) 1595 { 1596 int i, j; 1597 1598 for (i = 0; i < set_count; i++) 1599 if (set[i].stream == stream) 1600 break; 1601 1602 if (i == set_count) { 1603 dm_error("Stream %p not found in set!\n", stream); 1604 return false; 1605 } 1606 1607 for (j = 0; j < set[i].plane_count; j++) 1608 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) 1609 return false; 1610 1611 return true; 1612 } 1613 1614 bool dc_add_all_planes_for_stream( 1615 const struct dc *dc, 1616 struct dc_stream_state *stream, 1617 struct dc_plane_state * const *plane_states, 1618 int plane_count, 1619 struct dc_state *context) 1620 { 1621 struct dc_validation_set set; 1622 int i; 1623 1624 set.stream = stream; 1625 set.plane_count = plane_count; 1626 1627 for (i = 0; i < plane_count; i++) 1628 set.plane_states[i] = plane_states[i]; 1629 1630 return add_all_planes_for_stream(dc, stream, &set, 1, context); 1631 } 1632 1633 bool is_timing_changed(struct dc_stream_state *cur_stream, 1634 struct dc_stream_state *new_stream) 1635 { 1636 if (cur_stream == NULL) 1637 return true; 1638 1639 /* If output color space is changed, need to reprogram info frames */ 1640 if (cur_stream->output_color_space != new_stream->output_color_space) 1641 return true; 1642 1643 return memcmp( 1644 &cur_stream->timing, 1645 &new_stream->timing, 1646 sizeof(struct dc_crtc_timing)) != 0; 1647 } 1648 1649 static bool are_stream_backends_same( 1650 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) 1651 { 1652 if (stream_a == stream_b) 1653 return true; 1654 1655 if (stream_a == NULL || stream_b == NULL) 1656 return false; 1657 1658 if (is_timing_changed(stream_a, stream_b)) 1659 return false; 1660 1661 if (stream_a->signal != stream_b->signal) 1662 return false; 1663 1664 if (stream_a->dpms_off != stream_b->dpms_off) 1665 return false; 1666 1667 return true; 1668 } 1669 1670 /* 1671 * dc_is_stream_unchanged() - Compare two stream states for equivalence. 1672 * 1673 * Checks if there a difference between the two states 1674 * that would require a mode change. 1675 * 1676 * Does not compare cursor position or attributes. 1677 */ 1678 bool dc_is_stream_unchanged( 1679 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1680 { 1681 1682 if (!are_stream_backends_same(old_stream, stream)) 1683 return false; 1684 1685 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param) 1686 return false; 1687 1688 /*compare audio info*/ 1689 if (memcmp(&old_stream->audio_info, &stream->audio_info, sizeof(stream->audio_info)) != 0) 1690 return false; 1691 1692 return true; 1693 } 1694 1695 /* 1696 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams. 1697 */ 1698 bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream, 1699 struct dc_stream_state *stream) 1700 { 1701 if (old_stream == stream) 1702 return true; 1703 1704 if (old_stream == NULL || stream == NULL) 1705 return false; 1706 1707 if (memcmp(&old_stream->src, 1708 &stream->src, 1709 sizeof(struct rect)) != 0) 1710 return false; 1711 1712 if (memcmp(&old_stream->dst, 1713 &stream->dst, 1714 sizeof(struct rect)) != 0) 1715 return false; 1716 1717 return true; 1718 } 1719 1720 static void update_stream_engine_usage( 1721 struct resource_context *res_ctx, 1722 const struct resource_pool *pool, 1723 struct stream_encoder *stream_enc, 1724 bool acquired) 1725 { 1726 int i; 1727 1728 for (i = 0; i < pool->stream_enc_count; i++) { 1729 if (pool->stream_enc[i] == stream_enc) 1730 res_ctx->is_stream_enc_acquired[i] = acquired; 1731 } 1732 } 1733 1734 static void update_hpo_dp_stream_engine_usage( 1735 struct resource_context *res_ctx, 1736 const struct resource_pool *pool, 1737 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, 1738 bool acquired) 1739 { 1740 int i; 1741 1742 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { 1743 if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc) 1744 res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired; 1745 } 1746 } 1747 1748 static inline int find_acquired_hpo_dp_link_enc_for_link( 1749 const struct resource_context *res_ctx, 1750 const struct dc_link *link) 1751 { 1752 int i; 1753 1754 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++) 1755 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 && 1756 res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index) 1757 return i; 1758 1759 return -1; 1760 } 1761 1762 static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx, 1763 const struct resource_pool *pool) 1764 { 1765 int i; 1766 1767 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++) 1768 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0) 1769 break; 1770 1771 return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) && 1772 i < pool->hpo_dp_link_enc_count) ? i : -1; 1773 } 1774 1775 static inline void acquire_hpo_dp_link_enc( 1776 struct resource_context *res_ctx, 1777 unsigned int link_index, 1778 int enc_index) 1779 { 1780 res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index; 1781 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1; 1782 } 1783 1784 static inline void retain_hpo_dp_link_enc( 1785 struct resource_context *res_ctx, 1786 int enc_index) 1787 { 1788 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++; 1789 } 1790 1791 static inline void release_hpo_dp_link_enc( 1792 struct resource_context *res_ctx, 1793 int enc_index) 1794 { 1795 ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0); 1796 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--; 1797 } 1798 1799 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx, 1800 const struct resource_pool *pool, 1801 struct pipe_ctx *pipe_ctx, 1802 struct dc_stream_state *stream) 1803 { 1804 int enc_index; 1805 1806 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link); 1807 1808 if (enc_index >= 0) { 1809 retain_hpo_dp_link_enc(res_ctx, enc_index); 1810 } else { 1811 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool); 1812 if (enc_index >= 0) 1813 acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index); 1814 } 1815 1816 if (enc_index >= 0) 1817 pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index]; 1818 1819 return pipe_ctx->link_res.hpo_dp_link_enc != NULL; 1820 } 1821 1822 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx, 1823 struct pipe_ctx *pipe_ctx, 1824 struct dc_stream_state *stream) 1825 { 1826 int enc_index; 1827 1828 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link); 1829 1830 if (enc_index >= 0) { 1831 release_hpo_dp_link_enc(res_ctx, enc_index); 1832 pipe_ctx->link_res.hpo_dp_link_enc = NULL; 1833 } 1834 } 1835 1836 /* TODO: release audio object */ 1837 void update_audio_usage( 1838 struct resource_context *res_ctx, 1839 const struct resource_pool *pool, 1840 struct audio *audio, 1841 bool acquired) 1842 { 1843 int i; 1844 for (i = 0; i < pool->audio_count; i++) { 1845 if (pool->audios[i] == audio) 1846 res_ctx->is_audio_acquired[i] = acquired; 1847 } 1848 } 1849 1850 static int acquire_first_free_pipe( 1851 struct resource_context *res_ctx, 1852 const struct resource_pool *pool, 1853 struct dc_stream_state *stream) 1854 { 1855 int i; 1856 1857 for (i = 0; i < pool->pipe_count; i++) { 1858 if (!res_ctx->pipe_ctx[i].stream) { 1859 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 1860 1861 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 1862 pipe_ctx->plane_res.mi = pool->mis[i]; 1863 pipe_ctx->plane_res.hubp = pool->hubps[i]; 1864 pipe_ctx->plane_res.ipp = pool->ipps[i]; 1865 pipe_ctx->plane_res.xfm = pool->transforms[i]; 1866 pipe_ctx->plane_res.dpp = pool->dpps[i]; 1867 pipe_ctx->stream_res.opp = pool->opps[i]; 1868 if (pool->dpps[i]) 1869 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; 1870 pipe_ctx->pipe_idx = i; 1871 1872 1873 pipe_ctx->stream = stream; 1874 return i; 1875 } 1876 } 1877 return -1; 1878 } 1879 1880 static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link( 1881 struct resource_context *res_ctx, 1882 const struct resource_pool *pool, 1883 struct dc_stream_state *stream) 1884 { 1885 int i; 1886 1887 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { 1888 if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] && 1889 pool->hpo_dp_stream_enc[i]) { 1890 1891 return pool->hpo_dp_stream_enc[i]; 1892 } 1893 } 1894 1895 return NULL; 1896 } 1897 1898 static struct audio *find_first_free_audio( 1899 struct resource_context *res_ctx, 1900 const struct resource_pool *pool, 1901 enum engine_id id, 1902 enum dce_version dc_version) 1903 { 1904 int i, available_audio_count; 1905 1906 available_audio_count = pool->audio_count; 1907 1908 for (i = 0; i < available_audio_count; i++) { 1909 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { 1910 /*we have enough audio endpoint, find the matching inst*/ 1911 if (id != i) 1912 continue; 1913 return pool->audios[i]; 1914 } 1915 } 1916 1917 /* use engine id to find free audio */ 1918 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) { 1919 return pool->audios[id]; 1920 } 1921 /*not found the matching one, first come first serve*/ 1922 for (i = 0; i < available_audio_count; i++) { 1923 if (res_ctx->is_audio_acquired[i] == false) { 1924 return pool->audios[i]; 1925 } 1926 } 1927 return NULL; 1928 } 1929 1930 /* 1931 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state. 1932 */ 1933 enum dc_status dc_add_stream_to_ctx( 1934 struct dc *dc, 1935 struct dc_state *new_ctx, 1936 struct dc_stream_state *stream) 1937 { 1938 enum dc_status res; 1939 DC_LOGGER_INIT(dc->ctx->logger); 1940 1941 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) { 1942 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream); 1943 return DC_ERROR_UNEXPECTED; 1944 } 1945 1946 new_ctx->streams[new_ctx->stream_count] = stream; 1947 dc_stream_retain(stream); 1948 new_ctx->stream_count++; 1949 1950 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); 1951 if (res != DC_OK) 1952 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res); 1953 1954 return res; 1955 } 1956 1957 /* 1958 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state. 1959 */ 1960 enum dc_status dc_remove_stream_from_ctx( 1961 struct dc *dc, 1962 struct dc_state *new_ctx, 1963 struct dc_stream_state *stream) 1964 { 1965 int i; 1966 struct dc_context *dc_ctx = dc->ctx; 1967 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream); 1968 struct pipe_ctx *odm_pipe; 1969 1970 if (!del_pipe) { 1971 DC_ERROR("Pipe not found for stream %p !\n", stream); 1972 return DC_ERROR_UNEXPECTED; 1973 } 1974 1975 odm_pipe = del_pipe->next_odm_pipe; 1976 1977 /* Release primary pipe */ 1978 ASSERT(del_pipe->stream_res.stream_enc); 1979 update_stream_engine_usage( 1980 &new_ctx->res_ctx, 1981 dc->res_pool, 1982 del_pipe->stream_res.stream_enc, 1983 false); 1984 if (is_dp_128b_132b_signal(del_pipe)) { 1985 update_hpo_dp_stream_engine_usage( 1986 &new_ctx->res_ctx, dc->res_pool, 1987 del_pipe->stream_res.hpo_dp_stream_enc, 1988 false); 1989 remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream); 1990 } 1991 1992 if (del_pipe->stream_res.audio) 1993 update_audio_usage( 1994 &new_ctx->res_ctx, 1995 dc->res_pool, 1996 del_pipe->stream_res.audio, 1997 false); 1998 1999 resource_unreference_clock_source(&new_ctx->res_ctx, 2000 dc->res_pool, 2001 del_pipe->clock_source); 2002 2003 if (dc->res_pool->funcs->remove_stream_from_ctx) 2004 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream); 2005 2006 while (odm_pipe) { 2007 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 2008 2009 memset(odm_pipe, 0, sizeof(*odm_pipe)); 2010 odm_pipe = next_odm_pipe; 2011 } 2012 memset(del_pipe, 0, sizeof(*del_pipe)); 2013 2014 for (i = 0; i < new_ctx->stream_count; i++) 2015 if (new_ctx->streams[i] == stream) 2016 break; 2017 2018 if (new_ctx->streams[i] != stream) { 2019 DC_ERROR("Context doesn't have stream %p !\n", stream); 2020 return DC_ERROR_UNEXPECTED; 2021 } 2022 2023 dc_stream_release(new_ctx->streams[i]); 2024 new_ctx->stream_count--; 2025 2026 /* Trim back arrays */ 2027 for (; i < new_ctx->stream_count; i++) { 2028 new_ctx->streams[i] = new_ctx->streams[i + 1]; 2029 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; 2030 } 2031 2032 new_ctx->streams[new_ctx->stream_count] = NULL; 2033 memset( 2034 &new_ctx->stream_status[new_ctx->stream_count], 2035 0, 2036 sizeof(new_ctx->stream_status[0])); 2037 2038 return DC_OK; 2039 } 2040 2041 static struct dc_stream_state *find_pll_sharable_stream( 2042 struct dc_stream_state *stream_needs_pll, 2043 struct dc_state *context) 2044 { 2045 int i; 2046 2047 for (i = 0; i < context->stream_count; i++) { 2048 struct dc_stream_state *stream_has_pll = context->streams[i]; 2049 2050 /* We are looking for non dp, non virtual stream */ 2051 if (resource_are_streams_timing_synchronizable( 2052 stream_needs_pll, stream_has_pll) 2053 && !dc_is_dp_signal(stream_has_pll->signal) 2054 && stream_has_pll->link->connector_signal 2055 != SIGNAL_TYPE_VIRTUAL) 2056 return stream_has_pll; 2057 2058 } 2059 2060 return NULL; 2061 } 2062 2063 static int get_norm_pix_clk(const struct dc_crtc_timing *timing) 2064 { 2065 uint32_t pix_clk = timing->pix_clk_100hz; 2066 uint32_t normalized_pix_clk = pix_clk; 2067 2068 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 2069 pix_clk /= 2; 2070 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 2071 switch (timing->display_color_depth) { 2072 case COLOR_DEPTH_666: 2073 case COLOR_DEPTH_888: 2074 normalized_pix_clk = pix_clk; 2075 break; 2076 case COLOR_DEPTH_101010: 2077 normalized_pix_clk = (pix_clk * 30) / 24; 2078 break; 2079 case COLOR_DEPTH_121212: 2080 normalized_pix_clk = (pix_clk * 36) / 24; 2081 break; 2082 case COLOR_DEPTH_161616: 2083 normalized_pix_clk = (pix_clk * 48) / 24; 2084 break; 2085 default: 2086 ASSERT(0); 2087 break; 2088 } 2089 } 2090 return normalized_pix_clk; 2091 } 2092 2093 static void calculate_phy_pix_clks(struct dc_stream_state *stream) 2094 { 2095 /* update actual pixel clock on all streams */ 2096 if (dc_is_hdmi_signal(stream->signal)) 2097 stream->phy_pix_clk = get_norm_pix_clk( 2098 &stream->timing) / 10; 2099 else 2100 stream->phy_pix_clk = 2101 stream->timing.pix_clk_100hz / 10; 2102 2103 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 2104 stream->phy_pix_clk *= 2; 2105 } 2106 2107 static int acquire_resource_from_hw_enabled_state( 2108 struct resource_context *res_ctx, 2109 const struct resource_pool *pool, 2110 struct dc_stream_state *stream) 2111 { 2112 struct dc_link *link = stream->link; 2113 unsigned int i, inst, tg_inst = 0; 2114 2115 /* Check for enabled DIG to identify enabled display */ 2116 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) 2117 return -1; 2118 2119 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); 2120 2121 if (inst == ENGINE_ID_UNKNOWN) 2122 return -1; 2123 2124 for (i = 0; i < pool->stream_enc_count; i++) { 2125 if (pool->stream_enc[i]->id == inst) { 2126 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( 2127 pool->stream_enc[i]); 2128 break; 2129 } 2130 } 2131 2132 // tg_inst not found 2133 if (i == pool->stream_enc_count) 2134 return -1; 2135 2136 if (tg_inst >= pool->timing_generator_count) 2137 return -1; 2138 2139 if (!res_ctx->pipe_ctx[tg_inst].stream) { 2140 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; 2141 2142 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 2143 pipe_ctx->plane_res.mi = pool->mis[tg_inst]; 2144 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; 2145 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; 2146 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; 2147 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst]; 2148 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; 2149 2150 if (pool->dpps[tg_inst]) { 2151 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; 2152 2153 // Read DPP->MPCC->OPP Pipe from HW State 2154 if (pool->mpc->funcs->read_mpcc_state) { 2155 struct mpcc_state s = {0}; 2156 2157 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); 2158 2159 if (s.dpp_id < MAX_MPCC) 2160 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id; 2161 2162 if (s.bot_mpcc_id < MAX_MPCC) 2163 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = 2164 &pool->mpc->mpcc_array[s.bot_mpcc_id]; 2165 2166 if (s.opp_id < MAX_OPP) 2167 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; 2168 } 2169 } 2170 pipe_ctx->pipe_idx = tg_inst; 2171 2172 pipe_ctx->stream = stream; 2173 return tg_inst; 2174 } 2175 2176 return -1; 2177 } 2178 2179 static void mark_seamless_boot_stream( 2180 const struct dc *dc, 2181 struct dc_stream_state *stream) 2182 { 2183 struct dc_bios *dcb = dc->ctx->dc_bios; 2184 2185 if (dc->config.allow_seamless_boot_optimization && 2186 !dcb->funcs->is_accelerated_mode(dcb)) { 2187 if (dc_validate_boot_timing(dc, stream->sink, &stream->timing)) 2188 stream->apply_seamless_boot_optimization = true; 2189 } 2190 } 2191 2192 enum dc_status resource_map_pool_resources( 2193 const struct dc *dc, 2194 struct dc_state *context, 2195 struct dc_stream_state *stream) 2196 { 2197 const struct resource_pool *pool = dc->res_pool; 2198 int i; 2199 struct dc_context *dc_ctx = dc->ctx; 2200 struct pipe_ctx *pipe_ctx = NULL; 2201 int pipe_idx = -1; 2202 2203 calculate_phy_pix_clks(stream); 2204 2205 mark_seamless_boot_stream(dc, stream); 2206 2207 if (stream->apply_seamless_boot_optimization) { 2208 pipe_idx = acquire_resource_from_hw_enabled_state( 2209 &context->res_ctx, 2210 pool, 2211 stream); 2212 if (pipe_idx < 0) 2213 /* hw resource was assigned to other stream */ 2214 stream->apply_seamless_boot_optimization = false; 2215 } 2216 2217 if (pipe_idx < 0) 2218 /* acquire new resources */ 2219 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); 2220 2221 #ifdef CONFIG_DRM_AMD_DC_DCN 2222 if (pipe_idx < 0) 2223 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 2224 #endif 2225 2226 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL) 2227 return DC_NO_CONTROLLER_RESOURCE; 2228 2229 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2230 2231 pipe_ctx->stream_res.stream_enc = 2232 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link( 2233 &context->res_ctx, pool, stream); 2234 2235 if (!pipe_ctx->stream_res.stream_enc) 2236 return DC_NO_STREAM_ENC_RESOURCE; 2237 2238 update_stream_engine_usage( 2239 &context->res_ctx, pool, 2240 pipe_ctx->stream_res.stream_enc, 2241 true); 2242 2243 /* Allocate DP HPO Stream Encoder based on signal, hw capabilities 2244 * and link settings 2245 */ 2246 if (dc_is_dp_signal(stream->signal) && 2247 dc->caps.dp_hpo) { 2248 struct dc_link_settings link_settings = {0}; 2249 2250 decide_link_settings(stream, &link_settings); 2251 if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) { 2252 pipe_ctx->stream_res.hpo_dp_stream_enc = 2253 find_first_free_match_hpo_dp_stream_enc_for_link( 2254 &context->res_ctx, pool, stream); 2255 2256 if (!pipe_ctx->stream_res.hpo_dp_stream_enc) 2257 return DC_NO_STREAM_ENC_RESOURCE; 2258 2259 update_hpo_dp_stream_engine_usage( 2260 &context->res_ctx, pool, 2261 pipe_ctx->stream_res.hpo_dp_stream_enc, 2262 true); 2263 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream)) 2264 return DC_NO_LINK_ENC_RESOURCE; 2265 } 2266 } 2267 2268 /* TODO: Add check if ASIC support and EDID audio */ 2269 if (!stream->converter_disable_audio && 2270 dc_is_audio_capable_signal(pipe_ctx->stream->signal) && 2271 stream->audio_info.mode_count && stream->audio_info.flags.all) { 2272 pipe_ctx->stream_res.audio = find_first_free_audio( 2273 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version); 2274 2275 /* 2276 * Audio assigned in order first come first get. 2277 * There are asics which has number of audio 2278 * resources less then number of pipes 2279 */ 2280 if (pipe_ctx->stream_res.audio) 2281 update_audio_usage(&context->res_ctx, pool, 2282 pipe_ctx->stream_res.audio, true); 2283 } 2284 2285 /* Add ABM to the resource if on EDP */ 2286 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) { 2287 #if defined(CONFIG_DRM_AMD_DC_DCN) 2288 if (pool->abm) 2289 pipe_ctx->stream_res.abm = pool->abm; 2290 else 2291 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst]; 2292 #else 2293 pipe_ctx->stream_res.abm = pool->abm; 2294 #endif 2295 } 2296 2297 for (i = 0; i < context->stream_count; i++) 2298 if (context->streams[i] == stream) { 2299 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; 2300 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst; 2301 context->stream_status[i].audio_inst = 2302 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; 2303 2304 return DC_OK; 2305 } 2306 2307 DC_ERROR("Stream %p not found in new ctx!\n", stream); 2308 return DC_ERROR_UNEXPECTED; 2309 } 2310 2311 /** 2312 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state 2313 * Is a shallow copy. Increments refcounts on existing streams and planes. 2314 * @dc: copy out of dc->current_state 2315 * @dst_ctx: copy into this 2316 */ 2317 void dc_resource_state_copy_construct_current( 2318 const struct dc *dc, 2319 struct dc_state *dst_ctx) 2320 { 2321 dc_resource_state_copy_construct(dc->current_state, dst_ctx); 2322 } 2323 2324 2325 void dc_resource_state_construct( 2326 const struct dc *dc, 2327 struct dc_state *dst_ctx) 2328 { 2329 dst_ctx->clk_mgr = dc->clk_mgr; 2330 2331 /* Initialise DIG link encoder resource tracking variables. */ 2332 link_enc_cfg_init(dc, dst_ctx); 2333 } 2334 2335 2336 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) 2337 { 2338 if (dc->res_pool == NULL) 2339 return false; 2340 2341 return dc->res_pool->res_cap->num_dsc > 0; 2342 } 2343 2344 2345 /** 2346 * dc_validate_global_state() - Determine if HW can support a given state 2347 * Checks HW resource availability and bandwidth requirement. 2348 * @dc: dc struct for this driver 2349 * @new_ctx: state to be validated 2350 * @fast_validate: set to true if only yes/no to support matters 2351 * 2352 * Return: DC_OK if the result can be programmed. Otherwise, an error code. 2353 */ 2354 enum dc_status dc_validate_global_state( 2355 struct dc *dc, 2356 struct dc_state *new_ctx, 2357 bool fast_validate) 2358 { 2359 enum dc_status result = DC_ERROR_UNEXPECTED; 2360 int i, j; 2361 2362 if (!new_ctx) 2363 return DC_ERROR_UNEXPECTED; 2364 2365 if (dc->res_pool->funcs->validate_global) { 2366 result = dc->res_pool->funcs->validate_global(dc, new_ctx); 2367 if (result != DC_OK) 2368 return result; 2369 } 2370 2371 for (i = 0; i < new_ctx->stream_count; i++) { 2372 struct dc_stream_state *stream = new_ctx->streams[i]; 2373 2374 for (j = 0; j < dc->res_pool->pipe_count; j++) { 2375 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; 2376 2377 if (pipe_ctx->stream != stream) 2378 continue; 2379 2380 if (dc->res_pool->funcs->patch_unknown_plane_state && 2381 pipe_ctx->plane_state && 2382 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { 2383 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); 2384 if (result != DC_OK) 2385 return result; 2386 } 2387 2388 /* Switch to dp clock source only if there is 2389 * no non dp stream that shares the same timing 2390 * with the dp stream. 2391 */ 2392 if (dc_is_dp_signal(pipe_ctx->stream->signal) && 2393 !find_pll_sharable_stream(stream, new_ctx)) { 2394 2395 resource_unreference_clock_source( 2396 &new_ctx->res_ctx, 2397 dc->res_pool, 2398 pipe_ctx->clock_source); 2399 2400 pipe_ctx->clock_source = dc->res_pool->dp_clock_source; 2401 resource_reference_clock_source( 2402 &new_ctx->res_ctx, 2403 dc->res_pool, 2404 pipe_ctx->clock_source); 2405 } 2406 } 2407 } 2408 2409 result = resource_build_scaling_params_for_context(dc, new_ctx); 2410 2411 if (result == DC_OK) 2412 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate)) 2413 result = DC_FAIL_BANDWIDTH_VALIDATE; 2414 2415 #if defined(CONFIG_DRM_AMD_DC_DCN) 2416 /* 2417 * Only update link encoder to stream assignment after bandwidth validation passed. 2418 * TODO: Split out assignment and validation. 2419 */ 2420 if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false) 2421 dc->res_pool->funcs->link_encs_assign( 2422 dc, new_ctx, new_ctx->streams, new_ctx->stream_count); 2423 #endif 2424 2425 return result; 2426 } 2427 2428 static void patch_gamut_packet_checksum( 2429 struct dc_info_packet *gamut_packet) 2430 { 2431 /* For gamut we recalc checksum */ 2432 if (gamut_packet->valid) { 2433 uint8_t chk_sum = 0; 2434 uint8_t *ptr; 2435 uint8_t i; 2436 2437 /*start of the Gamut data. */ 2438 ptr = &gamut_packet->sb[3]; 2439 2440 for (i = 0; i <= gamut_packet->sb[1]; i++) 2441 chk_sum += ptr[i]; 2442 2443 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); 2444 } 2445 } 2446 2447 static void set_avi_info_frame( 2448 struct dc_info_packet *info_packet, 2449 struct pipe_ctx *pipe_ctx) 2450 { 2451 struct dc_stream_state *stream = pipe_ctx->stream; 2452 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; 2453 uint32_t pixel_encoding = 0; 2454 enum scanning_type scan_type = SCANNING_TYPE_NODATA; 2455 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA; 2456 bool itc = false; 2457 uint8_t itc_value = 0; 2458 uint8_t cn0_cn1 = 0; 2459 unsigned int cn0_cn1_value = 0; 2460 uint8_t *check_sum = NULL; 2461 uint8_t byte_index = 0; 2462 union hdmi_info_packet hdmi_info; 2463 union display_content_support support = {0}; 2464 unsigned int vic = pipe_ctx->stream->timing.vic; 2465 enum dc_timing_3d_format format; 2466 2467 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet)); 2468 2469 color_space = pipe_ctx->stream->output_color_space; 2470 if (color_space == COLOR_SPACE_UNKNOWN) 2471 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? 2472 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; 2473 2474 /* Initialize header */ 2475 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI; 2476 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall 2477 * not be used in HDMI 2.0 (Section 10.1) */ 2478 hdmi_info.bits.header.version = 2; 2479 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE; 2480 2481 /* 2482 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built 2483 * according to HDMI 2.0 spec (Section 10.1) 2484 */ 2485 2486 switch (stream->timing.pixel_encoding) { 2487 case PIXEL_ENCODING_YCBCR422: 2488 pixel_encoding = 1; 2489 break; 2490 2491 case PIXEL_ENCODING_YCBCR444: 2492 pixel_encoding = 2; 2493 break; 2494 case PIXEL_ENCODING_YCBCR420: 2495 pixel_encoding = 3; 2496 break; 2497 2498 case PIXEL_ENCODING_RGB: 2499 default: 2500 pixel_encoding = 0; 2501 } 2502 2503 /* Y0_Y1_Y2 : The pixel encoding */ 2504 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ 2505 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding; 2506 2507 /* A0 = 1 Active Format Information valid */ 2508 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID; 2509 2510 /* B0, B1 = 3; Bar info data is valid */ 2511 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID; 2512 2513 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM; 2514 2515 /* S0, S1 : Underscan / Overscan */ 2516 /* TODO: un-hardcode scan type */ 2517 scan_type = SCANNING_TYPE_UNDERSCAN; 2518 hdmi_info.bits.S0_S1 = scan_type; 2519 2520 /* C0, C1 : Colorimetry */ 2521 if (color_space == COLOR_SPACE_YCBCR709 || 2522 color_space == COLOR_SPACE_YCBCR709_LIMITED) 2523 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709; 2524 else if (color_space == COLOR_SPACE_YCBCR601 || 2525 color_space == COLOR_SPACE_YCBCR601_LIMITED) 2526 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601; 2527 else { 2528 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA; 2529 } 2530 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE || 2531 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE || 2532 color_space == COLOR_SPACE_2020_YCBCR) { 2533 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR; 2534 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 2535 } else if (color_space == COLOR_SPACE_ADOBERGB) { 2536 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB; 2537 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 2538 } 2539 2540 /* TODO: un-hardcode aspect ratio */ 2541 aspect = stream->timing.aspect_ratio; 2542 2543 switch (aspect) { 2544 case ASPECT_RATIO_4_3: 2545 case ASPECT_RATIO_16_9: 2546 hdmi_info.bits.M0_M1 = aspect; 2547 break; 2548 2549 case ASPECT_RATIO_NO_DATA: 2550 case ASPECT_RATIO_64_27: 2551 case ASPECT_RATIO_256_135: 2552 default: 2553 hdmi_info.bits.M0_M1 = 0; 2554 } 2555 2556 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */ 2557 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE; 2558 2559 /* TODO: un-hardcode cn0_cn1 and itc */ 2560 2561 cn0_cn1 = 0; 2562 cn0_cn1_value = 0; 2563 2564 itc = true; 2565 itc_value = 1; 2566 2567 support = stream->content_support; 2568 2569 if (itc) { 2570 if (!support.bits.valid_content_type) { 2571 cn0_cn1_value = 0; 2572 } else { 2573 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) { 2574 if (support.bits.graphics_content == 1) { 2575 cn0_cn1_value = 0; 2576 } 2577 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) { 2578 if (support.bits.photo_content == 1) { 2579 cn0_cn1_value = 1; 2580 } else { 2581 cn0_cn1_value = 0; 2582 itc_value = 0; 2583 } 2584 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) { 2585 if (support.bits.cinema_content == 1) { 2586 cn0_cn1_value = 2; 2587 } else { 2588 cn0_cn1_value = 0; 2589 itc_value = 0; 2590 } 2591 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) { 2592 if (support.bits.game_content == 1) { 2593 cn0_cn1_value = 3; 2594 } else { 2595 cn0_cn1_value = 0; 2596 itc_value = 0; 2597 } 2598 } 2599 } 2600 hdmi_info.bits.CN0_CN1 = cn0_cn1_value; 2601 hdmi_info.bits.ITC = itc_value; 2602 } 2603 2604 if (stream->qs_bit == 1) { 2605 if (color_space == COLOR_SPACE_SRGB || 2606 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) 2607 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; 2608 else if (color_space == COLOR_SPACE_SRGB_LIMITED || 2609 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) 2610 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE; 2611 else 2612 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2613 } else 2614 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2615 2616 /* TODO : We should handle YCC quantization */ 2617 /* but we do not have matrix calculation */ 2618 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2619 2620 ///VIC 2621 if (pipe_ctx->stream->timing.hdmi_vic != 0) 2622 vic = 0; 2623 format = stream->timing.timing_3d_format; 2624 /*todo, add 3DStereo support*/ 2625 if (format != TIMING_3D_FORMAT_NONE) { 2626 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled 2627 switch (pipe_ctx->stream->timing.hdmi_vic) { 2628 case 1: 2629 vic = 95; 2630 break; 2631 case 2: 2632 vic = 94; 2633 break; 2634 case 3: 2635 vic = 93; 2636 break; 2637 case 4: 2638 vic = 98; 2639 break; 2640 default: 2641 break; 2642 } 2643 } 2644 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/ 2645 hdmi_info.bits.VIC0_VIC7 = vic; 2646 if (vic >= 128) 2647 hdmi_info.bits.header.version = 3; 2648 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1), 2649 * the Source shall use 20 AVI InfoFrame Version 4 2650 */ 2651 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED && 2652 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) { 2653 hdmi_info.bits.header.version = 4; 2654 hdmi_info.bits.header.length = 14; 2655 } 2656 2657 /* pixel repetition 2658 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel 2659 * repetition start from 1 */ 2660 hdmi_info.bits.PR0_PR3 = 0; 2661 2662 /* Bar Info 2663 * barTop: Line Number of End of Top Bar. 2664 * barBottom: Line Number of Start of Bottom Bar. 2665 * barLeft: Pixel Number of End of Left Bar. 2666 * barRight: Pixel Number of Start of Right Bar. */ 2667 hdmi_info.bits.bar_top = stream->timing.v_border_top; 2668 hdmi_info.bits.bar_bottom = (stream->timing.v_total 2669 - stream->timing.v_border_bottom + 1); 2670 hdmi_info.bits.bar_left = stream->timing.h_border_left; 2671 hdmi_info.bits.bar_right = (stream->timing.h_total 2672 - stream->timing.h_border_right + 1); 2673 2674 /* Additional Colorimetry Extension 2675 * Used in conduction with C0-C1 and EC0-EC2 2676 * 0 = DCI-P3 RGB (D65) 2677 * 1 = DCI-P3 RGB (theater) 2678 */ 2679 hdmi_info.bits.ACE0_ACE3 = 0; 2680 2681 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ 2682 check_sum = &hdmi_info.packet_raw_data.sb[0]; 2683 2684 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version; 2685 2686 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++) 2687 *check_sum += hdmi_info.packet_raw_data.sb[byte_index]; 2688 2689 /* one byte complement */ 2690 *check_sum = (uint8_t) (0x100 - *check_sum); 2691 2692 /* Store in hw_path_mode */ 2693 info_packet->hb0 = hdmi_info.packet_raw_data.hb0; 2694 info_packet->hb1 = hdmi_info.packet_raw_data.hb1; 2695 info_packet->hb2 = hdmi_info.packet_raw_data.hb2; 2696 2697 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++) 2698 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index]; 2699 2700 info_packet->valid = true; 2701 } 2702 2703 static void set_vendor_info_packet( 2704 struct dc_info_packet *info_packet, 2705 struct dc_stream_state *stream) 2706 { 2707 /* SPD info packet for FreeSync */ 2708 2709 /* Check if Freesync is supported. Return if false. If true, 2710 * set the corresponding bit in the info packet 2711 */ 2712 if (!stream->vsp_infopacket.valid) 2713 return; 2714 2715 *info_packet = stream->vsp_infopacket; 2716 } 2717 2718 static void set_spd_info_packet( 2719 struct dc_info_packet *info_packet, 2720 struct dc_stream_state *stream) 2721 { 2722 /* SPD info packet for FreeSync */ 2723 2724 /* Check if Freesync is supported. Return if false. If true, 2725 * set the corresponding bit in the info packet 2726 */ 2727 if (!stream->vrr_infopacket.valid) 2728 return; 2729 2730 *info_packet = stream->vrr_infopacket; 2731 } 2732 2733 static void set_hdr_static_info_packet( 2734 struct dc_info_packet *info_packet, 2735 struct dc_stream_state *stream) 2736 { 2737 /* HDR Static Metadata info packet for HDR10 */ 2738 2739 if (!stream->hdr_static_metadata.valid || 2740 stream->use_dynamic_meta) 2741 return; 2742 2743 *info_packet = stream->hdr_static_metadata; 2744 } 2745 2746 static void set_vsc_info_packet( 2747 struct dc_info_packet *info_packet, 2748 struct dc_stream_state *stream) 2749 { 2750 if (!stream->vsc_infopacket.valid) 2751 return; 2752 2753 *info_packet = stream->vsc_infopacket; 2754 } 2755 2756 void dc_resource_state_destruct(struct dc_state *context) 2757 { 2758 int i, j; 2759 2760 for (i = 0; i < context->stream_count; i++) { 2761 for (j = 0; j < context->stream_status[i].plane_count; j++) 2762 dc_plane_state_release( 2763 context->stream_status[i].plane_states[j]); 2764 2765 context->stream_status[i].plane_count = 0; 2766 dc_stream_release(context->streams[i]); 2767 context->streams[i] = NULL; 2768 } 2769 context->stream_count = 0; 2770 } 2771 2772 void dc_resource_state_copy_construct( 2773 const struct dc_state *src_ctx, 2774 struct dc_state *dst_ctx) 2775 { 2776 int i, j; 2777 struct kref refcount = dst_ctx->refcount; 2778 2779 *dst_ctx = *src_ctx; 2780 2781 for (i = 0; i < MAX_PIPES; i++) { 2782 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; 2783 2784 if (cur_pipe->top_pipe) 2785 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; 2786 2787 if (cur_pipe->bottom_pipe) 2788 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; 2789 2790 if (cur_pipe->next_odm_pipe) 2791 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; 2792 2793 if (cur_pipe->prev_odm_pipe) 2794 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; 2795 } 2796 2797 for (i = 0; i < dst_ctx->stream_count; i++) { 2798 dc_stream_retain(dst_ctx->streams[i]); 2799 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) 2800 dc_plane_state_retain( 2801 dst_ctx->stream_status[i].plane_states[j]); 2802 } 2803 2804 /* context refcount should not be overridden */ 2805 dst_ctx->refcount = refcount; 2806 2807 } 2808 2809 struct clock_source *dc_resource_find_first_free_pll( 2810 struct resource_context *res_ctx, 2811 const struct resource_pool *pool) 2812 { 2813 int i; 2814 2815 for (i = 0; i < pool->clk_src_count; ++i) { 2816 if (res_ctx->clock_source_ref_count[i] == 0) 2817 return pool->clock_sources[i]; 2818 } 2819 2820 return NULL; 2821 } 2822 2823 void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 2824 { 2825 enum signal_type signal = SIGNAL_TYPE_NONE; 2826 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; 2827 2828 /* default all packets to invalid */ 2829 info->avi.valid = false; 2830 info->gamut.valid = false; 2831 info->vendor.valid = false; 2832 info->spd.valid = false; 2833 info->hdrsmd.valid = false; 2834 info->vsc.valid = false; 2835 2836 signal = pipe_ctx->stream->signal; 2837 2838 /* HDMi and DP have different info packets*/ 2839 if (dc_is_hdmi_signal(signal)) { 2840 set_avi_info_frame(&info->avi, pipe_ctx); 2841 2842 set_vendor_info_packet(&info->vendor, pipe_ctx->stream); 2843 2844 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2845 2846 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 2847 2848 } else if (dc_is_dp_signal(signal)) { 2849 set_vsc_info_packet(&info->vsc, pipe_ctx->stream); 2850 2851 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2852 2853 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 2854 } 2855 2856 patch_gamut_packet_checksum(&info->gamut); 2857 } 2858 2859 enum dc_status resource_map_clock_resources( 2860 const struct dc *dc, 2861 struct dc_state *context, 2862 struct dc_stream_state *stream) 2863 { 2864 /* acquire new resources */ 2865 const struct resource_pool *pool = dc->res_pool; 2866 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 2867 &context->res_ctx, stream); 2868 2869 if (!pipe_ctx) 2870 return DC_ERROR_UNEXPECTED; 2871 2872 if (dc_is_dp_signal(pipe_ctx->stream->signal) 2873 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 2874 pipe_ctx->clock_source = pool->dp_clock_source; 2875 else { 2876 pipe_ctx->clock_source = NULL; 2877 2878 if (!dc->config.disable_disp_pll_sharing) 2879 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing( 2880 &context->res_ctx, 2881 pipe_ctx); 2882 2883 if (pipe_ctx->clock_source == NULL) 2884 pipe_ctx->clock_source = 2885 dc_resource_find_first_free_pll( 2886 &context->res_ctx, 2887 pool); 2888 } 2889 2890 if (pipe_ctx->clock_source == NULL) 2891 return DC_NO_CLOCK_SOURCE_RESOURCE; 2892 2893 resource_reference_clock_source( 2894 &context->res_ctx, pool, 2895 pipe_ctx->clock_source); 2896 2897 return DC_OK; 2898 } 2899 2900 /* 2901 * Note: We need to disable output if clock sources change, 2902 * since bios does optimization and doesn't apply if changing 2903 * PHY when not already disabled. 2904 */ 2905 bool pipe_need_reprogram( 2906 struct pipe_ctx *pipe_ctx_old, 2907 struct pipe_ctx *pipe_ctx) 2908 { 2909 if (!pipe_ctx_old->stream) 2910 return false; 2911 2912 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) 2913 return true; 2914 2915 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) 2916 return true; 2917 2918 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) 2919 return true; 2920 2921 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source 2922 && pipe_ctx_old->stream != pipe_ctx->stream) 2923 return true; 2924 2925 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) 2926 return true; 2927 2928 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) 2929 return true; 2930 2931 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off) 2932 return true; 2933 2934 if (false == pipe_ctx_old->stream->link->link_state_valid && 2935 false == pipe_ctx_old->stream->dpms_off) 2936 return true; 2937 2938 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) 2939 return true; 2940 2941 if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) 2942 return true; 2943 if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc) 2944 return true; 2945 2946 /* DIG link encoder resource assignment for stream changed. */ 2947 if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) { 2948 bool need_reprogram = false; 2949 struct dc *dc = pipe_ctx_old->stream->ctx->dc; 2950 enum link_enc_cfg_mode mode = dc->current_state->res_ctx.link_enc_cfg_ctx.mode; 2951 2952 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY; 2953 if (link_enc_cfg_get_link_enc_used_by_stream(dc, pipe_ctx_old->stream) != pipe_ctx->stream->link_enc) 2954 need_reprogram = true; 2955 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = mode; 2956 2957 return need_reprogram; 2958 } 2959 2960 return false; 2961 } 2962 2963 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 2964 struct bit_depth_reduction_params *fmt_bit_depth) 2965 { 2966 enum dc_dither_option option = stream->dither_option; 2967 enum dc_pixel_encoding pixel_encoding = 2968 stream->timing.pixel_encoding; 2969 2970 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); 2971 2972 if (option == DITHER_OPTION_DEFAULT) { 2973 switch (stream->timing.display_color_depth) { 2974 case COLOR_DEPTH_666: 2975 option = DITHER_OPTION_SPATIAL6; 2976 break; 2977 case COLOR_DEPTH_888: 2978 option = DITHER_OPTION_SPATIAL8; 2979 break; 2980 case COLOR_DEPTH_101010: 2981 option = DITHER_OPTION_SPATIAL10; 2982 break; 2983 default: 2984 option = DITHER_OPTION_DISABLE; 2985 } 2986 } 2987 2988 if (option == DITHER_OPTION_DISABLE) 2989 return; 2990 2991 if (option == DITHER_OPTION_TRUN6) { 2992 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2993 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; 2994 } else if (option == DITHER_OPTION_TRUN8 || 2995 option == DITHER_OPTION_TRUN8_SPATIAL6 || 2996 option == DITHER_OPTION_TRUN8_FM6) { 2997 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2998 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; 2999 } else if (option == DITHER_OPTION_TRUN10 || 3000 option == DITHER_OPTION_TRUN10_SPATIAL6 || 3001 option == DITHER_OPTION_TRUN10_SPATIAL8 || 3002 option == DITHER_OPTION_TRUN10_FM8 || 3003 option == DITHER_OPTION_TRUN10_FM6 || 3004 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 3005 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 3006 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 3007 } 3008 3009 /* special case - Formatter can only reduce by 4 bits at most. 3010 * When reducing from 12 to 6 bits, 3011 * HW recommends we use trunc with round mode 3012 * (if we did nothing, trunc to 10 bits would be used) 3013 * note that any 12->10 bit reduction is ignored prior to DCE8, 3014 * as the input was 10 bits. 3015 */ 3016 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 3017 option == DITHER_OPTION_SPATIAL6 || 3018 option == DITHER_OPTION_FM6) { 3019 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 3020 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 3021 fmt_bit_depth->flags.TRUNCATE_MODE = 1; 3022 } 3023 3024 /* spatial dither 3025 * note that spatial modes 1-3 are never used 3026 */ 3027 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 3028 option == DITHER_OPTION_SPATIAL6 || 3029 option == DITHER_OPTION_TRUN10_SPATIAL6 || 3030 option == DITHER_OPTION_TRUN8_SPATIAL6) { 3031 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 3032 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; 3033 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 3034 fmt_bit_depth->flags.RGB_RANDOM = 3035 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 3036 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || 3037 option == DITHER_OPTION_SPATIAL8 || 3038 option == DITHER_OPTION_SPATIAL8_FM6 || 3039 option == DITHER_OPTION_TRUN10_SPATIAL8 || 3040 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 3041 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 3042 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; 3043 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 3044 fmt_bit_depth->flags.RGB_RANDOM = 3045 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 3046 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || 3047 option == DITHER_OPTION_SPATIAL10 || 3048 option == DITHER_OPTION_SPATIAL10_FM8 || 3049 option == DITHER_OPTION_SPATIAL10_FM6) { 3050 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 3051 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; 3052 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 3053 fmt_bit_depth->flags.RGB_RANDOM = 3054 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 3055 } 3056 3057 if (option == DITHER_OPTION_SPATIAL6 || 3058 option == DITHER_OPTION_SPATIAL8 || 3059 option == DITHER_OPTION_SPATIAL10) { 3060 fmt_bit_depth->flags.FRAME_RANDOM = 0; 3061 } else { 3062 fmt_bit_depth->flags.FRAME_RANDOM = 1; 3063 } 3064 3065 ////////////////////// 3066 //// temporal dither 3067 ////////////////////// 3068 if (option == DITHER_OPTION_FM6 || 3069 option == DITHER_OPTION_SPATIAL8_FM6 || 3070 option == DITHER_OPTION_SPATIAL10_FM6 || 3071 option == DITHER_OPTION_TRUN10_FM6 || 3072 option == DITHER_OPTION_TRUN8_FM6 || 3073 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 3074 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 3075 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; 3076 } else if (option == DITHER_OPTION_FM8 || 3077 option == DITHER_OPTION_SPATIAL10_FM8 || 3078 option == DITHER_OPTION_TRUN10_FM8) { 3079 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 3080 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; 3081 } else if (option == DITHER_OPTION_FM10) { 3082 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 3083 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; 3084 } 3085 3086 fmt_bit_depth->pixel_encoding = pixel_encoding; 3087 } 3088 3089 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) 3090 { 3091 struct dc_link *link = stream->link; 3092 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 3093 enum dc_status res = DC_OK; 3094 3095 calculate_phy_pix_clks(stream); 3096 3097 if (!tg->funcs->validate_timing(tg, &stream->timing)) 3098 res = DC_FAIL_CONTROLLER_VALIDATE; 3099 3100 if (res == DC_OK) { 3101 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 3102 !link->link_enc->funcs->validate_output_with_stream( 3103 link->link_enc, stream)) 3104 res = DC_FAIL_ENC_VALIDATE; 3105 } 3106 3107 /* TODO: validate audio ASIC caps, encoder */ 3108 3109 if (res == DC_OK) 3110 res = dc_link_validate_mode_timing(stream, 3111 link, 3112 &stream->timing); 3113 3114 return res; 3115 } 3116 3117 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) 3118 { 3119 enum dc_status res = DC_OK; 3120 3121 /* check if surface has invalid dimensions */ 3122 if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 || 3123 plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0) 3124 return DC_FAIL_SURFACE_VALIDATE; 3125 3126 /* TODO For now validates pixel format only */ 3127 if (dc->res_pool->funcs->validate_plane) 3128 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps); 3129 3130 return res; 3131 } 3132 3133 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format) 3134 { 3135 switch (format) { 3136 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 3137 return 8; 3138 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 3139 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 3140 return 12; 3141 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 3142 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 3143 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 3144 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 3145 return 16; 3146 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 3147 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 3148 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 3149 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 3150 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 3151 #if defined(CONFIG_DRM_AMD_DC_DCN) 3152 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 3153 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 3154 #endif 3155 return 32; 3156 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 3157 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 3158 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 3159 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 3160 return 64; 3161 default: 3162 ASSERT_CRITICAL(false); 3163 return -1; 3164 } 3165 } 3166 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes) 3167 { 3168 if (modes) { 3169 if (modes->sample_rates.rate.RATE_192) 3170 return 192000; 3171 if (modes->sample_rates.rate.RATE_176_4) 3172 return 176400; 3173 if (modes->sample_rates.rate.RATE_96) 3174 return 96000; 3175 if (modes->sample_rates.rate.RATE_88_2) 3176 return 88200; 3177 if (modes->sample_rates.rate.RATE_48) 3178 return 48000; 3179 if (modes->sample_rates.rate.RATE_44_1) 3180 return 44100; 3181 if (modes->sample_rates.rate.RATE_32) 3182 return 32000; 3183 } 3184 /*original logic when no audio info*/ 3185 return 441000; 3186 } 3187 3188 void get_audio_check(struct audio_info *aud_modes, 3189 struct audio_check *audio_chk) 3190 { 3191 unsigned int i; 3192 unsigned int max_sample_rate = 0; 3193 3194 if (aud_modes) { 3195 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/ 3196 3197 audio_chk->max_audiosample_rate = 0; 3198 for (i = 0; i < aud_modes->mode_count; i++) { 3199 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]); 3200 if (audio_chk->max_audiosample_rate < max_sample_rate) 3201 audio_chk->max_audiosample_rate = max_sample_rate; 3202 /*dts takes the same as type 2: AP = 0.25*/ 3203 } 3204 /*check which one take more bandwidth*/ 3205 if (audio_chk->max_audiosample_rate > 192000) 3206 audio_chk->audio_packet_type = 0x9;/*AP =1*/ 3207 audio_chk->acat = 0;/*not support*/ 3208 } 3209 } 3210 3211 static struct hpo_dp_link_encoder *get_temp_hpo_dp_link_enc( 3212 const struct resource_context *res_ctx, 3213 const struct resource_pool *const pool, 3214 const struct dc_link *link) 3215 { 3216 struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL; 3217 int enc_index; 3218 3219 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link); 3220 3221 if (enc_index < 0) 3222 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool); 3223 3224 if (enc_index >= 0) 3225 hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index]; 3226 3227 return hpo_dp_link_enc; 3228 } 3229 3230 bool get_temp_dp_link_res(struct dc_link *link, 3231 struct link_resource *link_res, 3232 struct dc_link_settings *link_settings) 3233 { 3234 const struct dc *dc = link->dc; 3235 const struct resource_context *res_ctx = &dc->current_state->res_ctx; 3236 3237 memset(link_res, 0, sizeof(*link_res)); 3238 3239 if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 3240 link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx, 3241 dc->res_pool, link); 3242 if (!link_res->hpo_dp_link_enc) 3243 return false; 3244 } 3245 return true; 3246 } 3247 3248 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc, 3249 struct dc_state *context) 3250 { 3251 int i, j; 3252 struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd; 3253 3254 /* If pipe backend is reset, need to reset pipe syncd status */ 3255 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3256 pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i]; 3257 pipe_ctx = &context->res_ctx.pipe_ctx[i]; 3258 3259 if (!pipe_ctx_old->stream) 3260 continue; 3261 3262 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 3263 continue; 3264 3265 if (!pipe_ctx->stream || 3266 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 3267 3268 /* Reset all the syncd pipes from the disabled pipe */ 3269 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3270 pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j]; 3271 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) || 3272 !IS_PIPE_SYNCD_VALID(pipe_ctx_syncd)) 3273 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j); 3274 } 3275 } 3276 } 3277 } 3278 3279 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc, 3280 struct dc_state *context, 3281 uint8_t disabled_master_pipe_idx) 3282 { 3283 int i; 3284 struct pipe_ctx *pipe_ctx, *pipe_ctx_check; 3285 3286 pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx]; 3287 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) || 3288 !IS_PIPE_SYNCD_VALID(pipe_ctx)) 3289 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx); 3290 3291 /* for the pipe disabled, check if any slave pipe exists and assert */ 3292 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3293 pipe_ctx_check = &context->res_ctx.pipe_ctx[i]; 3294 3295 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) && 3296 IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx)) 3297 DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n", 3298 i, disabled_master_pipe_idx); 3299 } 3300 } 3301 3302 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter) 3303 { 3304 /* TODO - get transmitter to phy idx mapping from DMUB */ 3305 uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A; 3306 3307 #if defined(CONFIG_DRM_AMD_DC_DCN) 3308 if (dc->ctx->dce_version == DCN_VERSION_3_1 && 3309 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 3310 switch (transmitter) { 3311 case TRANSMITTER_UNIPHY_A: 3312 phy_idx = 0; 3313 break; 3314 case TRANSMITTER_UNIPHY_B: 3315 phy_idx = 1; 3316 break; 3317 case TRANSMITTER_UNIPHY_C: 3318 phy_idx = 5; 3319 break; 3320 case TRANSMITTER_UNIPHY_D: 3321 phy_idx = 6; 3322 break; 3323 case TRANSMITTER_UNIPHY_E: 3324 phy_idx = 4; 3325 break; 3326 default: 3327 phy_idx = 0; 3328 break; 3329 } 3330 } 3331 #endif 3332 return phy_idx; 3333 } 3334 3335 const struct link_hwss *get_link_hwss(const struct dc_link *link, 3336 const struct link_resource *link_res) 3337 { 3338 /* Link_hwss is only accessible by getter function instead of accessing 3339 * by pointers in dc with the intent to protect against breaking polymorphism. 3340 */ 3341 if (can_use_hpo_dp_link_hwss(link, link_res)) 3342 /* TODO: some assumes that if decided link settings is 128b/132b 3343 * channel coding format hpo_dp_link_enc should be used. 3344 * Others believe that if hpo_dp_link_enc is available in link 3345 * resource then hpo_dp_link_enc must be used. This bound between 3346 * hpo_dp_link_enc != NULL and decided link settings is loosely coupled 3347 * with a premise that both hpo_dp_link_enc pointer and decided link 3348 * settings are determined based on single policy function like 3349 * "decide_link_settings" from upper layer. This "convention" 3350 * cannot be maintained and enforced at current level. 3351 * Therefore a refactor is due so we can enforce a strong bound 3352 * between those two parameters at this level. 3353 * 3354 * To put it simple, we want to make enforcement at low level so that 3355 * we will not return link hwss if caller plans to do 8b/10b 3356 * with an hpo encoder. Or we can return a very dummy one that doesn't 3357 * do work for all functions 3358 */ 3359 return get_hpo_dp_link_hwss(); 3360 else if (can_use_dpia_link_hwss(link, link_res)) 3361 return get_dpia_link_hwss(); 3362 else if (can_use_dio_link_hwss(link, link_res)) 3363 return get_dio_link_hwss(); 3364 else 3365 return get_virtual_link_hwss(); 3366 } 3367