1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 27 #include "resource.h" 28 #include "include/irq_service_interface.h" 29 #include "link_encoder.h" 30 #include "stream_encoder.h" 31 #include "opp.h" 32 #include "timing_generator.h" 33 #include "transform.h" 34 #include "dpp.h" 35 #include "core_types.h" 36 #include "set_mode_types.h" 37 #include "virtual/virtual_stream_encoder.h" 38 39 #include "dce80/dce80_resource.h" 40 #include "dce100/dce100_resource.h" 41 #include "dce110/dce110_resource.h" 42 #include "dce112/dce112_resource.h" 43 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 44 #include "dcn10/dcn10_resource.h" 45 #endif 46 #include "dce120/dce120_resource.h" 47 48 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 49 { 50 enum dce_version dc_version = DCE_VERSION_UNKNOWN; 51 switch (asic_id.chip_family) { 52 53 case FAMILY_CI: 54 dc_version = DCE_VERSION_8_0; 55 break; 56 case FAMILY_KV: 57 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) || 58 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) || 59 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev)) 60 dc_version = DCE_VERSION_8_3; 61 else 62 dc_version = DCE_VERSION_8_1; 63 break; 64 case FAMILY_CZ: 65 dc_version = DCE_VERSION_11_0; 66 break; 67 68 case FAMILY_VI: 69 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || 70 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { 71 dc_version = DCE_VERSION_10_0; 72 break; 73 } 74 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || 75 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || 76 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { 77 dc_version = DCE_VERSION_11_2; 78 } 79 break; 80 case FAMILY_AI: 81 dc_version = DCE_VERSION_12_0; 82 break; 83 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 84 case FAMILY_RV: 85 dc_version = DCN_VERSION_1_0; 86 break; 87 #endif 88 default: 89 dc_version = DCE_VERSION_UNKNOWN; 90 break; 91 } 92 return dc_version; 93 } 94 95 struct resource_pool *dc_create_resource_pool( 96 struct dc *dc, 97 int num_virtual_links, 98 enum dce_version dc_version, 99 struct hw_asic_id asic_id) 100 { 101 struct resource_pool *res_pool = NULL; 102 103 switch (dc_version) { 104 case DCE_VERSION_8_0: 105 res_pool = dce80_create_resource_pool( 106 num_virtual_links, dc); 107 break; 108 case DCE_VERSION_8_1: 109 res_pool = dce81_create_resource_pool( 110 num_virtual_links, dc); 111 break; 112 case DCE_VERSION_8_3: 113 res_pool = dce83_create_resource_pool( 114 num_virtual_links, dc); 115 break; 116 case DCE_VERSION_10_0: 117 res_pool = dce100_create_resource_pool( 118 num_virtual_links, dc); 119 break; 120 case DCE_VERSION_11_0: 121 res_pool = dce110_create_resource_pool( 122 num_virtual_links, dc, asic_id); 123 break; 124 case DCE_VERSION_11_2: 125 res_pool = dce112_create_resource_pool( 126 num_virtual_links, dc); 127 break; 128 case DCE_VERSION_12_0: 129 res_pool = dce120_create_resource_pool( 130 num_virtual_links, dc); 131 break; 132 133 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 134 case DCN_VERSION_1_0: 135 res_pool = dcn10_create_resource_pool( 136 num_virtual_links, dc); 137 break; 138 #endif 139 140 141 default: 142 break; 143 } 144 if (res_pool != NULL) { 145 struct dc_firmware_info fw_info = { { 0 } }; 146 147 if (dc->ctx->dc_bios->funcs->get_firmware_info( 148 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { 149 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency; 150 } else 151 ASSERT_CRITICAL(false); 152 } 153 154 return res_pool; 155 } 156 157 void dc_destroy_resource_pool(struct dc *dc) 158 { 159 if (dc) { 160 if (dc->res_pool) 161 dc->res_pool->funcs->destroy(&dc->res_pool); 162 163 kfree(dc->hwseq); 164 } 165 } 166 167 static void update_num_audio( 168 const struct resource_straps *straps, 169 unsigned int *num_audio, 170 struct audio_support *aud_support) 171 { 172 aud_support->dp_audio = true; 173 aud_support->hdmi_audio_native = false; 174 aud_support->hdmi_audio_on_dongle = false; 175 176 if (straps->hdmi_disable == 0) { 177 if (straps->dc_pinstraps_audio & 0x2) { 178 aud_support->hdmi_audio_on_dongle = true; 179 aud_support->hdmi_audio_native = true; 180 } 181 } 182 183 switch (straps->audio_stream_number) { 184 case 0: /* multi streams supported */ 185 break; 186 case 1: /* multi streams not supported */ 187 *num_audio = 1; 188 break; 189 default: 190 DC_ERR("DC: unexpected audio fuse!\n"); 191 } 192 } 193 194 bool resource_construct( 195 unsigned int num_virtual_links, 196 struct dc *dc, 197 struct resource_pool *pool, 198 const struct resource_create_funcs *create_funcs) 199 { 200 struct dc_context *ctx = dc->ctx; 201 const struct resource_caps *caps = pool->res_cap; 202 int i; 203 unsigned int num_audio = caps->num_audio; 204 struct resource_straps straps = {0}; 205 206 if (create_funcs->read_dce_straps) 207 create_funcs->read_dce_straps(dc->ctx, &straps); 208 209 pool->audio_count = 0; 210 if (create_funcs->create_audio) { 211 /* find the total number of streams available via the 212 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 213 * registers (one for each pin) starting from pin 1 214 * up to the max number of audio pins. 215 * We stop on the first pin where 216 * PORT_CONNECTIVITY == 1 (as instructed by HW team). 217 */ 218 update_num_audio(&straps, &num_audio, &pool->audio_support); 219 for (i = 0; i < pool->pipe_count && i < num_audio; i++) { 220 struct audio *aud = create_funcs->create_audio(ctx, i); 221 222 if (aud == NULL) { 223 DC_ERR("DC: failed to create audio!\n"); 224 return false; 225 } 226 227 if (!aud->funcs->endpoint_valid(aud)) { 228 aud->funcs->destroy(&aud); 229 break; 230 } 231 232 pool->audios[i] = aud; 233 pool->audio_count++; 234 } 235 } 236 237 pool->stream_enc_count = 0; 238 if (create_funcs->create_stream_encoder) { 239 for (i = 0; i < caps->num_stream_encoder; i++) { 240 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); 241 if (pool->stream_enc[i] == NULL) 242 DC_ERR("DC: failed to create stream_encoder!\n"); 243 pool->stream_enc_count++; 244 } 245 } 246 dc->caps.dynamic_audio = false; 247 if (pool->audio_count < pool->stream_enc_count) { 248 dc->caps.dynamic_audio = true; 249 } 250 for (i = 0; i < num_virtual_links; i++) { 251 pool->stream_enc[pool->stream_enc_count] = 252 virtual_stream_encoder_create( 253 ctx, ctx->dc_bios); 254 if (pool->stream_enc[pool->stream_enc_count] == NULL) { 255 DC_ERR("DC: failed to create stream_encoder!\n"); 256 return false; 257 } 258 pool->stream_enc_count++; 259 } 260 261 dc->hwseq = create_funcs->create_hwseq(ctx); 262 263 return true; 264 } 265 266 267 void resource_unreference_clock_source( 268 struct resource_context *res_ctx, 269 const struct resource_pool *pool, 270 struct clock_source *clock_source) 271 { 272 int i; 273 274 for (i = 0; i < pool->clk_src_count; i++) { 275 if (pool->clock_sources[i] != clock_source) 276 continue; 277 278 res_ctx->clock_source_ref_count[i]--; 279 280 break; 281 } 282 283 if (pool->dp_clock_source == clock_source) 284 res_ctx->dp_clock_source_ref_count--; 285 } 286 287 void resource_reference_clock_source( 288 struct resource_context *res_ctx, 289 const struct resource_pool *pool, 290 struct clock_source *clock_source) 291 { 292 int i; 293 for (i = 0; i < pool->clk_src_count; i++) { 294 if (pool->clock_sources[i] != clock_source) 295 continue; 296 297 res_ctx->clock_source_ref_count[i]++; 298 break; 299 } 300 301 if (pool->dp_clock_source == clock_source) 302 res_ctx->dp_clock_source_ref_count++; 303 } 304 305 bool resource_are_streams_timing_synchronizable( 306 struct dc_stream_state *stream1, 307 struct dc_stream_state *stream2) 308 { 309 if (stream1->timing.h_total != stream2->timing.h_total) 310 return false; 311 312 if (stream1->timing.v_total != stream2->timing.v_total) 313 return false; 314 315 if (stream1->timing.h_addressable 316 != stream2->timing.h_addressable) 317 return false; 318 319 if (stream1->timing.v_addressable 320 != stream2->timing.v_addressable) 321 return false; 322 323 if (stream1->timing.pix_clk_khz 324 != stream2->timing.pix_clk_khz) 325 return false; 326 327 if (stream1->phy_pix_clk != stream2->phy_pix_clk 328 && (!dc_is_dp_signal(stream1->signal) 329 || !dc_is_dp_signal(stream2->signal))) 330 return false; 331 332 return true; 333 } 334 335 static bool is_sharable_clk_src( 336 const struct pipe_ctx *pipe_with_clk_src, 337 const struct pipe_ctx *pipe) 338 { 339 if (pipe_with_clk_src->clock_source == NULL) 340 return false; 341 342 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) 343 return false; 344 345 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal)) 346 return false; 347 348 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) 349 && dc_is_dvi_signal(pipe->stream->signal)) 350 return false; 351 352 if (dc_is_hdmi_signal(pipe->stream->signal) 353 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal)) 354 return false; 355 356 if (!resource_are_streams_timing_synchronizable( 357 pipe_with_clk_src->stream, pipe->stream)) 358 return false; 359 360 return true; 361 } 362 363 struct clock_source *resource_find_used_clk_src_for_sharing( 364 struct resource_context *res_ctx, 365 struct pipe_ctx *pipe_ctx) 366 { 367 int i; 368 369 for (i = 0; i < MAX_PIPES; i++) { 370 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) 371 return res_ctx->pipe_ctx[i].clock_source; 372 } 373 374 return NULL; 375 } 376 377 static enum pixel_format convert_pixel_format_to_dalsurface( 378 enum surface_pixel_format surface_pixel_format) 379 { 380 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 381 382 switch (surface_pixel_format) { 383 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 384 dal_pixel_format = PIXEL_FORMAT_INDEX8; 385 break; 386 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 387 dal_pixel_format = PIXEL_FORMAT_RGB565; 388 break; 389 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 390 dal_pixel_format = PIXEL_FORMAT_RGB565; 391 break; 392 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 393 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 394 break; 395 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 396 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 397 break; 398 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 399 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 400 break; 401 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 402 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 403 break; 404 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 405 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS; 406 break; 407 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 408 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 409 dal_pixel_format = PIXEL_FORMAT_FP16; 410 break; 411 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 412 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 413 dal_pixel_format = PIXEL_FORMAT_420BPP8; 414 break; 415 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 416 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 417 dal_pixel_format = PIXEL_FORMAT_420BPP10; 418 break; 419 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 420 default: 421 dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 422 break; 423 } 424 return dal_pixel_format; 425 } 426 427 static void rect_swap_helper(struct rect *rect) 428 { 429 uint32_t temp = 0; 430 431 temp = rect->height; 432 rect->height = rect->width; 433 rect->width = temp; 434 435 temp = rect->x; 436 rect->x = rect->y; 437 rect->y = temp; 438 } 439 440 static void calculate_viewport(struct pipe_ctx *pipe_ctx) 441 { 442 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 443 const struct dc_stream_state *stream = pipe_ctx->stream; 444 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 445 struct rect surf_src = plane_state->src_rect; 446 struct rect clip = { 0 }; 447 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 448 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 449 bool pri_split = pipe_ctx->bottom_pipe && 450 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state; 451 bool sec_split = pipe_ctx->top_pipe && 452 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 453 454 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || 455 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { 456 pri_split = false; 457 sec_split = false; 458 } 459 460 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 461 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 462 rect_swap_helper(&surf_src); 463 464 /* The actual clip is an intersection between stream 465 * source and surface clip 466 */ 467 clip.x = stream->src.x > plane_state->clip_rect.x ? 468 stream->src.x : plane_state->clip_rect.x; 469 470 clip.width = stream->src.x + stream->src.width < 471 plane_state->clip_rect.x + plane_state->clip_rect.width ? 472 stream->src.x + stream->src.width - clip.x : 473 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ; 474 475 clip.y = stream->src.y > plane_state->clip_rect.y ? 476 stream->src.y : plane_state->clip_rect.y; 477 478 clip.height = stream->src.y + stream->src.height < 479 plane_state->clip_rect.y + plane_state->clip_rect.height ? 480 stream->src.y + stream->src.height - clip.y : 481 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ; 482 483 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio 484 * num_pixels = clip.num_pix * scl_ratio 485 */ 486 data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) * 487 surf_src.width / plane_state->dst_rect.width; 488 data->viewport.width = clip.width * 489 surf_src.width / plane_state->dst_rect.width; 490 491 data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) * 492 surf_src.height / plane_state->dst_rect.height; 493 data->viewport.height = clip.height * 494 surf_src.height / plane_state->dst_rect.height; 495 496 /* Round down, compensate in init */ 497 data->viewport_c.x = data->viewport.x / vpc_div; 498 data->viewport_c.y = data->viewport.y / vpc_div; 499 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? 500 dal_fixed31_32_half : dal_fixed31_32_zero; 501 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? 502 dal_fixed31_32_half : dal_fixed31_32_zero; 503 /* Round up, assume original video size always even dimensions */ 504 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div; 505 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div; 506 507 /* Handle hsplit */ 508 if (pri_split || sec_split) { 509 /* HMirror XOR Secondary_pipe XOR Rotation_180 */ 510 bool right_view = (sec_split != plane_state->horizontal_mirror) != 511 (plane_state->rotation == ROTATION_ANGLE_180); 512 513 if (plane_state->rotation == ROTATION_ANGLE_90 514 || plane_state->rotation == ROTATION_ANGLE_270) 515 /* Secondary_pipe XOR Rotation_270 */ 516 right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split; 517 518 if (right_view) { 519 data->viewport.x += data->viewport.width / 2; 520 data->viewport_c.x += data->viewport_c.width / 2; 521 /* Ceil offset pipe */ 522 data->viewport.width = (data->viewport.width + 1) / 2; 523 data->viewport_c.width = (data->viewport_c.width + 1) / 2; 524 } else { 525 data->viewport.width /= 2; 526 data->viewport_c.width /= 2; 527 } 528 } 529 530 if (plane_state->rotation == ROTATION_ANGLE_90 || 531 plane_state->rotation == ROTATION_ANGLE_270) { 532 rect_swap_helper(&data->viewport_c); 533 rect_swap_helper(&data->viewport); 534 } 535 } 536 537 static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) 538 { 539 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 540 const struct dc_stream_state *stream = pipe_ctx->stream; 541 struct rect surf_src = plane_state->src_rect; 542 struct rect surf_clip = plane_state->clip_rect; 543 int recout_full_x, recout_full_y; 544 545 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 546 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 547 rect_swap_helper(&surf_src); 548 549 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x; 550 if (stream->src.x < surf_clip.x) 551 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x 552 - stream->src.x) * stream->dst.width 553 / stream->src.width; 554 555 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width * 556 stream->dst.width / stream->src.width; 557 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x > 558 stream->dst.x + stream->dst.width) 559 pipe_ctx->plane_res.scl_data.recout.width = 560 stream->dst.x + stream->dst.width 561 - pipe_ctx->plane_res.scl_data.recout.x; 562 563 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y; 564 if (stream->src.y < surf_clip.y) 565 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y 566 - stream->src.y) * stream->dst.height 567 / stream->src.height; 568 569 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height * 570 stream->dst.height / stream->src.height; 571 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y > 572 stream->dst.y + stream->dst.height) 573 pipe_ctx->plane_res.scl_data.recout.height = 574 stream->dst.y + stream->dst.height 575 - pipe_ctx->plane_res.scl_data.recout.y; 576 577 /* Handle h & vsplit */ 578 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == 579 pipe_ctx->plane_state) { 580 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { 581 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height / 2; 582 /* Floor primary pipe, ceil 2ndary pipe */ 583 pipe_ctx->plane_res.scl_data.recout.height = (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2; 584 } else { 585 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width / 2; 586 pipe_ctx->plane_res.scl_data.recout.width = (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2; 587 } 588 } else if (pipe_ctx->bottom_pipe && 589 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) { 590 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 591 pipe_ctx->plane_res.scl_data.recout.height /= 2; 592 else 593 pipe_ctx->plane_res.scl_data.recout.width /= 2; 594 } 595 596 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset) 597 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl 598 * ratio) 599 */ 600 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) 601 * stream->dst.width / stream->src.width - 602 surf_src.x * plane_state->dst_rect.width / surf_src.width 603 * stream->dst.width / stream->src.width; 604 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) 605 * stream->dst.height / stream->src.height - 606 surf_src.y * plane_state->dst_rect.height / surf_src.height 607 * stream->dst.height / stream->src.height; 608 609 recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x; 610 recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y; 611 } 612 613 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) 614 { 615 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 616 const struct dc_stream_state *stream = pipe_ctx->stream; 617 struct rect surf_src = plane_state->src_rect; 618 const int in_w = stream->src.width; 619 const int in_h = stream->src.height; 620 const int out_w = stream->dst.width; 621 const int out_h = stream->dst.height; 622 623 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 624 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 625 rect_swap_helper(&surf_src); 626 627 pipe_ctx->plane_res.scl_data.ratios.horz = dal_fixed31_32_from_fraction( 628 surf_src.width, 629 plane_state->dst_rect.width); 630 pipe_ctx->plane_res.scl_data.ratios.vert = dal_fixed31_32_from_fraction( 631 surf_src.height, 632 plane_state->dst_rect.height); 633 634 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 635 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; 636 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 637 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; 638 639 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( 640 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); 641 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( 642 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); 643 644 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; 645 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; 646 647 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 648 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { 649 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; 650 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; 651 } 652 } 653 654 static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip) 655 { 656 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 657 struct rect src = pipe_ctx->plane_state->src_rect; 658 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 659 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 660 661 662 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 663 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { 664 rect_swap_helper(&src); 665 rect_swap_helper(&data->viewport_c); 666 rect_swap_helper(&data->viewport); 667 } 668 669 /* 670 * Init calculated according to formula: 671 * init = (scaling_ratio + number_of_taps + 1) / 2 672 * init_bot = init + scaling_ratio 673 * init_c = init + truncated_vp_c_offset(from calculate viewport) 674 */ 675 data->inits.h = dal_fixed31_32_div_int( 676 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2); 677 678 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int( 679 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)); 680 681 data->inits.v = dal_fixed31_32_div_int( 682 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2); 683 684 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int( 685 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)); 686 687 688 /* Adjust for viewport end clip-off */ 689 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) { 690 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x; 691 int int_part = dal_fixed31_32_floor( 692 dal_fixed31_32_sub(data->inits.h, data->ratios.horz)); 693 694 int_part = int_part > 0 ? int_part : 0; 695 data->viewport.width += int_part < vp_clip ? int_part : vp_clip; 696 } 697 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) { 698 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y; 699 int int_part = dal_fixed31_32_floor( 700 dal_fixed31_32_sub(data->inits.v, data->ratios.vert)); 701 702 int_part = int_part > 0 ? int_part : 0; 703 data->viewport.height += int_part < vp_clip ? int_part : vp_clip; 704 } 705 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) { 706 int vp_clip = (src.x + src.width) / vpc_div - 707 data->viewport_c.width - data->viewport_c.x; 708 int int_part = dal_fixed31_32_floor( 709 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c)); 710 711 int_part = int_part > 0 ? int_part : 0; 712 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip; 713 } 714 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) { 715 int vp_clip = (src.y + src.height) / vpc_div - 716 data->viewport_c.height - data->viewport_c.y; 717 int int_part = dal_fixed31_32_floor( 718 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c)); 719 720 int_part = int_part > 0 ? int_part : 0; 721 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip; 722 } 723 724 /* Adjust for non-0 viewport offset */ 725 if (data->viewport.x) { 726 int int_part; 727 728 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int( 729 data->ratios.horz, recout_skip->width)); 730 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x; 731 if (int_part < data->taps.h_taps) { 732 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ? 733 (data->taps.h_taps - int_part) : data->viewport.x; 734 data->viewport.x -= int_adj; 735 data->viewport.width += int_adj; 736 int_part += int_adj; 737 } else if (int_part > data->taps.h_taps) { 738 data->viewport.x += int_part - data->taps.h_taps; 739 data->viewport.width -= int_part - data->taps.h_taps; 740 int_part = data->taps.h_taps; 741 } 742 data->inits.h.value &= 0xffffffff; 743 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part); 744 } 745 746 if (data->viewport_c.x) { 747 int int_part; 748 749 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int( 750 data->ratios.horz_c, recout_skip->width)); 751 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x; 752 if (int_part < data->taps.h_taps_c) { 753 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ? 754 (data->taps.h_taps_c - int_part) : data->viewport_c.x; 755 data->viewport_c.x -= int_adj; 756 data->viewport_c.width += int_adj; 757 int_part += int_adj; 758 } else if (int_part > data->taps.h_taps_c) { 759 data->viewport_c.x += int_part - data->taps.h_taps_c; 760 data->viewport_c.width -= int_part - data->taps.h_taps_c; 761 int_part = data->taps.h_taps_c; 762 } 763 data->inits.h_c.value &= 0xffffffff; 764 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part); 765 } 766 767 if (data->viewport.y) { 768 int int_part; 769 770 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int( 771 data->ratios.vert, recout_skip->height)); 772 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y; 773 if (int_part < data->taps.v_taps) { 774 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ? 775 (data->taps.v_taps - int_part) : data->viewport.y; 776 data->viewport.y -= int_adj; 777 data->viewport.height += int_adj; 778 int_part += int_adj; 779 } else if (int_part > data->taps.v_taps) { 780 data->viewport.y += int_part - data->taps.v_taps; 781 data->viewport.height -= int_part - data->taps.v_taps; 782 int_part = data->taps.v_taps; 783 } 784 data->inits.v.value &= 0xffffffff; 785 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part); 786 } 787 788 if (data->viewport_c.y) { 789 int int_part; 790 791 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int( 792 data->ratios.vert_c, recout_skip->height)); 793 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y; 794 if (int_part < data->taps.v_taps_c) { 795 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ? 796 (data->taps.v_taps_c - int_part) : data->viewport_c.y; 797 data->viewport_c.y -= int_adj; 798 data->viewport_c.height += int_adj; 799 int_part += int_adj; 800 } else if (int_part > data->taps.v_taps_c) { 801 data->viewport_c.y += int_part - data->taps.v_taps_c; 802 data->viewport_c.height -= int_part - data->taps.v_taps_c; 803 int_part = data->taps.v_taps_c; 804 } 805 data->inits.v_c.value &= 0xffffffff; 806 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part); 807 } 808 809 /* Interlaced inits based on final vert inits */ 810 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert); 811 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c); 812 813 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 814 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { 815 rect_swap_helper(&data->viewport_c); 816 rect_swap_helper(&data->viewport); 817 } 818 } 819 820 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 821 { 822 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 823 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 824 struct view recout_skip = { 0 }; 825 bool res = false; 826 827 /* Important: scaling ratio calculation requires pixel format, 828 * lb depth calculation requires recout and taps require scaling ratios. 829 * Inits require viewport, taps, ratios and recout of split pipe 830 */ 831 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( 832 pipe_ctx->plane_state->format); 833 834 calculate_scaling_ratios(pipe_ctx); 835 836 calculate_viewport(pipe_ctx); 837 838 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16) 839 return false; 840 841 calculate_recout(pipe_ctx, &recout_skip); 842 843 /** 844 * Setting line buffer pixel depth to 24bpp yields banding 845 * on certain displays, such as the Sharp 4k 846 */ 847 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; 848 849 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left; 850 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top; 851 852 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; 853 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; 854 855 856 /* Taps calculations */ 857 if (pipe_ctx->plane_res.xfm != NULL) 858 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 859 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 860 861 if (pipe_ctx->plane_res.dpp != NULL) 862 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 863 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 864 if (!res) { 865 /* Try 24 bpp linebuffer */ 866 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; 867 868 if (pipe_ctx->plane_res.xfm != NULL) 869 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 870 pipe_ctx->plane_res.xfm, 871 &pipe_ctx->plane_res.scl_data, 872 &plane_state->scaling_quality); 873 874 if (pipe_ctx->plane_res.dpp != NULL) 875 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 876 pipe_ctx->plane_res.dpp, 877 &pipe_ctx->plane_res.scl_data, 878 &plane_state->scaling_quality); 879 } 880 881 if (res) 882 /* May need to re-check lb size after this in some obscure scenario */ 883 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip); 884 885 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER, 886 "%s: Viewport:\nheight:%d width:%d x:%d " 887 "y:%d\n dst_rect:\nheight:%d width:%d x:%d " 888 "y:%d\n", 889 __func__, 890 pipe_ctx->plane_res.scl_data.viewport.height, 891 pipe_ctx->plane_res.scl_data.viewport.width, 892 pipe_ctx->plane_res.scl_data.viewport.x, 893 pipe_ctx->plane_res.scl_data.viewport.y, 894 plane_state->dst_rect.height, 895 plane_state->dst_rect.width, 896 plane_state->dst_rect.x, 897 plane_state->dst_rect.y); 898 899 return res; 900 } 901 902 903 enum dc_status resource_build_scaling_params_for_context( 904 const struct dc *dc, 905 struct dc_state *context) 906 { 907 int i; 908 909 for (i = 0; i < MAX_PIPES; i++) { 910 if (context->res_ctx.pipe_ctx[i].plane_state != NULL && 911 context->res_ctx.pipe_ctx[i].stream != NULL) 912 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) 913 return DC_FAIL_SCALING; 914 } 915 916 return DC_OK; 917 } 918 919 struct pipe_ctx *find_idle_secondary_pipe( 920 struct resource_context *res_ctx, 921 const struct resource_pool *pool) 922 { 923 int i; 924 struct pipe_ctx *secondary_pipe = NULL; 925 926 /* 927 * search backwards for the second pipe to keep pipe 928 * assignment more consistent 929 */ 930 931 for (i = pool->pipe_count - 1; i >= 0; i--) { 932 if (res_ctx->pipe_ctx[i].stream == NULL) { 933 secondary_pipe = &res_ctx->pipe_ctx[i]; 934 secondary_pipe->pipe_idx = i; 935 break; 936 } 937 } 938 939 940 return secondary_pipe; 941 } 942 943 struct pipe_ctx *resource_get_head_pipe_for_stream( 944 struct resource_context *res_ctx, 945 struct dc_stream_state *stream) 946 { 947 int i; 948 for (i = 0; i < MAX_PIPES; i++) { 949 if (res_ctx->pipe_ctx[i].stream == stream && 950 !res_ctx->pipe_ctx[i].top_pipe) { 951 return &res_ctx->pipe_ctx[i]; 952 break; 953 } 954 } 955 return NULL; 956 } 957 958 static struct pipe_ctx *resource_get_tail_pipe_for_stream( 959 struct resource_context *res_ctx, 960 struct dc_stream_state *stream) 961 { 962 struct pipe_ctx *head_pipe, *tail_pipe; 963 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 964 965 if (!head_pipe) 966 return NULL; 967 968 tail_pipe = head_pipe->bottom_pipe; 969 970 while (tail_pipe) { 971 head_pipe = tail_pipe; 972 tail_pipe = tail_pipe->bottom_pipe; 973 } 974 975 return head_pipe; 976 } 977 978 /* 979 * A free_pipe for a stream is defined here as a pipe 980 * that has no surface attached yet 981 */ 982 static struct pipe_ctx *acquire_free_pipe_for_stream( 983 struct dc_state *context, 984 const struct resource_pool *pool, 985 struct dc_stream_state *stream) 986 { 987 int i; 988 struct resource_context *res_ctx = &context->res_ctx; 989 990 struct pipe_ctx *head_pipe = NULL; 991 992 /* Find head pipe, which has the back end set up*/ 993 994 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 995 996 if (!head_pipe) { 997 ASSERT(0); 998 return NULL; 999 } 1000 1001 if (!head_pipe->plane_state) 1002 return head_pipe; 1003 1004 /* Re-use pipe already acquired for this stream if available*/ 1005 for (i = pool->pipe_count - 1; i >= 0; i--) { 1006 if (res_ctx->pipe_ctx[i].stream == stream && 1007 !res_ctx->pipe_ctx[i].plane_state) { 1008 return &res_ctx->pipe_ctx[i]; 1009 } 1010 } 1011 1012 /* 1013 * At this point we have no re-useable pipe for this stream and we need 1014 * to acquire an idle one to satisfy the request 1015 */ 1016 1017 if (!pool->funcs->acquire_idle_pipe_for_layer) 1018 return NULL; 1019 1020 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream); 1021 1022 } 1023 1024 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1025 static int acquire_first_split_pipe( 1026 struct resource_context *res_ctx, 1027 const struct resource_pool *pool, 1028 struct dc_stream_state *stream) 1029 { 1030 int i; 1031 1032 for (i = 0; i < pool->pipe_count; i++) { 1033 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 1034 1035 if (pipe_ctx->top_pipe && 1036 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) { 1037 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1038 if (pipe_ctx->bottom_pipe) 1039 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1040 1041 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1042 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 1043 pipe_ctx->plane_res.hubp = pool->hubps[i]; 1044 pipe_ctx->plane_res.ipp = pool->ipps[i]; 1045 pipe_ctx->plane_res.dpp = pool->dpps[i]; 1046 pipe_ctx->stream_res.opp = pool->opps[i]; 1047 pipe_ctx->pipe_idx = i; 1048 1049 pipe_ctx->stream = stream; 1050 return i; 1051 } 1052 } 1053 return -1; 1054 } 1055 #endif 1056 1057 bool dc_add_plane_to_context( 1058 const struct dc *dc, 1059 struct dc_stream_state *stream, 1060 struct dc_plane_state *plane_state, 1061 struct dc_state *context) 1062 { 1063 int i; 1064 struct resource_pool *pool = dc->res_pool; 1065 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; 1066 struct dc_stream_status *stream_status = NULL; 1067 1068 for (i = 0; i < context->stream_count; i++) 1069 if (context->streams[i] == stream) { 1070 stream_status = &context->stream_status[i]; 1071 break; 1072 } 1073 if (stream_status == NULL) { 1074 dm_error("Existing stream not found; failed to attach surface!\n"); 1075 return false; 1076 } 1077 1078 1079 if (stream_status->plane_count == MAX_SURFACE_NUM) { 1080 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", 1081 plane_state, MAX_SURFACE_NUM); 1082 return false; 1083 } 1084 1085 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1086 1087 if (!head_pipe) { 1088 dm_error("Head pipe not found for stream_state %p !\n", stream); 1089 return false; 1090 } 1091 1092 free_pipe = acquire_free_pipe_for_stream(context, pool, stream); 1093 1094 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1095 if (!free_pipe) { 1096 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 1097 if (pipe_idx >= 0) 1098 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; 1099 } 1100 #endif 1101 if (!free_pipe) 1102 return false; 1103 1104 /* retain new surfaces */ 1105 dc_plane_state_retain(plane_state); 1106 free_pipe->plane_state = plane_state; 1107 1108 if (head_pipe != free_pipe) { 1109 1110 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream); 1111 ASSERT(tail_pipe); 1112 1113 free_pipe->stream_res.tg = tail_pipe->stream_res.tg; 1114 free_pipe->stream_res.opp = tail_pipe->stream_res.opp; 1115 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; 1116 free_pipe->stream_res.audio = tail_pipe->stream_res.audio; 1117 free_pipe->clock_source = tail_pipe->clock_source; 1118 free_pipe->top_pipe = tail_pipe; 1119 tail_pipe->bottom_pipe = free_pipe; 1120 } 1121 1122 /* assign new surfaces*/ 1123 stream_status->plane_states[stream_status->plane_count] = plane_state; 1124 1125 stream_status->plane_count++; 1126 1127 return true; 1128 } 1129 1130 bool dc_remove_plane_from_context( 1131 const struct dc *dc, 1132 struct dc_stream_state *stream, 1133 struct dc_plane_state *plane_state, 1134 struct dc_state *context) 1135 { 1136 int i; 1137 struct dc_stream_status *stream_status = NULL; 1138 struct resource_pool *pool = dc->res_pool; 1139 1140 for (i = 0; i < context->stream_count; i++) 1141 if (context->streams[i] == stream) { 1142 stream_status = &context->stream_status[i]; 1143 break; 1144 } 1145 1146 if (stream_status == NULL) { 1147 dm_error("Existing stream not found; failed to remove plane.\n"); 1148 return false; 1149 } 1150 1151 /* release pipe for plane*/ 1152 for (i = pool->pipe_count - 1; i >= 0; i--) { 1153 struct pipe_ctx *pipe_ctx; 1154 1155 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) { 1156 pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1157 1158 if (pipe_ctx->top_pipe) 1159 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1160 1161 /* Second condition is to avoid setting NULL to top pipe 1162 * of tail pipe making it look like head pipe in subsequent 1163 * deletes 1164 */ 1165 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) 1166 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1167 1168 /* 1169 * For head pipe detach surfaces from pipe for tail 1170 * pipe just zero it out 1171 */ 1172 if (!pipe_ctx->top_pipe) { 1173 pipe_ctx->plane_state = NULL; 1174 pipe_ctx->bottom_pipe = NULL; 1175 } else { 1176 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1177 } 1178 } 1179 } 1180 1181 1182 for (i = 0; i < stream_status->plane_count; i++) { 1183 if (stream_status->plane_states[i] == plane_state) { 1184 1185 dc_plane_state_release(stream_status->plane_states[i]); 1186 break; 1187 } 1188 } 1189 1190 if (i == stream_status->plane_count) { 1191 dm_error("Existing plane_state not found; failed to detach it!\n"); 1192 return false; 1193 } 1194 1195 stream_status->plane_count--; 1196 1197 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */ 1198 for (; i < stream_status->plane_count; i++) 1199 stream_status->plane_states[i] = stream_status->plane_states[i + 1]; 1200 1201 stream_status->plane_states[stream_status->plane_count] = NULL; 1202 1203 return true; 1204 } 1205 1206 bool dc_rem_all_planes_for_stream( 1207 const struct dc *dc, 1208 struct dc_stream_state *stream, 1209 struct dc_state *context) 1210 { 1211 int i, old_plane_count; 1212 struct dc_stream_status *stream_status = NULL; 1213 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; 1214 1215 for (i = 0; i < context->stream_count; i++) 1216 if (context->streams[i] == stream) { 1217 stream_status = &context->stream_status[i]; 1218 break; 1219 } 1220 1221 if (stream_status == NULL) { 1222 dm_error("Existing stream %p not found!\n", stream); 1223 return false; 1224 } 1225 1226 old_plane_count = stream_status->plane_count; 1227 1228 for (i = 0; i < old_plane_count; i++) 1229 del_planes[i] = stream_status->plane_states[i]; 1230 1231 for (i = 0; i < old_plane_count; i++) 1232 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) 1233 return false; 1234 1235 return true; 1236 } 1237 1238 static bool add_all_planes_for_stream( 1239 const struct dc *dc, 1240 struct dc_stream_state *stream, 1241 const struct dc_validation_set set[], 1242 int set_count, 1243 struct dc_state *context) 1244 { 1245 int i, j; 1246 1247 for (i = 0; i < set_count; i++) 1248 if (set[i].stream == stream) 1249 break; 1250 1251 if (i == set_count) { 1252 dm_error("Stream %p not found in set!\n", stream); 1253 return false; 1254 } 1255 1256 for (j = 0; j < set[i].plane_count; j++) 1257 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) 1258 return false; 1259 1260 return true; 1261 } 1262 1263 bool dc_add_all_planes_for_stream( 1264 const struct dc *dc, 1265 struct dc_stream_state *stream, 1266 struct dc_plane_state * const *plane_states, 1267 int plane_count, 1268 struct dc_state *context) 1269 { 1270 struct dc_validation_set set; 1271 int i; 1272 1273 set.stream = stream; 1274 set.plane_count = plane_count; 1275 1276 for (i = 0; i < plane_count; i++) 1277 set.plane_states[i] = plane_states[i]; 1278 1279 return add_all_planes_for_stream(dc, stream, &set, 1, context); 1280 } 1281 1282 1283 1284 static bool is_timing_changed(struct dc_stream_state *cur_stream, 1285 struct dc_stream_state *new_stream) 1286 { 1287 if (cur_stream == NULL) 1288 return true; 1289 1290 /* If sink pointer changed, it means this is a hotplug, we should do 1291 * full hw setting. 1292 */ 1293 if (cur_stream->sink != new_stream->sink) 1294 return true; 1295 1296 /* If output color space is changed, need to reprogram info frames */ 1297 if (cur_stream->output_color_space != new_stream->output_color_space) 1298 return true; 1299 1300 return memcmp( 1301 &cur_stream->timing, 1302 &new_stream->timing, 1303 sizeof(struct dc_crtc_timing)) != 0; 1304 } 1305 1306 static bool are_stream_backends_same( 1307 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) 1308 { 1309 if (stream_a == stream_b) 1310 return true; 1311 1312 if (stream_a == NULL || stream_b == NULL) 1313 return false; 1314 1315 if (is_timing_changed(stream_a, stream_b)) 1316 return false; 1317 1318 return true; 1319 } 1320 1321 bool dc_is_stream_unchanged( 1322 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1323 { 1324 1325 if (!are_stream_backends_same(old_stream, stream)) 1326 return false; 1327 1328 return true; 1329 } 1330 1331 bool dc_is_stream_scaling_unchanged( 1332 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1333 { 1334 if (old_stream == stream) 1335 return true; 1336 1337 if (old_stream == NULL || stream == NULL) 1338 return false; 1339 1340 if (memcmp(&old_stream->src, 1341 &stream->src, 1342 sizeof(struct rect)) != 0) 1343 return false; 1344 1345 if (memcmp(&old_stream->dst, 1346 &stream->dst, 1347 sizeof(struct rect)) != 0) 1348 return false; 1349 1350 return true; 1351 } 1352 1353 /* Maximum TMDS single link pixel clock 165MHz */ 1354 #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000 1355 1356 static void update_stream_engine_usage( 1357 struct resource_context *res_ctx, 1358 const struct resource_pool *pool, 1359 struct stream_encoder *stream_enc, 1360 bool acquired) 1361 { 1362 int i; 1363 1364 for (i = 0; i < pool->stream_enc_count; i++) { 1365 if (pool->stream_enc[i] == stream_enc) 1366 res_ctx->is_stream_enc_acquired[i] = acquired; 1367 } 1368 } 1369 1370 /* TODO: release audio object */ 1371 void update_audio_usage( 1372 struct resource_context *res_ctx, 1373 const struct resource_pool *pool, 1374 struct audio *audio, 1375 bool acquired) 1376 { 1377 int i; 1378 for (i = 0; i < pool->audio_count; i++) { 1379 if (pool->audios[i] == audio) 1380 res_ctx->is_audio_acquired[i] = acquired; 1381 } 1382 } 1383 1384 static int acquire_first_free_pipe( 1385 struct resource_context *res_ctx, 1386 const struct resource_pool *pool, 1387 struct dc_stream_state *stream) 1388 { 1389 int i; 1390 1391 for (i = 0; i < pool->pipe_count; i++) { 1392 if (!res_ctx->pipe_ctx[i].stream) { 1393 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 1394 1395 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 1396 pipe_ctx->plane_res.mi = pool->mis[i]; 1397 pipe_ctx->plane_res.hubp = pool->hubps[i]; 1398 pipe_ctx->plane_res.ipp = pool->ipps[i]; 1399 pipe_ctx->plane_res.xfm = pool->transforms[i]; 1400 pipe_ctx->plane_res.dpp = pool->dpps[i]; 1401 pipe_ctx->stream_res.opp = pool->opps[i]; 1402 pipe_ctx->pipe_idx = i; 1403 1404 1405 pipe_ctx->stream = stream; 1406 return i; 1407 } 1408 } 1409 return -1; 1410 } 1411 1412 static struct stream_encoder *find_first_free_match_stream_enc_for_link( 1413 struct resource_context *res_ctx, 1414 const struct resource_pool *pool, 1415 struct dc_stream_state *stream) 1416 { 1417 int i; 1418 int j = -1; 1419 struct dc_link *link = stream->sink->link; 1420 1421 for (i = 0; i < pool->stream_enc_count; i++) { 1422 if (!res_ctx->is_stream_enc_acquired[i] && 1423 pool->stream_enc[i]) { 1424 /* Store first available for MST second display 1425 * in daisy chain use case */ 1426 j = i; 1427 if (pool->stream_enc[i]->id == 1428 link->link_enc->preferred_engine) 1429 return pool->stream_enc[i]; 1430 } 1431 } 1432 1433 /* 1434 * below can happen in cases when stream encoder is acquired: 1435 * 1) for second MST display in chain, so preferred engine already 1436 * acquired; 1437 * 2) for another link, which preferred engine already acquired by any 1438 * MST configuration. 1439 * 1440 * If signal is of DP type and preferred engine not found, return last available 1441 * 1442 * TODO - This is just a patch up and a generic solution is 1443 * required for non DP connectors. 1444 */ 1445 1446 if (j >= 0 && dc_is_dp_signal(stream->signal)) 1447 return pool->stream_enc[j]; 1448 1449 return NULL; 1450 } 1451 1452 static struct audio *find_first_free_audio( 1453 struct resource_context *res_ctx, 1454 const struct resource_pool *pool, 1455 enum engine_id id) 1456 { 1457 int i; 1458 for (i = 0; i < pool->audio_count; i++) { 1459 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { 1460 /*we have enough audio endpoint, find the matching inst*/ 1461 if (id != i) 1462 continue; 1463 1464 return pool->audios[i]; 1465 } 1466 } 1467 /*not found the matching one, first come first serve*/ 1468 for (i = 0; i < pool->audio_count; i++) { 1469 if (res_ctx->is_audio_acquired[i] == false) { 1470 return pool->audios[i]; 1471 } 1472 } 1473 return 0; 1474 } 1475 1476 bool resource_is_stream_unchanged( 1477 struct dc_state *old_context, struct dc_stream_state *stream) 1478 { 1479 int i; 1480 1481 for (i = 0; i < old_context->stream_count; i++) { 1482 struct dc_stream_state *old_stream = old_context->streams[i]; 1483 1484 if (are_stream_backends_same(old_stream, stream)) 1485 return true; 1486 } 1487 1488 return false; 1489 } 1490 1491 enum dc_status dc_add_stream_to_ctx( 1492 struct dc *dc, 1493 struct dc_state *new_ctx, 1494 struct dc_stream_state *stream) 1495 { 1496 struct dc_context *dc_ctx = dc->ctx; 1497 enum dc_status res; 1498 1499 if (new_ctx->stream_count >= dc->res_pool->pipe_count) { 1500 DC_ERROR("Max streams reached, can add stream %p !\n", stream); 1501 return DC_ERROR_UNEXPECTED; 1502 } 1503 1504 new_ctx->streams[new_ctx->stream_count] = stream; 1505 dc_stream_retain(stream); 1506 new_ctx->stream_count++; 1507 1508 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); 1509 if (res != DC_OK) 1510 DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res); 1511 1512 return res; 1513 } 1514 1515 enum dc_status dc_remove_stream_from_ctx( 1516 struct dc *dc, 1517 struct dc_state *new_ctx, 1518 struct dc_stream_state *stream) 1519 { 1520 int i; 1521 struct dc_context *dc_ctx = dc->ctx; 1522 struct pipe_ctx *del_pipe = NULL; 1523 1524 /* Release primary pipe */ 1525 for (i = 0; i < MAX_PIPES; i++) { 1526 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream && 1527 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { 1528 del_pipe = &new_ctx->res_ctx.pipe_ctx[i]; 1529 1530 ASSERT(del_pipe->stream_res.stream_enc); 1531 update_stream_engine_usage( 1532 &new_ctx->res_ctx, 1533 dc->res_pool, 1534 del_pipe->stream_res.stream_enc, 1535 false); 1536 1537 if (del_pipe->stream_res.audio) 1538 update_audio_usage( 1539 &new_ctx->res_ctx, 1540 dc->res_pool, 1541 del_pipe->stream_res.audio, 1542 false); 1543 1544 resource_unreference_clock_source(&new_ctx->res_ctx, 1545 dc->res_pool, 1546 del_pipe->clock_source); 1547 1548 memset(del_pipe, 0, sizeof(*del_pipe)); 1549 1550 break; 1551 } 1552 } 1553 1554 if (!del_pipe) { 1555 DC_ERROR("Pipe not found for stream %p !\n", stream); 1556 return DC_ERROR_UNEXPECTED; 1557 } 1558 1559 for (i = 0; i < new_ctx->stream_count; i++) 1560 if (new_ctx->streams[i] == stream) 1561 break; 1562 1563 if (new_ctx->streams[i] != stream) { 1564 DC_ERROR("Context doesn't have stream %p !\n", stream); 1565 return DC_ERROR_UNEXPECTED; 1566 } 1567 1568 dc_stream_release(new_ctx->streams[i]); 1569 new_ctx->stream_count--; 1570 1571 /* Trim back arrays */ 1572 for (; i < new_ctx->stream_count; i++) { 1573 new_ctx->streams[i] = new_ctx->streams[i + 1]; 1574 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; 1575 } 1576 1577 new_ctx->streams[new_ctx->stream_count] = NULL; 1578 memset( 1579 &new_ctx->stream_status[new_ctx->stream_count], 1580 0, 1581 sizeof(new_ctx->stream_status[0])); 1582 1583 return DC_OK; 1584 } 1585 1586 static void copy_pipe_ctx( 1587 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) 1588 { 1589 struct dc_plane_state *plane_state = to_pipe_ctx->plane_state; 1590 struct dc_stream_state *stream = to_pipe_ctx->stream; 1591 1592 *to_pipe_ctx = *from_pipe_ctx; 1593 to_pipe_ctx->stream = stream; 1594 if (plane_state != NULL) 1595 to_pipe_ctx->plane_state = plane_state; 1596 } 1597 1598 static struct dc_stream_state *find_pll_sharable_stream( 1599 struct dc_stream_state *stream_needs_pll, 1600 struct dc_state *context) 1601 { 1602 int i; 1603 1604 for (i = 0; i < context->stream_count; i++) { 1605 struct dc_stream_state *stream_has_pll = context->streams[i]; 1606 1607 /* We are looking for non dp, non virtual stream */ 1608 if (resource_are_streams_timing_synchronizable( 1609 stream_needs_pll, stream_has_pll) 1610 && !dc_is_dp_signal(stream_has_pll->signal) 1611 && stream_has_pll->sink->link->connector_signal 1612 != SIGNAL_TYPE_VIRTUAL) 1613 return stream_has_pll; 1614 1615 } 1616 1617 return NULL; 1618 } 1619 1620 static int get_norm_pix_clk(const struct dc_crtc_timing *timing) 1621 { 1622 uint32_t pix_clk = timing->pix_clk_khz; 1623 uint32_t normalized_pix_clk = pix_clk; 1624 1625 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 1626 pix_clk /= 2; 1627 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 1628 switch (timing->display_color_depth) { 1629 case COLOR_DEPTH_888: 1630 normalized_pix_clk = pix_clk; 1631 break; 1632 case COLOR_DEPTH_101010: 1633 normalized_pix_clk = (pix_clk * 30) / 24; 1634 break; 1635 case COLOR_DEPTH_121212: 1636 normalized_pix_clk = (pix_clk * 36) / 24; 1637 break; 1638 case COLOR_DEPTH_161616: 1639 normalized_pix_clk = (pix_clk * 48) / 24; 1640 break; 1641 default: 1642 ASSERT(0); 1643 break; 1644 } 1645 } 1646 return normalized_pix_clk; 1647 } 1648 1649 static void calculate_phy_pix_clks(struct dc_stream_state *stream) 1650 { 1651 /* update actual pixel clock on all streams */ 1652 if (dc_is_hdmi_signal(stream->signal)) 1653 stream->phy_pix_clk = get_norm_pix_clk( 1654 &stream->timing); 1655 else 1656 stream->phy_pix_clk = 1657 stream->timing.pix_clk_khz; 1658 } 1659 1660 enum dc_status resource_map_pool_resources( 1661 const struct dc *dc, 1662 struct dc_state *context, 1663 struct dc_stream_state *stream) 1664 { 1665 const struct resource_pool *pool = dc->res_pool; 1666 int i; 1667 struct dc_context *dc_ctx = dc->ctx; 1668 struct pipe_ctx *pipe_ctx = NULL; 1669 int pipe_idx = -1; 1670 1671 /* TODO Check if this is needed */ 1672 /*if (!resource_is_stream_unchanged(old_context, stream)) { 1673 if (stream != NULL && old_context->streams[i] != NULL) { 1674 stream->bit_depth_params = 1675 old_context->streams[i]->bit_depth_params; 1676 stream->clamping = old_context->streams[i]->clamping; 1677 continue; 1678 } 1679 } 1680 */ 1681 1682 /* acquire new resources */ 1683 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); 1684 1685 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 1686 if (pipe_idx < 0) 1687 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 1688 #endif 1689 1690 if (pipe_idx < 0) 1691 return DC_NO_CONTROLLER_RESOURCE; 1692 1693 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 1694 1695 pipe_ctx->stream_res.stream_enc = 1696 find_first_free_match_stream_enc_for_link( 1697 &context->res_ctx, pool, stream); 1698 1699 if (!pipe_ctx->stream_res.stream_enc) 1700 return DC_NO_STREAM_ENG_RESOURCE; 1701 1702 update_stream_engine_usage( 1703 &context->res_ctx, pool, 1704 pipe_ctx->stream_res.stream_enc, 1705 true); 1706 1707 /* TODO: Add check if ASIC support and EDID audio */ 1708 if (!stream->sink->converter_disable_audio && 1709 dc_is_audio_capable_signal(pipe_ctx->stream->signal) && 1710 stream->audio_info.mode_count) { 1711 pipe_ctx->stream_res.audio = find_first_free_audio( 1712 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id); 1713 1714 /* 1715 * Audio assigned in order first come first get. 1716 * There are asics which has number of audio 1717 * resources less then number of pipes 1718 */ 1719 if (pipe_ctx->stream_res.audio) 1720 update_audio_usage(&context->res_ctx, pool, 1721 pipe_ctx->stream_res.audio, true); 1722 } 1723 1724 for (i = 0; i < context->stream_count; i++) 1725 if (context->streams[i] == stream) { 1726 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; 1727 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id; 1728 return DC_OK; 1729 } 1730 1731 DC_ERROR("Stream %p not found in new ctx!\n", stream); 1732 return DC_ERROR_UNEXPECTED; 1733 } 1734 1735 /* first stream in the context is used to populate the rest */ 1736 void validate_guaranteed_copy_streams( 1737 struct dc_state *context, 1738 int max_streams) 1739 { 1740 int i; 1741 1742 for (i = 1; i < max_streams; i++) { 1743 context->streams[i] = context->streams[0]; 1744 1745 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0], 1746 &context->res_ctx.pipe_ctx[i]); 1747 context->res_ctx.pipe_ctx[i].stream = 1748 context->res_ctx.pipe_ctx[0].stream; 1749 1750 dc_stream_retain(context->streams[i]); 1751 context->stream_count++; 1752 } 1753 } 1754 1755 void dc_resource_state_copy_construct_current( 1756 const struct dc *dc, 1757 struct dc_state *dst_ctx) 1758 { 1759 dc_resource_state_copy_construct(dc->current_state, dst_ctx); 1760 } 1761 1762 1763 void dc_resource_state_construct( 1764 const struct dc *dc, 1765 struct dc_state *dst_ctx) 1766 { 1767 dst_ctx->dis_clk = dc->res_pool->display_clock; 1768 } 1769 1770 enum dc_status dc_validate_global_state( 1771 struct dc *dc, 1772 struct dc_state *new_ctx) 1773 { 1774 enum dc_status result = DC_ERROR_UNEXPECTED; 1775 int i, j; 1776 1777 if (!new_ctx) 1778 return DC_ERROR_UNEXPECTED; 1779 1780 if (dc->res_pool->funcs->validate_global) { 1781 result = dc->res_pool->funcs->validate_global(dc, new_ctx); 1782 if (result != DC_OK) 1783 return result; 1784 } 1785 1786 for (i = 0; i < new_ctx->stream_count; i++) { 1787 struct dc_stream_state *stream = new_ctx->streams[i]; 1788 1789 for (j = 0; j < dc->res_pool->pipe_count; j++) { 1790 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; 1791 1792 if (pipe_ctx->stream != stream) 1793 continue; 1794 1795 /* Switch to dp clock source only if there is 1796 * no non dp stream that shares the same timing 1797 * with the dp stream. 1798 */ 1799 if (dc_is_dp_signal(pipe_ctx->stream->signal) && 1800 !find_pll_sharable_stream(stream, new_ctx)) { 1801 1802 resource_unreference_clock_source( 1803 &new_ctx->res_ctx, 1804 dc->res_pool, 1805 pipe_ctx->clock_source); 1806 1807 pipe_ctx->clock_source = dc->res_pool->dp_clock_source; 1808 resource_reference_clock_source( 1809 &new_ctx->res_ctx, 1810 dc->res_pool, 1811 pipe_ctx->clock_source); 1812 } 1813 } 1814 } 1815 1816 result = resource_build_scaling_params_for_context(dc, new_ctx); 1817 1818 if (result == DC_OK) 1819 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx)) 1820 result = DC_FAIL_BANDWIDTH_VALIDATE; 1821 1822 return result; 1823 } 1824 1825 static void patch_gamut_packet_checksum( 1826 struct encoder_info_packet *gamut_packet) 1827 { 1828 /* For gamut we recalc checksum */ 1829 if (gamut_packet->valid) { 1830 uint8_t chk_sum = 0; 1831 uint8_t *ptr; 1832 uint8_t i; 1833 1834 /*start of the Gamut data. */ 1835 ptr = &gamut_packet->sb[3]; 1836 1837 for (i = 0; i <= gamut_packet->sb[1]; i++) 1838 chk_sum += ptr[i]; 1839 1840 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); 1841 } 1842 } 1843 1844 static void set_avi_info_frame( 1845 struct encoder_info_packet *info_packet, 1846 struct pipe_ctx *pipe_ctx) 1847 { 1848 struct dc_stream_state *stream = pipe_ctx->stream; 1849 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; 1850 struct info_frame info_frame = { {0} }; 1851 uint32_t pixel_encoding = 0; 1852 enum scanning_type scan_type = SCANNING_TYPE_NODATA; 1853 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA; 1854 bool itc = false; 1855 uint8_t itc_value = 0; 1856 uint8_t cn0_cn1 = 0; 1857 unsigned int cn0_cn1_value = 0; 1858 uint8_t *check_sum = NULL; 1859 uint8_t byte_index = 0; 1860 union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi; 1861 union display_content_support support = {0}; 1862 unsigned int vic = pipe_ctx->stream->timing.vic; 1863 enum dc_timing_3d_format format; 1864 1865 color_space = pipe_ctx->stream->output_color_space; 1866 if (color_space == COLOR_SPACE_UNKNOWN) 1867 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? 1868 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; 1869 1870 /* Initialize header */ 1871 hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI; 1872 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall 1873 * not be used in HDMI 2.0 (Section 10.1) */ 1874 hdmi_info->bits.header.version = 2; 1875 hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE; 1876 1877 /* 1878 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built 1879 * according to HDMI 2.0 spec (Section 10.1) 1880 */ 1881 1882 switch (stream->timing.pixel_encoding) { 1883 case PIXEL_ENCODING_YCBCR422: 1884 pixel_encoding = 1; 1885 break; 1886 1887 case PIXEL_ENCODING_YCBCR444: 1888 pixel_encoding = 2; 1889 break; 1890 case PIXEL_ENCODING_YCBCR420: 1891 pixel_encoding = 3; 1892 break; 1893 1894 case PIXEL_ENCODING_RGB: 1895 default: 1896 pixel_encoding = 0; 1897 } 1898 1899 /* Y0_Y1_Y2 : The pixel encoding */ 1900 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ 1901 hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding; 1902 1903 /* A0 = 1 Active Format Information valid */ 1904 hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID; 1905 1906 /* B0, B1 = 3; Bar info data is valid */ 1907 hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID; 1908 1909 hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM; 1910 1911 /* S0, S1 : Underscan / Overscan */ 1912 /* TODO: un-hardcode scan type */ 1913 scan_type = SCANNING_TYPE_UNDERSCAN; 1914 hdmi_info->bits.S0_S1 = scan_type; 1915 1916 /* C0, C1 : Colorimetry */ 1917 if (color_space == COLOR_SPACE_YCBCR709 || 1918 color_space == COLOR_SPACE_YCBCR709_LIMITED) 1919 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709; 1920 else if (color_space == COLOR_SPACE_YCBCR601 || 1921 color_space == COLOR_SPACE_YCBCR601_LIMITED) 1922 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601; 1923 else { 1924 hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA; 1925 } 1926 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE || 1927 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE || 1928 color_space == COLOR_SPACE_2020_YCBCR) { 1929 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR; 1930 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED; 1931 } else if (color_space == COLOR_SPACE_ADOBERGB) { 1932 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB; 1933 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED; 1934 } 1935 1936 /* TODO: un-hardcode aspect ratio */ 1937 aspect = stream->timing.aspect_ratio; 1938 1939 switch (aspect) { 1940 case ASPECT_RATIO_4_3: 1941 case ASPECT_RATIO_16_9: 1942 hdmi_info->bits.M0_M1 = aspect; 1943 break; 1944 1945 case ASPECT_RATIO_NO_DATA: 1946 case ASPECT_RATIO_64_27: 1947 case ASPECT_RATIO_256_135: 1948 default: 1949 hdmi_info->bits.M0_M1 = 0; 1950 } 1951 1952 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */ 1953 hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE; 1954 1955 /* TODO: un-hardcode cn0_cn1 and itc */ 1956 1957 cn0_cn1 = 0; 1958 cn0_cn1_value = 0; 1959 1960 itc = true; 1961 itc_value = 1; 1962 1963 support = stream->sink->edid_caps.content_support; 1964 1965 if (itc) { 1966 if (!support.bits.valid_content_type) { 1967 cn0_cn1_value = 0; 1968 } else { 1969 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) { 1970 if (support.bits.graphics_content == 1) { 1971 cn0_cn1_value = 0; 1972 } 1973 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) { 1974 if (support.bits.photo_content == 1) { 1975 cn0_cn1_value = 1; 1976 } else { 1977 cn0_cn1_value = 0; 1978 itc_value = 0; 1979 } 1980 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) { 1981 if (support.bits.cinema_content == 1) { 1982 cn0_cn1_value = 2; 1983 } else { 1984 cn0_cn1_value = 0; 1985 itc_value = 0; 1986 } 1987 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) { 1988 if (support.bits.game_content == 1) { 1989 cn0_cn1_value = 3; 1990 } else { 1991 cn0_cn1_value = 0; 1992 itc_value = 0; 1993 } 1994 } 1995 } 1996 hdmi_info->bits.CN0_CN1 = cn0_cn1_value; 1997 hdmi_info->bits.ITC = itc_value; 1998 } 1999 2000 /* TODO : We should handle YCC quantization */ 2001 /* but we do not have matrix calculation */ 2002 if (stream->sink->edid_caps.qs_bit == 1 && 2003 stream->sink->edid_caps.qy_bit == 1) { 2004 if (color_space == COLOR_SPACE_SRGB || 2005 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) { 2006 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; 2007 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE; 2008 } else if (color_space == COLOR_SPACE_SRGB_LIMITED || 2009 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) { 2010 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE; 2011 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2012 } else { 2013 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2014 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2015 } 2016 } else { 2017 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2018 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2019 } 2020 2021 ///VIC 2022 format = stream->timing.timing_3d_format; 2023 /*todo, add 3DStereo support*/ 2024 if (format != TIMING_3D_FORMAT_NONE) { 2025 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled 2026 switch (pipe_ctx->stream->timing.hdmi_vic) { 2027 case 1: 2028 vic = 95; 2029 break; 2030 case 2: 2031 vic = 94; 2032 break; 2033 case 3: 2034 vic = 93; 2035 break; 2036 case 4: 2037 vic = 98; 2038 break; 2039 default: 2040 break; 2041 } 2042 } 2043 hdmi_info->bits.VIC0_VIC7 = vic; 2044 2045 /* pixel repetition 2046 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel 2047 * repetition start from 1 */ 2048 hdmi_info->bits.PR0_PR3 = 0; 2049 2050 /* Bar Info 2051 * barTop: Line Number of End of Top Bar. 2052 * barBottom: Line Number of Start of Bottom Bar. 2053 * barLeft: Pixel Number of End of Left Bar. 2054 * barRight: Pixel Number of Start of Right Bar. */ 2055 hdmi_info->bits.bar_top = stream->timing.v_border_top; 2056 hdmi_info->bits.bar_bottom = (stream->timing.v_total 2057 - stream->timing.v_border_bottom + 1); 2058 hdmi_info->bits.bar_left = stream->timing.h_border_left; 2059 hdmi_info->bits.bar_right = (stream->timing.h_total 2060 - stream->timing.h_border_right + 1); 2061 2062 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ 2063 check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0]; 2064 2065 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2; 2066 2067 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++) 2068 *check_sum += hdmi_info->packet_raw_data.sb[byte_index]; 2069 2070 /* one byte complement */ 2071 *check_sum = (uint8_t) (0x100 - *check_sum); 2072 2073 /* Store in hw_path_mode */ 2074 info_packet->hb0 = hdmi_info->packet_raw_data.hb0; 2075 info_packet->hb1 = hdmi_info->packet_raw_data.hb1; 2076 info_packet->hb2 = hdmi_info->packet_raw_data.hb2; 2077 2078 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet. 2079 info_packet_hdmi.packet_raw_data.sb); byte_index++) 2080 info_packet->sb[byte_index] = info_frame.avi_info_packet. 2081 info_packet_hdmi.packet_raw_data.sb[byte_index]; 2082 2083 info_packet->valid = true; 2084 } 2085 2086 static void set_vendor_info_packet( 2087 struct encoder_info_packet *info_packet, 2088 struct dc_stream_state *stream) 2089 { 2090 uint32_t length = 0; 2091 bool hdmi_vic_mode = false; 2092 uint8_t checksum = 0; 2093 uint32_t i = 0; 2094 enum dc_timing_3d_format format; 2095 // Can be different depending on packet content /*todo*/ 2096 // unsigned int length = pPathMode->dolbyVision ? 24 : 5; 2097 2098 info_packet->valid = false; 2099 2100 format = stream->timing.timing_3d_format; 2101 if (stream->view_format == VIEW_3D_FORMAT_NONE) 2102 format = TIMING_3D_FORMAT_NONE; 2103 2104 /* Can be different depending on packet content */ 2105 length = 5; 2106 2107 if (stream->timing.hdmi_vic != 0 2108 && stream->timing.h_total >= 3840 2109 && stream->timing.v_total >= 2160) 2110 hdmi_vic_mode = true; 2111 2112 /* According to HDMI 1.4a CTS, VSIF should be sent 2113 * for both 3D stereo and HDMI VIC modes. 2114 * For all other modes, there is no VSIF sent. */ 2115 2116 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode) 2117 return; 2118 2119 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */ 2120 info_packet->sb[1] = 0x03; 2121 info_packet->sb[2] = 0x0C; 2122 info_packet->sb[3] = 0x00; 2123 2124 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format. 2125 * The value for HDMI_Video_Format are: 2126 * 0x0 (0b000) - No additional HDMI video format is presented in this 2127 * packet 2128 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC 2129 * parameter follows 2130 * 0x2 (0b010) - 3D format indication present. 3D_Structure and 2131 * potentially 3D_Ext_Data follows 2132 * 0x3..0x7 (0b011..0b111) - reserved for future use */ 2133 if (format != TIMING_3D_FORMAT_NONE) 2134 info_packet->sb[4] = (2 << 5); 2135 else if (hdmi_vic_mode) 2136 info_packet->sb[4] = (1 << 5); 2137 2138 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2): 2139 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure. 2140 * The value for 3D_Structure are: 2141 * 0x0 - Frame Packing 2142 * 0x1 - Field Alternative 2143 * 0x2 - Line Alternative 2144 * 0x3 - Side-by-Side (full) 2145 * 0x4 - L + depth 2146 * 0x5 - L + depth + graphics + graphics-depth 2147 * 0x6 - Top-and-Bottom 2148 * 0x7 - Reserved for future use 2149 * 0x8 - Side-by-Side (Half) 2150 * 0x9..0xE - Reserved for future use 2151 * 0xF - Not used */ 2152 switch (format) { 2153 case TIMING_3D_FORMAT_HW_FRAME_PACKING: 2154 case TIMING_3D_FORMAT_SW_FRAME_PACKING: 2155 info_packet->sb[5] = (0x0 << 4); 2156 break; 2157 2158 case TIMING_3D_FORMAT_SIDE_BY_SIDE: 2159 case TIMING_3D_FORMAT_SBS_SW_PACKED: 2160 info_packet->sb[5] = (0x8 << 4); 2161 length = 6; 2162 break; 2163 2164 case TIMING_3D_FORMAT_TOP_AND_BOTTOM: 2165 case TIMING_3D_FORMAT_TB_SW_PACKED: 2166 info_packet->sb[5] = (0x6 << 4); 2167 break; 2168 2169 default: 2170 break; 2171 } 2172 2173 /*PB5: If PB4 is set to 0x1 (extended resolution format) 2174 * fill PB5 with the correct HDMI VIC code */ 2175 if (hdmi_vic_mode) 2176 info_packet->sb[5] = stream->timing.hdmi_vic; 2177 2178 /* Header */ 2179 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */ 2180 info_packet->hb1 = 0x01; /* Version */ 2181 2182 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */ 2183 info_packet->hb2 = (uint8_t) (length); 2184 2185 /* Calculate checksum */ 2186 checksum = 0; 2187 checksum += info_packet->hb0; 2188 checksum += info_packet->hb1; 2189 checksum += info_packet->hb2; 2190 2191 for (i = 1; i <= length; i++) 2192 checksum += info_packet->sb[i]; 2193 2194 info_packet->sb[0] = (uint8_t) (0x100 - checksum); 2195 2196 info_packet->valid = true; 2197 } 2198 2199 static void set_spd_info_packet( 2200 struct encoder_info_packet *info_packet, 2201 struct dc_stream_state *stream) 2202 { 2203 /* SPD info packet for FreeSync */ 2204 2205 unsigned char checksum = 0; 2206 unsigned int idx, payload_size = 0; 2207 2208 /* Check if Freesync is supported. Return if false. If true, 2209 * set the corresponding bit in the info packet 2210 */ 2211 if (stream->freesync_ctx.supported == false) 2212 return; 2213 2214 if (dc_is_hdmi_signal(stream->signal)) { 2215 2216 /* HEADER */ 2217 2218 /* HB0 = Packet Type = 0x83 (Source Product 2219 * Descriptor InfoFrame) 2220 */ 2221 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD; 2222 2223 /* HB1 = Version = 0x01 */ 2224 info_packet->hb1 = 0x01; 2225 2226 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */ 2227 info_packet->hb2 = 0x08; 2228 2229 payload_size = 0x08; 2230 2231 } else if (dc_is_dp_signal(stream->signal)) { 2232 2233 /* HEADER */ 2234 2235 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero 2236 * when used to associate audio related info packets 2237 */ 2238 info_packet->hb0 = 0x00; 2239 2240 /* HB1 = Packet Type = 0x83 (Source Product 2241 * Descriptor InfoFrame) 2242 */ 2243 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD; 2244 2245 /* HB2 = [Bits 7:0 = Least significant eight bits - 2246 * For INFOFRAME, the value must be 1Bh] 2247 */ 2248 info_packet->hb2 = 0x1B; 2249 2250 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1] 2251 * [Bits 1:0 = Most significant two bits = 0x00] 2252 */ 2253 info_packet->hb3 = 0x04; 2254 2255 payload_size = 0x1B; 2256 } 2257 2258 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */ 2259 info_packet->sb[1] = 0x1A; 2260 2261 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */ 2262 info_packet->sb[2] = 0x00; 2263 2264 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */ 2265 info_packet->sb[3] = 0x00; 2266 2267 /* PB4 = Reserved */ 2268 info_packet->sb[4] = 0x00; 2269 2270 /* PB5 = Reserved */ 2271 info_packet->sb[5] = 0x00; 2272 2273 /* PB6 = [Bits 7:3 = Reserved] */ 2274 info_packet->sb[6] = 0x00; 2275 2276 if (stream->freesync_ctx.supported == true) 2277 /* PB6 = [Bit 0 = FreeSync Supported] */ 2278 info_packet->sb[6] |= 0x01; 2279 2280 if (stream->freesync_ctx.enabled == true) 2281 /* PB6 = [Bit 1 = FreeSync Enabled] */ 2282 info_packet->sb[6] |= 0x02; 2283 2284 if (stream->freesync_ctx.active == true) 2285 /* PB6 = [Bit 2 = FreeSync Active] */ 2286 info_packet->sb[6] |= 0x04; 2287 2288 /* PB7 = FreeSync Minimum refresh rate (Hz) */ 2289 info_packet->sb[7] = (unsigned char) (stream->freesync_ctx. 2290 min_refresh_in_micro_hz / 1000000); 2291 2292 /* PB8 = FreeSync Maximum refresh rate (Hz) 2293 * 2294 * Note: We do not use the maximum capable refresh rate 2295 * of the panel, because we should never go above the field 2296 * rate of the mode timing set. 2297 */ 2298 info_packet->sb[8] = (unsigned char) (stream->freesync_ctx. 2299 nominal_refresh_in_micro_hz / 1000000); 2300 2301 /* PB9 - PB27 = Reserved */ 2302 for (idx = 9; idx <= 27; idx++) 2303 info_packet->sb[idx] = 0x00; 2304 2305 /* Calculate checksum */ 2306 checksum += info_packet->hb0; 2307 checksum += info_packet->hb1; 2308 checksum += info_packet->hb2; 2309 checksum += info_packet->hb3; 2310 2311 for (idx = 1; idx <= payload_size; idx++) 2312 checksum += info_packet->sb[idx]; 2313 2314 /* PB0 = Checksum (one byte complement) */ 2315 info_packet->sb[0] = (unsigned char) (0x100 - checksum); 2316 2317 info_packet->valid = true; 2318 } 2319 2320 static void set_hdr_static_info_packet( 2321 struct encoder_info_packet *info_packet, 2322 struct dc_plane_state *plane_state, 2323 struct dc_stream_state *stream) 2324 { 2325 uint16_t i = 0; 2326 enum signal_type signal = stream->signal; 2327 struct dc_hdr_static_metadata hdr_metadata; 2328 uint32_t data; 2329 2330 if (!plane_state) 2331 return; 2332 2333 hdr_metadata = plane_state->hdr_static_ctx; 2334 2335 if (!hdr_metadata.hdr_supported) 2336 return; 2337 2338 if (dc_is_hdmi_signal(signal)) { 2339 info_packet->valid = true; 2340 2341 info_packet->hb0 = 0x87; 2342 info_packet->hb1 = 0x01; 2343 info_packet->hb2 = 0x1A; 2344 i = 1; 2345 } else if (dc_is_dp_signal(signal)) { 2346 info_packet->valid = true; 2347 2348 info_packet->hb0 = 0x00; 2349 info_packet->hb1 = 0x87; 2350 info_packet->hb2 = 0x1D; 2351 info_packet->hb3 = (0x13 << 2); 2352 i = 2; 2353 } 2354 2355 data = hdr_metadata.is_hdr; 2356 info_packet->sb[i++] = data ? 0x02 : 0x00; 2357 info_packet->sb[i++] = 0x00; 2358 2359 data = hdr_metadata.chromaticity_green_x / 2; 2360 info_packet->sb[i++] = data & 0xFF; 2361 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2362 2363 data = hdr_metadata.chromaticity_green_y / 2; 2364 info_packet->sb[i++] = data & 0xFF; 2365 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2366 2367 data = hdr_metadata.chromaticity_blue_x / 2; 2368 info_packet->sb[i++] = data & 0xFF; 2369 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2370 2371 data = hdr_metadata.chromaticity_blue_y / 2; 2372 info_packet->sb[i++] = data & 0xFF; 2373 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2374 2375 data = hdr_metadata.chromaticity_red_x / 2; 2376 info_packet->sb[i++] = data & 0xFF; 2377 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2378 2379 data = hdr_metadata.chromaticity_red_y / 2; 2380 info_packet->sb[i++] = data & 0xFF; 2381 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2382 2383 data = hdr_metadata.chromaticity_white_point_x / 2; 2384 info_packet->sb[i++] = data & 0xFF; 2385 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2386 2387 data = hdr_metadata.chromaticity_white_point_y / 2; 2388 info_packet->sb[i++] = data & 0xFF; 2389 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2390 2391 data = hdr_metadata.max_luminance; 2392 info_packet->sb[i++] = data & 0xFF; 2393 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2394 2395 data = hdr_metadata.min_luminance; 2396 info_packet->sb[i++] = data & 0xFF; 2397 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2398 2399 data = hdr_metadata.maximum_content_light_level; 2400 info_packet->sb[i++] = data & 0xFF; 2401 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2402 2403 data = hdr_metadata.maximum_frame_average_light_level; 2404 info_packet->sb[i++] = data & 0xFF; 2405 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2406 2407 if (dc_is_hdmi_signal(signal)) { 2408 uint32_t checksum = 0; 2409 2410 checksum += info_packet->hb0; 2411 checksum += info_packet->hb1; 2412 checksum += info_packet->hb2; 2413 2414 for (i = 1; i <= info_packet->hb2; i++) 2415 checksum += info_packet->sb[i]; 2416 2417 info_packet->sb[0] = 0x100 - checksum; 2418 } else if (dc_is_dp_signal(signal)) { 2419 info_packet->sb[0] = 0x01; 2420 info_packet->sb[1] = 0x1A; 2421 } 2422 } 2423 2424 static void set_vsc_info_packet( 2425 struct encoder_info_packet *info_packet, 2426 struct dc_stream_state *stream) 2427 { 2428 unsigned int vscPacketRevision = 0; 2429 unsigned int i; 2430 2431 if (stream->sink->link->psr_enabled) { 2432 vscPacketRevision = 2; 2433 } 2434 2435 /* VSC packet not needed based on the features 2436 * supported by this DP display 2437 */ 2438 if (vscPacketRevision == 0) 2439 return; 2440 2441 if (vscPacketRevision == 0x2) { 2442 /* Secondary-data Packet ID = 0*/ 2443 info_packet->hb0 = 0x00; 2444 /* 07h - Packet Type Value indicating Video 2445 * Stream Configuration packet 2446 */ 2447 info_packet->hb1 = 0x07; 2448 /* 02h = VSC SDP supporting 3D stereo and PSR 2449 * (applies to eDP v1.3 or higher). 2450 */ 2451 info_packet->hb2 = 0x02; 2452 /* 08h = VSC packet supporting 3D stereo + PSR 2453 * (HB2 = 02h). 2454 */ 2455 info_packet->hb3 = 0x08; 2456 2457 for (i = 0; i < 28; i++) 2458 info_packet->sb[i] = 0; 2459 2460 info_packet->valid = true; 2461 } 2462 2463 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/ 2464 } 2465 2466 void dc_resource_state_destruct(struct dc_state *context) 2467 { 2468 int i, j; 2469 2470 for (i = 0; i < context->stream_count; i++) { 2471 for (j = 0; j < context->stream_status[i].plane_count; j++) 2472 dc_plane_state_release( 2473 context->stream_status[i].plane_states[j]); 2474 2475 context->stream_status[i].plane_count = 0; 2476 dc_stream_release(context->streams[i]); 2477 context->streams[i] = NULL; 2478 } 2479 } 2480 2481 /* 2482 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced 2483 * by the src_ctx 2484 */ 2485 void dc_resource_state_copy_construct( 2486 const struct dc_state *src_ctx, 2487 struct dc_state *dst_ctx) 2488 { 2489 int i, j; 2490 struct kref refcount = dst_ctx->refcount; 2491 2492 *dst_ctx = *src_ctx; 2493 2494 for (i = 0; i < MAX_PIPES; i++) { 2495 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; 2496 2497 if (cur_pipe->top_pipe) 2498 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; 2499 2500 if (cur_pipe->bottom_pipe) 2501 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; 2502 2503 } 2504 2505 for (i = 0; i < dst_ctx->stream_count; i++) { 2506 dc_stream_retain(dst_ctx->streams[i]); 2507 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) 2508 dc_plane_state_retain( 2509 dst_ctx->stream_status[i].plane_states[j]); 2510 } 2511 2512 /* context refcount should not be overridden */ 2513 dst_ctx->refcount = refcount; 2514 2515 } 2516 2517 struct clock_source *dc_resource_find_first_free_pll( 2518 struct resource_context *res_ctx, 2519 const struct resource_pool *pool) 2520 { 2521 int i; 2522 2523 for (i = 0; i < pool->clk_src_count; ++i) { 2524 if (res_ctx->clock_source_ref_count[i] == 0) 2525 return pool->clock_sources[i]; 2526 } 2527 2528 return NULL; 2529 } 2530 2531 void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 2532 { 2533 enum signal_type signal = SIGNAL_TYPE_NONE; 2534 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; 2535 2536 /* default all packets to invalid */ 2537 info->avi.valid = false; 2538 info->gamut.valid = false; 2539 info->vendor.valid = false; 2540 info->spd.valid = false; 2541 info->hdrsmd.valid = false; 2542 info->vsc.valid = false; 2543 2544 signal = pipe_ctx->stream->signal; 2545 2546 /* HDMi and DP have different info packets*/ 2547 if (dc_is_hdmi_signal(signal)) { 2548 set_avi_info_frame(&info->avi, pipe_ctx); 2549 2550 set_vendor_info_packet(&info->vendor, pipe_ctx->stream); 2551 2552 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2553 2554 set_hdr_static_info_packet(&info->hdrsmd, 2555 pipe_ctx->plane_state, pipe_ctx->stream); 2556 2557 } else if (dc_is_dp_signal(signal)) { 2558 set_vsc_info_packet(&info->vsc, pipe_ctx->stream); 2559 2560 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2561 2562 set_hdr_static_info_packet(&info->hdrsmd, 2563 pipe_ctx->plane_state, pipe_ctx->stream); 2564 } 2565 2566 patch_gamut_packet_checksum(&info->gamut); 2567 } 2568 2569 enum dc_status resource_map_clock_resources( 2570 const struct dc *dc, 2571 struct dc_state *context, 2572 struct dc_stream_state *stream) 2573 { 2574 /* acquire new resources */ 2575 const struct resource_pool *pool = dc->res_pool; 2576 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 2577 &context->res_ctx, stream); 2578 2579 if (!pipe_ctx) 2580 return DC_ERROR_UNEXPECTED; 2581 2582 if (dc_is_dp_signal(pipe_ctx->stream->signal) 2583 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 2584 pipe_ctx->clock_source = pool->dp_clock_source; 2585 else { 2586 pipe_ctx->clock_source = NULL; 2587 2588 if (!dc->config.disable_disp_pll_sharing) 2589 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing( 2590 &context->res_ctx, 2591 pipe_ctx); 2592 2593 if (pipe_ctx->clock_source == NULL) 2594 pipe_ctx->clock_source = 2595 dc_resource_find_first_free_pll( 2596 &context->res_ctx, 2597 pool); 2598 } 2599 2600 if (pipe_ctx->clock_source == NULL) 2601 return DC_NO_CLOCK_SOURCE_RESOURCE; 2602 2603 resource_reference_clock_source( 2604 &context->res_ctx, pool, 2605 pipe_ctx->clock_source); 2606 2607 return DC_OK; 2608 } 2609 2610 /* 2611 * Note: We need to disable output if clock sources change, 2612 * since bios does optimization and doesn't apply if changing 2613 * PHY when not already disabled. 2614 */ 2615 bool pipe_need_reprogram( 2616 struct pipe_ctx *pipe_ctx_old, 2617 struct pipe_ctx *pipe_ctx) 2618 { 2619 if (!pipe_ctx_old->stream) 2620 return false; 2621 2622 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) 2623 return true; 2624 2625 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) 2626 return true; 2627 2628 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) 2629 return true; 2630 2631 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source 2632 && pipe_ctx_old->stream != pipe_ctx->stream) 2633 return true; 2634 2635 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) 2636 return true; 2637 2638 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) 2639 return true; 2640 2641 2642 return false; 2643 } 2644 2645 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 2646 struct bit_depth_reduction_params *fmt_bit_depth) 2647 { 2648 enum dc_dither_option option = stream->dither_option; 2649 enum dc_pixel_encoding pixel_encoding = 2650 stream->timing.pixel_encoding; 2651 2652 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); 2653 2654 if (option == DITHER_OPTION_DEFAULT) { 2655 switch (stream->timing.display_color_depth) { 2656 case COLOR_DEPTH_666: 2657 option = DITHER_OPTION_SPATIAL6; 2658 break; 2659 case COLOR_DEPTH_888: 2660 option = DITHER_OPTION_SPATIAL8; 2661 break; 2662 case COLOR_DEPTH_101010: 2663 option = DITHER_OPTION_SPATIAL10; 2664 break; 2665 default: 2666 option = DITHER_OPTION_DISABLE; 2667 } 2668 } 2669 2670 if (option == DITHER_OPTION_DISABLE) 2671 return; 2672 2673 if (option == DITHER_OPTION_TRUN6) { 2674 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2675 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; 2676 } else if (option == DITHER_OPTION_TRUN8 || 2677 option == DITHER_OPTION_TRUN8_SPATIAL6 || 2678 option == DITHER_OPTION_TRUN8_FM6) { 2679 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2680 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; 2681 } else if (option == DITHER_OPTION_TRUN10 || 2682 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2683 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2684 option == DITHER_OPTION_TRUN10_FM8 || 2685 option == DITHER_OPTION_TRUN10_FM6 || 2686 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2687 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2688 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2689 } 2690 2691 /* special case - Formatter can only reduce by 4 bits at most. 2692 * When reducing from 12 to 6 bits, 2693 * HW recommends we use trunc with round mode 2694 * (if we did nothing, trunc to 10 bits would be used) 2695 * note that any 12->10 bit reduction is ignored prior to DCE8, 2696 * as the input was 10 bits. 2697 */ 2698 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2699 option == DITHER_OPTION_SPATIAL6 || 2700 option == DITHER_OPTION_FM6) { 2701 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2702 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2703 fmt_bit_depth->flags.TRUNCATE_MODE = 1; 2704 } 2705 2706 /* spatial dither 2707 * note that spatial modes 1-3 are never used 2708 */ 2709 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2710 option == DITHER_OPTION_SPATIAL6 || 2711 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2712 option == DITHER_OPTION_TRUN8_SPATIAL6) { 2713 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2714 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; 2715 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2716 fmt_bit_depth->flags.RGB_RANDOM = 2717 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2718 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || 2719 option == DITHER_OPTION_SPATIAL8 || 2720 option == DITHER_OPTION_SPATIAL8_FM6 || 2721 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2722 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2723 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2724 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; 2725 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2726 fmt_bit_depth->flags.RGB_RANDOM = 2727 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2728 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || 2729 option == DITHER_OPTION_SPATIAL10 || 2730 option == DITHER_OPTION_SPATIAL10_FM8 || 2731 option == DITHER_OPTION_SPATIAL10_FM6) { 2732 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2733 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; 2734 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2735 fmt_bit_depth->flags.RGB_RANDOM = 2736 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2737 } 2738 2739 if (option == DITHER_OPTION_SPATIAL6 || 2740 option == DITHER_OPTION_SPATIAL8 || 2741 option == DITHER_OPTION_SPATIAL10) { 2742 fmt_bit_depth->flags.FRAME_RANDOM = 0; 2743 } else { 2744 fmt_bit_depth->flags.FRAME_RANDOM = 1; 2745 } 2746 2747 ////////////////////// 2748 //// temporal dither 2749 ////////////////////// 2750 if (option == DITHER_OPTION_FM6 || 2751 option == DITHER_OPTION_SPATIAL8_FM6 || 2752 option == DITHER_OPTION_SPATIAL10_FM6 || 2753 option == DITHER_OPTION_TRUN10_FM6 || 2754 option == DITHER_OPTION_TRUN8_FM6 || 2755 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2756 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2757 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; 2758 } else if (option == DITHER_OPTION_FM8 || 2759 option == DITHER_OPTION_SPATIAL10_FM8 || 2760 option == DITHER_OPTION_TRUN10_FM8) { 2761 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2762 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; 2763 } else if (option == DITHER_OPTION_FM10) { 2764 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2765 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; 2766 } 2767 2768 fmt_bit_depth->pixel_encoding = pixel_encoding; 2769 } 2770 2771 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) 2772 { 2773 struct dc *core_dc = dc; 2774 struct dc_link *link = stream->sink->link; 2775 struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; 2776 enum dc_status res = DC_OK; 2777 2778 calculate_phy_pix_clks(stream); 2779 2780 if (!tg->funcs->validate_timing(tg, &stream->timing)) 2781 res = DC_FAIL_CONTROLLER_VALIDATE; 2782 2783 if (res == DC_OK) 2784 if (!link->link_enc->funcs->validate_output_with_stream( 2785 link->link_enc, stream)) 2786 res = DC_FAIL_ENC_VALIDATE; 2787 2788 /* TODO: validate audio ASIC caps, encoder */ 2789 2790 if (res == DC_OK) 2791 res = dc_link_validate_mode_timing(stream, 2792 link, 2793 &stream->timing); 2794 2795 return res; 2796 } 2797 2798 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) 2799 { 2800 enum dc_status res = DC_OK; 2801 2802 /* TODO For now validates pixel format only */ 2803 if (dc->res_pool->funcs->validate_plane) 2804 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps); 2805 2806 return res; 2807 } 2808