1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "link_encoder.h" 33 #include "stream_encoder.h" 34 #include "opp.h" 35 #include "timing_generator.h" 36 #include "transform.h" 37 #include "dccg.h" 38 #include "dchubbub.h" 39 #include "dpp.h" 40 #include "core_types.h" 41 #include "set_mode_types.h" 42 #include "virtual/virtual_stream_encoder.h" 43 #include "dpcd_defs.h" 44 #include "link_enc_cfg.h" 45 #include "dc_link_dp.h" 46 47 #if defined(CONFIG_DRM_AMD_DC_SI) 48 #include "dce60/dce60_resource.h" 49 #endif 50 #include "dce80/dce80_resource.h" 51 #include "dce100/dce100_resource.h" 52 #include "dce110/dce110_resource.h" 53 #include "dce112/dce112_resource.h" 54 #include "dce120/dce120_resource.h" 55 #if defined(CONFIG_DRM_AMD_DC_DCN) 56 #include "dcn10/dcn10_resource.h" 57 #include "dcn20/dcn20_resource.h" 58 #include "dcn21/dcn21_resource.h" 59 #include "dcn201/dcn201_resource.h" 60 #include "dcn30/dcn30_resource.h" 61 #include "dcn301/dcn301_resource.h" 62 #include "dcn302/dcn302_resource.h" 63 #include "dcn303/dcn303_resource.h" 64 #include "dcn31/dcn31_resource.h" 65 #endif 66 67 #define DC_LOGGER_INIT(logger) 68 69 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 70 { 71 enum dce_version dc_version = DCE_VERSION_UNKNOWN; 72 switch (asic_id.chip_family) { 73 74 #if defined(CONFIG_DRM_AMD_DC_SI) 75 case FAMILY_SI: 76 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) || 77 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) || 78 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev)) 79 dc_version = DCE_VERSION_6_0; 80 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev)) 81 dc_version = DCE_VERSION_6_4; 82 else 83 dc_version = DCE_VERSION_6_1; 84 break; 85 #endif 86 case FAMILY_CI: 87 dc_version = DCE_VERSION_8_0; 88 break; 89 case FAMILY_KV: 90 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) || 91 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) || 92 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev)) 93 dc_version = DCE_VERSION_8_3; 94 else 95 dc_version = DCE_VERSION_8_1; 96 break; 97 case FAMILY_CZ: 98 dc_version = DCE_VERSION_11_0; 99 break; 100 101 case FAMILY_VI: 102 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || 103 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { 104 dc_version = DCE_VERSION_10_0; 105 break; 106 } 107 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || 108 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || 109 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { 110 dc_version = DCE_VERSION_11_2; 111 } 112 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) 113 dc_version = DCE_VERSION_11_22; 114 break; 115 case FAMILY_AI: 116 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev)) 117 dc_version = DCE_VERSION_12_1; 118 else 119 dc_version = DCE_VERSION_12_0; 120 break; 121 #if defined(CONFIG_DRM_AMD_DC_DCN) 122 case FAMILY_RV: 123 dc_version = DCN_VERSION_1_0; 124 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) 125 dc_version = DCN_VERSION_1_01; 126 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) 127 dc_version = DCN_VERSION_2_1; 128 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) 129 dc_version = DCN_VERSION_2_1; 130 break; 131 132 case FAMILY_NV: 133 dc_version = DCN_VERSION_2_0; 134 if (asic_id.chip_id == DEVICE_ID_NV_13FE) { 135 dc_version = DCN_VERSION_2_01; 136 break; 137 } 138 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) 139 dc_version = DCN_VERSION_3_0; 140 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) 141 dc_version = DCN_VERSION_3_02; 142 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) 143 dc_version = DCN_VERSION_3_03; 144 break; 145 146 case FAMILY_VGH: 147 dc_version = DCN_VERSION_3_01; 148 break; 149 150 case FAMILY_YELLOW_CARP: 151 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) 152 dc_version = DCN_VERSION_3_1; 153 break; 154 #endif 155 156 default: 157 dc_version = DCE_VERSION_UNKNOWN; 158 break; 159 } 160 return dc_version; 161 } 162 163 struct resource_pool *dc_create_resource_pool(struct dc *dc, 164 const struct dc_init_data *init_data, 165 enum dce_version dc_version) 166 { 167 struct resource_pool *res_pool = NULL; 168 169 switch (dc_version) { 170 #if defined(CONFIG_DRM_AMD_DC_SI) 171 case DCE_VERSION_6_0: 172 res_pool = dce60_create_resource_pool( 173 init_data->num_virtual_links, dc); 174 break; 175 case DCE_VERSION_6_1: 176 res_pool = dce61_create_resource_pool( 177 init_data->num_virtual_links, dc); 178 break; 179 case DCE_VERSION_6_4: 180 res_pool = dce64_create_resource_pool( 181 init_data->num_virtual_links, dc); 182 break; 183 #endif 184 case DCE_VERSION_8_0: 185 res_pool = dce80_create_resource_pool( 186 init_data->num_virtual_links, dc); 187 break; 188 case DCE_VERSION_8_1: 189 res_pool = dce81_create_resource_pool( 190 init_data->num_virtual_links, dc); 191 break; 192 case DCE_VERSION_8_3: 193 res_pool = dce83_create_resource_pool( 194 init_data->num_virtual_links, dc); 195 break; 196 case DCE_VERSION_10_0: 197 res_pool = dce100_create_resource_pool( 198 init_data->num_virtual_links, dc); 199 break; 200 case DCE_VERSION_11_0: 201 res_pool = dce110_create_resource_pool( 202 init_data->num_virtual_links, dc, 203 init_data->asic_id); 204 break; 205 case DCE_VERSION_11_2: 206 case DCE_VERSION_11_22: 207 res_pool = dce112_create_resource_pool( 208 init_data->num_virtual_links, dc); 209 break; 210 case DCE_VERSION_12_0: 211 case DCE_VERSION_12_1: 212 res_pool = dce120_create_resource_pool( 213 init_data->num_virtual_links, dc); 214 break; 215 216 #if defined(CONFIG_DRM_AMD_DC_DCN) 217 case DCN_VERSION_1_0: 218 case DCN_VERSION_1_01: 219 res_pool = dcn10_create_resource_pool(init_data, dc); 220 break; 221 case DCN_VERSION_2_0: 222 res_pool = dcn20_create_resource_pool(init_data, dc); 223 break; 224 case DCN_VERSION_2_1: 225 res_pool = dcn21_create_resource_pool(init_data, dc); 226 break; 227 case DCN_VERSION_2_01: 228 res_pool = dcn201_create_resource_pool(init_data, dc); 229 break; 230 case DCN_VERSION_3_0: 231 res_pool = dcn30_create_resource_pool(init_data, dc); 232 break; 233 case DCN_VERSION_3_01: 234 res_pool = dcn301_create_resource_pool(init_data, dc); 235 break; 236 case DCN_VERSION_3_02: 237 res_pool = dcn302_create_resource_pool(init_data, dc); 238 break; 239 case DCN_VERSION_3_03: 240 res_pool = dcn303_create_resource_pool(init_data, dc); 241 break; 242 case DCN_VERSION_3_1: 243 res_pool = dcn31_create_resource_pool(init_data, dc); 244 break; 245 #endif 246 default: 247 break; 248 } 249 250 if (res_pool != NULL) { 251 if (dc->ctx->dc_bios->fw_info_valid) { 252 res_pool->ref_clocks.xtalin_clock_inKhz = 253 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 254 /* initialize with firmware data first, no all 255 * ASIC have DCCG SW component. FPGA or 256 * simulation need initialization of 257 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz 258 * with xtalin_clock_inKhz 259 */ 260 res_pool->ref_clocks.dccg_ref_clock_inKhz = 261 res_pool->ref_clocks.xtalin_clock_inKhz; 262 res_pool->ref_clocks.dchub_ref_clock_inKhz = 263 res_pool->ref_clocks.xtalin_clock_inKhz; 264 } else 265 ASSERT_CRITICAL(false); 266 } 267 268 return res_pool; 269 } 270 271 void dc_destroy_resource_pool(struct dc *dc) 272 { 273 if (dc) { 274 if (dc->res_pool) 275 dc->res_pool->funcs->destroy(&dc->res_pool); 276 277 kfree(dc->hwseq); 278 } 279 } 280 281 static void update_num_audio( 282 const struct resource_straps *straps, 283 unsigned int *num_audio, 284 struct audio_support *aud_support) 285 { 286 aud_support->dp_audio = true; 287 aud_support->hdmi_audio_native = false; 288 aud_support->hdmi_audio_on_dongle = false; 289 290 if (straps->hdmi_disable == 0) { 291 if (straps->dc_pinstraps_audio & 0x2) { 292 aud_support->hdmi_audio_on_dongle = true; 293 aud_support->hdmi_audio_native = true; 294 } 295 } 296 297 switch (straps->audio_stream_number) { 298 case 0: /* multi streams supported */ 299 break; 300 case 1: /* multi streams not supported */ 301 *num_audio = 1; 302 break; 303 default: 304 DC_ERR("DC: unexpected audio fuse!\n"); 305 } 306 } 307 308 bool resource_construct( 309 unsigned int num_virtual_links, 310 struct dc *dc, 311 struct resource_pool *pool, 312 const struct resource_create_funcs *create_funcs) 313 { 314 struct dc_context *ctx = dc->ctx; 315 const struct resource_caps *caps = pool->res_cap; 316 int i; 317 unsigned int num_audio = caps->num_audio; 318 struct resource_straps straps = {0}; 319 320 if (create_funcs->read_dce_straps) 321 create_funcs->read_dce_straps(dc->ctx, &straps); 322 323 pool->audio_count = 0; 324 if (create_funcs->create_audio) { 325 /* find the total number of streams available via the 326 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 327 * registers (one for each pin) starting from pin 1 328 * up to the max number of audio pins. 329 * We stop on the first pin where 330 * PORT_CONNECTIVITY == 1 (as instructed by HW team). 331 */ 332 update_num_audio(&straps, &num_audio, &pool->audio_support); 333 for (i = 0; i < caps->num_audio; i++) { 334 struct audio *aud = create_funcs->create_audio(ctx, i); 335 336 if (aud == NULL) { 337 DC_ERR("DC: failed to create audio!\n"); 338 return false; 339 } 340 if (!aud->funcs->endpoint_valid(aud)) { 341 aud->funcs->destroy(&aud); 342 break; 343 } 344 pool->audios[i] = aud; 345 pool->audio_count++; 346 } 347 } 348 349 pool->stream_enc_count = 0; 350 if (create_funcs->create_stream_encoder) { 351 for (i = 0; i < caps->num_stream_encoder; i++) { 352 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); 353 if (pool->stream_enc[i] == NULL) 354 DC_ERR("DC: failed to create stream_encoder!\n"); 355 pool->stream_enc_count++; 356 } 357 } 358 359 #if defined(CONFIG_DRM_AMD_DC_DCN) 360 pool->hpo_dp_stream_enc_count = 0; 361 if (create_funcs->create_hpo_dp_stream_encoder) { 362 for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) { 363 pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx); 364 if (pool->hpo_dp_stream_enc[i] == NULL) 365 DC_ERR("DC: failed to create HPO DP stream encoder!\n"); 366 pool->hpo_dp_stream_enc_count++; 367 368 } 369 } 370 371 pool->hpo_dp_link_enc_count = 0; 372 if (create_funcs->create_hpo_dp_link_encoder) { 373 for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) { 374 pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx); 375 if (pool->hpo_dp_link_enc[i] == NULL) 376 DC_ERR("DC: failed to create HPO DP link encoder!\n"); 377 pool->hpo_dp_link_enc_count++; 378 } 379 } 380 #endif 381 382 #if defined(CONFIG_DRM_AMD_DC_DCN) 383 for (i = 0; i < caps->num_mpc_3dlut; i++) { 384 pool->mpc_lut[i] = dc_create_3dlut_func(); 385 if (pool->mpc_lut[i] == NULL) 386 DC_ERR("DC: failed to create MPC 3dlut!\n"); 387 pool->mpc_shaper[i] = dc_create_transfer_func(); 388 if (pool->mpc_shaper[i] == NULL) 389 DC_ERR("DC: failed to create MPC shaper!\n"); 390 } 391 #endif 392 dc->caps.dynamic_audio = false; 393 if (pool->audio_count < pool->stream_enc_count) { 394 dc->caps.dynamic_audio = true; 395 } 396 for (i = 0; i < num_virtual_links; i++) { 397 pool->stream_enc[pool->stream_enc_count] = 398 virtual_stream_encoder_create( 399 ctx, ctx->dc_bios); 400 if (pool->stream_enc[pool->stream_enc_count] == NULL) { 401 DC_ERR("DC: failed to create stream_encoder!\n"); 402 return false; 403 } 404 pool->stream_enc_count++; 405 } 406 407 dc->hwseq = create_funcs->create_hwseq(ctx); 408 409 return true; 410 } 411 static int find_matching_clock_source( 412 const struct resource_pool *pool, 413 struct clock_source *clock_source) 414 { 415 416 int i; 417 418 for (i = 0; i < pool->clk_src_count; i++) { 419 if (pool->clock_sources[i] == clock_source) 420 return i; 421 } 422 return -1; 423 } 424 425 void resource_unreference_clock_source( 426 struct resource_context *res_ctx, 427 const struct resource_pool *pool, 428 struct clock_source *clock_source) 429 { 430 int i = find_matching_clock_source(pool, clock_source); 431 432 if (i > -1) 433 res_ctx->clock_source_ref_count[i]--; 434 435 if (pool->dp_clock_source == clock_source) 436 res_ctx->dp_clock_source_ref_count--; 437 } 438 439 void resource_reference_clock_source( 440 struct resource_context *res_ctx, 441 const struct resource_pool *pool, 442 struct clock_source *clock_source) 443 { 444 int i = find_matching_clock_source(pool, clock_source); 445 446 if (i > -1) 447 res_ctx->clock_source_ref_count[i]++; 448 449 if (pool->dp_clock_source == clock_source) 450 res_ctx->dp_clock_source_ref_count++; 451 } 452 453 int resource_get_clock_source_reference( 454 struct resource_context *res_ctx, 455 const struct resource_pool *pool, 456 struct clock_source *clock_source) 457 { 458 int i = find_matching_clock_source(pool, clock_source); 459 460 if (i > -1) 461 return res_ctx->clock_source_ref_count[i]; 462 463 if (pool->dp_clock_source == clock_source) 464 return res_ctx->dp_clock_source_ref_count; 465 466 return -1; 467 } 468 469 bool resource_are_vblanks_synchronizable( 470 struct dc_stream_state *stream1, 471 struct dc_stream_state *stream2) 472 { 473 uint32_t base60_refresh_rates[] = {10, 20, 5}; 474 uint8_t i; 475 uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates); 476 uint64_t frame_time_diff; 477 478 if (stream1->ctx->dc->config.vblank_alignment_dto_params && 479 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 && 480 dc_is_dp_signal(stream1->signal) && 481 dc_is_dp_signal(stream2->signal) && 482 false == stream1->has_non_synchronizable_pclk && 483 false == stream2->has_non_synchronizable_pclk && 484 stream1->timing.flags.VBLANK_SYNCHRONIZABLE && 485 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) { 486 /* disable refresh rates higher than 60Hz for now */ 487 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/ 488 stream1->timing.v_total > 60) 489 return false; 490 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/ 491 stream2->timing.v_total > 60) 492 return false; 493 frame_time_diff = (uint64_t)10000 * 494 stream1->timing.h_total * 495 stream1->timing.v_total * 496 stream2->timing.pix_clk_100hz; 497 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz); 498 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total); 499 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total); 500 for (i = 0; i < rr_count; i++) { 501 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000; 502 503 if (diff < 0) 504 diff = -diff; 505 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff) 506 return true; 507 } 508 } 509 return false; 510 } 511 512 bool resource_are_streams_timing_synchronizable( 513 struct dc_stream_state *stream1, 514 struct dc_stream_state *stream2) 515 { 516 if (stream1->timing.h_total != stream2->timing.h_total) 517 return false; 518 519 if (stream1->timing.v_total != stream2->timing.v_total) 520 return false; 521 522 if (stream1->timing.h_addressable 523 != stream2->timing.h_addressable) 524 return false; 525 526 if (stream1->timing.v_addressable 527 != stream2->timing.v_addressable) 528 return false; 529 530 if (stream1->timing.v_front_porch 531 != stream2->timing.v_front_porch) 532 return false; 533 534 if (stream1->timing.pix_clk_100hz 535 != stream2->timing.pix_clk_100hz) 536 return false; 537 538 if (stream1->clamping.c_depth != stream2->clamping.c_depth) 539 return false; 540 541 if (stream1->phy_pix_clk != stream2->phy_pix_clk 542 && (!dc_is_dp_signal(stream1->signal) 543 || !dc_is_dp_signal(stream2->signal))) 544 return false; 545 546 if (stream1->view_format != stream2->view_format) 547 return false; 548 549 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param) 550 return false; 551 552 return true; 553 } 554 static bool is_dp_and_hdmi_sharable( 555 struct dc_stream_state *stream1, 556 struct dc_stream_state *stream2) 557 { 558 if (stream1->ctx->dc->caps.disable_dp_clk_share) 559 return false; 560 561 if (stream1->clamping.c_depth != COLOR_DEPTH_888 || 562 stream2->clamping.c_depth != COLOR_DEPTH_888) 563 return false; 564 565 return true; 566 567 } 568 569 static bool is_sharable_clk_src( 570 const struct pipe_ctx *pipe_with_clk_src, 571 const struct pipe_ctx *pipe) 572 { 573 if (pipe_with_clk_src->clock_source == NULL) 574 return false; 575 576 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) 577 return false; 578 579 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) || 580 (dc_is_dp_signal(pipe->stream->signal) && 581 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream, 582 pipe->stream))) 583 return false; 584 585 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) 586 && dc_is_dual_link_signal(pipe->stream->signal)) 587 return false; 588 589 if (dc_is_hdmi_signal(pipe->stream->signal) 590 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal)) 591 return false; 592 593 if (!resource_are_streams_timing_synchronizable( 594 pipe_with_clk_src->stream, pipe->stream)) 595 return false; 596 597 return true; 598 } 599 600 struct clock_source *resource_find_used_clk_src_for_sharing( 601 struct resource_context *res_ctx, 602 struct pipe_ctx *pipe_ctx) 603 { 604 int i; 605 606 for (i = 0; i < MAX_PIPES; i++) { 607 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) 608 return res_ctx->pipe_ctx[i].clock_source; 609 } 610 611 return NULL; 612 } 613 614 static enum pixel_format convert_pixel_format_to_dalsurface( 615 enum surface_pixel_format surface_pixel_format) 616 { 617 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 618 619 switch (surface_pixel_format) { 620 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 621 dal_pixel_format = PIXEL_FORMAT_INDEX8; 622 break; 623 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 624 dal_pixel_format = PIXEL_FORMAT_RGB565; 625 break; 626 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 627 dal_pixel_format = PIXEL_FORMAT_RGB565; 628 break; 629 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 630 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 631 break; 632 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 633 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 634 break; 635 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 636 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 637 break; 638 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 639 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 640 break; 641 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 642 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS; 643 break; 644 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 645 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 646 dal_pixel_format = PIXEL_FORMAT_FP16; 647 break; 648 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 649 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 650 dal_pixel_format = PIXEL_FORMAT_420BPP8; 651 break; 652 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 653 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 654 dal_pixel_format = PIXEL_FORMAT_420BPP10; 655 break; 656 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 657 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 658 default: 659 dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 660 break; 661 } 662 return dal_pixel_format; 663 } 664 665 static inline void get_vp_scan_direction( 666 enum dc_rotation_angle rotation, 667 bool horizontal_mirror, 668 bool *orthogonal_rotation, 669 bool *flip_vert_scan_dir, 670 bool *flip_horz_scan_dir) 671 { 672 *orthogonal_rotation = false; 673 *flip_vert_scan_dir = false; 674 *flip_horz_scan_dir = false; 675 if (rotation == ROTATION_ANGLE_180) { 676 *flip_vert_scan_dir = true; 677 *flip_horz_scan_dir = true; 678 } else if (rotation == ROTATION_ANGLE_90) { 679 *orthogonal_rotation = true; 680 *flip_horz_scan_dir = true; 681 } else if (rotation == ROTATION_ANGLE_270) { 682 *orthogonal_rotation = true; 683 *flip_vert_scan_dir = true; 684 } 685 686 if (horizontal_mirror) 687 *flip_horz_scan_dir = !*flip_horz_scan_dir; 688 } 689 690 int get_num_mpc_splits(struct pipe_ctx *pipe) 691 { 692 int mpc_split_count = 0; 693 struct pipe_ctx *other_pipe = pipe->bottom_pipe; 694 695 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 696 mpc_split_count++; 697 other_pipe = other_pipe->bottom_pipe; 698 } 699 other_pipe = pipe->top_pipe; 700 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 701 mpc_split_count++; 702 other_pipe = other_pipe->top_pipe; 703 } 704 705 return mpc_split_count; 706 } 707 708 int get_num_odm_splits(struct pipe_ctx *pipe) 709 { 710 int odm_split_count = 0; 711 struct pipe_ctx *next_pipe = pipe->next_odm_pipe; 712 while (next_pipe) { 713 odm_split_count++; 714 next_pipe = next_pipe->next_odm_pipe; 715 } 716 pipe = pipe->prev_odm_pipe; 717 while (pipe) { 718 odm_split_count++; 719 pipe = pipe->prev_odm_pipe; 720 } 721 return odm_split_count; 722 } 723 724 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx) 725 { 726 *split_count = get_num_odm_splits(pipe_ctx); 727 *split_idx = 0; 728 if (*split_count == 0) { 729 /*Check for mpc split*/ 730 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe; 731 732 *split_count = get_num_mpc_splits(pipe_ctx); 733 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) { 734 (*split_idx)++; 735 split_pipe = split_pipe->top_pipe; 736 } 737 } else { 738 /*Get odm split index*/ 739 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe; 740 741 while (split_pipe) { 742 (*split_idx)++; 743 split_pipe = split_pipe->prev_odm_pipe; 744 } 745 } 746 } 747 748 /* 749 * This is a preliminary vp size calculation to allow us to check taps support. 750 * The result is completely overridden afterwards. 751 */ 752 static void calculate_viewport_size(struct pipe_ctx *pipe_ctx) 753 { 754 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 755 756 data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width)); 757 data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height)); 758 data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width)); 759 data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height)); 760 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 761 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { 762 swap(data->viewport.width, data->viewport.height); 763 swap(data->viewport_c.width, data->viewport_c.height); 764 } 765 } 766 767 static void calculate_recout(struct pipe_ctx *pipe_ctx) 768 { 769 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 770 const struct dc_stream_state *stream = pipe_ctx->stream; 771 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 772 struct rect surf_clip = plane_state->clip_rect; 773 bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; 774 int split_count, split_idx; 775 776 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 777 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 778 split_idx = 0; 779 780 /* 781 * Only the leftmost ODM pipe should be offset by a nonzero distance 782 */ 783 if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) { 784 data->recout.x = stream->dst.x; 785 if (stream->src.x < surf_clip.x) 786 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width 787 / stream->src.width; 788 } else 789 data->recout.x = 0; 790 791 if (stream->src.x > surf_clip.x) 792 surf_clip.width -= stream->src.x - surf_clip.x; 793 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width; 794 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width) 795 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x; 796 797 data->recout.y = stream->dst.y; 798 if (stream->src.y < surf_clip.y) 799 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height 800 / stream->src.height; 801 else if (stream->src.y > surf_clip.y) 802 surf_clip.height -= stream->src.y - surf_clip.y; 803 804 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height; 805 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height) 806 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y; 807 808 /* Handle h & v split */ 809 if (split_tb) { 810 ASSERT(data->recout.height % 2 == 0); 811 data->recout.height /= 2; 812 } else if (split_count) { 813 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) { 814 /* extra pixels in the division remainder need to go to pipes after 815 * the extra pixel index minus one(epimo) defined here as: 816 */ 817 int epimo = split_count - data->recout.width % (split_count + 1); 818 819 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx; 820 if (split_idx > epimo) 821 data->recout.x += split_idx - epimo - 1; 822 ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0); 823 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0); 824 } else { 825 /* odm */ 826 if (split_idx == split_count) { 827 /* rightmost pipe is the remainder recout */ 828 data->recout.width -= data->h_active * split_count - data->recout.x; 829 830 /* ODM combine cases with MPO we can get negative widths */ 831 if (data->recout.width < 0) 832 data->recout.width = 0; 833 834 data->recout.x = 0; 835 } else 836 data->recout.width = data->h_active - data->recout.x; 837 } 838 } 839 } 840 841 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) 842 { 843 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 844 const struct dc_stream_state *stream = pipe_ctx->stream; 845 struct rect surf_src = plane_state->src_rect; 846 const int in_w = stream->src.width; 847 const int in_h = stream->src.height; 848 const int out_w = stream->dst.width; 849 const int out_h = stream->dst.height; 850 851 /*Swap surf_src height and width since scaling ratios are in recout rotation*/ 852 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 853 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 854 swap(surf_src.height, surf_src.width); 855 856 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( 857 surf_src.width, 858 plane_state->dst_rect.width); 859 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( 860 surf_src.height, 861 plane_state->dst_rect.height); 862 863 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 864 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; 865 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 866 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; 867 868 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( 869 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); 870 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( 871 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); 872 873 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; 874 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; 875 876 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 877 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { 878 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; 879 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; 880 } 881 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate( 882 pipe_ctx->plane_res.scl_data.ratios.horz, 19); 883 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( 884 pipe_ctx->plane_res.scl_data.ratios.vert, 19); 885 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate( 886 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19); 887 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate( 888 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); 889 } 890 891 892 /* 893 * We completely calculate vp offset, size and inits here based entirely on scaling 894 * ratios and recout for pixel perfect pipe combine. 895 */ 896 static void calculate_init_and_vp( 897 bool flip_scan_dir, 898 int recout_offset_within_recout_full, 899 int recout_size, 900 int src_size, 901 int taps, 902 struct fixed31_32 ratio, 903 struct fixed31_32 *init, 904 int *vp_offset, 905 int *vp_size) 906 { 907 struct fixed31_32 temp; 908 int int_part; 909 910 /* 911 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout 912 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on. 913 * All following calculations are based on this logic. 914 * 915 * Init calculated according to formula: 916 * init = (scaling_ratio + number_of_taps + 1) / 2 917 * init_bot = init + scaling_ratio 918 * to get pixel perfect combine add the fraction from calculating vp offset 919 */ 920 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full); 921 *vp_offset = dc_fixpt_floor(temp); 922 temp.value &= 0xffffffff; 923 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int( 924 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19); 925 /* 926 * If viewport has non 0 offset and there are more taps than covered by init then 927 * we should decrease the offset and increase init so we are never sampling 928 * outside of viewport. 929 */ 930 int_part = dc_fixpt_floor(*init); 931 if (int_part < taps) { 932 int_part = taps - int_part; 933 if (int_part > *vp_offset) 934 int_part = *vp_offset; 935 *vp_offset -= int_part; 936 *init = dc_fixpt_add_int(*init, int_part); 937 } 938 /* 939 * If taps are sampling outside of viewport at end of recout and there are more pixels 940 * available in the surface we should increase the viewport size, regardless set vp to 941 * only what is used. 942 */ 943 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1)); 944 *vp_size = dc_fixpt_floor(temp); 945 if (*vp_size + *vp_offset > src_size) 946 *vp_size = src_size - *vp_offset; 947 948 /* We did all the math assuming we are scanning same direction as display does, 949 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction 950 * is flipped we simply need to calculate offset from the other side of plane. 951 * Note that outside of viewport all scaling hardware works in recout space. 952 */ 953 if (flip_scan_dir) 954 *vp_offset = src_size - *vp_offset - *vp_size; 955 } 956 957 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx) 958 { 959 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 960 const struct dc_stream_state *stream = pipe_ctx->stream; 961 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 962 struct rect src = plane_state->src_rect; 963 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 964 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 965 int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y; 966 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; 967 968 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 969 /* 970 * recout full is what the recout would have been if we didnt clip 971 * the source plane at all. We only care about left(ro_lb) and top(ro_tb) 972 * offsets of recout within recout full because those are the directions 973 * we scan from and therefore the only ones that affect inits. 974 */ 975 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) 976 * stream->dst.width / stream->src.width; 977 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) 978 * stream->dst.height / stream->src.height; 979 if (pipe_ctx->prev_odm_pipe && split_idx) 980 ro_lb = data->h_active * split_idx - recout_full_x; 981 else 982 ro_lb = data->recout.x - recout_full_x; 983 ro_tb = data->recout.y - recout_full_y; 984 ASSERT(ro_lb >= 0 && ro_tb >= 0); 985 986 /* 987 * Work in recout rotation since that requires less transformations 988 */ 989 get_vp_scan_direction( 990 plane_state->rotation, 991 plane_state->horizontal_mirror, 992 &orthogonal_rotation, 993 &flip_vert_scan_dir, 994 &flip_horz_scan_dir); 995 996 if (orthogonal_rotation) { 997 swap(src.width, src.height); 998 swap(flip_vert_scan_dir, flip_horz_scan_dir); 999 } 1000 1001 calculate_init_and_vp( 1002 flip_horz_scan_dir, 1003 ro_lb, 1004 data->recout.width, 1005 src.width, 1006 data->taps.h_taps, 1007 data->ratios.horz, 1008 &data->inits.h, 1009 &data->viewport.x, 1010 &data->viewport.width); 1011 calculate_init_and_vp( 1012 flip_horz_scan_dir, 1013 ro_lb, 1014 data->recout.width, 1015 src.width / vpc_div, 1016 data->taps.h_taps_c, 1017 data->ratios.horz_c, 1018 &data->inits.h_c, 1019 &data->viewport_c.x, 1020 &data->viewport_c.width); 1021 calculate_init_and_vp( 1022 flip_vert_scan_dir, 1023 ro_tb, 1024 data->recout.height, 1025 src.height, 1026 data->taps.v_taps, 1027 data->ratios.vert, 1028 &data->inits.v, 1029 &data->viewport.y, 1030 &data->viewport.height); 1031 calculate_init_and_vp( 1032 flip_vert_scan_dir, 1033 ro_tb, 1034 data->recout.height, 1035 src.height / vpc_div, 1036 data->taps.v_taps_c, 1037 data->ratios.vert_c, 1038 &data->inits.v_c, 1039 &data->viewport_c.y, 1040 &data->viewport_c.height); 1041 if (orthogonal_rotation) { 1042 swap(data->viewport.x, data->viewport.y); 1043 swap(data->viewport.width, data->viewport.height); 1044 swap(data->viewport_c.x, data->viewport_c.y); 1045 swap(data->viewport_c.width, data->viewport_c.height); 1046 } 1047 data->viewport.x += src.x; 1048 data->viewport.y += src.y; 1049 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); 1050 data->viewport_c.x += src.x / vpc_div; 1051 data->viewport_c.y += src.y / vpc_div; 1052 } 1053 1054 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 1055 { 1056 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1057 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 1058 bool res = false; 1059 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 1060 1061 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( 1062 pipe_ctx->plane_state->format); 1063 1064 /* Timing borders are part of vactive that we are also supposed to skip in addition 1065 * to any stream dst offset. Since dm logic assumes dst is in addressable 1066 * space we need to add the left and top borders to dst offsets temporarily. 1067 * TODO: fix in DM, stream dst is supposed to be in vactive 1068 */ 1069 pipe_ctx->stream->dst.x += timing->h_border_left; 1070 pipe_ctx->stream->dst.y += timing->v_border_top; 1071 1072 /* Calculate H and V active size */ 1073 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + 1074 timing->h_border_left + timing->h_border_right; 1075 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + 1076 timing->v_border_top + timing->v_border_bottom; 1077 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe) 1078 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1; 1079 1080 /* depends on h_active */ 1081 calculate_recout(pipe_ctx); 1082 /* depends on pixel format */ 1083 calculate_scaling_ratios(pipe_ctx); 1084 /* depends on scaling ratios and recout, does not calculate offset yet */ 1085 calculate_viewport_size(pipe_ctx); 1086 1087 /* Stopgap for validation of ODM + MPO on one side of screen case */ 1088 if (pipe_ctx->plane_res.scl_data.viewport.height < 1 || 1089 pipe_ctx->plane_res.scl_data.viewport.width < 1) 1090 return false; 1091 1092 /* 1093 * LB calculations depend on vp size, h/v_active and scaling ratios 1094 * Setting line buffer pixel depth to 24bpp yields banding 1095 * on certain displays, such as the Sharp 4k. 36bpp is needed 1096 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and 1097 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc 1098 * precision on at least DCN display engines. However, at least 1099 * Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth, 1100 * so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3 1101 * did not show such problems, so this seems to be the exception. 1102 */ 1103 if (plane_state->ctx->dce_version > DCE_VERSION_11_0) 1104 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; 1105 else 1106 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; 1107 1108 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; 1109 1110 if (pipe_ctx->plane_res.xfm != NULL) 1111 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1112 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1113 1114 if (pipe_ctx->plane_res.dpp != NULL) 1115 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1116 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1117 1118 1119 if (!res) { 1120 /* Try 24 bpp linebuffer */ 1121 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; 1122 1123 if (pipe_ctx->plane_res.xfm != NULL) 1124 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1125 pipe_ctx->plane_res.xfm, 1126 &pipe_ctx->plane_res.scl_data, 1127 &plane_state->scaling_quality); 1128 1129 if (pipe_ctx->plane_res.dpp != NULL) 1130 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1131 pipe_ctx->plane_res.dpp, 1132 &pipe_ctx->plane_res.scl_data, 1133 &plane_state->scaling_quality); 1134 } 1135 1136 /* 1137 * Depends on recout, scaling ratios, h_active and taps 1138 * May need to re-check lb size after this in some obscure scenario 1139 */ 1140 if (res) 1141 calculate_inits_and_viewports(pipe_ctx); 1142 1143 /* 1144 * Handle side by side and top bottom 3d recout offsets after vp calculation 1145 * since 3d is special and needs to calculate vp as if there is no recout offset 1146 * This may break with rotation, good thing we aren't mixing hw rotation and 3d 1147 */ 1148 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) { 1149 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 || 1150 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM && 1151 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE)); 1152 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 1153 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; 1154 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 1155 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; 1156 } 1157 1158 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE || 1159 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) 1160 res = false; 1161 1162 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n" 1163 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n", 1164 __func__, 1165 pipe_ctx->pipe_idx, 1166 pipe_ctx->plane_res.scl_data.viewport.height, 1167 pipe_ctx->plane_res.scl_data.viewport.width, 1168 pipe_ctx->plane_res.scl_data.viewport.x, 1169 pipe_ctx->plane_res.scl_data.viewport.y, 1170 pipe_ctx->plane_res.scl_data.recout.height, 1171 pipe_ctx->plane_res.scl_data.recout.width, 1172 pipe_ctx->plane_res.scl_data.recout.x, 1173 pipe_ctx->plane_res.scl_data.recout.y, 1174 pipe_ctx->plane_res.scl_data.h_active, 1175 pipe_ctx->plane_res.scl_data.v_active, 1176 plane_state->src_rect.height, 1177 plane_state->src_rect.width, 1178 plane_state->src_rect.x, 1179 plane_state->src_rect.y, 1180 plane_state->dst_rect.height, 1181 plane_state->dst_rect.width, 1182 plane_state->dst_rect.x, 1183 plane_state->dst_rect.y, 1184 plane_state->clip_rect.height, 1185 plane_state->clip_rect.width, 1186 plane_state->clip_rect.x, 1187 plane_state->clip_rect.y); 1188 1189 pipe_ctx->stream->dst.x -= timing->h_border_left; 1190 pipe_ctx->stream->dst.y -= timing->v_border_top; 1191 1192 return res; 1193 } 1194 1195 1196 enum dc_status resource_build_scaling_params_for_context( 1197 const struct dc *dc, 1198 struct dc_state *context) 1199 { 1200 int i; 1201 1202 for (i = 0; i < MAX_PIPES; i++) { 1203 if (context->res_ctx.pipe_ctx[i].plane_state != NULL && 1204 context->res_ctx.pipe_ctx[i].stream != NULL) 1205 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) 1206 return DC_FAIL_SCALING; 1207 } 1208 1209 return DC_OK; 1210 } 1211 1212 struct pipe_ctx *find_idle_secondary_pipe( 1213 struct resource_context *res_ctx, 1214 const struct resource_pool *pool, 1215 const struct pipe_ctx *primary_pipe) 1216 { 1217 int i; 1218 struct pipe_ctx *secondary_pipe = NULL; 1219 1220 /* 1221 * We add a preferred pipe mapping to avoid the chance that 1222 * MPCCs already in use will need to be reassigned to other trees. 1223 * For example, if we went with the strict, assign backwards logic: 1224 * 1225 * (State 1) 1226 * Display A on, no surface, top pipe = 0 1227 * Display B on, no surface, top pipe = 1 1228 * 1229 * (State 2) 1230 * Display A on, no surface, top pipe = 0 1231 * Display B on, surface enable, top pipe = 1, bottom pipe = 5 1232 * 1233 * (State 3) 1234 * Display A on, surface enable, top pipe = 0, bottom pipe = 5 1235 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1236 * 1237 * The state 2->3 transition requires remapping MPCC 5 from display B 1238 * to display A. 1239 * 1240 * However, with the preferred pipe logic, state 2 would look like: 1241 * 1242 * (State 2) 1243 * Display A on, no surface, top pipe = 0 1244 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1245 * 1246 * This would then cause 2->3 to not require remapping any MPCCs. 1247 */ 1248 if (primary_pipe) { 1249 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 1250 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1251 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1252 secondary_pipe->pipe_idx = preferred_pipe_idx; 1253 } 1254 } 1255 1256 /* 1257 * search backwards for the second pipe to keep pipe 1258 * assignment more consistent 1259 */ 1260 if (!secondary_pipe) 1261 for (i = pool->pipe_count - 1; i >= 0; i--) { 1262 if (res_ctx->pipe_ctx[i].stream == NULL) { 1263 secondary_pipe = &res_ctx->pipe_ctx[i]; 1264 secondary_pipe->pipe_idx = i; 1265 break; 1266 } 1267 } 1268 1269 return secondary_pipe; 1270 } 1271 1272 struct pipe_ctx *resource_get_head_pipe_for_stream( 1273 struct resource_context *res_ctx, 1274 struct dc_stream_state *stream) 1275 { 1276 int i; 1277 1278 for (i = 0; i < MAX_PIPES; i++) { 1279 if (res_ctx->pipe_ctx[i].stream == stream 1280 && !res_ctx->pipe_ctx[i].top_pipe 1281 && !res_ctx->pipe_ctx[i].prev_odm_pipe) 1282 return &res_ctx->pipe_ctx[i]; 1283 } 1284 return NULL; 1285 } 1286 1287 static struct pipe_ctx *resource_get_tail_pipe( 1288 struct resource_context *res_ctx, 1289 struct pipe_ctx *head_pipe) 1290 { 1291 struct pipe_ctx *tail_pipe; 1292 1293 tail_pipe = head_pipe->bottom_pipe; 1294 1295 while (tail_pipe) { 1296 head_pipe = tail_pipe; 1297 tail_pipe = tail_pipe->bottom_pipe; 1298 } 1299 1300 return head_pipe; 1301 } 1302 1303 /* 1304 * A free_pipe for a stream is defined here as a pipe 1305 * that has no surface attached yet 1306 */ 1307 static struct pipe_ctx *acquire_free_pipe_for_head( 1308 struct dc_state *context, 1309 const struct resource_pool *pool, 1310 struct pipe_ctx *head_pipe) 1311 { 1312 int i; 1313 struct resource_context *res_ctx = &context->res_ctx; 1314 1315 if (!head_pipe->plane_state) 1316 return head_pipe; 1317 1318 /* Re-use pipe already acquired for this stream if available*/ 1319 for (i = pool->pipe_count - 1; i >= 0; i--) { 1320 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream && 1321 !res_ctx->pipe_ctx[i].plane_state) { 1322 return &res_ctx->pipe_ctx[i]; 1323 } 1324 } 1325 1326 /* 1327 * At this point we have no re-useable pipe for this stream and we need 1328 * to acquire an idle one to satisfy the request 1329 */ 1330 1331 if (!pool->funcs->acquire_idle_pipe_for_layer) 1332 return NULL; 1333 1334 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream); 1335 } 1336 1337 #if defined(CONFIG_DRM_AMD_DC_DCN) 1338 static int acquire_first_split_pipe( 1339 struct resource_context *res_ctx, 1340 const struct resource_pool *pool, 1341 struct dc_stream_state *stream) 1342 { 1343 int i; 1344 1345 for (i = 0; i < pool->pipe_count; i++) { 1346 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; 1347 1348 if (split_pipe->top_pipe && 1349 split_pipe->top_pipe->plane_state == split_pipe->plane_state) { 1350 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; 1351 if (split_pipe->bottom_pipe) 1352 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; 1353 1354 if (split_pipe->top_pipe->plane_state) 1355 resource_build_scaling_params(split_pipe->top_pipe); 1356 1357 memset(split_pipe, 0, sizeof(*split_pipe)); 1358 split_pipe->stream_res.tg = pool->timing_generators[i]; 1359 split_pipe->plane_res.hubp = pool->hubps[i]; 1360 split_pipe->plane_res.ipp = pool->ipps[i]; 1361 split_pipe->plane_res.dpp = pool->dpps[i]; 1362 split_pipe->stream_res.opp = pool->opps[i]; 1363 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; 1364 split_pipe->pipe_idx = i; 1365 1366 split_pipe->stream = stream; 1367 return i; 1368 } 1369 } 1370 return -1; 1371 } 1372 #endif 1373 1374 bool dc_add_plane_to_context( 1375 const struct dc *dc, 1376 struct dc_stream_state *stream, 1377 struct dc_plane_state *plane_state, 1378 struct dc_state *context) 1379 { 1380 int i; 1381 struct resource_pool *pool = dc->res_pool; 1382 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; 1383 struct dc_stream_status *stream_status = NULL; 1384 1385 for (i = 0; i < context->stream_count; i++) 1386 if (context->streams[i] == stream) { 1387 stream_status = &context->stream_status[i]; 1388 break; 1389 } 1390 if (stream_status == NULL) { 1391 dm_error("Existing stream not found; failed to attach surface!\n"); 1392 return false; 1393 } 1394 1395 1396 if (stream_status->plane_count == MAX_SURFACE_NUM) { 1397 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", 1398 plane_state, MAX_SURFACE_NUM); 1399 return false; 1400 } 1401 1402 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1403 1404 if (!head_pipe) { 1405 dm_error("Head pipe not found for stream_state %p !\n", stream); 1406 return false; 1407 } 1408 1409 /* retain new surface, but only once per stream */ 1410 dc_plane_state_retain(plane_state); 1411 1412 while (head_pipe) { 1413 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe); 1414 1415 #if defined(CONFIG_DRM_AMD_DC_DCN) 1416 if (!free_pipe) { 1417 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 1418 if (pipe_idx >= 0) 1419 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; 1420 } 1421 #endif 1422 if (!free_pipe) { 1423 dc_plane_state_release(plane_state); 1424 return false; 1425 } 1426 1427 free_pipe->plane_state = plane_state; 1428 1429 if (head_pipe != free_pipe) { 1430 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe); 1431 ASSERT(tail_pipe); 1432 free_pipe->stream_res.tg = tail_pipe->stream_res.tg; 1433 free_pipe->stream_res.abm = tail_pipe->stream_res.abm; 1434 free_pipe->stream_res.opp = tail_pipe->stream_res.opp; 1435 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; 1436 free_pipe->stream_res.audio = tail_pipe->stream_res.audio; 1437 free_pipe->clock_source = tail_pipe->clock_source; 1438 free_pipe->top_pipe = tail_pipe; 1439 tail_pipe->bottom_pipe = free_pipe; 1440 if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) { 1441 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe; 1442 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe; 1443 } 1444 if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) { 1445 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe; 1446 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe; 1447 } 1448 } 1449 head_pipe = head_pipe->next_odm_pipe; 1450 } 1451 /* assign new surfaces*/ 1452 stream_status->plane_states[stream_status->plane_count] = plane_state; 1453 1454 stream_status->plane_count++; 1455 1456 return true; 1457 } 1458 1459 bool dc_remove_plane_from_context( 1460 const struct dc *dc, 1461 struct dc_stream_state *stream, 1462 struct dc_plane_state *plane_state, 1463 struct dc_state *context) 1464 { 1465 int i; 1466 struct dc_stream_status *stream_status = NULL; 1467 struct resource_pool *pool = dc->res_pool; 1468 1469 for (i = 0; i < context->stream_count; i++) 1470 if (context->streams[i] == stream) { 1471 stream_status = &context->stream_status[i]; 1472 break; 1473 } 1474 1475 if (stream_status == NULL) { 1476 dm_error("Existing stream not found; failed to remove plane.\n"); 1477 return false; 1478 } 1479 1480 /* release pipe for plane*/ 1481 for (i = pool->pipe_count - 1; i >= 0; i--) { 1482 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1483 1484 if (pipe_ctx->plane_state == plane_state) { 1485 if (pipe_ctx->top_pipe) 1486 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1487 1488 /* Second condition is to avoid setting NULL to top pipe 1489 * of tail pipe making it look like head pipe in subsequent 1490 * deletes 1491 */ 1492 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) 1493 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1494 1495 /* 1496 * For head pipe detach surfaces from pipe for tail 1497 * pipe just zero it out 1498 */ 1499 if (!pipe_ctx->top_pipe) 1500 pipe_ctx->plane_state = NULL; 1501 else 1502 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1503 } 1504 } 1505 1506 1507 for (i = 0; i < stream_status->plane_count; i++) { 1508 if (stream_status->plane_states[i] == plane_state) { 1509 1510 dc_plane_state_release(stream_status->plane_states[i]); 1511 break; 1512 } 1513 } 1514 1515 if (i == stream_status->plane_count) { 1516 dm_error("Existing plane_state not found; failed to detach it!\n"); 1517 return false; 1518 } 1519 1520 stream_status->plane_count--; 1521 1522 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */ 1523 for (; i < stream_status->plane_count; i++) 1524 stream_status->plane_states[i] = stream_status->plane_states[i + 1]; 1525 1526 stream_status->plane_states[stream_status->plane_count] = NULL; 1527 1528 return true; 1529 } 1530 1531 bool dc_rem_all_planes_for_stream( 1532 const struct dc *dc, 1533 struct dc_stream_state *stream, 1534 struct dc_state *context) 1535 { 1536 int i, old_plane_count; 1537 struct dc_stream_status *stream_status = NULL; 1538 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; 1539 1540 for (i = 0; i < context->stream_count; i++) 1541 if (context->streams[i] == stream) { 1542 stream_status = &context->stream_status[i]; 1543 break; 1544 } 1545 1546 if (stream_status == NULL) { 1547 dm_error("Existing stream %p not found!\n", stream); 1548 return false; 1549 } 1550 1551 old_plane_count = stream_status->plane_count; 1552 1553 for (i = 0; i < old_plane_count; i++) 1554 del_planes[i] = stream_status->plane_states[i]; 1555 1556 for (i = 0; i < old_plane_count; i++) 1557 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) 1558 return false; 1559 1560 return true; 1561 } 1562 1563 static bool add_all_planes_for_stream( 1564 const struct dc *dc, 1565 struct dc_stream_state *stream, 1566 const struct dc_validation_set set[], 1567 int set_count, 1568 struct dc_state *context) 1569 { 1570 int i, j; 1571 1572 for (i = 0; i < set_count; i++) 1573 if (set[i].stream == stream) 1574 break; 1575 1576 if (i == set_count) { 1577 dm_error("Stream %p not found in set!\n", stream); 1578 return false; 1579 } 1580 1581 for (j = 0; j < set[i].plane_count; j++) 1582 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) 1583 return false; 1584 1585 return true; 1586 } 1587 1588 bool dc_add_all_planes_for_stream( 1589 const struct dc *dc, 1590 struct dc_stream_state *stream, 1591 struct dc_plane_state * const *plane_states, 1592 int plane_count, 1593 struct dc_state *context) 1594 { 1595 struct dc_validation_set set; 1596 int i; 1597 1598 set.stream = stream; 1599 set.plane_count = plane_count; 1600 1601 for (i = 0; i < plane_count; i++) 1602 set.plane_states[i] = plane_states[i]; 1603 1604 return add_all_planes_for_stream(dc, stream, &set, 1, context); 1605 } 1606 1607 static bool is_timing_changed(struct dc_stream_state *cur_stream, 1608 struct dc_stream_state *new_stream) 1609 { 1610 if (cur_stream == NULL) 1611 return true; 1612 1613 /* If output color space is changed, need to reprogram info frames */ 1614 if (cur_stream->output_color_space != new_stream->output_color_space) 1615 return true; 1616 1617 return memcmp( 1618 &cur_stream->timing, 1619 &new_stream->timing, 1620 sizeof(struct dc_crtc_timing)) != 0; 1621 } 1622 1623 static bool are_stream_backends_same( 1624 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) 1625 { 1626 if (stream_a == stream_b) 1627 return true; 1628 1629 if (stream_a == NULL || stream_b == NULL) 1630 return false; 1631 1632 if (is_timing_changed(stream_a, stream_b)) 1633 return false; 1634 1635 if (stream_a->dpms_off != stream_b->dpms_off) 1636 return false; 1637 1638 return true; 1639 } 1640 1641 /* 1642 * dc_is_stream_unchanged() - Compare two stream states for equivalence. 1643 * 1644 * Checks if there a difference between the two states 1645 * that would require a mode change. 1646 * 1647 * Does not compare cursor position or attributes. 1648 */ 1649 bool dc_is_stream_unchanged( 1650 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1651 { 1652 1653 if (!are_stream_backends_same(old_stream, stream)) 1654 return false; 1655 1656 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param) 1657 return false; 1658 1659 return true; 1660 } 1661 1662 /* 1663 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams. 1664 */ 1665 bool dc_is_stream_scaling_unchanged( 1666 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1667 { 1668 if (old_stream == stream) 1669 return true; 1670 1671 if (old_stream == NULL || stream == NULL) 1672 return false; 1673 1674 if (memcmp(&old_stream->src, 1675 &stream->src, 1676 sizeof(struct rect)) != 0) 1677 return false; 1678 1679 if (memcmp(&old_stream->dst, 1680 &stream->dst, 1681 sizeof(struct rect)) != 0) 1682 return false; 1683 1684 return true; 1685 } 1686 1687 static void update_stream_engine_usage( 1688 struct resource_context *res_ctx, 1689 const struct resource_pool *pool, 1690 struct stream_encoder *stream_enc, 1691 bool acquired) 1692 { 1693 int i; 1694 1695 for (i = 0; i < pool->stream_enc_count; i++) { 1696 if (pool->stream_enc[i] == stream_enc) 1697 res_ctx->is_stream_enc_acquired[i] = acquired; 1698 } 1699 } 1700 1701 #if defined(CONFIG_DRM_AMD_DC_DCN) 1702 static void update_hpo_dp_stream_engine_usage( 1703 struct resource_context *res_ctx, 1704 const struct resource_pool *pool, 1705 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, 1706 bool acquired) 1707 { 1708 int i; 1709 1710 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { 1711 if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc) 1712 res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired; 1713 } 1714 } 1715 #endif 1716 1717 /* TODO: release audio object */ 1718 void update_audio_usage( 1719 struct resource_context *res_ctx, 1720 const struct resource_pool *pool, 1721 struct audio *audio, 1722 bool acquired) 1723 { 1724 int i; 1725 for (i = 0; i < pool->audio_count; i++) { 1726 if (pool->audios[i] == audio) 1727 res_ctx->is_audio_acquired[i] = acquired; 1728 } 1729 } 1730 1731 static int acquire_first_free_pipe( 1732 struct resource_context *res_ctx, 1733 const struct resource_pool *pool, 1734 struct dc_stream_state *stream) 1735 { 1736 int i; 1737 1738 for (i = 0; i < pool->pipe_count; i++) { 1739 if (!res_ctx->pipe_ctx[i].stream) { 1740 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 1741 1742 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 1743 pipe_ctx->plane_res.mi = pool->mis[i]; 1744 pipe_ctx->plane_res.hubp = pool->hubps[i]; 1745 pipe_ctx->plane_res.ipp = pool->ipps[i]; 1746 pipe_ctx->plane_res.xfm = pool->transforms[i]; 1747 pipe_ctx->plane_res.dpp = pool->dpps[i]; 1748 pipe_ctx->stream_res.opp = pool->opps[i]; 1749 if (pool->dpps[i]) 1750 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; 1751 pipe_ctx->pipe_idx = i; 1752 1753 1754 pipe_ctx->stream = stream; 1755 return i; 1756 } 1757 } 1758 return -1; 1759 } 1760 1761 #if defined(CONFIG_DRM_AMD_DC_DCN) 1762 static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link( 1763 struct resource_context *res_ctx, 1764 const struct resource_pool *pool, 1765 struct dc_stream_state *stream) 1766 { 1767 int i; 1768 1769 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { 1770 if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] && 1771 pool->hpo_dp_stream_enc[i]) { 1772 1773 return pool->hpo_dp_stream_enc[i]; 1774 } 1775 } 1776 1777 return NULL; 1778 } 1779 #endif 1780 1781 static struct audio *find_first_free_audio( 1782 struct resource_context *res_ctx, 1783 const struct resource_pool *pool, 1784 enum engine_id id, 1785 enum dce_version dc_version) 1786 { 1787 int i, available_audio_count; 1788 1789 available_audio_count = pool->audio_count; 1790 1791 for (i = 0; i < available_audio_count; i++) { 1792 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { 1793 /*we have enough audio endpoint, find the matching inst*/ 1794 if (id != i) 1795 continue; 1796 return pool->audios[i]; 1797 } 1798 } 1799 1800 /* use engine id to find free audio */ 1801 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) { 1802 return pool->audios[id]; 1803 } 1804 /*not found the matching one, first come first serve*/ 1805 for (i = 0; i < available_audio_count; i++) { 1806 if (res_ctx->is_audio_acquired[i] == false) { 1807 return pool->audios[i]; 1808 } 1809 } 1810 return 0; 1811 } 1812 1813 /* 1814 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state. 1815 */ 1816 enum dc_status dc_add_stream_to_ctx( 1817 struct dc *dc, 1818 struct dc_state *new_ctx, 1819 struct dc_stream_state *stream) 1820 { 1821 enum dc_status res; 1822 DC_LOGGER_INIT(dc->ctx->logger); 1823 1824 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) { 1825 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream); 1826 return DC_ERROR_UNEXPECTED; 1827 } 1828 1829 new_ctx->streams[new_ctx->stream_count] = stream; 1830 dc_stream_retain(stream); 1831 new_ctx->stream_count++; 1832 1833 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); 1834 if (res != DC_OK) 1835 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res); 1836 1837 return res; 1838 } 1839 1840 /* 1841 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state. 1842 */ 1843 enum dc_status dc_remove_stream_from_ctx( 1844 struct dc *dc, 1845 struct dc_state *new_ctx, 1846 struct dc_stream_state *stream) 1847 { 1848 int i; 1849 struct dc_context *dc_ctx = dc->ctx; 1850 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream); 1851 struct pipe_ctx *odm_pipe; 1852 1853 if (!del_pipe) { 1854 DC_ERROR("Pipe not found for stream %p !\n", stream); 1855 return DC_ERROR_UNEXPECTED; 1856 } 1857 1858 odm_pipe = del_pipe->next_odm_pipe; 1859 1860 /* Release primary pipe */ 1861 ASSERT(del_pipe->stream_res.stream_enc); 1862 update_stream_engine_usage( 1863 &new_ctx->res_ctx, 1864 dc->res_pool, 1865 del_pipe->stream_res.stream_enc, 1866 false); 1867 /* Release link encoder from stream in new dc_state. */ 1868 if (dc->res_pool->funcs->link_enc_unassign) 1869 dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream); 1870 1871 #if defined(CONFIG_DRM_AMD_DC_DCN) 1872 if (is_dp_128b_132b_signal(del_pipe)) { 1873 update_hpo_dp_stream_engine_usage( 1874 &new_ctx->res_ctx, dc->res_pool, 1875 del_pipe->stream_res.hpo_dp_stream_enc, 1876 false); 1877 } 1878 #endif 1879 1880 if (del_pipe->stream_res.audio) 1881 update_audio_usage( 1882 &new_ctx->res_ctx, 1883 dc->res_pool, 1884 del_pipe->stream_res.audio, 1885 false); 1886 1887 resource_unreference_clock_source(&new_ctx->res_ctx, 1888 dc->res_pool, 1889 del_pipe->clock_source); 1890 1891 if (dc->res_pool->funcs->remove_stream_from_ctx) 1892 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream); 1893 1894 while (odm_pipe) { 1895 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 1896 1897 memset(odm_pipe, 0, sizeof(*odm_pipe)); 1898 odm_pipe = next_odm_pipe; 1899 } 1900 memset(del_pipe, 0, sizeof(*del_pipe)); 1901 1902 for (i = 0; i < new_ctx->stream_count; i++) 1903 if (new_ctx->streams[i] == stream) 1904 break; 1905 1906 if (new_ctx->streams[i] != stream) { 1907 DC_ERROR("Context doesn't have stream %p !\n", stream); 1908 return DC_ERROR_UNEXPECTED; 1909 } 1910 1911 dc_stream_release(new_ctx->streams[i]); 1912 new_ctx->stream_count--; 1913 1914 /* Trim back arrays */ 1915 for (; i < new_ctx->stream_count; i++) { 1916 new_ctx->streams[i] = new_ctx->streams[i + 1]; 1917 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; 1918 } 1919 1920 new_ctx->streams[new_ctx->stream_count] = NULL; 1921 memset( 1922 &new_ctx->stream_status[new_ctx->stream_count], 1923 0, 1924 sizeof(new_ctx->stream_status[0])); 1925 1926 return DC_OK; 1927 } 1928 1929 static struct dc_stream_state *find_pll_sharable_stream( 1930 struct dc_stream_state *stream_needs_pll, 1931 struct dc_state *context) 1932 { 1933 int i; 1934 1935 for (i = 0; i < context->stream_count; i++) { 1936 struct dc_stream_state *stream_has_pll = context->streams[i]; 1937 1938 /* We are looking for non dp, non virtual stream */ 1939 if (resource_are_streams_timing_synchronizable( 1940 stream_needs_pll, stream_has_pll) 1941 && !dc_is_dp_signal(stream_has_pll->signal) 1942 && stream_has_pll->link->connector_signal 1943 != SIGNAL_TYPE_VIRTUAL) 1944 return stream_has_pll; 1945 1946 } 1947 1948 return NULL; 1949 } 1950 1951 static int get_norm_pix_clk(const struct dc_crtc_timing *timing) 1952 { 1953 uint32_t pix_clk = timing->pix_clk_100hz; 1954 uint32_t normalized_pix_clk = pix_clk; 1955 1956 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 1957 pix_clk /= 2; 1958 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 1959 switch (timing->display_color_depth) { 1960 case COLOR_DEPTH_666: 1961 case COLOR_DEPTH_888: 1962 normalized_pix_clk = pix_clk; 1963 break; 1964 case COLOR_DEPTH_101010: 1965 normalized_pix_clk = (pix_clk * 30) / 24; 1966 break; 1967 case COLOR_DEPTH_121212: 1968 normalized_pix_clk = (pix_clk * 36) / 24; 1969 break; 1970 case COLOR_DEPTH_161616: 1971 normalized_pix_clk = (pix_clk * 48) / 24; 1972 break; 1973 default: 1974 ASSERT(0); 1975 break; 1976 } 1977 } 1978 return normalized_pix_clk; 1979 } 1980 1981 static void calculate_phy_pix_clks(struct dc_stream_state *stream) 1982 { 1983 /* update actual pixel clock on all streams */ 1984 if (dc_is_hdmi_signal(stream->signal)) 1985 stream->phy_pix_clk = get_norm_pix_clk( 1986 &stream->timing) / 10; 1987 else 1988 stream->phy_pix_clk = 1989 stream->timing.pix_clk_100hz / 10; 1990 1991 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1992 stream->phy_pix_clk *= 2; 1993 } 1994 1995 static int acquire_resource_from_hw_enabled_state( 1996 struct resource_context *res_ctx, 1997 const struct resource_pool *pool, 1998 struct dc_stream_state *stream) 1999 { 2000 struct dc_link *link = stream->link; 2001 unsigned int i, inst, tg_inst = 0; 2002 2003 /* Check for enabled DIG to identify enabled display */ 2004 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) 2005 return -1; 2006 2007 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); 2008 2009 if (inst == ENGINE_ID_UNKNOWN) 2010 return -1; 2011 2012 for (i = 0; i < pool->stream_enc_count; i++) { 2013 if (pool->stream_enc[i]->id == inst) { 2014 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( 2015 pool->stream_enc[i]); 2016 break; 2017 } 2018 } 2019 2020 // tg_inst not found 2021 if (i == pool->stream_enc_count) 2022 return -1; 2023 2024 if (tg_inst >= pool->timing_generator_count) 2025 return -1; 2026 2027 if (!res_ctx->pipe_ctx[tg_inst].stream) { 2028 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; 2029 2030 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 2031 pipe_ctx->plane_res.mi = pool->mis[tg_inst]; 2032 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; 2033 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; 2034 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; 2035 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst]; 2036 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; 2037 2038 if (pool->dpps[tg_inst]) { 2039 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; 2040 2041 // Read DPP->MPCC->OPP Pipe from HW State 2042 if (pool->mpc->funcs->read_mpcc_state) { 2043 struct mpcc_state s = {0}; 2044 2045 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); 2046 2047 if (s.dpp_id < MAX_MPCC) 2048 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id; 2049 2050 if (s.bot_mpcc_id < MAX_MPCC) 2051 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = 2052 &pool->mpc->mpcc_array[s.bot_mpcc_id]; 2053 2054 if (s.opp_id < MAX_OPP) 2055 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; 2056 } 2057 } 2058 pipe_ctx->pipe_idx = tg_inst; 2059 2060 pipe_ctx->stream = stream; 2061 return tg_inst; 2062 } 2063 2064 return -1; 2065 } 2066 2067 static void mark_seamless_boot_stream( 2068 const struct dc *dc, 2069 struct dc_stream_state *stream) 2070 { 2071 struct dc_bios *dcb = dc->ctx->dc_bios; 2072 2073 /* TODO: Check Linux */ 2074 if (dc->config.allow_seamless_boot_optimization && 2075 !dcb->funcs->is_accelerated_mode(dcb)) { 2076 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing)) 2077 stream->apply_seamless_boot_optimization = true; 2078 } 2079 } 2080 2081 enum dc_status resource_map_pool_resources( 2082 const struct dc *dc, 2083 struct dc_state *context, 2084 struct dc_stream_state *stream) 2085 { 2086 const struct resource_pool *pool = dc->res_pool; 2087 int i; 2088 struct dc_context *dc_ctx = dc->ctx; 2089 struct pipe_ctx *pipe_ctx = NULL; 2090 int pipe_idx = -1; 2091 2092 calculate_phy_pix_clks(stream); 2093 2094 mark_seamless_boot_stream(dc, stream); 2095 2096 if (stream->apply_seamless_boot_optimization) { 2097 pipe_idx = acquire_resource_from_hw_enabled_state( 2098 &context->res_ctx, 2099 pool, 2100 stream); 2101 if (pipe_idx < 0) 2102 /* hw resource was assigned to other stream */ 2103 stream->apply_seamless_boot_optimization = false; 2104 } 2105 2106 if (pipe_idx < 0) 2107 /* acquire new resources */ 2108 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); 2109 2110 #ifdef CONFIG_DRM_AMD_DC_DCN 2111 if (pipe_idx < 0) 2112 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 2113 #endif 2114 2115 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL) 2116 return DC_NO_CONTROLLER_RESOURCE; 2117 2118 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2119 2120 pipe_ctx->stream_res.stream_enc = 2121 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link( 2122 &context->res_ctx, pool, stream); 2123 2124 if (!pipe_ctx->stream_res.stream_enc) 2125 return DC_NO_STREAM_ENC_RESOURCE; 2126 2127 update_stream_engine_usage( 2128 &context->res_ctx, pool, 2129 pipe_ctx->stream_res.stream_enc, 2130 true); 2131 2132 #if defined(CONFIG_DRM_AMD_DC_DCN) 2133 /* Allocate DP HPO Stream Encoder based on signal, hw capabilities 2134 * and link settings 2135 */ 2136 if (dc_is_dp_signal(stream->signal) && 2137 dc->caps.dp_hpo) { 2138 struct dc_link_settings link_settings = {0}; 2139 2140 decide_link_settings(stream, &link_settings); 2141 if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) { 2142 pipe_ctx->stream_res.hpo_dp_stream_enc = 2143 find_first_free_match_hpo_dp_stream_enc_for_link( 2144 &context->res_ctx, pool, stream); 2145 2146 if (!pipe_ctx->stream_res.hpo_dp_stream_enc) 2147 return DC_NO_STREAM_ENC_RESOURCE; 2148 2149 update_hpo_dp_stream_engine_usage( 2150 &context->res_ctx, pool, 2151 pipe_ctx->stream_res.hpo_dp_stream_enc, 2152 true); 2153 } 2154 } 2155 #endif 2156 2157 /* TODO: Add check if ASIC support and EDID audio */ 2158 if (!stream->converter_disable_audio && 2159 dc_is_audio_capable_signal(pipe_ctx->stream->signal) && 2160 stream->audio_info.mode_count && stream->audio_info.flags.all) { 2161 pipe_ctx->stream_res.audio = find_first_free_audio( 2162 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version); 2163 2164 /* 2165 * Audio assigned in order first come first get. 2166 * There are asics which has number of audio 2167 * resources less then number of pipes 2168 */ 2169 if (pipe_ctx->stream_res.audio) 2170 update_audio_usage(&context->res_ctx, pool, 2171 pipe_ctx->stream_res.audio, true); 2172 } 2173 2174 /* Add ABM to the resource if on EDP */ 2175 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) { 2176 #if defined(CONFIG_DRM_AMD_DC_DCN) 2177 if (pool->abm) 2178 pipe_ctx->stream_res.abm = pool->abm; 2179 else 2180 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst]; 2181 #else 2182 pipe_ctx->stream_res.abm = pool->abm; 2183 #endif 2184 } 2185 2186 for (i = 0; i < context->stream_count; i++) 2187 if (context->streams[i] == stream) { 2188 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; 2189 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst; 2190 context->stream_status[i].audio_inst = 2191 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; 2192 2193 return DC_OK; 2194 } 2195 2196 DC_ERROR("Stream %p not found in new ctx!\n", stream); 2197 return DC_ERROR_UNEXPECTED; 2198 } 2199 2200 /** 2201 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state 2202 * Is a shallow copy. Increments refcounts on existing streams and planes. 2203 * @dc: copy out of dc->current_state 2204 * @dst_ctx: copy into this 2205 */ 2206 void dc_resource_state_copy_construct_current( 2207 const struct dc *dc, 2208 struct dc_state *dst_ctx) 2209 { 2210 dc_resource_state_copy_construct(dc->current_state, dst_ctx); 2211 } 2212 2213 2214 void dc_resource_state_construct( 2215 const struct dc *dc, 2216 struct dc_state *dst_ctx) 2217 { 2218 dst_ctx->clk_mgr = dc->clk_mgr; 2219 } 2220 2221 2222 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) 2223 { 2224 return dc->res_pool->res_cap->num_dsc > 0; 2225 } 2226 2227 2228 /** 2229 * dc_validate_global_state() - Determine if HW can support a given state 2230 * Checks HW resource availability and bandwidth requirement. 2231 * @dc: dc struct for this driver 2232 * @new_ctx: state to be validated 2233 * @fast_validate: set to true if only yes/no to support matters 2234 * 2235 * Return: DC_OK if the result can be programmed. Otherwise, an error code. 2236 */ 2237 enum dc_status dc_validate_global_state( 2238 struct dc *dc, 2239 struct dc_state *new_ctx, 2240 bool fast_validate) 2241 { 2242 enum dc_status result = DC_ERROR_UNEXPECTED; 2243 int i, j; 2244 2245 if (!new_ctx) 2246 return DC_ERROR_UNEXPECTED; 2247 #if defined(CONFIG_DRM_AMD_DC_DCN) 2248 2249 /* 2250 * Update link encoder to stream assignment. 2251 * TODO: Split out reason allocation from validation. 2252 */ 2253 if (dc->res_pool->funcs->link_encs_assign && fast_validate == false) 2254 dc->res_pool->funcs->link_encs_assign( 2255 dc, new_ctx, new_ctx->streams, new_ctx->stream_count); 2256 #endif 2257 2258 if (dc->res_pool->funcs->validate_global) { 2259 result = dc->res_pool->funcs->validate_global(dc, new_ctx); 2260 if (result != DC_OK) 2261 return result; 2262 } 2263 2264 for (i = 0; i < new_ctx->stream_count; i++) { 2265 struct dc_stream_state *stream = new_ctx->streams[i]; 2266 2267 for (j = 0; j < dc->res_pool->pipe_count; j++) { 2268 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; 2269 2270 if (pipe_ctx->stream != stream) 2271 continue; 2272 2273 if (dc->res_pool->funcs->patch_unknown_plane_state && 2274 pipe_ctx->plane_state && 2275 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { 2276 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); 2277 if (result != DC_OK) 2278 return result; 2279 } 2280 2281 /* Switch to dp clock source only if there is 2282 * no non dp stream that shares the same timing 2283 * with the dp stream. 2284 */ 2285 if (dc_is_dp_signal(pipe_ctx->stream->signal) && 2286 !find_pll_sharable_stream(stream, new_ctx)) { 2287 2288 resource_unreference_clock_source( 2289 &new_ctx->res_ctx, 2290 dc->res_pool, 2291 pipe_ctx->clock_source); 2292 2293 pipe_ctx->clock_source = dc->res_pool->dp_clock_source; 2294 resource_reference_clock_source( 2295 &new_ctx->res_ctx, 2296 dc->res_pool, 2297 pipe_ctx->clock_source); 2298 } 2299 } 2300 } 2301 2302 result = resource_build_scaling_params_for_context(dc, new_ctx); 2303 2304 if (result == DC_OK) 2305 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate)) 2306 result = DC_FAIL_BANDWIDTH_VALIDATE; 2307 2308 return result; 2309 } 2310 2311 static void patch_gamut_packet_checksum( 2312 struct dc_info_packet *gamut_packet) 2313 { 2314 /* For gamut we recalc checksum */ 2315 if (gamut_packet->valid) { 2316 uint8_t chk_sum = 0; 2317 uint8_t *ptr; 2318 uint8_t i; 2319 2320 /*start of the Gamut data. */ 2321 ptr = &gamut_packet->sb[3]; 2322 2323 for (i = 0; i <= gamut_packet->sb[1]; i++) 2324 chk_sum += ptr[i]; 2325 2326 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); 2327 } 2328 } 2329 2330 static void set_avi_info_frame( 2331 struct dc_info_packet *info_packet, 2332 struct pipe_ctx *pipe_ctx) 2333 { 2334 struct dc_stream_state *stream = pipe_ctx->stream; 2335 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; 2336 uint32_t pixel_encoding = 0; 2337 enum scanning_type scan_type = SCANNING_TYPE_NODATA; 2338 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA; 2339 bool itc = false; 2340 uint8_t itc_value = 0; 2341 uint8_t cn0_cn1 = 0; 2342 unsigned int cn0_cn1_value = 0; 2343 uint8_t *check_sum = NULL; 2344 uint8_t byte_index = 0; 2345 union hdmi_info_packet hdmi_info; 2346 union display_content_support support = {0}; 2347 unsigned int vic = pipe_ctx->stream->timing.vic; 2348 enum dc_timing_3d_format format; 2349 2350 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet)); 2351 2352 color_space = pipe_ctx->stream->output_color_space; 2353 if (color_space == COLOR_SPACE_UNKNOWN) 2354 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? 2355 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; 2356 2357 /* Initialize header */ 2358 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI; 2359 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall 2360 * not be used in HDMI 2.0 (Section 10.1) */ 2361 hdmi_info.bits.header.version = 2; 2362 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE; 2363 2364 /* 2365 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built 2366 * according to HDMI 2.0 spec (Section 10.1) 2367 */ 2368 2369 switch (stream->timing.pixel_encoding) { 2370 case PIXEL_ENCODING_YCBCR422: 2371 pixel_encoding = 1; 2372 break; 2373 2374 case PIXEL_ENCODING_YCBCR444: 2375 pixel_encoding = 2; 2376 break; 2377 case PIXEL_ENCODING_YCBCR420: 2378 pixel_encoding = 3; 2379 break; 2380 2381 case PIXEL_ENCODING_RGB: 2382 default: 2383 pixel_encoding = 0; 2384 } 2385 2386 /* Y0_Y1_Y2 : The pixel encoding */ 2387 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ 2388 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding; 2389 2390 /* A0 = 1 Active Format Information valid */ 2391 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID; 2392 2393 /* B0, B1 = 3; Bar info data is valid */ 2394 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID; 2395 2396 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM; 2397 2398 /* S0, S1 : Underscan / Overscan */ 2399 /* TODO: un-hardcode scan type */ 2400 scan_type = SCANNING_TYPE_UNDERSCAN; 2401 hdmi_info.bits.S0_S1 = scan_type; 2402 2403 /* C0, C1 : Colorimetry */ 2404 if (color_space == COLOR_SPACE_YCBCR709 || 2405 color_space == COLOR_SPACE_YCBCR709_LIMITED) 2406 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709; 2407 else if (color_space == COLOR_SPACE_YCBCR601 || 2408 color_space == COLOR_SPACE_YCBCR601_LIMITED) 2409 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601; 2410 else { 2411 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA; 2412 } 2413 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE || 2414 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE || 2415 color_space == COLOR_SPACE_2020_YCBCR) { 2416 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR; 2417 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 2418 } else if (color_space == COLOR_SPACE_ADOBERGB) { 2419 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB; 2420 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 2421 } 2422 2423 /* TODO: un-hardcode aspect ratio */ 2424 aspect = stream->timing.aspect_ratio; 2425 2426 switch (aspect) { 2427 case ASPECT_RATIO_4_3: 2428 case ASPECT_RATIO_16_9: 2429 hdmi_info.bits.M0_M1 = aspect; 2430 break; 2431 2432 case ASPECT_RATIO_NO_DATA: 2433 case ASPECT_RATIO_64_27: 2434 case ASPECT_RATIO_256_135: 2435 default: 2436 hdmi_info.bits.M0_M1 = 0; 2437 } 2438 2439 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */ 2440 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE; 2441 2442 /* TODO: un-hardcode cn0_cn1 and itc */ 2443 2444 cn0_cn1 = 0; 2445 cn0_cn1_value = 0; 2446 2447 itc = true; 2448 itc_value = 1; 2449 2450 support = stream->content_support; 2451 2452 if (itc) { 2453 if (!support.bits.valid_content_type) { 2454 cn0_cn1_value = 0; 2455 } else { 2456 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) { 2457 if (support.bits.graphics_content == 1) { 2458 cn0_cn1_value = 0; 2459 } 2460 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) { 2461 if (support.bits.photo_content == 1) { 2462 cn0_cn1_value = 1; 2463 } else { 2464 cn0_cn1_value = 0; 2465 itc_value = 0; 2466 } 2467 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) { 2468 if (support.bits.cinema_content == 1) { 2469 cn0_cn1_value = 2; 2470 } else { 2471 cn0_cn1_value = 0; 2472 itc_value = 0; 2473 } 2474 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) { 2475 if (support.bits.game_content == 1) { 2476 cn0_cn1_value = 3; 2477 } else { 2478 cn0_cn1_value = 0; 2479 itc_value = 0; 2480 } 2481 } 2482 } 2483 hdmi_info.bits.CN0_CN1 = cn0_cn1_value; 2484 hdmi_info.bits.ITC = itc_value; 2485 } 2486 2487 if (stream->qs_bit == 1) { 2488 if (color_space == COLOR_SPACE_SRGB || 2489 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) 2490 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; 2491 else if (color_space == COLOR_SPACE_SRGB_LIMITED || 2492 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) 2493 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE; 2494 else 2495 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2496 } else 2497 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2498 2499 /* TODO : We should handle YCC quantization */ 2500 /* but we do not have matrix calculation */ 2501 if (stream->qy_bit == 1) { 2502 if (color_space == COLOR_SPACE_SRGB || 2503 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) 2504 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2505 else if (color_space == COLOR_SPACE_SRGB_LIMITED || 2506 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) 2507 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2508 else 2509 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2510 } else 2511 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2512 2513 ///VIC 2514 format = stream->timing.timing_3d_format; 2515 /*todo, add 3DStereo support*/ 2516 if (format != TIMING_3D_FORMAT_NONE) { 2517 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled 2518 switch (pipe_ctx->stream->timing.hdmi_vic) { 2519 case 1: 2520 vic = 95; 2521 break; 2522 case 2: 2523 vic = 94; 2524 break; 2525 case 3: 2526 vic = 93; 2527 break; 2528 case 4: 2529 vic = 98; 2530 break; 2531 default: 2532 break; 2533 } 2534 } 2535 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/ 2536 hdmi_info.bits.VIC0_VIC7 = vic; 2537 if (vic >= 128) 2538 hdmi_info.bits.header.version = 3; 2539 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1), 2540 * the Source shall use 20 AVI InfoFrame Version 4 2541 */ 2542 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED && 2543 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) { 2544 hdmi_info.bits.header.version = 4; 2545 hdmi_info.bits.header.length = 14; 2546 } 2547 2548 /* pixel repetition 2549 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel 2550 * repetition start from 1 */ 2551 hdmi_info.bits.PR0_PR3 = 0; 2552 2553 /* Bar Info 2554 * barTop: Line Number of End of Top Bar. 2555 * barBottom: Line Number of Start of Bottom Bar. 2556 * barLeft: Pixel Number of End of Left Bar. 2557 * barRight: Pixel Number of Start of Right Bar. */ 2558 hdmi_info.bits.bar_top = stream->timing.v_border_top; 2559 hdmi_info.bits.bar_bottom = (stream->timing.v_total 2560 - stream->timing.v_border_bottom + 1); 2561 hdmi_info.bits.bar_left = stream->timing.h_border_left; 2562 hdmi_info.bits.bar_right = (stream->timing.h_total 2563 - stream->timing.h_border_right + 1); 2564 2565 /* Additional Colorimetry Extension 2566 * Used in conduction with C0-C1 and EC0-EC2 2567 * 0 = DCI-P3 RGB (D65) 2568 * 1 = DCI-P3 RGB (theater) 2569 */ 2570 hdmi_info.bits.ACE0_ACE3 = 0; 2571 2572 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ 2573 check_sum = &hdmi_info.packet_raw_data.sb[0]; 2574 2575 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version; 2576 2577 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++) 2578 *check_sum += hdmi_info.packet_raw_data.sb[byte_index]; 2579 2580 /* one byte complement */ 2581 *check_sum = (uint8_t) (0x100 - *check_sum); 2582 2583 /* Store in hw_path_mode */ 2584 info_packet->hb0 = hdmi_info.packet_raw_data.hb0; 2585 info_packet->hb1 = hdmi_info.packet_raw_data.hb1; 2586 info_packet->hb2 = hdmi_info.packet_raw_data.hb2; 2587 2588 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++) 2589 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index]; 2590 2591 info_packet->valid = true; 2592 } 2593 2594 static void set_vendor_info_packet( 2595 struct dc_info_packet *info_packet, 2596 struct dc_stream_state *stream) 2597 { 2598 /* SPD info packet for FreeSync */ 2599 2600 /* Check if Freesync is supported. Return if false. If true, 2601 * set the corresponding bit in the info packet 2602 */ 2603 if (!stream->vsp_infopacket.valid) 2604 return; 2605 2606 *info_packet = stream->vsp_infopacket; 2607 } 2608 2609 static void set_spd_info_packet( 2610 struct dc_info_packet *info_packet, 2611 struct dc_stream_state *stream) 2612 { 2613 /* SPD info packet for FreeSync */ 2614 2615 /* Check if Freesync is supported. Return if false. If true, 2616 * set the corresponding bit in the info packet 2617 */ 2618 if (!stream->vrr_infopacket.valid) 2619 return; 2620 2621 *info_packet = stream->vrr_infopacket; 2622 } 2623 2624 static void set_hdr_static_info_packet( 2625 struct dc_info_packet *info_packet, 2626 struct dc_stream_state *stream) 2627 { 2628 /* HDR Static Metadata info packet for HDR10 */ 2629 2630 if (!stream->hdr_static_metadata.valid || 2631 stream->use_dynamic_meta) 2632 return; 2633 2634 *info_packet = stream->hdr_static_metadata; 2635 } 2636 2637 static void set_vsc_info_packet( 2638 struct dc_info_packet *info_packet, 2639 struct dc_stream_state *stream) 2640 { 2641 if (!stream->vsc_infopacket.valid) 2642 return; 2643 2644 *info_packet = stream->vsc_infopacket; 2645 } 2646 2647 void dc_resource_state_destruct(struct dc_state *context) 2648 { 2649 int i, j; 2650 2651 for (i = 0; i < context->stream_count; i++) { 2652 for (j = 0; j < context->stream_status[i].plane_count; j++) 2653 dc_plane_state_release( 2654 context->stream_status[i].plane_states[j]); 2655 2656 context->stream_status[i].plane_count = 0; 2657 dc_stream_release(context->streams[i]); 2658 context->streams[i] = NULL; 2659 } 2660 context->stream_count = 0; 2661 } 2662 2663 void dc_resource_state_copy_construct( 2664 const struct dc_state *src_ctx, 2665 struct dc_state *dst_ctx) 2666 { 2667 int i, j; 2668 struct kref refcount = dst_ctx->refcount; 2669 2670 *dst_ctx = *src_ctx; 2671 2672 for (i = 0; i < MAX_PIPES; i++) { 2673 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; 2674 2675 if (cur_pipe->top_pipe) 2676 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; 2677 2678 if (cur_pipe->bottom_pipe) 2679 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; 2680 2681 if (cur_pipe->next_odm_pipe) 2682 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; 2683 2684 if (cur_pipe->prev_odm_pipe) 2685 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; 2686 } 2687 2688 for (i = 0; i < dst_ctx->stream_count; i++) { 2689 dc_stream_retain(dst_ctx->streams[i]); 2690 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) 2691 dc_plane_state_retain( 2692 dst_ctx->stream_status[i].plane_states[j]); 2693 } 2694 2695 /* context refcount should not be overridden */ 2696 dst_ctx->refcount = refcount; 2697 2698 } 2699 2700 struct clock_source *dc_resource_find_first_free_pll( 2701 struct resource_context *res_ctx, 2702 const struct resource_pool *pool) 2703 { 2704 int i; 2705 2706 for (i = 0; i < pool->clk_src_count; ++i) { 2707 if (res_ctx->clock_source_ref_count[i] == 0) 2708 return pool->clock_sources[i]; 2709 } 2710 2711 return NULL; 2712 } 2713 2714 void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 2715 { 2716 enum signal_type signal = SIGNAL_TYPE_NONE; 2717 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; 2718 2719 /* default all packets to invalid */ 2720 info->avi.valid = false; 2721 info->gamut.valid = false; 2722 info->vendor.valid = false; 2723 info->spd.valid = false; 2724 info->hdrsmd.valid = false; 2725 info->vsc.valid = false; 2726 2727 signal = pipe_ctx->stream->signal; 2728 2729 /* HDMi and DP have different info packets*/ 2730 if (dc_is_hdmi_signal(signal)) { 2731 set_avi_info_frame(&info->avi, pipe_ctx); 2732 2733 set_vendor_info_packet(&info->vendor, pipe_ctx->stream); 2734 2735 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2736 2737 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 2738 2739 } else if (dc_is_dp_signal(signal)) { 2740 set_vsc_info_packet(&info->vsc, pipe_ctx->stream); 2741 2742 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2743 2744 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 2745 } 2746 2747 patch_gamut_packet_checksum(&info->gamut); 2748 } 2749 2750 enum dc_status resource_map_clock_resources( 2751 const struct dc *dc, 2752 struct dc_state *context, 2753 struct dc_stream_state *stream) 2754 { 2755 /* acquire new resources */ 2756 const struct resource_pool *pool = dc->res_pool; 2757 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 2758 &context->res_ctx, stream); 2759 2760 if (!pipe_ctx) 2761 return DC_ERROR_UNEXPECTED; 2762 2763 if (dc_is_dp_signal(pipe_ctx->stream->signal) 2764 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 2765 pipe_ctx->clock_source = pool->dp_clock_source; 2766 else { 2767 pipe_ctx->clock_source = NULL; 2768 2769 if (!dc->config.disable_disp_pll_sharing) 2770 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing( 2771 &context->res_ctx, 2772 pipe_ctx); 2773 2774 if (pipe_ctx->clock_source == NULL) 2775 pipe_ctx->clock_source = 2776 dc_resource_find_first_free_pll( 2777 &context->res_ctx, 2778 pool); 2779 } 2780 2781 if (pipe_ctx->clock_source == NULL) 2782 return DC_NO_CLOCK_SOURCE_RESOURCE; 2783 2784 resource_reference_clock_source( 2785 &context->res_ctx, pool, 2786 pipe_ctx->clock_source); 2787 2788 return DC_OK; 2789 } 2790 2791 /* 2792 * Note: We need to disable output if clock sources change, 2793 * since bios does optimization and doesn't apply if changing 2794 * PHY when not already disabled. 2795 */ 2796 bool pipe_need_reprogram( 2797 struct pipe_ctx *pipe_ctx_old, 2798 struct pipe_ctx *pipe_ctx) 2799 { 2800 if (!pipe_ctx_old->stream) 2801 return false; 2802 2803 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) 2804 return true; 2805 2806 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) 2807 return true; 2808 2809 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) 2810 return true; 2811 2812 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source 2813 && pipe_ctx_old->stream != pipe_ctx->stream) 2814 return true; 2815 2816 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) 2817 return true; 2818 2819 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) 2820 return true; 2821 2822 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off) 2823 return true; 2824 2825 if (false == pipe_ctx_old->stream->link->link_state_valid && 2826 false == pipe_ctx_old->stream->dpms_off) 2827 return true; 2828 2829 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) 2830 return true; 2831 2832 #if defined(CONFIG_DRM_AMD_DC_DCN) 2833 if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) 2834 return true; 2835 #endif 2836 2837 /* DIG link encoder resource assignment for stream changed. */ 2838 if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) { 2839 bool need_reprogram = false; 2840 struct dc *dc = pipe_ctx_old->stream->ctx->dc; 2841 enum link_enc_cfg_mode mode = dc->current_state->res_ctx.link_enc_cfg_ctx.mode; 2842 2843 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY; 2844 if (link_enc_cfg_get_link_enc_used_by_stream(dc, pipe_ctx_old->stream) != pipe_ctx->stream->link_enc) 2845 need_reprogram = true; 2846 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = mode; 2847 2848 return need_reprogram; 2849 } 2850 2851 return false; 2852 } 2853 2854 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 2855 struct bit_depth_reduction_params *fmt_bit_depth) 2856 { 2857 enum dc_dither_option option = stream->dither_option; 2858 enum dc_pixel_encoding pixel_encoding = 2859 stream->timing.pixel_encoding; 2860 2861 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); 2862 2863 if (option == DITHER_OPTION_DEFAULT) { 2864 switch (stream->timing.display_color_depth) { 2865 case COLOR_DEPTH_666: 2866 option = DITHER_OPTION_SPATIAL6; 2867 break; 2868 case COLOR_DEPTH_888: 2869 option = DITHER_OPTION_SPATIAL8; 2870 break; 2871 case COLOR_DEPTH_101010: 2872 option = DITHER_OPTION_SPATIAL10; 2873 break; 2874 default: 2875 option = DITHER_OPTION_DISABLE; 2876 } 2877 } 2878 2879 if (option == DITHER_OPTION_DISABLE) 2880 return; 2881 2882 if (option == DITHER_OPTION_TRUN6) { 2883 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2884 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; 2885 } else if (option == DITHER_OPTION_TRUN8 || 2886 option == DITHER_OPTION_TRUN8_SPATIAL6 || 2887 option == DITHER_OPTION_TRUN8_FM6) { 2888 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2889 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; 2890 } else if (option == DITHER_OPTION_TRUN10 || 2891 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2892 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2893 option == DITHER_OPTION_TRUN10_FM8 || 2894 option == DITHER_OPTION_TRUN10_FM6 || 2895 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2896 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2897 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2898 } 2899 2900 /* special case - Formatter can only reduce by 4 bits at most. 2901 * When reducing from 12 to 6 bits, 2902 * HW recommends we use trunc with round mode 2903 * (if we did nothing, trunc to 10 bits would be used) 2904 * note that any 12->10 bit reduction is ignored prior to DCE8, 2905 * as the input was 10 bits. 2906 */ 2907 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2908 option == DITHER_OPTION_SPATIAL6 || 2909 option == DITHER_OPTION_FM6) { 2910 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2911 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2912 fmt_bit_depth->flags.TRUNCATE_MODE = 1; 2913 } 2914 2915 /* spatial dither 2916 * note that spatial modes 1-3 are never used 2917 */ 2918 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2919 option == DITHER_OPTION_SPATIAL6 || 2920 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2921 option == DITHER_OPTION_TRUN8_SPATIAL6) { 2922 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2923 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; 2924 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2925 fmt_bit_depth->flags.RGB_RANDOM = 2926 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2927 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || 2928 option == DITHER_OPTION_SPATIAL8 || 2929 option == DITHER_OPTION_SPATIAL8_FM6 || 2930 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2931 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2932 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2933 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; 2934 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2935 fmt_bit_depth->flags.RGB_RANDOM = 2936 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2937 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || 2938 option == DITHER_OPTION_SPATIAL10 || 2939 option == DITHER_OPTION_SPATIAL10_FM8 || 2940 option == DITHER_OPTION_SPATIAL10_FM6) { 2941 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2942 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; 2943 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2944 fmt_bit_depth->flags.RGB_RANDOM = 2945 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2946 } 2947 2948 if (option == DITHER_OPTION_SPATIAL6 || 2949 option == DITHER_OPTION_SPATIAL8 || 2950 option == DITHER_OPTION_SPATIAL10) { 2951 fmt_bit_depth->flags.FRAME_RANDOM = 0; 2952 } else { 2953 fmt_bit_depth->flags.FRAME_RANDOM = 1; 2954 } 2955 2956 ////////////////////// 2957 //// temporal dither 2958 ////////////////////// 2959 if (option == DITHER_OPTION_FM6 || 2960 option == DITHER_OPTION_SPATIAL8_FM6 || 2961 option == DITHER_OPTION_SPATIAL10_FM6 || 2962 option == DITHER_OPTION_TRUN10_FM6 || 2963 option == DITHER_OPTION_TRUN8_FM6 || 2964 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2965 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2966 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; 2967 } else if (option == DITHER_OPTION_FM8 || 2968 option == DITHER_OPTION_SPATIAL10_FM8 || 2969 option == DITHER_OPTION_TRUN10_FM8) { 2970 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2971 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; 2972 } else if (option == DITHER_OPTION_FM10) { 2973 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2974 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; 2975 } 2976 2977 fmt_bit_depth->pixel_encoding = pixel_encoding; 2978 } 2979 2980 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) 2981 { 2982 struct dc_link *link = stream->link; 2983 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 2984 enum dc_status res = DC_OK; 2985 2986 calculate_phy_pix_clks(stream); 2987 2988 if (!tg->funcs->validate_timing(tg, &stream->timing)) 2989 res = DC_FAIL_CONTROLLER_VALIDATE; 2990 2991 if (res == DC_OK) { 2992 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 2993 !link->link_enc->funcs->validate_output_with_stream( 2994 link->link_enc, stream)) 2995 res = DC_FAIL_ENC_VALIDATE; 2996 } 2997 2998 /* TODO: validate audio ASIC caps, encoder */ 2999 3000 if (res == DC_OK) 3001 res = dc_link_validate_mode_timing(stream, 3002 link, 3003 &stream->timing); 3004 3005 return res; 3006 } 3007 3008 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) 3009 { 3010 enum dc_status res = DC_OK; 3011 3012 /* check if surface has invalid dimensions */ 3013 if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 || 3014 plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0) 3015 return DC_FAIL_SURFACE_VALIDATE; 3016 3017 /* TODO For now validates pixel format only */ 3018 if (dc->res_pool->funcs->validate_plane) 3019 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps); 3020 3021 return res; 3022 } 3023 3024 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format) 3025 { 3026 switch (format) { 3027 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 3028 return 8; 3029 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 3030 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 3031 return 12; 3032 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 3033 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 3034 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 3035 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 3036 return 16; 3037 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 3038 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 3039 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 3040 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 3041 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 3042 #if defined(CONFIG_DRM_AMD_DC_DCN) 3043 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 3044 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 3045 #endif 3046 return 32; 3047 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 3048 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 3049 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 3050 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 3051 return 64; 3052 default: 3053 ASSERT_CRITICAL(false); 3054 return -1; 3055 } 3056 } 3057 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes) 3058 { 3059 if (modes) { 3060 if (modes->sample_rates.rate.RATE_192) 3061 return 192000; 3062 if (modes->sample_rates.rate.RATE_176_4) 3063 return 176400; 3064 if (modes->sample_rates.rate.RATE_96) 3065 return 96000; 3066 if (modes->sample_rates.rate.RATE_88_2) 3067 return 88200; 3068 if (modes->sample_rates.rate.RATE_48) 3069 return 48000; 3070 if (modes->sample_rates.rate.RATE_44_1) 3071 return 44100; 3072 if (modes->sample_rates.rate.RATE_32) 3073 return 32000; 3074 } 3075 /*original logic when no audio info*/ 3076 return 441000; 3077 } 3078 3079 void get_audio_check(struct audio_info *aud_modes, 3080 struct audio_check *audio_chk) 3081 { 3082 unsigned int i; 3083 unsigned int max_sample_rate = 0; 3084 3085 if (aud_modes) { 3086 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/ 3087 3088 audio_chk->max_audiosample_rate = 0; 3089 for (i = 0; i < aud_modes->mode_count; i++) { 3090 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]); 3091 if (audio_chk->max_audiosample_rate < max_sample_rate) 3092 audio_chk->max_audiosample_rate = max_sample_rate; 3093 /*dts takes the same as type 2: AP = 0.25*/ 3094 } 3095 /*check which one take more bandwidth*/ 3096 if (audio_chk->max_audiosample_rate > 192000) 3097 audio_chk->audio_packet_type = 0x9;/*AP =1*/ 3098 audio_chk->acat = 0;/*not support*/ 3099 } 3100 } 3101 3102 #if defined(CONFIG_DRM_AMD_DC_DCN) 3103 struct hpo_dp_link_encoder *resource_get_unused_hpo_dp_link_encoder( 3104 const struct resource_pool *pool) 3105 { 3106 uint8_t i; 3107 struct hpo_dp_link_encoder *enc = NULL; 3108 3109 ASSERT(pool->hpo_dp_link_enc_count <= MAX_HPO_DP2_LINK_ENCODERS); 3110 3111 for (i = 0; i < pool->hpo_dp_link_enc_count; i++) { 3112 if (pool->hpo_dp_link_enc[i]->transmitter == TRANSMITTER_UNKNOWN) { 3113 enc = pool->hpo_dp_link_enc[i]; 3114 break; 3115 } 3116 } 3117 3118 return enc; 3119 } 3120 #endif 3121