1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "link_encoder.h" 33 #include "stream_encoder.h" 34 #include "opp.h" 35 #include "timing_generator.h" 36 #include "transform.h" 37 #include "dccg.h" 38 #include "dchubbub.h" 39 #include "dpp.h" 40 #include "core_types.h" 41 #include "set_mode_types.h" 42 #include "virtual/virtual_stream_encoder.h" 43 #include "dpcd_defs.h" 44 45 #if defined(CONFIG_DRM_AMD_DC_SI) 46 #include "dce60/dce60_resource.h" 47 #endif 48 #include "dce80/dce80_resource.h" 49 #include "dce100/dce100_resource.h" 50 #include "dce110/dce110_resource.h" 51 #include "dce112/dce112_resource.h" 52 #include "dce120/dce120_resource.h" 53 #if defined(CONFIG_DRM_AMD_DC_DCN) 54 #include "dcn10/dcn10_resource.h" 55 #include "dcn20/dcn20_resource.h" 56 #include "dcn21/dcn21_resource.h" 57 #include "dcn30/dcn30_resource.h" 58 #include "dcn301/dcn301_resource.h" 59 #include "dcn302/dcn302_resource.h" 60 #include "dcn303/dcn303_resource.h" 61 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 62 #include "../dcn31/dcn31_resource.h" 63 #endif 64 #endif 65 66 #define DC_LOGGER_INIT(logger) 67 68 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 69 { 70 enum dce_version dc_version = DCE_VERSION_UNKNOWN; 71 switch (asic_id.chip_family) { 72 73 #if defined(CONFIG_DRM_AMD_DC_SI) 74 case FAMILY_SI: 75 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) || 76 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) || 77 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev)) 78 dc_version = DCE_VERSION_6_0; 79 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev)) 80 dc_version = DCE_VERSION_6_4; 81 else 82 dc_version = DCE_VERSION_6_1; 83 break; 84 #endif 85 case FAMILY_CI: 86 dc_version = DCE_VERSION_8_0; 87 break; 88 case FAMILY_KV: 89 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) || 90 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) || 91 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev)) 92 dc_version = DCE_VERSION_8_3; 93 else 94 dc_version = DCE_VERSION_8_1; 95 break; 96 case FAMILY_CZ: 97 dc_version = DCE_VERSION_11_0; 98 break; 99 100 case FAMILY_VI: 101 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || 102 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { 103 dc_version = DCE_VERSION_10_0; 104 break; 105 } 106 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || 107 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || 108 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { 109 dc_version = DCE_VERSION_11_2; 110 } 111 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) 112 dc_version = DCE_VERSION_11_22; 113 break; 114 case FAMILY_AI: 115 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev)) 116 dc_version = DCE_VERSION_12_1; 117 else 118 dc_version = DCE_VERSION_12_0; 119 break; 120 #if defined(CONFIG_DRM_AMD_DC_DCN) 121 case FAMILY_RV: 122 dc_version = DCN_VERSION_1_0; 123 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) 124 dc_version = DCN_VERSION_1_01; 125 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) 126 dc_version = DCN_VERSION_2_1; 127 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) 128 dc_version = DCN_VERSION_2_1; 129 break; 130 131 case FAMILY_NV: 132 dc_version = DCN_VERSION_2_0; 133 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) 134 dc_version = DCN_VERSION_3_0; 135 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) 136 dc_version = DCN_VERSION_3_02; 137 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) 138 dc_version = DCN_VERSION_3_03; 139 break; 140 141 case FAMILY_VGH: 142 dc_version = DCN_VERSION_3_01; 143 break; 144 #endif 145 146 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 147 case FAMILY_YELLOW_CARP: 148 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) 149 dc_version = DCN_VERSION_3_1; 150 break; 151 #endif 152 153 default: 154 dc_version = DCE_VERSION_UNKNOWN; 155 break; 156 } 157 return dc_version; 158 } 159 160 struct resource_pool *dc_create_resource_pool(struct dc *dc, 161 const struct dc_init_data *init_data, 162 enum dce_version dc_version) 163 { 164 struct resource_pool *res_pool = NULL; 165 166 switch (dc_version) { 167 #if defined(CONFIG_DRM_AMD_DC_SI) 168 case DCE_VERSION_6_0: 169 res_pool = dce60_create_resource_pool( 170 init_data->num_virtual_links, dc); 171 break; 172 case DCE_VERSION_6_1: 173 res_pool = dce61_create_resource_pool( 174 init_data->num_virtual_links, dc); 175 break; 176 case DCE_VERSION_6_4: 177 res_pool = dce64_create_resource_pool( 178 init_data->num_virtual_links, dc); 179 break; 180 #endif 181 case DCE_VERSION_8_0: 182 res_pool = dce80_create_resource_pool( 183 init_data->num_virtual_links, dc); 184 break; 185 case DCE_VERSION_8_1: 186 res_pool = dce81_create_resource_pool( 187 init_data->num_virtual_links, dc); 188 break; 189 case DCE_VERSION_8_3: 190 res_pool = dce83_create_resource_pool( 191 init_data->num_virtual_links, dc); 192 break; 193 case DCE_VERSION_10_0: 194 res_pool = dce100_create_resource_pool( 195 init_data->num_virtual_links, dc); 196 break; 197 case DCE_VERSION_11_0: 198 res_pool = dce110_create_resource_pool( 199 init_data->num_virtual_links, dc, 200 init_data->asic_id); 201 break; 202 case DCE_VERSION_11_2: 203 case DCE_VERSION_11_22: 204 res_pool = dce112_create_resource_pool( 205 init_data->num_virtual_links, dc); 206 break; 207 case DCE_VERSION_12_0: 208 case DCE_VERSION_12_1: 209 res_pool = dce120_create_resource_pool( 210 init_data->num_virtual_links, dc); 211 break; 212 213 #if defined(CONFIG_DRM_AMD_DC_DCN) 214 case DCN_VERSION_1_0: 215 case DCN_VERSION_1_01: 216 res_pool = dcn10_create_resource_pool(init_data, dc); 217 break; 218 case DCN_VERSION_2_0: 219 res_pool = dcn20_create_resource_pool(init_data, dc); 220 break; 221 case DCN_VERSION_2_1: 222 res_pool = dcn21_create_resource_pool(init_data, dc); 223 break; 224 case DCN_VERSION_3_0: 225 res_pool = dcn30_create_resource_pool(init_data, dc); 226 break; 227 case DCN_VERSION_3_01: 228 res_pool = dcn301_create_resource_pool(init_data, dc); 229 break; 230 case DCN_VERSION_3_02: 231 res_pool = dcn302_create_resource_pool(init_data, dc); 232 break; 233 case DCN_VERSION_3_03: 234 res_pool = dcn303_create_resource_pool(init_data, dc); 235 break; 236 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 237 case DCN_VERSION_3_1: 238 res_pool = dcn31_create_resource_pool(init_data, dc); 239 break; 240 #endif 241 #endif 242 default: 243 break; 244 } 245 246 if (res_pool != NULL) { 247 if (dc->ctx->dc_bios->fw_info_valid) { 248 res_pool->ref_clocks.xtalin_clock_inKhz = 249 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 250 /* initialize with firmware data first, no all 251 * ASIC have DCCG SW component. FPGA or 252 * simulation need initialization of 253 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz 254 * with xtalin_clock_inKhz 255 */ 256 res_pool->ref_clocks.dccg_ref_clock_inKhz = 257 res_pool->ref_clocks.xtalin_clock_inKhz; 258 res_pool->ref_clocks.dchub_ref_clock_inKhz = 259 res_pool->ref_clocks.xtalin_clock_inKhz; 260 } else 261 ASSERT_CRITICAL(false); 262 } 263 264 return res_pool; 265 } 266 267 void dc_destroy_resource_pool(struct dc *dc) 268 { 269 if (dc) { 270 if (dc->res_pool) 271 dc->res_pool->funcs->destroy(&dc->res_pool); 272 273 kfree(dc->hwseq); 274 } 275 } 276 277 static void update_num_audio( 278 const struct resource_straps *straps, 279 unsigned int *num_audio, 280 struct audio_support *aud_support) 281 { 282 aud_support->dp_audio = true; 283 aud_support->hdmi_audio_native = false; 284 aud_support->hdmi_audio_on_dongle = false; 285 286 if (straps->hdmi_disable == 0) { 287 if (straps->dc_pinstraps_audio & 0x2) { 288 aud_support->hdmi_audio_on_dongle = true; 289 aud_support->hdmi_audio_native = true; 290 } 291 } 292 293 switch (straps->audio_stream_number) { 294 case 0: /* multi streams supported */ 295 break; 296 case 1: /* multi streams not supported */ 297 *num_audio = 1; 298 break; 299 default: 300 DC_ERR("DC: unexpected audio fuse!\n"); 301 } 302 } 303 304 bool resource_construct( 305 unsigned int num_virtual_links, 306 struct dc *dc, 307 struct resource_pool *pool, 308 const struct resource_create_funcs *create_funcs) 309 { 310 struct dc_context *ctx = dc->ctx; 311 const struct resource_caps *caps = pool->res_cap; 312 int i; 313 unsigned int num_audio = caps->num_audio; 314 struct resource_straps straps = {0}; 315 316 if (create_funcs->read_dce_straps) 317 create_funcs->read_dce_straps(dc->ctx, &straps); 318 319 pool->audio_count = 0; 320 if (create_funcs->create_audio) { 321 /* find the total number of streams available via the 322 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 323 * registers (one for each pin) starting from pin 1 324 * up to the max number of audio pins. 325 * We stop on the first pin where 326 * PORT_CONNECTIVITY == 1 (as instructed by HW team). 327 */ 328 update_num_audio(&straps, &num_audio, &pool->audio_support); 329 for (i = 0; i < caps->num_audio; i++) { 330 struct audio *aud = create_funcs->create_audio(ctx, i); 331 332 if (aud == NULL) { 333 DC_ERR("DC: failed to create audio!\n"); 334 return false; 335 } 336 if (!aud->funcs->endpoint_valid(aud)) { 337 aud->funcs->destroy(&aud); 338 break; 339 } 340 pool->audios[i] = aud; 341 pool->audio_count++; 342 } 343 } 344 345 pool->stream_enc_count = 0; 346 if (create_funcs->create_stream_encoder) { 347 for (i = 0; i < caps->num_stream_encoder; i++) { 348 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); 349 if (pool->stream_enc[i] == NULL) 350 DC_ERR("DC: failed to create stream_encoder!\n"); 351 pool->stream_enc_count++; 352 } 353 } 354 355 #if defined(CONFIG_DRM_AMD_DC_DCN) 356 for (i = 0; i < caps->num_mpc_3dlut; i++) { 357 pool->mpc_lut[i] = dc_create_3dlut_func(); 358 if (pool->mpc_lut[i] == NULL) 359 DC_ERR("DC: failed to create MPC 3dlut!\n"); 360 pool->mpc_shaper[i] = dc_create_transfer_func(); 361 if (pool->mpc_shaper[i] == NULL) 362 DC_ERR("DC: failed to create MPC shaper!\n"); 363 } 364 #endif 365 dc->caps.dynamic_audio = false; 366 if (pool->audio_count < pool->stream_enc_count) { 367 dc->caps.dynamic_audio = true; 368 } 369 for (i = 0; i < num_virtual_links; i++) { 370 pool->stream_enc[pool->stream_enc_count] = 371 virtual_stream_encoder_create( 372 ctx, ctx->dc_bios); 373 if (pool->stream_enc[pool->stream_enc_count] == NULL) { 374 DC_ERR("DC: failed to create stream_encoder!\n"); 375 return false; 376 } 377 pool->stream_enc_count++; 378 } 379 380 dc->hwseq = create_funcs->create_hwseq(ctx); 381 382 return true; 383 } 384 static int find_matching_clock_source( 385 const struct resource_pool *pool, 386 struct clock_source *clock_source) 387 { 388 389 int i; 390 391 for (i = 0; i < pool->clk_src_count; i++) { 392 if (pool->clock_sources[i] == clock_source) 393 return i; 394 } 395 return -1; 396 } 397 398 void resource_unreference_clock_source( 399 struct resource_context *res_ctx, 400 const struct resource_pool *pool, 401 struct clock_source *clock_source) 402 { 403 int i = find_matching_clock_source(pool, clock_source); 404 405 if (i > -1) 406 res_ctx->clock_source_ref_count[i]--; 407 408 if (pool->dp_clock_source == clock_source) 409 res_ctx->dp_clock_source_ref_count--; 410 } 411 412 void resource_reference_clock_source( 413 struct resource_context *res_ctx, 414 const struct resource_pool *pool, 415 struct clock_source *clock_source) 416 { 417 int i = find_matching_clock_source(pool, clock_source); 418 419 if (i > -1) 420 res_ctx->clock_source_ref_count[i]++; 421 422 if (pool->dp_clock_source == clock_source) 423 res_ctx->dp_clock_source_ref_count++; 424 } 425 426 int resource_get_clock_source_reference( 427 struct resource_context *res_ctx, 428 const struct resource_pool *pool, 429 struct clock_source *clock_source) 430 { 431 int i = find_matching_clock_source(pool, clock_source); 432 433 if (i > -1) 434 return res_ctx->clock_source_ref_count[i]; 435 436 if (pool->dp_clock_source == clock_source) 437 return res_ctx->dp_clock_source_ref_count; 438 439 return -1; 440 } 441 442 bool resource_are_vblanks_synchronizable( 443 struct dc_stream_state *stream1, 444 struct dc_stream_state *stream2) 445 { 446 uint32_t base60_refresh_rates[] = {10, 20, 5}; 447 uint8_t i; 448 uint8_t rr_count = sizeof(base60_refresh_rates)/sizeof(base60_refresh_rates[0]); 449 uint64_t frame_time_diff; 450 451 if (stream1->ctx->dc->config.vblank_alignment_dto_params && 452 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 && 453 dc_is_dp_signal(stream1->signal) && 454 dc_is_dp_signal(stream2->signal) && 455 false == stream1->has_non_synchronizable_pclk && 456 false == stream2->has_non_synchronizable_pclk && 457 stream1->timing.flags.VBLANK_SYNCHRONIZABLE && 458 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) { 459 /* disable refresh rates higher than 60Hz for now */ 460 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/ 461 stream1->timing.v_total > 60) 462 return false; 463 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/ 464 stream2->timing.v_total > 60) 465 return false; 466 frame_time_diff = (uint64_t)10000 * 467 stream1->timing.h_total * 468 stream1->timing.v_total * 469 stream2->timing.pix_clk_100hz; 470 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz); 471 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total); 472 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total); 473 for (i = 0; i < rr_count; i++) { 474 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000; 475 476 if (diff < 0) 477 diff = -diff; 478 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff) 479 return true; 480 } 481 } 482 return false; 483 } 484 485 bool resource_are_streams_timing_synchronizable( 486 struct dc_stream_state *stream1, 487 struct dc_stream_state *stream2) 488 { 489 if (stream1->timing.h_total != stream2->timing.h_total) 490 return false; 491 492 if (stream1->timing.v_total != stream2->timing.v_total) 493 return false; 494 495 if (stream1->timing.h_addressable 496 != stream2->timing.h_addressable) 497 return false; 498 499 if (stream1->timing.v_addressable 500 != stream2->timing.v_addressable) 501 return false; 502 503 if (stream1->timing.v_front_porch 504 != stream2->timing.v_front_porch) 505 return false; 506 507 if (stream1->timing.pix_clk_100hz 508 != stream2->timing.pix_clk_100hz) 509 return false; 510 511 if (stream1->clamping.c_depth != stream2->clamping.c_depth) 512 return false; 513 514 if (stream1->phy_pix_clk != stream2->phy_pix_clk 515 && (!dc_is_dp_signal(stream1->signal) 516 || !dc_is_dp_signal(stream2->signal))) 517 return false; 518 519 if (stream1->view_format != stream2->view_format) 520 return false; 521 522 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param) 523 return false; 524 525 return true; 526 } 527 static bool is_dp_and_hdmi_sharable( 528 struct dc_stream_state *stream1, 529 struct dc_stream_state *stream2) 530 { 531 if (stream1->ctx->dc->caps.disable_dp_clk_share) 532 return false; 533 534 if (stream1->clamping.c_depth != COLOR_DEPTH_888 || 535 stream2->clamping.c_depth != COLOR_DEPTH_888) 536 return false; 537 538 return true; 539 540 } 541 542 static bool is_sharable_clk_src( 543 const struct pipe_ctx *pipe_with_clk_src, 544 const struct pipe_ctx *pipe) 545 { 546 if (pipe_with_clk_src->clock_source == NULL) 547 return false; 548 549 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) 550 return false; 551 552 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) || 553 (dc_is_dp_signal(pipe->stream->signal) && 554 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream, 555 pipe->stream))) 556 return false; 557 558 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) 559 && dc_is_dual_link_signal(pipe->stream->signal)) 560 return false; 561 562 if (dc_is_hdmi_signal(pipe->stream->signal) 563 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal)) 564 return false; 565 566 if (!resource_are_streams_timing_synchronizable( 567 pipe_with_clk_src->stream, pipe->stream)) 568 return false; 569 570 return true; 571 } 572 573 struct clock_source *resource_find_used_clk_src_for_sharing( 574 struct resource_context *res_ctx, 575 struct pipe_ctx *pipe_ctx) 576 { 577 int i; 578 579 for (i = 0; i < MAX_PIPES; i++) { 580 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) 581 return res_ctx->pipe_ctx[i].clock_source; 582 } 583 584 return NULL; 585 } 586 587 static enum pixel_format convert_pixel_format_to_dalsurface( 588 enum surface_pixel_format surface_pixel_format) 589 { 590 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 591 592 switch (surface_pixel_format) { 593 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 594 dal_pixel_format = PIXEL_FORMAT_INDEX8; 595 break; 596 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 597 dal_pixel_format = PIXEL_FORMAT_RGB565; 598 break; 599 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 600 dal_pixel_format = PIXEL_FORMAT_RGB565; 601 break; 602 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 603 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 604 break; 605 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 606 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 607 break; 608 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 609 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 610 break; 611 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 612 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 613 break; 614 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 615 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS; 616 break; 617 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 618 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 619 dal_pixel_format = PIXEL_FORMAT_FP16; 620 break; 621 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 622 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 623 dal_pixel_format = PIXEL_FORMAT_420BPP8; 624 break; 625 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 626 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 627 dal_pixel_format = PIXEL_FORMAT_420BPP10; 628 break; 629 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 630 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 631 default: 632 dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 633 break; 634 } 635 return dal_pixel_format; 636 } 637 638 static inline void get_vp_scan_direction( 639 enum dc_rotation_angle rotation, 640 bool horizontal_mirror, 641 bool *orthogonal_rotation, 642 bool *flip_vert_scan_dir, 643 bool *flip_horz_scan_dir) 644 { 645 *orthogonal_rotation = false; 646 *flip_vert_scan_dir = false; 647 *flip_horz_scan_dir = false; 648 if (rotation == ROTATION_ANGLE_180) { 649 *flip_vert_scan_dir = true; 650 *flip_horz_scan_dir = true; 651 } else if (rotation == ROTATION_ANGLE_90) { 652 *orthogonal_rotation = true; 653 *flip_horz_scan_dir = true; 654 } else if (rotation == ROTATION_ANGLE_270) { 655 *orthogonal_rotation = true; 656 *flip_vert_scan_dir = true; 657 } 658 659 if (horizontal_mirror) 660 *flip_horz_scan_dir = !*flip_horz_scan_dir; 661 } 662 663 int get_num_mpc_splits(struct pipe_ctx *pipe) 664 { 665 int mpc_split_count = 0; 666 struct pipe_ctx *other_pipe = pipe->bottom_pipe; 667 668 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 669 mpc_split_count++; 670 other_pipe = other_pipe->bottom_pipe; 671 } 672 other_pipe = pipe->top_pipe; 673 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 674 mpc_split_count++; 675 other_pipe = other_pipe->top_pipe; 676 } 677 678 return mpc_split_count; 679 } 680 681 int get_num_odm_splits(struct pipe_ctx *pipe) 682 { 683 int odm_split_count = 0; 684 struct pipe_ctx *next_pipe = pipe->next_odm_pipe; 685 while (next_pipe) { 686 odm_split_count++; 687 next_pipe = next_pipe->next_odm_pipe; 688 } 689 pipe = pipe->prev_odm_pipe; 690 while (pipe) { 691 odm_split_count++; 692 pipe = pipe->prev_odm_pipe; 693 } 694 return odm_split_count; 695 } 696 697 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx) 698 { 699 *split_count = get_num_odm_splits(pipe_ctx); 700 *split_idx = 0; 701 if (*split_count == 0) { 702 /*Check for mpc split*/ 703 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe; 704 705 *split_count = get_num_mpc_splits(pipe_ctx); 706 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) { 707 (*split_idx)++; 708 split_pipe = split_pipe->top_pipe; 709 } 710 } else { 711 /*Get odm split index*/ 712 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe; 713 714 while (split_pipe) { 715 (*split_idx)++; 716 split_pipe = split_pipe->prev_odm_pipe; 717 } 718 } 719 } 720 721 /* 722 * This is a preliminary vp size calculation to allow us to check taps support. 723 * The result is completely overridden afterwards. 724 */ 725 static void calculate_viewport_size(struct pipe_ctx *pipe_ctx) 726 { 727 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 728 729 data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width)); 730 data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height)); 731 data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width)); 732 data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height)); 733 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 734 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { 735 swap(data->viewport.width, data->viewport.height); 736 swap(data->viewport_c.width, data->viewport_c.height); 737 } 738 } 739 740 static void calculate_recout(struct pipe_ctx *pipe_ctx) 741 { 742 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 743 const struct dc_stream_state *stream = pipe_ctx->stream; 744 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 745 struct rect surf_clip = plane_state->clip_rect; 746 bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; 747 int split_count, split_idx; 748 749 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 750 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 751 split_idx = 0; 752 753 /* 754 * Only the leftmost ODM pipe should be offset by a nonzero distance 755 */ 756 if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) { 757 data->recout.x = stream->dst.x; 758 if (stream->src.x < surf_clip.x) 759 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width 760 / stream->src.width; 761 } else 762 data->recout.x = 0; 763 764 if (stream->src.x > surf_clip.x) 765 surf_clip.width -= stream->src.x - surf_clip.x; 766 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width; 767 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width) 768 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x; 769 770 data->recout.y = stream->dst.y; 771 if (stream->src.y < surf_clip.y) 772 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height 773 / stream->src.height; 774 else if (stream->src.y > surf_clip.y) 775 surf_clip.height -= stream->src.y - surf_clip.y; 776 777 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height; 778 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height) 779 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y; 780 781 /* Handle h & v split */ 782 if (split_tb) { 783 ASSERT(data->recout.height % 2 == 0); 784 data->recout.height /= 2; 785 } else if (split_count) { 786 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) { 787 /* extra pixels in the division remainder need to go to pipes after 788 * the extra pixel index minus one(epimo) defined here as: 789 */ 790 int epimo = split_count - data->recout.width % (split_count + 1); 791 792 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx; 793 if (split_idx > epimo) 794 data->recout.x += split_idx - epimo - 1; 795 ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0); 796 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0); 797 } else { 798 /* odm */ 799 if (split_idx == split_count) { 800 /* rightmost pipe is the remainder recout */ 801 data->recout.width -= data->h_active * split_count - data->recout.x; 802 803 /* ODM combine cases with MPO we can get negative widths */ 804 if (data->recout.width < 0) 805 data->recout.width = 0; 806 807 data->recout.x = 0; 808 } else 809 data->recout.width = data->h_active - data->recout.x; 810 } 811 } 812 } 813 814 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) 815 { 816 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 817 const struct dc_stream_state *stream = pipe_ctx->stream; 818 struct rect surf_src = plane_state->src_rect; 819 const int in_w = stream->src.width; 820 const int in_h = stream->src.height; 821 const int out_w = stream->dst.width; 822 const int out_h = stream->dst.height; 823 824 /*Swap surf_src height and width since scaling ratios are in recout rotation*/ 825 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 826 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 827 swap(surf_src.height, surf_src.width); 828 829 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( 830 surf_src.width, 831 plane_state->dst_rect.width); 832 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( 833 surf_src.height, 834 plane_state->dst_rect.height); 835 836 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 837 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; 838 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 839 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; 840 841 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( 842 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); 843 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( 844 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); 845 846 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; 847 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; 848 849 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 850 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { 851 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; 852 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; 853 } 854 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate( 855 pipe_ctx->plane_res.scl_data.ratios.horz, 19); 856 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( 857 pipe_ctx->plane_res.scl_data.ratios.vert, 19); 858 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate( 859 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19); 860 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate( 861 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); 862 } 863 864 865 /* 866 * We completely calculate vp offset, size and inits here based entirely on scaling 867 * ratios and recout for pixel perfect pipe combine. 868 */ 869 static void calculate_init_and_vp( 870 bool flip_scan_dir, 871 int recout_offset_within_recout_full, 872 int recout_size, 873 int src_size, 874 int taps, 875 struct fixed31_32 ratio, 876 struct fixed31_32 *init, 877 int *vp_offset, 878 int *vp_size) 879 { 880 struct fixed31_32 temp; 881 int int_part; 882 883 /* 884 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout 885 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on. 886 * All following calculations are based on this logic. 887 * 888 * Init calculated according to formula: 889 * init = (scaling_ratio + number_of_taps + 1) / 2 890 * init_bot = init + scaling_ratio 891 * to get pixel perfect combine add the fraction from calculating vp offset 892 */ 893 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full); 894 *vp_offset = dc_fixpt_floor(temp); 895 temp.value &= 0xffffffff; 896 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int( 897 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19); 898 /* 899 * If viewport has non 0 offset and there are more taps than covered by init then 900 * we should decrease the offset and increase init so we are never sampling 901 * outside of viewport. 902 */ 903 int_part = dc_fixpt_floor(*init); 904 if (int_part < taps) { 905 int_part = taps - int_part; 906 if (int_part > *vp_offset) 907 int_part = *vp_offset; 908 *vp_offset -= int_part; 909 *init = dc_fixpt_add_int(*init, int_part); 910 } 911 /* 912 * If taps are sampling outside of viewport at end of recout and there are more pixels 913 * available in the surface we should increase the viewport size, regardless set vp to 914 * only what is used. 915 */ 916 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1)); 917 *vp_size = dc_fixpt_floor(temp); 918 if (*vp_size + *vp_offset > src_size) 919 *vp_size = src_size - *vp_offset; 920 921 /* We did all the math assuming we are scanning same direction as display does, 922 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction 923 * is flipped we simply need to calculate offset from the other side of plane. 924 * Note that outside of viewport all scaling hardware works in recout space. 925 */ 926 if (flip_scan_dir) 927 *vp_offset = src_size - *vp_offset - *vp_size; 928 } 929 930 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx) 931 { 932 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 933 const struct dc_stream_state *stream = pipe_ctx->stream; 934 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 935 struct rect src = plane_state->src_rect; 936 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 937 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 938 int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y; 939 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; 940 941 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 942 /* 943 * recout full is what the recout would have been if we didnt clip 944 * the source plane at all. We only care about left(ro_lb) and top(ro_tb) 945 * offsets of recout within recout full because those are the directions 946 * we scan from and therefore the only ones that affect inits. 947 */ 948 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) 949 * stream->dst.width / stream->src.width; 950 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) 951 * stream->dst.height / stream->src.height; 952 if (pipe_ctx->prev_odm_pipe && split_idx) 953 ro_lb = data->h_active * split_idx - recout_full_x; 954 else 955 ro_lb = data->recout.x - recout_full_x; 956 ro_tb = data->recout.y - recout_full_y; 957 ASSERT(ro_lb >= 0 && ro_tb >= 0); 958 959 /* 960 * Work in recout rotation since that requires less transformations 961 */ 962 get_vp_scan_direction( 963 plane_state->rotation, 964 plane_state->horizontal_mirror, 965 &orthogonal_rotation, 966 &flip_vert_scan_dir, 967 &flip_horz_scan_dir); 968 969 if (orthogonal_rotation) { 970 swap(src.width, src.height); 971 swap(flip_vert_scan_dir, flip_horz_scan_dir); 972 } 973 974 calculate_init_and_vp( 975 flip_horz_scan_dir, 976 ro_lb, 977 data->recout.width, 978 src.width, 979 data->taps.h_taps, 980 data->ratios.horz, 981 &data->inits.h, 982 &data->viewport.x, 983 &data->viewport.width); 984 calculate_init_and_vp( 985 flip_horz_scan_dir, 986 ro_lb, 987 data->recout.width, 988 src.width / vpc_div, 989 data->taps.h_taps_c, 990 data->ratios.horz_c, 991 &data->inits.h_c, 992 &data->viewport_c.x, 993 &data->viewport_c.width); 994 calculate_init_and_vp( 995 flip_vert_scan_dir, 996 ro_tb, 997 data->recout.height, 998 src.height, 999 data->taps.v_taps, 1000 data->ratios.vert, 1001 &data->inits.v, 1002 &data->viewport.y, 1003 &data->viewport.height); 1004 calculate_init_and_vp( 1005 flip_vert_scan_dir, 1006 ro_tb, 1007 data->recout.height, 1008 src.height / vpc_div, 1009 data->taps.v_taps_c, 1010 data->ratios.vert_c, 1011 &data->inits.v_c, 1012 &data->viewport_c.y, 1013 &data->viewport_c.height); 1014 if (orthogonal_rotation) { 1015 swap(data->viewport.x, data->viewport.y); 1016 swap(data->viewport.width, data->viewport.height); 1017 swap(data->viewport_c.x, data->viewport_c.y); 1018 swap(data->viewport_c.width, data->viewport_c.height); 1019 } 1020 data->viewport.x += src.x; 1021 data->viewport.y += src.y; 1022 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); 1023 data->viewport_c.x += src.x / vpc_div; 1024 data->viewport_c.y += src.y / vpc_div; 1025 } 1026 1027 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 1028 { 1029 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1030 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 1031 bool res = false; 1032 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 1033 1034 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( 1035 pipe_ctx->plane_state->format); 1036 1037 /* Timing borders are part of vactive that we are also supposed to skip in addition 1038 * to any stream dst offset. Since dm logic assumes dst is in addressable 1039 * space we need to add the the left and top borders to dst offsets temporarily. 1040 * TODO: fix in DM, stream dst is supposed to be in vactive 1041 */ 1042 pipe_ctx->stream->dst.x += timing->h_border_left; 1043 pipe_ctx->stream->dst.y += timing->v_border_top; 1044 1045 /* Calculate H and V active size */ 1046 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + 1047 timing->h_border_left + timing->h_border_right; 1048 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + 1049 timing->v_border_top + timing->v_border_bottom; 1050 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe) 1051 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1; 1052 1053 /* depends on h_active */ 1054 calculate_recout(pipe_ctx); 1055 /* depends on pixel format */ 1056 calculate_scaling_ratios(pipe_ctx); 1057 /* depends on scaling ratios and recout, does not calculate offset yet */ 1058 calculate_viewport_size(pipe_ctx); 1059 1060 /* 1061 * LB calculations depend on vp size, h/v_active and scaling ratios 1062 * Setting line buffer pixel depth to 24bpp yields banding 1063 * on certain displays, such as the Sharp 4k. 36bpp is needed 1064 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and 1065 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc 1066 * precision on at least DCN display engines. However, at least 1067 * Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth, 1068 * so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3 1069 * did not show such problems, so this seems to be the exception. 1070 */ 1071 if (plane_state->ctx->dce_version != DCE_VERSION_11_0) 1072 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; 1073 else 1074 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; 1075 1076 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; 1077 1078 if (pipe_ctx->plane_res.xfm != NULL) 1079 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1080 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1081 1082 if (pipe_ctx->plane_res.dpp != NULL) 1083 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1084 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1085 1086 1087 if (!res) { 1088 /* Try 24 bpp linebuffer */ 1089 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; 1090 1091 if (pipe_ctx->plane_res.xfm != NULL) 1092 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1093 pipe_ctx->plane_res.xfm, 1094 &pipe_ctx->plane_res.scl_data, 1095 &plane_state->scaling_quality); 1096 1097 if (pipe_ctx->plane_res.dpp != NULL) 1098 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1099 pipe_ctx->plane_res.dpp, 1100 &pipe_ctx->plane_res.scl_data, 1101 &plane_state->scaling_quality); 1102 } 1103 1104 /* 1105 * Depends on recout, scaling ratios, h_active and taps 1106 * May need to re-check lb size after this in some obscure scenario 1107 */ 1108 if (res) 1109 calculate_inits_and_viewports(pipe_ctx); 1110 1111 /* 1112 * Handle side by side and top bottom 3d recout offsets after vp calculation 1113 * since 3d is special and needs to calculate vp as if there is no recout offset 1114 * This may break with rotation, good thing we aren't mixing hw rotation and 3d 1115 */ 1116 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) { 1117 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 || 1118 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM && 1119 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE)); 1120 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 1121 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; 1122 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 1123 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; 1124 } 1125 1126 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE || 1127 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) 1128 res = false; 1129 1130 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n" 1131 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n", 1132 __func__, 1133 pipe_ctx->pipe_idx, 1134 pipe_ctx->plane_res.scl_data.viewport.height, 1135 pipe_ctx->plane_res.scl_data.viewport.width, 1136 pipe_ctx->plane_res.scl_data.viewport.x, 1137 pipe_ctx->plane_res.scl_data.viewport.y, 1138 pipe_ctx->plane_res.scl_data.recout.height, 1139 pipe_ctx->plane_res.scl_data.recout.width, 1140 pipe_ctx->plane_res.scl_data.recout.x, 1141 pipe_ctx->plane_res.scl_data.recout.y, 1142 pipe_ctx->plane_res.scl_data.h_active, 1143 pipe_ctx->plane_res.scl_data.v_active, 1144 plane_state->src_rect.height, 1145 plane_state->src_rect.width, 1146 plane_state->src_rect.x, 1147 plane_state->src_rect.y, 1148 plane_state->dst_rect.height, 1149 plane_state->dst_rect.width, 1150 plane_state->dst_rect.x, 1151 plane_state->dst_rect.y, 1152 plane_state->clip_rect.height, 1153 plane_state->clip_rect.width, 1154 plane_state->clip_rect.x, 1155 plane_state->clip_rect.y); 1156 1157 pipe_ctx->stream->dst.x -= timing->h_border_left; 1158 pipe_ctx->stream->dst.y -= timing->v_border_top; 1159 1160 return res; 1161 } 1162 1163 1164 enum dc_status resource_build_scaling_params_for_context( 1165 const struct dc *dc, 1166 struct dc_state *context) 1167 { 1168 int i; 1169 1170 for (i = 0; i < MAX_PIPES; i++) { 1171 if (context->res_ctx.pipe_ctx[i].plane_state != NULL && 1172 context->res_ctx.pipe_ctx[i].stream != NULL) 1173 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) 1174 return DC_FAIL_SCALING; 1175 } 1176 1177 return DC_OK; 1178 } 1179 1180 struct pipe_ctx *find_idle_secondary_pipe( 1181 struct resource_context *res_ctx, 1182 const struct resource_pool *pool, 1183 const struct pipe_ctx *primary_pipe) 1184 { 1185 int i; 1186 struct pipe_ctx *secondary_pipe = NULL; 1187 1188 /* 1189 * We add a preferred pipe mapping to avoid the chance that 1190 * MPCCs already in use will need to be reassigned to other trees. 1191 * For example, if we went with the strict, assign backwards logic: 1192 * 1193 * (State 1) 1194 * Display A on, no surface, top pipe = 0 1195 * Display B on, no surface, top pipe = 1 1196 * 1197 * (State 2) 1198 * Display A on, no surface, top pipe = 0 1199 * Display B on, surface enable, top pipe = 1, bottom pipe = 5 1200 * 1201 * (State 3) 1202 * Display A on, surface enable, top pipe = 0, bottom pipe = 5 1203 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1204 * 1205 * The state 2->3 transition requires remapping MPCC 5 from display B 1206 * to display A. 1207 * 1208 * However, with the preferred pipe logic, state 2 would look like: 1209 * 1210 * (State 2) 1211 * Display A on, no surface, top pipe = 0 1212 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1213 * 1214 * This would then cause 2->3 to not require remapping any MPCCs. 1215 */ 1216 if (primary_pipe) { 1217 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 1218 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1219 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1220 secondary_pipe->pipe_idx = preferred_pipe_idx; 1221 } 1222 } 1223 1224 /* 1225 * search backwards for the second pipe to keep pipe 1226 * assignment more consistent 1227 */ 1228 if (!secondary_pipe) 1229 for (i = pool->pipe_count - 1; i >= 0; i--) { 1230 if (res_ctx->pipe_ctx[i].stream == NULL) { 1231 secondary_pipe = &res_ctx->pipe_ctx[i]; 1232 secondary_pipe->pipe_idx = i; 1233 break; 1234 } 1235 } 1236 1237 return secondary_pipe; 1238 } 1239 1240 struct pipe_ctx *resource_get_head_pipe_for_stream( 1241 struct resource_context *res_ctx, 1242 struct dc_stream_state *stream) 1243 { 1244 int i; 1245 1246 for (i = 0; i < MAX_PIPES; i++) { 1247 if (res_ctx->pipe_ctx[i].stream == stream 1248 && !res_ctx->pipe_ctx[i].top_pipe 1249 && !res_ctx->pipe_ctx[i].prev_odm_pipe) 1250 return &res_ctx->pipe_ctx[i]; 1251 } 1252 return NULL; 1253 } 1254 1255 static struct pipe_ctx *resource_get_tail_pipe( 1256 struct resource_context *res_ctx, 1257 struct pipe_ctx *head_pipe) 1258 { 1259 struct pipe_ctx *tail_pipe; 1260 1261 tail_pipe = head_pipe->bottom_pipe; 1262 1263 while (tail_pipe) { 1264 head_pipe = tail_pipe; 1265 tail_pipe = tail_pipe->bottom_pipe; 1266 } 1267 1268 return head_pipe; 1269 } 1270 1271 /* 1272 * A free_pipe for a stream is defined here as a pipe 1273 * that has no surface attached yet 1274 */ 1275 static struct pipe_ctx *acquire_free_pipe_for_head( 1276 struct dc_state *context, 1277 const struct resource_pool *pool, 1278 struct pipe_ctx *head_pipe) 1279 { 1280 int i; 1281 struct resource_context *res_ctx = &context->res_ctx; 1282 1283 if (!head_pipe->plane_state) 1284 return head_pipe; 1285 1286 /* Re-use pipe already acquired for this stream if available*/ 1287 for (i = pool->pipe_count - 1; i >= 0; i--) { 1288 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream && 1289 !res_ctx->pipe_ctx[i].plane_state) { 1290 return &res_ctx->pipe_ctx[i]; 1291 } 1292 } 1293 1294 /* 1295 * At this point we have no re-useable pipe for this stream and we need 1296 * to acquire an idle one to satisfy the request 1297 */ 1298 1299 if (!pool->funcs->acquire_idle_pipe_for_layer) 1300 return NULL; 1301 1302 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream); 1303 } 1304 1305 #if defined(CONFIG_DRM_AMD_DC_DCN) 1306 static int acquire_first_split_pipe( 1307 struct resource_context *res_ctx, 1308 const struct resource_pool *pool, 1309 struct dc_stream_state *stream) 1310 { 1311 int i; 1312 1313 for (i = 0; i < pool->pipe_count; i++) { 1314 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; 1315 1316 if (split_pipe->top_pipe && 1317 split_pipe->top_pipe->plane_state == split_pipe->plane_state) { 1318 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; 1319 if (split_pipe->bottom_pipe) 1320 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; 1321 1322 if (split_pipe->top_pipe->plane_state) 1323 resource_build_scaling_params(split_pipe->top_pipe); 1324 1325 memset(split_pipe, 0, sizeof(*split_pipe)); 1326 split_pipe->stream_res.tg = pool->timing_generators[i]; 1327 split_pipe->plane_res.hubp = pool->hubps[i]; 1328 split_pipe->plane_res.ipp = pool->ipps[i]; 1329 split_pipe->plane_res.dpp = pool->dpps[i]; 1330 split_pipe->stream_res.opp = pool->opps[i]; 1331 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; 1332 split_pipe->pipe_idx = i; 1333 1334 split_pipe->stream = stream; 1335 return i; 1336 } 1337 } 1338 return -1; 1339 } 1340 #endif 1341 1342 bool dc_add_plane_to_context( 1343 const struct dc *dc, 1344 struct dc_stream_state *stream, 1345 struct dc_plane_state *plane_state, 1346 struct dc_state *context) 1347 { 1348 int i; 1349 struct resource_pool *pool = dc->res_pool; 1350 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; 1351 struct dc_stream_status *stream_status = NULL; 1352 1353 for (i = 0; i < context->stream_count; i++) 1354 if (context->streams[i] == stream) { 1355 stream_status = &context->stream_status[i]; 1356 break; 1357 } 1358 if (stream_status == NULL) { 1359 dm_error("Existing stream not found; failed to attach surface!\n"); 1360 return false; 1361 } 1362 1363 1364 if (stream_status->plane_count == MAX_SURFACE_NUM) { 1365 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", 1366 plane_state, MAX_SURFACE_NUM); 1367 return false; 1368 } 1369 1370 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1371 1372 if (!head_pipe) { 1373 dm_error("Head pipe not found for stream_state %p !\n", stream); 1374 return false; 1375 } 1376 1377 /* retain new surface, but only once per stream */ 1378 dc_plane_state_retain(plane_state); 1379 1380 while (head_pipe) { 1381 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe); 1382 1383 #if defined(CONFIG_DRM_AMD_DC_DCN) 1384 if (!free_pipe) { 1385 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 1386 if (pipe_idx >= 0) 1387 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; 1388 } 1389 #endif 1390 if (!free_pipe) { 1391 dc_plane_state_release(plane_state); 1392 return false; 1393 } 1394 1395 free_pipe->plane_state = plane_state; 1396 1397 if (head_pipe != free_pipe) { 1398 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe); 1399 ASSERT(tail_pipe); 1400 free_pipe->stream_res.tg = tail_pipe->stream_res.tg; 1401 free_pipe->stream_res.abm = tail_pipe->stream_res.abm; 1402 free_pipe->stream_res.opp = tail_pipe->stream_res.opp; 1403 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; 1404 free_pipe->stream_res.audio = tail_pipe->stream_res.audio; 1405 free_pipe->clock_source = tail_pipe->clock_source; 1406 free_pipe->top_pipe = tail_pipe; 1407 tail_pipe->bottom_pipe = free_pipe; 1408 if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) { 1409 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe; 1410 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe; 1411 } 1412 if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) { 1413 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe; 1414 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe; 1415 } 1416 } 1417 head_pipe = head_pipe->next_odm_pipe; 1418 } 1419 /* assign new surfaces*/ 1420 stream_status->plane_states[stream_status->plane_count] = plane_state; 1421 1422 stream_status->plane_count++; 1423 1424 return true; 1425 } 1426 1427 bool dc_remove_plane_from_context( 1428 const struct dc *dc, 1429 struct dc_stream_state *stream, 1430 struct dc_plane_state *plane_state, 1431 struct dc_state *context) 1432 { 1433 int i; 1434 struct dc_stream_status *stream_status = NULL; 1435 struct resource_pool *pool = dc->res_pool; 1436 1437 for (i = 0; i < context->stream_count; i++) 1438 if (context->streams[i] == stream) { 1439 stream_status = &context->stream_status[i]; 1440 break; 1441 } 1442 1443 if (stream_status == NULL) { 1444 dm_error("Existing stream not found; failed to remove plane.\n"); 1445 return false; 1446 } 1447 1448 /* release pipe for plane*/ 1449 for (i = pool->pipe_count - 1; i >= 0; i--) { 1450 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1451 1452 if (pipe_ctx->plane_state == plane_state) { 1453 if (pipe_ctx->top_pipe) 1454 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1455 1456 /* Second condition is to avoid setting NULL to top pipe 1457 * of tail pipe making it look like head pipe in subsequent 1458 * deletes 1459 */ 1460 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) 1461 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1462 1463 /* 1464 * For head pipe detach surfaces from pipe for tail 1465 * pipe just zero it out 1466 */ 1467 if (!pipe_ctx->top_pipe) 1468 pipe_ctx->plane_state = NULL; 1469 else 1470 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1471 } 1472 } 1473 1474 1475 for (i = 0; i < stream_status->plane_count; i++) { 1476 if (stream_status->plane_states[i] == plane_state) { 1477 1478 dc_plane_state_release(stream_status->plane_states[i]); 1479 break; 1480 } 1481 } 1482 1483 if (i == stream_status->plane_count) { 1484 dm_error("Existing plane_state not found; failed to detach it!\n"); 1485 return false; 1486 } 1487 1488 stream_status->plane_count--; 1489 1490 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */ 1491 for (; i < stream_status->plane_count; i++) 1492 stream_status->plane_states[i] = stream_status->plane_states[i + 1]; 1493 1494 stream_status->plane_states[stream_status->plane_count] = NULL; 1495 1496 return true; 1497 } 1498 1499 bool dc_rem_all_planes_for_stream( 1500 const struct dc *dc, 1501 struct dc_stream_state *stream, 1502 struct dc_state *context) 1503 { 1504 int i, old_plane_count; 1505 struct dc_stream_status *stream_status = NULL; 1506 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; 1507 1508 for (i = 0; i < context->stream_count; i++) 1509 if (context->streams[i] == stream) { 1510 stream_status = &context->stream_status[i]; 1511 break; 1512 } 1513 1514 if (stream_status == NULL) { 1515 dm_error("Existing stream %p not found!\n", stream); 1516 return false; 1517 } 1518 1519 old_plane_count = stream_status->plane_count; 1520 1521 for (i = 0; i < old_plane_count; i++) 1522 del_planes[i] = stream_status->plane_states[i]; 1523 1524 for (i = 0; i < old_plane_count; i++) 1525 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) 1526 return false; 1527 1528 return true; 1529 } 1530 1531 static bool add_all_planes_for_stream( 1532 const struct dc *dc, 1533 struct dc_stream_state *stream, 1534 const struct dc_validation_set set[], 1535 int set_count, 1536 struct dc_state *context) 1537 { 1538 int i, j; 1539 1540 for (i = 0; i < set_count; i++) 1541 if (set[i].stream == stream) 1542 break; 1543 1544 if (i == set_count) { 1545 dm_error("Stream %p not found in set!\n", stream); 1546 return false; 1547 } 1548 1549 for (j = 0; j < set[i].plane_count; j++) 1550 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) 1551 return false; 1552 1553 return true; 1554 } 1555 1556 bool dc_add_all_planes_for_stream( 1557 const struct dc *dc, 1558 struct dc_stream_state *stream, 1559 struct dc_plane_state * const *plane_states, 1560 int plane_count, 1561 struct dc_state *context) 1562 { 1563 struct dc_validation_set set; 1564 int i; 1565 1566 set.stream = stream; 1567 set.plane_count = plane_count; 1568 1569 for (i = 0; i < plane_count; i++) 1570 set.plane_states[i] = plane_states[i]; 1571 1572 return add_all_planes_for_stream(dc, stream, &set, 1, context); 1573 } 1574 1575 static bool is_timing_changed(struct dc_stream_state *cur_stream, 1576 struct dc_stream_state *new_stream) 1577 { 1578 if (cur_stream == NULL) 1579 return true; 1580 1581 /* If output color space is changed, need to reprogram info frames */ 1582 if (cur_stream->output_color_space != new_stream->output_color_space) 1583 return true; 1584 1585 return memcmp( 1586 &cur_stream->timing, 1587 &new_stream->timing, 1588 sizeof(struct dc_crtc_timing)) != 0; 1589 } 1590 1591 static bool are_stream_backends_same( 1592 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) 1593 { 1594 if (stream_a == stream_b) 1595 return true; 1596 1597 if (stream_a == NULL || stream_b == NULL) 1598 return false; 1599 1600 if (is_timing_changed(stream_a, stream_b)) 1601 return false; 1602 1603 if (stream_a->dpms_off != stream_b->dpms_off) 1604 return false; 1605 1606 return true; 1607 } 1608 1609 /* 1610 * dc_is_stream_unchanged() - Compare two stream states for equivalence. 1611 * 1612 * Checks if there a difference between the two states 1613 * that would require a mode change. 1614 * 1615 * Does not compare cursor position or attributes. 1616 */ 1617 bool dc_is_stream_unchanged( 1618 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1619 { 1620 1621 if (!are_stream_backends_same(old_stream, stream)) 1622 return false; 1623 1624 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param) 1625 return false; 1626 1627 return true; 1628 } 1629 1630 /* 1631 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams. 1632 */ 1633 bool dc_is_stream_scaling_unchanged( 1634 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1635 { 1636 if (old_stream == stream) 1637 return true; 1638 1639 if (old_stream == NULL || stream == NULL) 1640 return false; 1641 1642 if (memcmp(&old_stream->src, 1643 &stream->src, 1644 sizeof(struct rect)) != 0) 1645 return false; 1646 1647 if (memcmp(&old_stream->dst, 1648 &stream->dst, 1649 sizeof(struct rect)) != 0) 1650 return false; 1651 1652 return true; 1653 } 1654 1655 static void update_stream_engine_usage( 1656 struct resource_context *res_ctx, 1657 const struct resource_pool *pool, 1658 struct stream_encoder *stream_enc, 1659 bool acquired) 1660 { 1661 int i; 1662 1663 for (i = 0; i < pool->stream_enc_count; i++) { 1664 if (pool->stream_enc[i] == stream_enc) 1665 res_ctx->is_stream_enc_acquired[i] = acquired; 1666 } 1667 } 1668 1669 /* TODO: release audio object */ 1670 void update_audio_usage( 1671 struct resource_context *res_ctx, 1672 const struct resource_pool *pool, 1673 struct audio *audio, 1674 bool acquired) 1675 { 1676 int i; 1677 for (i = 0; i < pool->audio_count; i++) { 1678 if (pool->audios[i] == audio) 1679 res_ctx->is_audio_acquired[i] = acquired; 1680 } 1681 } 1682 1683 static int acquire_first_free_pipe( 1684 struct resource_context *res_ctx, 1685 const struct resource_pool *pool, 1686 struct dc_stream_state *stream) 1687 { 1688 int i; 1689 1690 for (i = 0; i < pool->pipe_count; i++) { 1691 if (!res_ctx->pipe_ctx[i].stream) { 1692 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 1693 1694 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 1695 pipe_ctx->plane_res.mi = pool->mis[i]; 1696 pipe_ctx->plane_res.hubp = pool->hubps[i]; 1697 pipe_ctx->plane_res.ipp = pool->ipps[i]; 1698 pipe_ctx->plane_res.xfm = pool->transforms[i]; 1699 pipe_ctx->plane_res.dpp = pool->dpps[i]; 1700 pipe_ctx->stream_res.opp = pool->opps[i]; 1701 if (pool->dpps[i]) 1702 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; 1703 pipe_ctx->pipe_idx = i; 1704 1705 1706 pipe_ctx->stream = stream; 1707 return i; 1708 } 1709 } 1710 return -1; 1711 } 1712 1713 static struct audio *find_first_free_audio( 1714 struct resource_context *res_ctx, 1715 const struct resource_pool *pool, 1716 enum engine_id id, 1717 enum dce_version dc_version) 1718 { 1719 int i, available_audio_count; 1720 1721 available_audio_count = pool->audio_count; 1722 1723 for (i = 0; i < available_audio_count; i++) { 1724 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { 1725 /*we have enough audio endpoint, find the matching inst*/ 1726 if (id != i) 1727 continue; 1728 return pool->audios[i]; 1729 } 1730 } 1731 1732 /* use engine id to find free audio */ 1733 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) { 1734 return pool->audios[id]; 1735 } 1736 /*not found the matching one, first come first serve*/ 1737 for (i = 0; i < available_audio_count; i++) { 1738 if (res_ctx->is_audio_acquired[i] == false) { 1739 return pool->audios[i]; 1740 } 1741 } 1742 return 0; 1743 } 1744 1745 /* 1746 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state. 1747 */ 1748 enum dc_status dc_add_stream_to_ctx( 1749 struct dc *dc, 1750 struct dc_state *new_ctx, 1751 struct dc_stream_state *stream) 1752 { 1753 enum dc_status res; 1754 DC_LOGGER_INIT(dc->ctx->logger); 1755 1756 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) { 1757 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream); 1758 return DC_ERROR_UNEXPECTED; 1759 } 1760 1761 new_ctx->streams[new_ctx->stream_count] = stream; 1762 dc_stream_retain(stream); 1763 new_ctx->stream_count++; 1764 1765 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); 1766 if (res != DC_OK) 1767 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res); 1768 1769 return res; 1770 } 1771 1772 /* 1773 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state. 1774 */ 1775 enum dc_status dc_remove_stream_from_ctx( 1776 struct dc *dc, 1777 struct dc_state *new_ctx, 1778 struct dc_stream_state *stream) 1779 { 1780 int i; 1781 struct dc_context *dc_ctx = dc->ctx; 1782 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream); 1783 struct pipe_ctx *odm_pipe; 1784 1785 if (!del_pipe) { 1786 DC_ERROR("Pipe not found for stream %p !\n", stream); 1787 return DC_ERROR_UNEXPECTED; 1788 } 1789 1790 odm_pipe = del_pipe->next_odm_pipe; 1791 1792 /* Release primary pipe */ 1793 ASSERT(del_pipe->stream_res.stream_enc); 1794 update_stream_engine_usage( 1795 &new_ctx->res_ctx, 1796 dc->res_pool, 1797 del_pipe->stream_res.stream_enc, 1798 false); 1799 /* Release link encoder from stream in new dc_state. */ 1800 if (dc->res_pool->funcs->link_enc_unassign) 1801 dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream); 1802 1803 if (del_pipe->stream_res.audio) 1804 update_audio_usage( 1805 &new_ctx->res_ctx, 1806 dc->res_pool, 1807 del_pipe->stream_res.audio, 1808 false); 1809 1810 resource_unreference_clock_source(&new_ctx->res_ctx, 1811 dc->res_pool, 1812 del_pipe->clock_source); 1813 1814 if (dc->res_pool->funcs->remove_stream_from_ctx) 1815 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream); 1816 1817 while (odm_pipe) { 1818 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 1819 1820 memset(odm_pipe, 0, sizeof(*odm_pipe)); 1821 odm_pipe = next_odm_pipe; 1822 } 1823 memset(del_pipe, 0, sizeof(*del_pipe)); 1824 1825 for (i = 0; i < new_ctx->stream_count; i++) 1826 if (new_ctx->streams[i] == stream) 1827 break; 1828 1829 if (new_ctx->streams[i] != stream) { 1830 DC_ERROR("Context doesn't have stream %p !\n", stream); 1831 return DC_ERROR_UNEXPECTED; 1832 } 1833 1834 dc_stream_release(new_ctx->streams[i]); 1835 new_ctx->stream_count--; 1836 1837 /* Trim back arrays */ 1838 for (; i < new_ctx->stream_count; i++) { 1839 new_ctx->streams[i] = new_ctx->streams[i + 1]; 1840 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; 1841 } 1842 1843 new_ctx->streams[new_ctx->stream_count] = NULL; 1844 memset( 1845 &new_ctx->stream_status[new_ctx->stream_count], 1846 0, 1847 sizeof(new_ctx->stream_status[0])); 1848 1849 return DC_OK; 1850 } 1851 1852 static struct dc_stream_state *find_pll_sharable_stream( 1853 struct dc_stream_state *stream_needs_pll, 1854 struct dc_state *context) 1855 { 1856 int i; 1857 1858 for (i = 0; i < context->stream_count; i++) { 1859 struct dc_stream_state *stream_has_pll = context->streams[i]; 1860 1861 /* We are looking for non dp, non virtual stream */ 1862 if (resource_are_streams_timing_synchronizable( 1863 stream_needs_pll, stream_has_pll) 1864 && !dc_is_dp_signal(stream_has_pll->signal) 1865 && stream_has_pll->link->connector_signal 1866 != SIGNAL_TYPE_VIRTUAL) 1867 return stream_has_pll; 1868 1869 } 1870 1871 return NULL; 1872 } 1873 1874 static int get_norm_pix_clk(const struct dc_crtc_timing *timing) 1875 { 1876 uint32_t pix_clk = timing->pix_clk_100hz; 1877 uint32_t normalized_pix_clk = pix_clk; 1878 1879 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 1880 pix_clk /= 2; 1881 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 1882 switch (timing->display_color_depth) { 1883 case COLOR_DEPTH_666: 1884 case COLOR_DEPTH_888: 1885 normalized_pix_clk = pix_clk; 1886 break; 1887 case COLOR_DEPTH_101010: 1888 normalized_pix_clk = (pix_clk * 30) / 24; 1889 break; 1890 case COLOR_DEPTH_121212: 1891 normalized_pix_clk = (pix_clk * 36) / 24; 1892 break; 1893 case COLOR_DEPTH_161616: 1894 normalized_pix_clk = (pix_clk * 48) / 24; 1895 break; 1896 default: 1897 ASSERT(0); 1898 break; 1899 } 1900 } 1901 return normalized_pix_clk; 1902 } 1903 1904 static void calculate_phy_pix_clks(struct dc_stream_state *stream) 1905 { 1906 /* update actual pixel clock on all streams */ 1907 if (dc_is_hdmi_signal(stream->signal)) 1908 stream->phy_pix_clk = get_norm_pix_clk( 1909 &stream->timing) / 10; 1910 else 1911 stream->phy_pix_clk = 1912 stream->timing.pix_clk_100hz / 10; 1913 1914 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1915 stream->phy_pix_clk *= 2; 1916 } 1917 1918 static int acquire_resource_from_hw_enabled_state( 1919 struct resource_context *res_ctx, 1920 const struct resource_pool *pool, 1921 struct dc_stream_state *stream) 1922 { 1923 struct dc_link *link = stream->link; 1924 unsigned int i, inst, tg_inst = 0; 1925 1926 /* Check for enabled DIG to identify enabled display */ 1927 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) 1928 return -1; 1929 1930 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); 1931 1932 if (inst == ENGINE_ID_UNKNOWN) 1933 return -1; 1934 1935 for (i = 0; i < pool->stream_enc_count; i++) { 1936 if (pool->stream_enc[i]->id == inst) { 1937 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( 1938 pool->stream_enc[i]); 1939 break; 1940 } 1941 } 1942 1943 // tg_inst not found 1944 if (i == pool->stream_enc_count) 1945 return -1; 1946 1947 if (tg_inst >= pool->timing_generator_count) 1948 return -1; 1949 1950 if (!res_ctx->pipe_ctx[tg_inst].stream) { 1951 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; 1952 1953 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 1954 pipe_ctx->plane_res.mi = pool->mis[tg_inst]; 1955 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; 1956 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; 1957 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; 1958 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst]; 1959 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; 1960 1961 if (pool->dpps[tg_inst]) { 1962 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; 1963 1964 // Read DPP->MPCC->OPP Pipe from HW State 1965 if (pool->mpc->funcs->read_mpcc_state) { 1966 struct mpcc_state s = {0}; 1967 1968 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); 1969 1970 if (s.dpp_id < MAX_MPCC) 1971 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id; 1972 1973 if (s.bot_mpcc_id < MAX_MPCC) 1974 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = 1975 &pool->mpc->mpcc_array[s.bot_mpcc_id]; 1976 1977 if (s.opp_id < MAX_OPP) 1978 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; 1979 } 1980 } 1981 pipe_ctx->pipe_idx = tg_inst; 1982 1983 pipe_ctx->stream = stream; 1984 return tg_inst; 1985 } 1986 1987 return -1; 1988 } 1989 1990 static void mark_seamless_boot_stream( 1991 const struct dc *dc, 1992 struct dc_stream_state *stream) 1993 { 1994 struct dc_bios *dcb = dc->ctx->dc_bios; 1995 1996 /* TODO: Check Linux */ 1997 if (dc->config.allow_seamless_boot_optimization && 1998 !dcb->funcs->is_accelerated_mode(dcb)) { 1999 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing)) 2000 stream->apply_seamless_boot_optimization = true; 2001 } 2002 } 2003 2004 enum dc_status resource_map_pool_resources( 2005 const struct dc *dc, 2006 struct dc_state *context, 2007 struct dc_stream_state *stream) 2008 { 2009 const struct resource_pool *pool = dc->res_pool; 2010 int i; 2011 struct dc_context *dc_ctx = dc->ctx; 2012 struct pipe_ctx *pipe_ctx = NULL; 2013 int pipe_idx = -1; 2014 2015 calculate_phy_pix_clks(stream); 2016 2017 mark_seamless_boot_stream(dc, stream); 2018 2019 if (stream->apply_seamless_boot_optimization) { 2020 pipe_idx = acquire_resource_from_hw_enabled_state( 2021 &context->res_ctx, 2022 pool, 2023 stream); 2024 if (pipe_idx < 0) 2025 /* hw resource was assigned to other stream */ 2026 stream->apply_seamless_boot_optimization = false; 2027 } 2028 2029 if (pipe_idx < 0) 2030 /* acquire new resources */ 2031 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); 2032 2033 #ifdef CONFIG_DRM_AMD_DC_DCN 2034 if (pipe_idx < 0) 2035 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 2036 #endif 2037 2038 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL) 2039 return DC_NO_CONTROLLER_RESOURCE; 2040 2041 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2042 2043 pipe_ctx->stream_res.stream_enc = 2044 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link( 2045 &context->res_ctx, pool, stream); 2046 2047 if (!pipe_ctx->stream_res.stream_enc) 2048 return DC_NO_STREAM_ENC_RESOURCE; 2049 2050 update_stream_engine_usage( 2051 &context->res_ctx, pool, 2052 pipe_ctx->stream_res.stream_enc, 2053 true); 2054 2055 /* TODO: Add check if ASIC support and EDID audio */ 2056 if (!stream->converter_disable_audio && 2057 dc_is_audio_capable_signal(pipe_ctx->stream->signal) && 2058 stream->audio_info.mode_count && stream->audio_info.flags.all) { 2059 pipe_ctx->stream_res.audio = find_first_free_audio( 2060 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version); 2061 2062 /* 2063 * Audio assigned in order first come first get. 2064 * There are asics which has number of audio 2065 * resources less then number of pipes 2066 */ 2067 if (pipe_ctx->stream_res.audio) 2068 update_audio_usage(&context->res_ctx, pool, 2069 pipe_ctx->stream_res.audio, true); 2070 } 2071 2072 /* Add ABM to the resource if on EDP */ 2073 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) { 2074 #if defined(CONFIG_DRM_AMD_DC_DCN) 2075 if (pool->abm) 2076 pipe_ctx->stream_res.abm = pool->abm; 2077 else 2078 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst]; 2079 #else 2080 pipe_ctx->stream_res.abm = pool->abm; 2081 #endif 2082 } 2083 2084 for (i = 0; i < context->stream_count; i++) 2085 if (context->streams[i] == stream) { 2086 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; 2087 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst; 2088 context->stream_status[i].audio_inst = 2089 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; 2090 2091 return DC_OK; 2092 } 2093 2094 DC_ERROR("Stream %p not found in new ctx!\n", stream); 2095 return DC_ERROR_UNEXPECTED; 2096 } 2097 2098 /** 2099 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state 2100 * Is a shallow copy. Increments refcounts on existing streams and planes. 2101 * @dc: copy out of dc->current_state 2102 * @dst_ctx: copy into this 2103 */ 2104 void dc_resource_state_copy_construct_current( 2105 const struct dc *dc, 2106 struct dc_state *dst_ctx) 2107 { 2108 dc_resource_state_copy_construct(dc->current_state, dst_ctx); 2109 } 2110 2111 2112 void dc_resource_state_construct( 2113 const struct dc *dc, 2114 struct dc_state *dst_ctx) 2115 { 2116 dst_ctx->clk_mgr = dc->clk_mgr; 2117 } 2118 2119 2120 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) 2121 { 2122 return dc->res_pool->res_cap->num_dsc > 0; 2123 } 2124 2125 2126 /** 2127 * dc_validate_global_state() - Determine if HW can support a given state 2128 * Checks HW resource availability and bandwidth requirement. 2129 * @dc: dc struct for this driver 2130 * @new_ctx: state to be validated 2131 * @fast_validate: set to true if only yes/no to support matters 2132 * 2133 * Return: DC_OK if the result can be programmed. Otherwise, an error code. 2134 */ 2135 enum dc_status dc_validate_global_state( 2136 struct dc *dc, 2137 struct dc_state *new_ctx, 2138 bool fast_validate) 2139 { 2140 enum dc_status result = DC_ERROR_UNEXPECTED; 2141 int i, j; 2142 2143 if (!new_ctx) 2144 return DC_ERROR_UNEXPECTED; 2145 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2146 2147 /* 2148 * Update link encoder to stream assignment. 2149 * TODO: Split out reason allocation from validation. 2150 */ 2151 if (dc->res_pool->funcs->link_encs_assign) 2152 dc->res_pool->funcs->link_encs_assign( 2153 dc, new_ctx, new_ctx->streams, new_ctx->stream_count); 2154 #endif 2155 2156 if (dc->res_pool->funcs->validate_global) { 2157 result = dc->res_pool->funcs->validate_global(dc, new_ctx); 2158 if (result != DC_OK) 2159 return result; 2160 } 2161 2162 for (i = 0; i < new_ctx->stream_count; i++) { 2163 struct dc_stream_state *stream = new_ctx->streams[i]; 2164 2165 for (j = 0; j < dc->res_pool->pipe_count; j++) { 2166 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; 2167 2168 if (pipe_ctx->stream != stream) 2169 continue; 2170 2171 if (dc->res_pool->funcs->patch_unknown_plane_state && 2172 pipe_ctx->plane_state && 2173 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { 2174 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); 2175 if (result != DC_OK) 2176 return result; 2177 } 2178 2179 /* Switch to dp clock source only if there is 2180 * no non dp stream that shares the same timing 2181 * with the dp stream. 2182 */ 2183 if (dc_is_dp_signal(pipe_ctx->stream->signal) && 2184 !find_pll_sharable_stream(stream, new_ctx)) { 2185 2186 resource_unreference_clock_source( 2187 &new_ctx->res_ctx, 2188 dc->res_pool, 2189 pipe_ctx->clock_source); 2190 2191 pipe_ctx->clock_source = dc->res_pool->dp_clock_source; 2192 resource_reference_clock_source( 2193 &new_ctx->res_ctx, 2194 dc->res_pool, 2195 pipe_ctx->clock_source); 2196 } 2197 } 2198 } 2199 2200 result = resource_build_scaling_params_for_context(dc, new_ctx); 2201 2202 if (result == DC_OK) 2203 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate)) 2204 result = DC_FAIL_BANDWIDTH_VALIDATE; 2205 2206 return result; 2207 } 2208 2209 static void patch_gamut_packet_checksum( 2210 struct dc_info_packet *gamut_packet) 2211 { 2212 /* For gamut we recalc checksum */ 2213 if (gamut_packet->valid) { 2214 uint8_t chk_sum = 0; 2215 uint8_t *ptr; 2216 uint8_t i; 2217 2218 /*start of the Gamut data. */ 2219 ptr = &gamut_packet->sb[3]; 2220 2221 for (i = 0; i <= gamut_packet->sb[1]; i++) 2222 chk_sum += ptr[i]; 2223 2224 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); 2225 } 2226 } 2227 2228 static void set_avi_info_frame( 2229 struct dc_info_packet *info_packet, 2230 struct pipe_ctx *pipe_ctx) 2231 { 2232 struct dc_stream_state *stream = pipe_ctx->stream; 2233 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; 2234 uint32_t pixel_encoding = 0; 2235 enum scanning_type scan_type = SCANNING_TYPE_NODATA; 2236 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA; 2237 bool itc = false; 2238 uint8_t itc_value = 0; 2239 uint8_t cn0_cn1 = 0; 2240 unsigned int cn0_cn1_value = 0; 2241 uint8_t *check_sum = NULL; 2242 uint8_t byte_index = 0; 2243 union hdmi_info_packet hdmi_info; 2244 union display_content_support support = {0}; 2245 unsigned int vic = pipe_ctx->stream->timing.vic; 2246 enum dc_timing_3d_format format; 2247 2248 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet)); 2249 2250 color_space = pipe_ctx->stream->output_color_space; 2251 if (color_space == COLOR_SPACE_UNKNOWN) 2252 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? 2253 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; 2254 2255 /* Initialize header */ 2256 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI; 2257 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall 2258 * not be used in HDMI 2.0 (Section 10.1) */ 2259 hdmi_info.bits.header.version = 2; 2260 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE; 2261 2262 /* 2263 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built 2264 * according to HDMI 2.0 spec (Section 10.1) 2265 */ 2266 2267 switch (stream->timing.pixel_encoding) { 2268 case PIXEL_ENCODING_YCBCR422: 2269 pixel_encoding = 1; 2270 break; 2271 2272 case PIXEL_ENCODING_YCBCR444: 2273 pixel_encoding = 2; 2274 break; 2275 case PIXEL_ENCODING_YCBCR420: 2276 pixel_encoding = 3; 2277 break; 2278 2279 case PIXEL_ENCODING_RGB: 2280 default: 2281 pixel_encoding = 0; 2282 } 2283 2284 /* Y0_Y1_Y2 : The pixel encoding */ 2285 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ 2286 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding; 2287 2288 /* A0 = 1 Active Format Information valid */ 2289 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID; 2290 2291 /* B0, B1 = 3; Bar info data is valid */ 2292 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID; 2293 2294 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM; 2295 2296 /* S0, S1 : Underscan / Overscan */ 2297 /* TODO: un-hardcode scan type */ 2298 scan_type = SCANNING_TYPE_UNDERSCAN; 2299 hdmi_info.bits.S0_S1 = scan_type; 2300 2301 /* C0, C1 : Colorimetry */ 2302 if (color_space == COLOR_SPACE_YCBCR709 || 2303 color_space == COLOR_SPACE_YCBCR709_LIMITED) 2304 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709; 2305 else if (color_space == COLOR_SPACE_YCBCR601 || 2306 color_space == COLOR_SPACE_YCBCR601_LIMITED) 2307 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601; 2308 else { 2309 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA; 2310 } 2311 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE || 2312 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE || 2313 color_space == COLOR_SPACE_2020_YCBCR) { 2314 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR; 2315 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 2316 } else if (color_space == COLOR_SPACE_ADOBERGB) { 2317 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB; 2318 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 2319 } 2320 2321 /* TODO: un-hardcode aspect ratio */ 2322 aspect = stream->timing.aspect_ratio; 2323 2324 switch (aspect) { 2325 case ASPECT_RATIO_4_3: 2326 case ASPECT_RATIO_16_9: 2327 hdmi_info.bits.M0_M1 = aspect; 2328 break; 2329 2330 case ASPECT_RATIO_NO_DATA: 2331 case ASPECT_RATIO_64_27: 2332 case ASPECT_RATIO_256_135: 2333 default: 2334 hdmi_info.bits.M0_M1 = 0; 2335 } 2336 2337 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */ 2338 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE; 2339 2340 /* TODO: un-hardcode cn0_cn1 and itc */ 2341 2342 cn0_cn1 = 0; 2343 cn0_cn1_value = 0; 2344 2345 itc = true; 2346 itc_value = 1; 2347 2348 support = stream->content_support; 2349 2350 if (itc) { 2351 if (!support.bits.valid_content_type) { 2352 cn0_cn1_value = 0; 2353 } else { 2354 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) { 2355 if (support.bits.graphics_content == 1) { 2356 cn0_cn1_value = 0; 2357 } 2358 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) { 2359 if (support.bits.photo_content == 1) { 2360 cn0_cn1_value = 1; 2361 } else { 2362 cn0_cn1_value = 0; 2363 itc_value = 0; 2364 } 2365 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) { 2366 if (support.bits.cinema_content == 1) { 2367 cn0_cn1_value = 2; 2368 } else { 2369 cn0_cn1_value = 0; 2370 itc_value = 0; 2371 } 2372 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) { 2373 if (support.bits.game_content == 1) { 2374 cn0_cn1_value = 3; 2375 } else { 2376 cn0_cn1_value = 0; 2377 itc_value = 0; 2378 } 2379 } 2380 } 2381 hdmi_info.bits.CN0_CN1 = cn0_cn1_value; 2382 hdmi_info.bits.ITC = itc_value; 2383 } 2384 2385 if (stream->qs_bit == 1) { 2386 if (color_space == COLOR_SPACE_SRGB || 2387 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) 2388 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; 2389 else if (color_space == COLOR_SPACE_SRGB_LIMITED || 2390 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) 2391 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE; 2392 else 2393 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2394 } else 2395 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2396 2397 /* TODO : We should handle YCC quantization */ 2398 /* but we do not have matrix calculation */ 2399 if (stream->qy_bit == 1) { 2400 if (color_space == COLOR_SPACE_SRGB || 2401 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) 2402 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2403 else if (color_space == COLOR_SPACE_SRGB_LIMITED || 2404 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) 2405 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2406 else 2407 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2408 } else 2409 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2410 2411 ///VIC 2412 format = stream->timing.timing_3d_format; 2413 /*todo, add 3DStereo support*/ 2414 if (format != TIMING_3D_FORMAT_NONE) { 2415 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled 2416 switch (pipe_ctx->stream->timing.hdmi_vic) { 2417 case 1: 2418 vic = 95; 2419 break; 2420 case 2: 2421 vic = 94; 2422 break; 2423 case 3: 2424 vic = 93; 2425 break; 2426 case 4: 2427 vic = 98; 2428 break; 2429 default: 2430 break; 2431 } 2432 } 2433 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/ 2434 hdmi_info.bits.VIC0_VIC7 = vic; 2435 if (vic >= 128) 2436 hdmi_info.bits.header.version = 3; 2437 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1), 2438 * the Source shall use 20 AVI InfoFrame Version 4 2439 */ 2440 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED && 2441 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) { 2442 hdmi_info.bits.header.version = 4; 2443 hdmi_info.bits.header.length = 14; 2444 } 2445 2446 /* pixel repetition 2447 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel 2448 * repetition start from 1 */ 2449 hdmi_info.bits.PR0_PR3 = 0; 2450 2451 /* Bar Info 2452 * barTop: Line Number of End of Top Bar. 2453 * barBottom: Line Number of Start of Bottom Bar. 2454 * barLeft: Pixel Number of End of Left Bar. 2455 * barRight: Pixel Number of Start of Right Bar. */ 2456 hdmi_info.bits.bar_top = stream->timing.v_border_top; 2457 hdmi_info.bits.bar_bottom = (stream->timing.v_total 2458 - stream->timing.v_border_bottom + 1); 2459 hdmi_info.bits.bar_left = stream->timing.h_border_left; 2460 hdmi_info.bits.bar_right = (stream->timing.h_total 2461 - stream->timing.h_border_right + 1); 2462 2463 /* Additional Colorimetry Extension 2464 * Used in conduction with C0-C1 and EC0-EC2 2465 * 0 = DCI-P3 RGB (D65) 2466 * 1 = DCI-P3 RGB (theater) 2467 */ 2468 hdmi_info.bits.ACE0_ACE3 = 0; 2469 2470 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ 2471 check_sum = &hdmi_info.packet_raw_data.sb[0]; 2472 2473 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version; 2474 2475 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++) 2476 *check_sum += hdmi_info.packet_raw_data.sb[byte_index]; 2477 2478 /* one byte complement */ 2479 *check_sum = (uint8_t) (0x100 - *check_sum); 2480 2481 /* Store in hw_path_mode */ 2482 info_packet->hb0 = hdmi_info.packet_raw_data.hb0; 2483 info_packet->hb1 = hdmi_info.packet_raw_data.hb1; 2484 info_packet->hb2 = hdmi_info.packet_raw_data.hb2; 2485 2486 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++) 2487 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index]; 2488 2489 info_packet->valid = true; 2490 } 2491 2492 static void set_vendor_info_packet( 2493 struct dc_info_packet *info_packet, 2494 struct dc_stream_state *stream) 2495 { 2496 /* SPD info packet for FreeSync */ 2497 2498 /* Check if Freesync is supported. Return if false. If true, 2499 * set the corresponding bit in the info packet 2500 */ 2501 if (!stream->vsp_infopacket.valid) 2502 return; 2503 2504 *info_packet = stream->vsp_infopacket; 2505 } 2506 2507 static void set_spd_info_packet( 2508 struct dc_info_packet *info_packet, 2509 struct dc_stream_state *stream) 2510 { 2511 /* SPD info packet for FreeSync */ 2512 2513 /* Check if Freesync is supported. Return if false. If true, 2514 * set the corresponding bit in the info packet 2515 */ 2516 if (!stream->vrr_infopacket.valid) 2517 return; 2518 2519 *info_packet = stream->vrr_infopacket; 2520 } 2521 2522 static void set_hdr_static_info_packet( 2523 struct dc_info_packet *info_packet, 2524 struct dc_stream_state *stream) 2525 { 2526 /* HDR Static Metadata info packet for HDR10 */ 2527 2528 if (!stream->hdr_static_metadata.valid || 2529 stream->use_dynamic_meta) 2530 return; 2531 2532 *info_packet = stream->hdr_static_metadata; 2533 } 2534 2535 static void set_vsc_info_packet( 2536 struct dc_info_packet *info_packet, 2537 struct dc_stream_state *stream) 2538 { 2539 if (!stream->vsc_infopacket.valid) 2540 return; 2541 2542 *info_packet = stream->vsc_infopacket; 2543 } 2544 2545 void dc_resource_state_destruct(struct dc_state *context) 2546 { 2547 int i, j; 2548 2549 for (i = 0; i < context->stream_count; i++) { 2550 for (j = 0; j < context->stream_status[i].plane_count; j++) 2551 dc_plane_state_release( 2552 context->stream_status[i].plane_states[j]); 2553 2554 context->stream_status[i].plane_count = 0; 2555 dc_stream_release(context->streams[i]); 2556 context->streams[i] = NULL; 2557 } 2558 context->stream_count = 0; 2559 } 2560 2561 void dc_resource_state_copy_construct( 2562 const struct dc_state *src_ctx, 2563 struct dc_state *dst_ctx) 2564 { 2565 int i, j; 2566 struct kref refcount = dst_ctx->refcount; 2567 2568 *dst_ctx = *src_ctx; 2569 2570 for (i = 0; i < MAX_PIPES; i++) { 2571 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; 2572 2573 if (cur_pipe->top_pipe) 2574 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; 2575 2576 if (cur_pipe->bottom_pipe) 2577 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; 2578 2579 if (cur_pipe->next_odm_pipe) 2580 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; 2581 2582 if (cur_pipe->prev_odm_pipe) 2583 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; 2584 } 2585 2586 for (i = 0; i < dst_ctx->stream_count; i++) { 2587 dc_stream_retain(dst_ctx->streams[i]); 2588 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) 2589 dc_plane_state_retain( 2590 dst_ctx->stream_status[i].plane_states[j]); 2591 } 2592 2593 /* context refcount should not be overridden */ 2594 dst_ctx->refcount = refcount; 2595 2596 } 2597 2598 struct clock_source *dc_resource_find_first_free_pll( 2599 struct resource_context *res_ctx, 2600 const struct resource_pool *pool) 2601 { 2602 int i; 2603 2604 for (i = 0; i < pool->clk_src_count; ++i) { 2605 if (res_ctx->clock_source_ref_count[i] == 0) 2606 return pool->clock_sources[i]; 2607 } 2608 2609 return NULL; 2610 } 2611 2612 void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 2613 { 2614 enum signal_type signal = SIGNAL_TYPE_NONE; 2615 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; 2616 2617 /* default all packets to invalid */ 2618 info->avi.valid = false; 2619 info->gamut.valid = false; 2620 info->vendor.valid = false; 2621 info->spd.valid = false; 2622 info->hdrsmd.valid = false; 2623 info->vsc.valid = false; 2624 2625 signal = pipe_ctx->stream->signal; 2626 2627 /* HDMi and DP have different info packets*/ 2628 if (dc_is_hdmi_signal(signal)) { 2629 set_avi_info_frame(&info->avi, pipe_ctx); 2630 2631 set_vendor_info_packet(&info->vendor, pipe_ctx->stream); 2632 2633 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2634 2635 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 2636 2637 } else if (dc_is_dp_signal(signal)) { 2638 set_vsc_info_packet(&info->vsc, pipe_ctx->stream); 2639 2640 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2641 2642 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 2643 } 2644 2645 patch_gamut_packet_checksum(&info->gamut); 2646 } 2647 2648 enum dc_status resource_map_clock_resources( 2649 const struct dc *dc, 2650 struct dc_state *context, 2651 struct dc_stream_state *stream) 2652 { 2653 /* acquire new resources */ 2654 const struct resource_pool *pool = dc->res_pool; 2655 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 2656 &context->res_ctx, stream); 2657 2658 if (!pipe_ctx) 2659 return DC_ERROR_UNEXPECTED; 2660 2661 if (dc_is_dp_signal(pipe_ctx->stream->signal) 2662 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 2663 pipe_ctx->clock_source = pool->dp_clock_source; 2664 else { 2665 pipe_ctx->clock_source = NULL; 2666 2667 if (!dc->config.disable_disp_pll_sharing) 2668 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing( 2669 &context->res_ctx, 2670 pipe_ctx); 2671 2672 if (pipe_ctx->clock_source == NULL) 2673 pipe_ctx->clock_source = 2674 dc_resource_find_first_free_pll( 2675 &context->res_ctx, 2676 pool); 2677 } 2678 2679 if (pipe_ctx->clock_source == NULL) 2680 return DC_NO_CLOCK_SOURCE_RESOURCE; 2681 2682 resource_reference_clock_source( 2683 &context->res_ctx, pool, 2684 pipe_ctx->clock_source); 2685 2686 return DC_OK; 2687 } 2688 2689 /* 2690 * Note: We need to disable output if clock sources change, 2691 * since bios does optimization and doesn't apply if changing 2692 * PHY when not already disabled. 2693 */ 2694 bool pipe_need_reprogram( 2695 struct pipe_ctx *pipe_ctx_old, 2696 struct pipe_ctx *pipe_ctx) 2697 { 2698 if (!pipe_ctx_old->stream) 2699 return false; 2700 2701 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) 2702 return true; 2703 2704 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) 2705 return true; 2706 2707 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) 2708 return true; 2709 2710 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source 2711 && pipe_ctx_old->stream != pipe_ctx->stream) 2712 return true; 2713 2714 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) 2715 return true; 2716 2717 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) 2718 return true; 2719 2720 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off) 2721 return true; 2722 2723 if (false == pipe_ctx_old->stream->link->link_state_valid && 2724 false == pipe_ctx_old->stream->dpms_off) 2725 return true; 2726 2727 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) 2728 return true; 2729 2730 /* DIG link encoder resource assignment for stream changed. */ 2731 if (pipe_ctx_old->stream->link_enc != pipe_ctx->stream->link_enc) 2732 return true; 2733 2734 return false; 2735 } 2736 2737 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 2738 struct bit_depth_reduction_params *fmt_bit_depth) 2739 { 2740 enum dc_dither_option option = stream->dither_option; 2741 enum dc_pixel_encoding pixel_encoding = 2742 stream->timing.pixel_encoding; 2743 2744 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); 2745 2746 if (option == DITHER_OPTION_DEFAULT) { 2747 switch (stream->timing.display_color_depth) { 2748 case COLOR_DEPTH_666: 2749 option = DITHER_OPTION_SPATIAL6; 2750 break; 2751 case COLOR_DEPTH_888: 2752 option = DITHER_OPTION_SPATIAL8; 2753 break; 2754 case COLOR_DEPTH_101010: 2755 option = DITHER_OPTION_SPATIAL10; 2756 break; 2757 default: 2758 option = DITHER_OPTION_DISABLE; 2759 } 2760 } 2761 2762 if (option == DITHER_OPTION_DISABLE) 2763 return; 2764 2765 if (option == DITHER_OPTION_TRUN6) { 2766 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2767 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; 2768 } else if (option == DITHER_OPTION_TRUN8 || 2769 option == DITHER_OPTION_TRUN8_SPATIAL6 || 2770 option == DITHER_OPTION_TRUN8_FM6) { 2771 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2772 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; 2773 } else if (option == DITHER_OPTION_TRUN10 || 2774 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2775 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2776 option == DITHER_OPTION_TRUN10_FM8 || 2777 option == DITHER_OPTION_TRUN10_FM6 || 2778 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2779 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2780 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2781 } 2782 2783 /* special case - Formatter can only reduce by 4 bits at most. 2784 * When reducing from 12 to 6 bits, 2785 * HW recommends we use trunc with round mode 2786 * (if we did nothing, trunc to 10 bits would be used) 2787 * note that any 12->10 bit reduction is ignored prior to DCE8, 2788 * as the input was 10 bits. 2789 */ 2790 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2791 option == DITHER_OPTION_SPATIAL6 || 2792 option == DITHER_OPTION_FM6) { 2793 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2794 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2795 fmt_bit_depth->flags.TRUNCATE_MODE = 1; 2796 } 2797 2798 /* spatial dither 2799 * note that spatial modes 1-3 are never used 2800 */ 2801 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2802 option == DITHER_OPTION_SPATIAL6 || 2803 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2804 option == DITHER_OPTION_TRUN8_SPATIAL6) { 2805 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2806 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; 2807 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2808 fmt_bit_depth->flags.RGB_RANDOM = 2809 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2810 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || 2811 option == DITHER_OPTION_SPATIAL8 || 2812 option == DITHER_OPTION_SPATIAL8_FM6 || 2813 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2814 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2815 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2816 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; 2817 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2818 fmt_bit_depth->flags.RGB_RANDOM = 2819 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2820 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || 2821 option == DITHER_OPTION_SPATIAL10 || 2822 option == DITHER_OPTION_SPATIAL10_FM8 || 2823 option == DITHER_OPTION_SPATIAL10_FM6) { 2824 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2825 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; 2826 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2827 fmt_bit_depth->flags.RGB_RANDOM = 2828 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2829 } 2830 2831 if (option == DITHER_OPTION_SPATIAL6 || 2832 option == DITHER_OPTION_SPATIAL8 || 2833 option == DITHER_OPTION_SPATIAL10) { 2834 fmt_bit_depth->flags.FRAME_RANDOM = 0; 2835 } else { 2836 fmt_bit_depth->flags.FRAME_RANDOM = 1; 2837 } 2838 2839 ////////////////////// 2840 //// temporal dither 2841 ////////////////////// 2842 if (option == DITHER_OPTION_FM6 || 2843 option == DITHER_OPTION_SPATIAL8_FM6 || 2844 option == DITHER_OPTION_SPATIAL10_FM6 || 2845 option == DITHER_OPTION_TRUN10_FM6 || 2846 option == DITHER_OPTION_TRUN8_FM6 || 2847 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2848 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2849 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; 2850 } else if (option == DITHER_OPTION_FM8 || 2851 option == DITHER_OPTION_SPATIAL10_FM8 || 2852 option == DITHER_OPTION_TRUN10_FM8) { 2853 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2854 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; 2855 } else if (option == DITHER_OPTION_FM10) { 2856 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2857 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; 2858 } 2859 2860 fmt_bit_depth->pixel_encoding = pixel_encoding; 2861 } 2862 2863 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) 2864 { 2865 struct dc_link *link = stream->link; 2866 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 2867 enum dc_status res = DC_OK; 2868 2869 calculate_phy_pix_clks(stream); 2870 2871 if (!tg->funcs->validate_timing(tg, &stream->timing)) 2872 res = DC_FAIL_CONTROLLER_VALIDATE; 2873 2874 if (res == DC_OK) { 2875 if (!link->link_enc->funcs->validate_output_with_stream( 2876 link->link_enc, stream)) 2877 res = DC_FAIL_ENC_VALIDATE; 2878 } 2879 2880 /* TODO: validate audio ASIC caps, encoder */ 2881 2882 if (res == DC_OK) 2883 res = dc_link_validate_mode_timing(stream, 2884 link, 2885 &stream->timing); 2886 2887 return res; 2888 } 2889 2890 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) 2891 { 2892 enum dc_status res = DC_OK; 2893 2894 /* TODO For now validates pixel format only */ 2895 if (dc->res_pool->funcs->validate_plane) 2896 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps); 2897 2898 return res; 2899 } 2900 2901 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format) 2902 { 2903 switch (format) { 2904 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 2905 return 8; 2906 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 2907 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 2908 return 12; 2909 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 2910 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2911 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 2912 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 2913 return 16; 2914 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2915 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2916 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2917 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2918 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 2919 #if defined(CONFIG_DRM_AMD_DC_DCN) 2920 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 2921 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 2922 #endif 2923 return 32; 2924 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2925 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 2926 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 2927 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2928 return 64; 2929 default: 2930 ASSERT_CRITICAL(false); 2931 return -1; 2932 } 2933 } 2934 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes) 2935 { 2936 if (modes) { 2937 if (modes->sample_rates.rate.RATE_192) 2938 return 192000; 2939 if (modes->sample_rates.rate.RATE_176_4) 2940 return 176400; 2941 if (modes->sample_rates.rate.RATE_96) 2942 return 96000; 2943 if (modes->sample_rates.rate.RATE_88_2) 2944 return 88200; 2945 if (modes->sample_rates.rate.RATE_48) 2946 return 48000; 2947 if (modes->sample_rates.rate.RATE_44_1) 2948 return 44100; 2949 if (modes->sample_rates.rate.RATE_32) 2950 return 32000; 2951 } 2952 /*original logic when no audio info*/ 2953 return 441000; 2954 } 2955 2956 void get_audio_check(struct audio_info *aud_modes, 2957 struct audio_check *audio_chk) 2958 { 2959 unsigned int i; 2960 unsigned int max_sample_rate = 0; 2961 2962 if (aud_modes) { 2963 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/ 2964 2965 audio_chk->max_audiosample_rate = 0; 2966 for (i = 0; i < aud_modes->mode_count; i++) { 2967 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]); 2968 if (audio_chk->max_audiosample_rate < max_sample_rate) 2969 audio_chk->max_audiosample_rate = max_sample_rate; 2970 /*dts takes the same as type 2: AP = 0.25*/ 2971 } 2972 /*check which one take more bandwidth*/ 2973 if (audio_chk->max_audiosample_rate > 192000) 2974 audio_chk->audio_packet_type = 0x9;/*AP =1*/ 2975 audio_chk->acat = 0;/*not support*/ 2976 } 2977 } 2978 2979