1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "resource.h" 29 #include "include/irq_service_interface.h" 30 #include "link_encoder.h" 31 #include "stream_encoder.h" 32 #include "opp.h" 33 #include "timing_generator.h" 34 #include "transform.h" 35 #include "dccg.h" 36 #include "dchubbub.h" 37 #include "dpp.h" 38 #include "core_types.h" 39 #include "set_mode_types.h" 40 #include "virtual/virtual_stream_encoder.h" 41 #include "dpcd_defs.h" 42 #include "link_enc_cfg.h" 43 #include "link.h" 44 #include "virtual/virtual_link_hwss.h" 45 #include "link/hwss/link_hwss_dio.h" 46 #include "link/hwss/link_hwss_dpia.h" 47 #include "link/hwss/link_hwss_hpo_dp.h" 48 49 #if defined(CONFIG_DRM_AMD_DC_SI) 50 #include "dce60/dce60_resource.h" 51 #endif 52 #include "dce80/dce80_resource.h" 53 #include "dce100/dce100_resource.h" 54 #include "dce110/dce110_resource.h" 55 #include "dce112/dce112_resource.h" 56 #include "dce120/dce120_resource.h" 57 #include "dcn10/dcn10_resource.h" 58 #include "dcn20/dcn20_resource.h" 59 #include "dcn21/dcn21_resource.h" 60 #include "dcn201/dcn201_resource.h" 61 #include "dcn30/dcn30_resource.h" 62 #include "dcn301/dcn301_resource.h" 63 #include "dcn302/dcn302_resource.h" 64 #include "dcn303/dcn303_resource.h" 65 #include "dcn31/dcn31_resource.h" 66 #include "dcn314/dcn314_resource.h" 67 #include "dcn315/dcn315_resource.h" 68 #include "dcn316/dcn316_resource.h" 69 #include "../dcn32/dcn32_resource.h" 70 #include "../dcn321/dcn321_resource.h" 71 72 #define DC_LOGGER_INIT(logger) 73 74 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 75 { 76 enum dce_version dc_version = DCE_VERSION_UNKNOWN; 77 78 switch (asic_id.chip_family) { 79 80 #if defined(CONFIG_DRM_AMD_DC_SI) 81 case FAMILY_SI: 82 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) || 83 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) || 84 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev)) 85 dc_version = DCE_VERSION_6_0; 86 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev)) 87 dc_version = DCE_VERSION_6_4; 88 else 89 dc_version = DCE_VERSION_6_1; 90 break; 91 #endif 92 case FAMILY_CI: 93 dc_version = DCE_VERSION_8_0; 94 break; 95 case FAMILY_KV: 96 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) || 97 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) || 98 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev)) 99 dc_version = DCE_VERSION_8_3; 100 else 101 dc_version = DCE_VERSION_8_1; 102 break; 103 case FAMILY_CZ: 104 dc_version = DCE_VERSION_11_0; 105 break; 106 107 case FAMILY_VI: 108 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || 109 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { 110 dc_version = DCE_VERSION_10_0; 111 break; 112 } 113 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || 114 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || 115 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { 116 dc_version = DCE_VERSION_11_2; 117 } 118 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) 119 dc_version = DCE_VERSION_11_22; 120 break; 121 case FAMILY_AI: 122 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev)) 123 dc_version = DCE_VERSION_12_1; 124 else 125 dc_version = DCE_VERSION_12_0; 126 break; 127 case FAMILY_RV: 128 dc_version = DCN_VERSION_1_0; 129 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) 130 dc_version = DCN_VERSION_1_01; 131 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) 132 dc_version = DCN_VERSION_2_1; 133 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) 134 dc_version = DCN_VERSION_2_1; 135 break; 136 137 case FAMILY_NV: 138 dc_version = DCN_VERSION_2_0; 139 if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) { 140 dc_version = DCN_VERSION_2_01; 141 break; 142 } 143 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) 144 dc_version = DCN_VERSION_3_0; 145 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) 146 dc_version = DCN_VERSION_3_02; 147 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) 148 dc_version = DCN_VERSION_3_03; 149 break; 150 151 case FAMILY_VGH: 152 dc_version = DCN_VERSION_3_01; 153 break; 154 155 case FAMILY_YELLOW_CARP: 156 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) 157 dc_version = DCN_VERSION_3_1; 158 break; 159 case AMDGPU_FAMILY_GC_10_3_6: 160 if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev)) 161 dc_version = DCN_VERSION_3_15; 162 break; 163 case AMDGPU_FAMILY_GC_10_3_7: 164 if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev)) 165 dc_version = DCN_VERSION_3_16; 166 break; 167 case AMDGPU_FAMILY_GC_11_0_0: 168 dc_version = DCN_VERSION_3_2; 169 if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev)) 170 dc_version = DCN_VERSION_3_21; 171 break; 172 case AMDGPU_FAMILY_GC_11_0_1: 173 dc_version = DCN_VERSION_3_14; 174 break; 175 default: 176 dc_version = DCE_VERSION_UNKNOWN; 177 break; 178 } 179 return dc_version; 180 } 181 182 struct resource_pool *dc_create_resource_pool(struct dc *dc, 183 const struct dc_init_data *init_data, 184 enum dce_version dc_version) 185 { 186 struct resource_pool *res_pool = NULL; 187 188 switch (dc_version) { 189 #if defined(CONFIG_DRM_AMD_DC_SI) 190 case DCE_VERSION_6_0: 191 res_pool = dce60_create_resource_pool( 192 init_data->num_virtual_links, dc); 193 break; 194 case DCE_VERSION_6_1: 195 res_pool = dce61_create_resource_pool( 196 init_data->num_virtual_links, dc); 197 break; 198 case DCE_VERSION_6_4: 199 res_pool = dce64_create_resource_pool( 200 init_data->num_virtual_links, dc); 201 break; 202 #endif 203 case DCE_VERSION_8_0: 204 res_pool = dce80_create_resource_pool( 205 init_data->num_virtual_links, dc); 206 break; 207 case DCE_VERSION_8_1: 208 res_pool = dce81_create_resource_pool( 209 init_data->num_virtual_links, dc); 210 break; 211 case DCE_VERSION_8_3: 212 res_pool = dce83_create_resource_pool( 213 init_data->num_virtual_links, dc); 214 break; 215 case DCE_VERSION_10_0: 216 res_pool = dce100_create_resource_pool( 217 init_data->num_virtual_links, dc); 218 break; 219 case DCE_VERSION_11_0: 220 res_pool = dce110_create_resource_pool( 221 init_data->num_virtual_links, dc, 222 init_data->asic_id); 223 break; 224 case DCE_VERSION_11_2: 225 case DCE_VERSION_11_22: 226 res_pool = dce112_create_resource_pool( 227 init_data->num_virtual_links, dc); 228 break; 229 case DCE_VERSION_12_0: 230 case DCE_VERSION_12_1: 231 res_pool = dce120_create_resource_pool( 232 init_data->num_virtual_links, dc); 233 break; 234 235 #if defined(CONFIG_DRM_AMD_DC_FP) 236 case DCN_VERSION_1_0: 237 case DCN_VERSION_1_01: 238 res_pool = dcn10_create_resource_pool(init_data, dc); 239 break; 240 case DCN_VERSION_2_0: 241 res_pool = dcn20_create_resource_pool(init_data, dc); 242 break; 243 case DCN_VERSION_2_1: 244 res_pool = dcn21_create_resource_pool(init_data, dc); 245 break; 246 case DCN_VERSION_2_01: 247 res_pool = dcn201_create_resource_pool(init_data, dc); 248 break; 249 case DCN_VERSION_3_0: 250 res_pool = dcn30_create_resource_pool(init_data, dc); 251 break; 252 case DCN_VERSION_3_01: 253 res_pool = dcn301_create_resource_pool(init_data, dc); 254 break; 255 case DCN_VERSION_3_02: 256 res_pool = dcn302_create_resource_pool(init_data, dc); 257 break; 258 case DCN_VERSION_3_03: 259 res_pool = dcn303_create_resource_pool(init_data, dc); 260 break; 261 case DCN_VERSION_3_1: 262 res_pool = dcn31_create_resource_pool(init_data, dc); 263 break; 264 case DCN_VERSION_3_14: 265 res_pool = dcn314_create_resource_pool(init_data, dc); 266 break; 267 case DCN_VERSION_3_15: 268 res_pool = dcn315_create_resource_pool(init_data, dc); 269 break; 270 case DCN_VERSION_3_16: 271 res_pool = dcn316_create_resource_pool(init_data, dc); 272 break; 273 case DCN_VERSION_3_2: 274 res_pool = dcn32_create_resource_pool(init_data, dc); 275 break; 276 case DCN_VERSION_3_21: 277 res_pool = dcn321_create_resource_pool(init_data, dc); 278 break; 279 #endif /* CONFIG_DRM_AMD_DC_FP */ 280 default: 281 break; 282 } 283 284 if (res_pool != NULL) { 285 if (dc->ctx->dc_bios->fw_info_valid) { 286 res_pool->ref_clocks.xtalin_clock_inKhz = 287 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 288 /* initialize with firmware data first, no all 289 * ASIC have DCCG SW component. FPGA or 290 * simulation need initialization of 291 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz 292 * with xtalin_clock_inKhz 293 */ 294 res_pool->ref_clocks.dccg_ref_clock_inKhz = 295 res_pool->ref_clocks.xtalin_clock_inKhz; 296 res_pool->ref_clocks.dchub_ref_clock_inKhz = 297 res_pool->ref_clocks.xtalin_clock_inKhz; 298 } else 299 ASSERT_CRITICAL(false); 300 } 301 302 return res_pool; 303 } 304 305 void dc_destroy_resource_pool(struct dc *dc) 306 { 307 if (dc) { 308 if (dc->res_pool) 309 dc->res_pool->funcs->destroy(&dc->res_pool); 310 311 kfree(dc->hwseq); 312 } 313 } 314 315 static void update_num_audio( 316 const struct resource_straps *straps, 317 unsigned int *num_audio, 318 struct audio_support *aud_support) 319 { 320 aud_support->dp_audio = true; 321 aud_support->hdmi_audio_native = false; 322 aud_support->hdmi_audio_on_dongle = false; 323 324 if (straps->hdmi_disable == 0) { 325 if (straps->dc_pinstraps_audio & 0x2) { 326 aud_support->hdmi_audio_on_dongle = true; 327 aud_support->hdmi_audio_native = true; 328 } 329 } 330 331 switch (straps->audio_stream_number) { 332 case 0: /* multi streams supported */ 333 break; 334 case 1: /* multi streams not supported */ 335 *num_audio = 1; 336 break; 337 default: 338 DC_ERR("DC: unexpected audio fuse!\n"); 339 } 340 } 341 342 bool resource_construct( 343 unsigned int num_virtual_links, 344 struct dc *dc, 345 struct resource_pool *pool, 346 const struct resource_create_funcs *create_funcs) 347 { 348 struct dc_context *ctx = dc->ctx; 349 const struct resource_caps *caps = pool->res_cap; 350 int i; 351 unsigned int num_audio = caps->num_audio; 352 struct resource_straps straps = {0}; 353 354 if (create_funcs->read_dce_straps) 355 create_funcs->read_dce_straps(dc->ctx, &straps); 356 357 pool->audio_count = 0; 358 if (create_funcs->create_audio) { 359 /* find the total number of streams available via the 360 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 361 * registers (one for each pin) starting from pin 1 362 * up to the max number of audio pins. 363 * We stop on the first pin where 364 * PORT_CONNECTIVITY == 1 (as instructed by HW team). 365 */ 366 update_num_audio(&straps, &num_audio, &pool->audio_support); 367 for (i = 0; i < caps->num_audio; i++) { 368 struct audio *aud = create_funcs->create_audio(ctx, i); 369 370 if (aud == NULL) { 371 DC_ERR("DC: failed to create audio!\n"); 372 return false; 373 } 374 if (!aud->funcs->endpoint_valid(aud)) { 375 aud->funcs->destroy(&aud); 376 break; 377 } 378 pool->audios[i] = aud; 379 pool->audio_count++; 380 } 381 } 382 383 pool->stream_enc_count = 0; 384 if (create_funcs->create_stream_encoder) { 385 for (i = 0; i < caps->num_stream_encoder; i++) { 386 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); 387 if (pool->stream_enc[i] == NULL) 388 DC_ERR("DC: failed to create stream_encoder!\n"); 389 pool->stream_enc_count++; 390 } 391 } 392 393 pool->hpo_dp_stream_enc_count = 0; 394 if (create_funcs->create_hpo_dp_stream_encoder) { 395 for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) { 396 pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx); 397 if (pool->hpo_dp_stream_enc[i] == NULL) 398 DC_ERR("DC: failed to create HPO DP stream encoder!\n"); 399 pool->hpo_dp_stream_enc_count++; 400 401 } 402 } 403 404 pool->hpo_dp_link_enc_count = 0; 405 if (create_funcs->create_hpo_dp_link_encoder) { 406 for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) { 407 pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx); 408 if (pool->hpo_dp_link_enc[i] == NULL) 409 DC_ERR("DC: failed to create HPO DP link encoder!\n"); 410 pool->hpo_dp_link_enc_count++; 411 } 412 } 413 414 for (i = 0; i < caps->num_mpc_3dlut; i++) { 415 pool->mpc_lut[i] = dc_create_3dlut_func(); 416 if (pool->mpc_lut[i] == NULL) 417 DC_ERR("DC: failed to create MPC 3dlut!\n"); 418 pool->mpc_shaper[i] = dc_create_transfer_func(); 419 if (pool->mpc_shaper[i] == NULL) 420 DC_ERR("DC: failed to create MPC shaper!\n"); 421 } 422 423 dc->caps.dynamic_audio = false; 424 if (pool->audio_count < pool->stream_enc_count) { 425 dc->caps.dynamic_audio = true; 426 } 427 for (i = 0; i < num_virtual_links; i++) { 428 pool->stream_enc[pool->stream_enc_count] = 429 virtual_stream_encoder_create( 430 ctx, ctx->dc_bios); 431 if (pool->stream_enc[pool->stream_enc_count] == NULL) { 432 DC_ERR("DC: failed to create stream_encoder!\n"); 433 return false; 434 } 435 pool->stream_enc_count++; 436 } 437 438 dc->hwseq = create_funcs->create_hwseq(ctx); 439 440 return true; 441 } 442 static int find_matching_clock_source( 443 const struct resource_pool *pool, 444 struct clock_source *clock_source) 445 { 446 447 int i; 448 449 for (i = 0; i < pool->clk_src_count; i++) { 450 if (pool->clock_sources[i] == clock_source) 451 return i; 452 } 453 return -1; 454 } 455 456 void resource_unreference_clock_source( 457 struct resource_context *res_ctx, 458 const struct resource_pool *pool, 459 struct clock_source *clock_source) 460 { 461 int i = find_matching_clock_source(pool, clock_source); 462 463 if (i > -1) 464 res_ctx->clock_source_ref_count[i]--; 465 466 if (pool->dp_clock_source == clock_source) 467 res_ctx->dp_clock_source_ref_count--; 468 } 469 470 void resource_reference_clock_source( 471 struct resource_context *res_ctx, 472 const struct resource_pool *pool, 473 struct clock_source *clock_source) 474 { 475 int i = find_matching_clock_source(pool, clock_source); 476 477 if (i > -1) 478 res_ctx->clock_source_ref_count[i]++; 479 480 if (pool->dp_clock_source == clock_source) 481 res_ctx->dp_clock_source_ref_count++; 482 } 483 484 int resource_get_clock_source_reference( 485 struct resource_context *res_ctx, 486 const struct resource_pool *pool, 487 struct clock_source *clock_source) 488 { 489 int i = find_matching_clock_source(pool, clock_source); 490 491 if (i > -1) 492 return res_ctx->clock_source_ref_count[i]; 493 494 if (pool->dp_clock_source == clock_source) 495 return res_ctx->dp_clock_source_ref_count; 496 497 return -1; 498 } 499 500 bool resource_are_vblanks_synchronizable( 501 struct dc_stream_state *stream1, 502 struct dc_stream_state *stream2) 503 { 504 uint32_t base60_refresh_rates[] = {10, 20, 5}; 505 uint8_t i; 506 uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates); 507 uint64_t frame_time_diff; 508 509 if (stream1->ctx->dc->config.vblank_alignment_dto_params && 510 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 && 511 dc_is_dp_signal(stream1->signal) && 512 dc_is_dp_signal(stream2->signal) && 513 false == stream1->has_non_synchronizable_pclk && 514 false == stream2->has_non_synchronizable_pclk && 515 stream1->timing.flags.VBLANK_SYNCHRONIZABLE && 516 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) { 517 /* disable refresh rates higher than 60Hz for now */ 518 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/ 519 stream1->timing.v_total > 60) 520 return false; 521 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/ 522 stream2->timing.v_total > 60) 523 return false; 524 frame_time_diff = (uint64_t)10000 * 525 stream1->timing.h_total * 526 stream1->timing.v_total * 527 stream2->timing.pix_clk_100hz; 528 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz); 529 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total); 530 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total); 531 for (i = 0; i < rr_count; i++) { 532 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000; 533 534 if (diff < 0) 535 diff = -diff; 536 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff) 537 return true; 538 } 539 } 540 return false; 541 } 542 543 bool resource_are_streams_timing_synchronizable( 544 struct dc_stream_state *stream1, 545 struct dc_stream_state *stream2) 546 { 547 if (stream1->timing.h_total != stream2->timing.h_total) 548 return false; 549 550 if (stream1->timing.v_total != stream2->timing.v_total) 551 return false; 552 553 if (stream1->timing.h_addressable 554 != stream2->timing.h_addressable) 555 return false; 556 557 if (stream1->timing.v_addressable 558 != stream2->timing.v_addressable) 559 return false; 560 561 if (stream1->timing.v_front_porch 562 != stream2->timing.v_front_porch) 563 return false; 564 565 if (stream1->timing.pix_clk_100hz 566 != stream2->timing.pix_clk_100hz) 567 return false; 568 569 if (stream1->clamping.c_depth != stream2->clamping.c_depth) 570 return false; 571 572 if (stream1->phy_pix_clk != stream2->phy_pix_clk 573 && (!dc_is_dp_signal(stream1->signal) 574 || !dc_is_dp_signal(stream2->signal))) 575 return false; 576 577 if (stream1->view_format != stream2->view_format) 578 return false; 579 580 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param) 581 return false; 582 583 return true; 584 } 585 static bool is_dp_and_hdmi_sharable( 586 struct dc_stream_state *stream1, 587 struct dc_stream_state *stream2) 588 { 589 if (stream1->ctx->dc->caps.disable_dp_clk_share) 590 return false; 591 592 if (stream1->clamping.c_depth != COLOR_DEPTH_888 || 593 stream2->clamping.c_depth != COLOR_DEPTH_888) 594 return false; 595 596 return true; 597 598 } 599 600 static bool is_sharable_clk_src( 601 const struct pipe_ctx *pipe_with_clk_src, 602 const struct pipe_ctx *pipe) 603 { 604 if (pipe_with_clk_src->clock_source == NULL) 605 return false; 606 607 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) 608 return false; 609 610 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) || 611 (dc_is_dp_signal(pipe->stream->signal) && 612 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream, 613 pipe->stream))) 614 return false; 615 616 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) 617 && dc_is_dual_link_signal(pipe->stream->signal)) 618 return false; 619 620 if (dc_is_hdmi_signal(pipe->stream->signal) 621 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal)) 622 return false; 623 624 if (!resource_are_streams_timing_synchronizable( 625 pipe_with_clk_src->stream, pipe->stream)) 626 return false; 627 628 return true; 629 } 630 631 struct clock_source *resource_find_used_clk_src_for_sharing( 632 struct resource_context *res_ctx, 633 struct pipe_ctx *pipe_ctx) 634 { 635 int i; 636 637 for (i = 0; i < MAX_PIPES; i++) { 638 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) 639 return res_ctx->pipe_ctx[i].clock_source; 640 } 641 642 return NULL; 643 } 644 645 static enum pixel_format convert_pixel_format_to_dalsurface( 646 enum surface_pixel_format surface_pixel_format) 647 { 648 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 649 650 switch (surface_pixel_format) { 651 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 652 dal_pixel_format = PIXEL_FORMAT_INDEX8; 653 break; 654 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 655 dal_pixel_format = PIXEL_FORMAT_RGB565; 656 break; 657 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 658 dal_pixel_format = PIXEL_FORMAT_RGB565; 659 break; 660 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 661 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 662 break; 663 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 664 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 665 break; 666 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 667 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 668 break; 669 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 670 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 671 break; 672 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 673 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS; 674 break; 675 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 676 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 677 dal_pixel_format = PIXEL_FORMAT_FP16; 678 break; 679 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 680 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 681 dal_pixel_format = PIXEL_FORMAT_420BPP8; 682 break; 683 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 684 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 685 dal_pixel_format = PIXEL_FORMAT_420BPP10; 686 break; 687 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 688 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 689 default: 690 dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 691 break; 692 } 693 return dal_pixel_format; 694 } 695 696 static inline void get_vp_scan_direction( 697 enum dc_rotation_angle rotation, 698 bool horizontal_mirror, 699 bool *orthogonal_rotation, 700 bool *flip_vert_scan_dir, 701 bool *flip_horz_scan_dir) 702 { 703 *orthogonal_rotation = false; 704 *flip_vert_scan_dir = false; 705 *flip_horz_scan_dir = false; 706 if (rotation == ROTATION_ANGLE_180) { 707 *flip_vert_scan_dir = true; 708 *flip_horz_scan_dir = true; 709 } else if (rotation == ROTATION_ANGLE_90) { 710 *orthogonal_rotation = true; 711 *flip_horz_scan_dir = true; 712 } else if (rotation == ROTATION_ANGLE_270) { 713 *orthogonal_rotation = true; 714 *flip_vert_scan_dir = true; 715 } 716 717 if (horizontal_mirror) 718 *flip_horz_scan_dir = !*flip_horz_scan_dir; 719 } 720 721 int get_num_mpc_splits(struct pipe_ctx *pipe) 722 { 723 int mpc_split_count = 0; 724 struct pipe_ctx *other_pipe = pipe->bottom_pipe; 725 726 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 727 mpc_split_count++; 728 other_pipe = other_pipe->bottom_pipe; 729 } 730 other_pipe = pipe->top_pipe; 731 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 732 mpc_split_count++; 733 other_pipe = other_pipe->top_pipe; 734 } 735 736 return mpc_split_count; 737 } 738 739 int get_num_odm_splits(struct pipe_ctx *pipe) 740 { 741 int odm_split_count = 0; 742 struct pipe_ctx *next_pipe = pipe->next_odm_pipe; 743 while (next_pipe) { 744 odm_split_count++; 745 next_pipe = next_pipe->next_odm_pipe; 746 } 747 pipe = pipe->prev_odm_pipe; 748 while (pipe) { 749 odm_split_count++; 750 pipe = pipe->prev_odm_pipe; 751 } 752 return odm_split_count; 753 } 754 755 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx) 756 { 757 *split_count = get_num_odm_splits(pipe_ctx); 758 *split_idx = 0; 759 if (*split_count == 0) { 760 /*Check for mpc split*/ 761 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe; 762 763 *split_count = get_num_mpc_splits(pipe_ctx); 764 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) { 765 (*split_idx)++; 766 split_pipe = split_pipe->top_pipe; 767 } 768 769 /* MPO window on right side of ODM split */ 770 if (split_pipe && split_pipe->prev_odm_pipe && !pipe_ctx->prev_odm_pipe) 771 (*split_idx)++; 772 } else { 773 /*Get odm split index*/ 774 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe; 775 776 while (split_pipe) { 777 (*split_idx)++; 778 split_pipe = split_pipe->prev_odm_pipe; 779 } 780 } 781 } 782 783 /* 784 * This is a preliminary vp size calculation to allow us to check taps support. 785 * The result is completely overridden afterwards. 786 */ 787 static void calculate_viewport_size(struct pipe_ctx *pipe_ctx) 788 { 789 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 790 791 data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width)); 792 data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height)); 793 data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width)); 794 data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height)); 795 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 796 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { 797 swap(data->viewport.width, data->viewport.height); 798 swap(data->viewport_c.width, data->viewport_c.height); 799 } 800 } 801 802 static void calculate_recout(struct pipe_ctx *pipe_ctx) 803 { 804 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 805 const struct dc_stream_state *stream = pipe_ctx->stream; 806 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 807 struct rect surf_clip = plane_state->clip_rect; 808 bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; 809 int split_count, split_idx; 810 811 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 812 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 813 split_idx = 0; 814 815 /* 816 * Only the leftmost ODM pipe should be offset by a nonzero distance 817 */ 818 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->prev_odm_pipe && !pipe_ctx->prev_odm_pipe) { 819 /* MPO window on right side of ODM split */ 820 data->recout.x = stream->dst.x + (surf_clip.x - stream->src.x - stream->src.width/2) * 821 stream->dst.width / stream->src.width; 822 } else if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) { 823 data->recout.x = stream->dst.x; 824 if (stream->src.x < surf_clip.x) 825 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width 826 / stream->src.width; 827 } else 828 data->recout.x = 0; 829 830 if (stream->src.x > surf_clip.x) 831 surf_clip.width -= stream->src.x - surf_clip.x; 832 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width; 833 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width) 834 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x; 835 836 data->recout.y = stream->dst.y; 837 if (stream->src.y < surf_clip.y) 838 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height 839 / stream->src.height; 840 else if (stream->src.y > surf_clip.y) 841 surf_clip.height -= stream->src.y - surf_clip.y; 842 843 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height; 844 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height) 845 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y; 846 847 /* Handle h & v split */ 848 if (split_tb) { 849 ASSERT(data->recout.height % 2 == 0); 850 data->recout.height /= 2; 851 } else if (split_count) { 852 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) { 853 /* extra pixels in the division remainder need to go to pipes after 854 * the extra pixel index minus one(epimo) defined here as: 855 */ 856 int epimo = split_count - data->recout.width % (split_count + 1); 857 858 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx; 859 if (split_idx > epimo) 860 data->recout.x += split_idx - epimo - 1; 861 ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0); 862 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0); 863 } else { 864 /* odm */ 865 if (split_idx == split_count) { 866 /* rightmost pipe is the remainder recout */ 867 data->recout.width -= data->h_active * split_count - data->recout.x; 868 869 /* ODM combine cases with MPO we can get negative widths */ 870 if (data->recout.width < 0) 871 data->recout.width = 0; 872 873 data->recout.x = 0; 874 } else 875 data->recout.width = data->h_active - data->recout.x; 876 } 877 } 878 } 879 880 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) 881 { 882 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 883 const struct dc_stream_state *stream = pipe_ctx->stream; 884 struct rect surf_src = plane_state->src_rect; 885 const int in_w = stream->src.width; 886 const int in_h = stream->src.height; 887 const int out_w = stream->dst.width; 888 const int out_h = stream->dst.height; 889 890 /*Swap surf_src height and width since scaling ratios are in recout rotation*/ 891 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 892 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 893 swap(surf_src.height, surf_src.width); 894 895 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( 896 surf_src.width, 897 plane_state->dst_rect.width); 898 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( 899 surf_src.height, 900 plane_state->dst_rect.height); 901 902 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 903 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; 904 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 905 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; 906 907 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( 908 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); 909 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( 910 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); 911 912 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; 913 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; 914 915 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 916 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { 917 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; 918 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; 919 } 920 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate( 921 pipe_ctx->plane_res.scl_data.ratios.horz, 19); 922 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( 923 pipe_ctx->plane_res.scl_data.ratios.vert, 19); 924 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate( 925 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19); 926 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate( 927 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); 928 } 929 930 931 /* 932 * We completely calculate vp offset, size and inits here based entirely on scaling 933 * ratios and recout for pixel perfect pipe combine. 934 */ 935 static void calculate_init_and_vp( 936 bool flip_scan_dir, 937 int recout_offset_within_recout_full, 938 int recout_size, 939 int src_size, 940 int taps, 941 struct fixed31_32 ratio, 942 struct fixed31_32 *init, 943 int *vp_offset, 944 int *vp_size) 945 { 946 struct fixed31_32 temp; 947 int int_part; 948 949 /* 950 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout 951 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on. 952 * All following calculations are based on this logic. 953 * 954 * Init calculated according to formula: 955 * init = (scaling_ratio + number_of_taps + 1) / 2 956 * init_bot = init + scaling_ratio 957 * to get pixel perfect combine add the fraction from calculating vp offset 958 */ 959 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full); 960 *vp_offset = dc_fixpt_floor(temp); 961 temp.value &= 0xffffffff; 962 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int( 963 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19); 964 /* 965 * If viewport has non 0 offset and there are more taps than covered by init then 966 * we should decrease the offset and increase init so we are never sampling 967 * outside of viewport. 968 */ 969 int_part = dc_fixpt_floor(*init); 970 if (int_part < taps) { 971 int_part = taps - int_part; 972 if (int_part > *vp_offset) 973 int_part = *vp_offset; 974 *vp_offset -= int_part; 975 *init = dc_fixpt_add_int(*init, int_part); 976 } 977 /* 978 * If taps are sampling outside of viewport at end of recout and there are more pixels 979 * available in the surface we should increase the viewport size, regardless set vp to 980 * only what is used. 981 */ 982 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1)); 983 *vp_size = dc_fixpt_floor(temp); 984 if (*vp_size + *vp_offset > src_size) 985 *vp_size = src_size - *vp_offset; 986 987 /* We did all the math assuming we are scanning same direction as display does, 988 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction 989 * is flipped we simply need to calculate offset from the other side of plane. 990 * Note that outside of viewport all scaling hardware works in recout space. 991 */ 992 if (flip_scan_dir) 993 *vp_offset = src_size - *vp_offset - *vp_size; 994 } 995 996 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx) 997 { 998 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 999 const struct dc_stream_state *stream = pipe_ctx->stream; 1000 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 1001 struct rect src = plane_state->src_rect; 1002 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 1003 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 1004 int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y; 1005 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; 1006 1007 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 1008 /* 1009 * recout full is what the recout would have been if we didnt clip 1010 * the source plane at all. We only care about left(ro_lb) and top(ro_tb) 1011 * offsets of recout within recout full because those are the directions 1012 * we scan from and therefore the only ones that affect inits. 1013 */ 1014 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) 1015 * stream->dst.width / stream->src.width; 1016 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) 1017 * stream->dst.height / stream->src.height; 1018 if (pipe_ctx->prev_odm_pipe && split_idx) 1019 ro_lb = data->h_active * split_idx - recout_full_x; 1020 else if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->prev_odm_pipe) 1021 ro_lb = data->h_active * split_idx - recout_full_x + data->recout.x; 1022 else 1023 ro_lb = data->recout.x - recout_full_x; 1024 ro_tb = data->recout.y - recout_full_y; 1025 ASSERT(ro_lb >= 0 && ro_tb >= 0); 1026 1027 /* 1028 * Work in recout rotation since that requires less transformations 1029 */ 1030 get_vp_scan_direction( 1031 plane_state->rotation, 1032 plane_state->horizontal_mirror, 1033 &orthogonal_rotation, 1034 &flip_vert_scan_dir, 1035 &flip_horz_scan_dir); 1036 1037 if (orthogonal_rotation) { 1038 swap(src.width, src.height); 1039 swap(flip_vert_scan_dir, flip_horz_scan_dir); 1040 } 1041 1042 calculate_init_and_vp( 1043 flip_horz_scan_dir, 1044 ro_lb, 1045 data->recout.width, 1046 src.width, 1047 data->taps.h_taps, 1048 data->ratios.horz, 1049 &data->inits.h, 1050 &data->viewport.x, 1051 &data->viewport.width); 1052 calculate_init_and_vp( 1053 flip_horz_scan_dir, 1054 ro_lb, 1055 data->recout.width, 1056 src.width / vpc_div, 1057 data->taps.h_taps_c, 1058 data->ratios.horz_c, 1059 &data->inits.h_c, 1060 &data->viewport_c.x, 1061 &data->viewport_c.width); 1062 calculate_init_and_vp( 1063 flip_vert_scan_dir, 1064 ro_tb, 1065 data->recout.height, 1066 src.height, 1067 data->taps.v_taps, 1068 data->ratios.vert, 1069 &data->inits.v, 1070 &data->viewport.y, 1071 &data->viewport.height); 1072 calculate_init_and_vp( 1073 flip_vert_scan_dir, 1074 ro_tb, 1075 data->recout.height, 1076 src.height / vpc_div, 1077 data->taps.v_taps_c, 1078 data->ratios.vert_c, 1079 &data->inits.v_c, 1080 &data->viewport_c.y, 1081 &data->viewport_c.height); 1082 if (orthogonal_rotation) { 1083 swap(data->viewport.x, data->viewport.y); 1084 swap(data->viewport.width, data->viewport.height); 1085 swap(data->viewport_c.x, data->viewport_c.y); 1086 swap(data->viewport_c.width, data->viewport_c.height); 1087 } 1088 data->viewport.x += src.x; 1089 data->viewport.y += src.y; 1090 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); 1091 data->viewport_c.x += src.x / vpc_div; 1092 data->viewport_c.y += src.y / vpc_div; 1093 } 1094 1095 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 1096 { 1097 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1098 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 1099 bool res = false; 1100 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 1101 1102 /* Invalid input */ 1103 if (!plane_state->dst_rect.width || 1104 !plane_state->dst_rect.height || 1105 !plane_state->src_rect.width || 1106 !plane_state->src_rect.height) { 1107 ASSERT(0); 1108 return false; 1109 } 1110 1111 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( 1112 pipe_ctx->plane_state->format); 1113 1114 /* Timing borders are part of vactive that we are also supposed to skip in addition 1115 * to any stream dst offset. Since dm logic assumes dst is in addressable 1116 * space we need to add the left and top borders to dst offsets temporarily. 1117 * TODO: fix in DM, stream dst is supposed to be in vactive 1118 */ 1119 pipe_ctx->stream->dst.x += timing->h_border_left; 1120 pipe_ctx->stream->dst.y += timing->v_border_top; 1121 1122 /* Calculate H and V active size */ 1123 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + 1124 timing->h_border_left + timing->h_border_right; 1125 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + 1126 timing->v_border_top + timing->v_border_bottom; 1127 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe) { 1128 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1; 1129 1130 DC_LOG_SCALER("%s pipe %d: next_odm_pipe:%d prev_odm_pipe:%d\n", 1131 __func__, 1132 pipe_ctx->pipe_idx, 1133 pipe_ctx->next_odm_pipe ? pipe_ctx->next_odm_pipe->pipe_idx : -1, 1134 pipe_ctx->prev_odm_pipe ? pipe_ctx->prev_odm_pipe->pipe_idx : -1); 1135 } /* ODM + windows MPO, where window is on either right or left ODM half */ 1136 else if (pipe_ctx->top_pipe && (pipe_ctx->top_pipe->next_odm_pipe || pipe_ctx->top_pipe->prev_odm_pipe)) { 1137 1138 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx->top_pipe) + 1; 1139 1140 DC_LOG_SCALER("%s ODM + windows MPO: pipe:%d top_pipe:%d top_pipe->next_odm_pipe:%d top_pipe->prev_odm_pipe:%d\n", 1141 __func__, 1142 pipe_ctx->pipe_idx, 1143 pipe_ctx->top_pipe->pipe_idx, 1144 pipe_ctx->top_pipe->next_odm_pipe ? pipe_ctx->top_pipe->next_odm_pipe->pipe_idx : -1, 1145 pipe_ctx->top_pipe->prev_odm_pipe ? pipe_ctx->top_pipe->prev_odm_pipe->pipe_idx : -1); 1146 } 1147 /* depends on h_active */ 1148 calculate_recout(pipe_ctx); 1149 /* depends on pixel format */ 1150 calculate_scaling_ratios(pipe_ctx); 1151 /* depends on scaling ratios and recout, does not calculate offset yet */ 1152 calculate_viewport_size(pipe_ctx); 1153 1154 if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) { 1155 /* Stopgap for validation of ODM + MPO on one side of screen case */ 1156 if (pipe_ctx->plane_res.scl_data.viewport.height < 1 || 1157 pipe_ctx->plane_res.scl_data.viewport.width < 1) 1158 return false; 1159 } 1160 1161 /* 1162 * LB calculations depend on vp size, h/v_active and scaling ratios 1163 * Setting line buffer pixel depth to 24bpp yields banding 1164 * on certain displays, such as the Sharp 4k. 36bpp is needed 1165 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and 1166 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc 1167 * precision on DCN display engines, but apparently not for DCE, as 1168 * far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have 1169 * problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth, 1170 * neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel 1171 * passthrough). Therefore only use 36 bpp on DCN where it is actually needed. 1172 */ 1173 if (plane_state->ctx->dce_version > DCE_VERSION_MAX) 1174 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; 1175 else 1176 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; 1177 1178 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; 1179 1180 if (pipe_ctx->plane_res.xfm != NULL) 1181 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1182 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1183 1184 if (pipe_ctx->plane_res.dpp != NULL) 1185 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1186 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1187 1188 1189 if (!res) { 1190 /* Try 24 bpp linebuffer */ 1191 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; 1192 1193 if (pipe_ctx->plane_res.xfm != NULL) 1194 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1195 pipe_ctx->plane_res.xfm, 1196 &pipe_ctx->plane_res.scl_data, 1197 &plane_state->scaling_quality); 1198 1199 if (pipe_ctx->plane_res.dpp != NULL) 1200 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1201 pipe_ctx->plane_res.dpp, 1202 &pipe_ctx->plane_res.scl_data, 1203 &plane_state->scaling_quality); 1204 } 1205 1206 /* 1207 * Depends on recout, scaling ratios, h_active and taps 1208 * May need to re-check lb size after this in some obscure scenario 1209 */ 1210 if (res) 1211 calculate_inits_and_viewports(pipe_ctx); 1212 1213 /* 1214 * Handle side by side and top bottom 3d recout offsets after vp calculation 1215 * since 3d is special and needs to calculate vp as if there is no recout offset 1216 * This may break with rotation, good thing we aren't mixing hw rotation and 3d 1217 */ 1218 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) { 1219 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 || 1220 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM && 1221 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE)); 1222 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 1223 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; 1224 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 1225 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; 1226 } 1227 1228 if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) { 1229 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE || 1230 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) 1231 res = false; 1232 } else { 1233 /* Clamp minimum viewport size */ 1234 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE) 1235 pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE; 1236 if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) 1237 pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE; 1238 } 1239 1240 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n" 1241 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n", 1242 __func__, 1243 pipe_ctx->pipe_idx, 1244 pipe_ctx->plane_res.scl_data.viewport.height, 1245 pipe_ctx->plane_res.scl_data.viewport.width, 1246 pipe_ctx->plane_res.scl_data.viewport.x, 1247 pipe_ctx->plane_res.scl_data.viewport.y, 1248 pipe_ctx->plane_res.scl_data.recout.height, 1249 pipe_ctx->plane_res.scl_data.recout.width, 1250 pipe_ctx->plane_res.scl_data.recout.x, 1251 pipe_ctx->plane_res.scl_data.recout.y, 1252 pipe_ctx->plane_res.scl_data.h_active, 1253 pipe_ctx->plane_res.scl_data.v_active, 1254 plane_state->src_rect.height, 1255 plane_state->src_rect.width, 1256 plane_state->src_rect.x, 1257 plane_state->src_rect.y, 1258 plane_state->dst_rect.height, 1259 plane_state->dst_rect.width, 1260 plane_state->dst_rect.x, 1261 plane_state->dst_rect.y, 1262 plane_state->clip_rect.height, 1263 plane_state->clip_rect.width, 1264 plane_state->clip_rect.x, 1265 plane_state->clip_rect.y); 1266 1267 pipe_ctx->stream->dst.x -= timing->h_border_left; 1268 pipe_ctx->stream->dst.y -= timing->v_border_top; 1269 1270 return res; 1271 } 1272 1273 1274 enum dc_status resource_build_scaling_params_for_context( 1275 const struct dc *dc, 1276 struct dc_state *context) 1277 { 1278 int i; 1279 1280 for (i = 0; i < MAX_PIPES; i++) { 1281 if (context->res_ctx.pipe_ctx[i].plane_state != NULL && 1282 context->res_ctx.pipe_ctx[i].stream != NULL) 1283 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) 1284 return DC_FAIL_SCALING; 1285 } 1286 1287 return DC_OK; 1288 } 1289 1290 struct pipe_ctx *find_idle_secondary_pipe( 1291 struct resource_context *res_ctx, 1292 const struct resource_pool *pool, 1293 const struct pipe_ctx *primary_pipe) 1294 { 1295 int i; 1296 struct pipe_ctx *secondary_pipe = NULL; 1297 1298 /* 1299 * We add a preferred pipe mapping to avoid the chance that 1300 * MPCCs already in use will need to be reassigned to other trees. 1301 * For example, if we went with the strict, assign backwards logic: 1302 * 1303 * (State 1) 1304 * Display A on, no surface, top pipe = 0 1305 * Display B on, no surface, top pipe = 1 1306 * 1307 * (State 2) 1308 * Display A on, no surface, top pipe = 0 1309 * Display B on, surface enable, top pipe = 1, bottom pipe = 5 1310 * 1311 * (State 3) 1312 * Display A on, surface enable, top pipe = 0, bottom pipe = 5 1313 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1314 * 1315 * The state 2->3 transition requires remapping MPCC 5 from display B 1316 * to display A. 1317 * 1318 * However, with the preferred pipe logic, state 2 would look like: 1319 * 1320 * (State 2) 1321 * Display A on, no surface, top pipe = 0 1322 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1323 * 1324 * This would then cause 2->3 to not require remapping any MPCCs. 1325 */ 1326 if (primary_pipe) { 1327 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 1328 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1329 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1330 secondary_pipe->pipe_idx = preferred_pipe_idx; 1331 } 1332 } 1333 1334 /* 1335 * search backwards for the second pipe to keep pipe 1336 * assignment more consistent 1337 */ 1338 if (!secondary_pipe) 1339 for (i = pool->pipe_count - 1; i >= 0; i--) { 1340 if (res_ctx->pipe_ctx[i].stream == NULL) { 1341 secondary_pipe = &res_ctx->pipe_ctx[i]; 1342 secondary_pipe->pipe_idx = i; 1343 break; 1344 } 1345 } 1346 1347 return secondary_pipe; 1348 } 1349 1350 struct pipe_ctx *resource_get_head_pipe_for_stream( 1351 struct resource_context *res_ctx, 1352 struct dc_stream_state *stream) 1353 { 1354 int i; 1355 1356 for (i = 0; i < MAX_PIPES; i++) { 1357 if (res_ctx->pipe_ctx[i].stream == stream 1358 && !res_ctx->pipe_ctx[i].top_pipe 1359 && !res_ctx->pipe_ctx[i].prev_odm_pipe) 1360 return &res_ctx->pipe_ctx[i]; 1361 } 1362 return NULL; 1363 } 1364 1365 static struct pipe_ctx *resource_get_tail_pipe( 1366 struct resource_context *res_ctx, 1367 struct pipe_ctx *head_pipe) 1368 { 1369 struct pipe_ctx *tail_pipe; 1370 1371 tail_pipe = head_pipe->bottom_pipe; 1372 1373 while (tail_pipe) { 1374 head_pipe = tail_pipe; 1375 tail_pipe = tail_pipe->bottom_pipe; 1376 } 1377 1378 return head_pipe; 1379 } 1380 1381 /* 1382 * A free_pipe for a stream is defined here as a pipe 1383 * that has no surface attached yet 1384 */ 1385 static struct pipe_ctx *acquire_free_pipe_for_head( 1386 struct dc_state *context, 1387 const struct resource_pool *pool, 1388 struct pipe_ctx *head_pipe) 1389 { 1390 int i; 1391 struct resource_context *res_ctx = &context->res_ctx; 1392 1393 if (!head_pipe->plane_state) 1394 return head_pipe; 1395 1396 /* Re-use pipe already acquired for this stream if available*/ 1397 for (i = pool->pipe_count - 1; i >= 0; i--) { 1398 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream && 1399 !res_ctx->pipe_ctx[i].plane_state) { 1400 return &res_ctx->pipe_ctx[i]; 1401 } 1402 } 1403 1404 /* 1405 * At this point we have no re-useable pipe for this stream and we need 1406 * to acquire an idle one to satisfy the request 1407 */ 1408 1409 if (!pool->funcs->acquire_idle_pipe_for_layer) { 1410 if (!pool->funcs->acquire_idle_pipe_for_head_pipe_in_layer) 1411 return NULL; 1412 else 1413 return pool->funcs->acquire_idle_pipe_for_head_pipe_in_layer(context, pool, head_pipe->stream, head_pipe); 1414 } 1415 1416 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream); 1417 } 1418 1419 static int acquire_first_split_pipe( 1420 struct resource_context *res_ctx, 1421 const struct resource_pool *pool, 1422 struct dc_stream_state *stream) 1423 { 1424 int i; 1425 1426 for (i = 0; i < pool->pipe_count; i++) { 1427 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; 1428 1429 if (split_pipe->top_pipe && 1430 split_pipe->top_pipe->plane_state == split_pipe->plane_state) { 1431 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; 1432 if (split_pipe->bottom_pipe) 1433 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; 1434 1435 if (split_pipe->top_pipe->plane_state) 1436 resource_build_scaling_params(split_pipe->top_pipe); 1437 1438 memset(split_pipe, 0, sizeof(*split_pipe)); 1439 split_pipe->stream_res.tg = pool->timing_generators[i]; 1440 split_pipe->plane_res.hubp = pool->hubps[i]; 1441 split_pipe->plane_res.ipp = pool->ipps[i]; 1442 split_pipe->plane_res.dpp = pool->dpps[i]; 1443 split_pipe->stream_res.opp = pool->opps[i]; 1444 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; 1445 split_pipe->pipe_idx = i; 1446 1447 split_pipe->stream = stream; 1448 return i; 1449 } else if (split_pipe->prev_odm_pipe && 1450 split_pipe->prev_odm_pipe->plane_state == split_pipe->plane_state) { 1451 split_pipe->prev_odm_pipe->next_odm_pipe = split_pipe->next_odm_pipe; 1452 if (split_pipe->next_odm_pipe) 1453 split_pipe->next_odm_pipe->prev_odm_pipe = split_pipe->prev_odm_pipe; 1454 1455 if (split_pipe->prev_odm_pipe->plane_state) 1456 resource_build_scaling_params(split_pipe->prev_odm_pipe); 1457 1458 memset(split_pipe, 0, sizeof(*split_pipe)); 1459 split_pipe->stream_res.tg = pool->timing_generators[i]; 1460 split_pipe->plane_res.hubp = pool->hubps[i]; 1461 split_pipe->plane_res.ipp = pool->ipps[i]; 1462 split_pipe->plane_res.dpp = pool->dpps[i]; 1463 split_pipe->stream_res.opp = pool->opps[i]; 1464 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; 1465 split_pipe->pipe_idx = i; 1466 1467 split_pipe->stream = stream; 1468 return i; 1469 } 1470 } 1471 return -1; 1472 } 1473 1474 bool dc_add_plane_to_context( 1475 const struct dc *dc, 1476 struct dc_stream_state *stream, 1477 struct dc_plane_state *plane_state, 1478 struct dc_state *context) 1479 { 1480 int i; 1481 struct resource_pool *pool = dc->res_pool; 1482 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; 1483 struct dc_stream_status *stream_status = NULL; 1484 struct pipe_ctx *prev_right_head = NULL; 1485 struct pipe_ctx *free_right_pipe = NULL; 1486 struct pipe_ctx *prev_left_head = NULL; 1487 1488 DC_LOGGER_INIT(stream->ctx->logger); 1489 for (i = 0; i < context->stream_count; i++) 1490 if (context->streams[i] == stream) { 1491 stream_status = &context->stream_status[i]; 1492 break; 1493 } 1494 if (stream_status == NULL) { 1495 dm_error("Existing stream not found; failed to attach surface!\n"); 1496 return false; 1497 } 1498 1499 1500 if (stream_status->plane_count == MAX_SURFACE_NUM) { 1501 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", 1502 plane_state, MAX_SURFACE_NUM); 1503 return false; 1504 } 1505 1506 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1507 1508 if (!head_pipe) { 1509 dm_error("Head pipe not found for stream_state %p !\n", stream); 1510 return false; 1511 } 1512 1513 /* retain new surface, but only once per stream */ 1514 dc_plane_state_retain(plane_state); 1515 1516 while (head_pipe) { 1517 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe); 1518 1519 if (!free_pipe) { 1520 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 1521 if (pipe_idx >= 0) 1522 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; 1523 } 1524 1525 if (!free_pipe) { 1526 dc_plane_state_release(plane_state); 1527 return false; 1528 } 1529 1530 free_pipe->plane_state = plane_state; 1531 1532 if (head_pipe != free_pipe) { 1533 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe); 1534 ASSERT(tail_pipe); 1535 1536 /* ODM + window MPO, where MPO window is on right half only */ 1537 if (free_pipe->plane_state && 1538 (free_pipe->plane_state->clip_rect.x >= free_pipe->stream->src.x + free_pipe->stream->src.width/2) && 1539 tail_pipe->next_odm_pipe) { 1540 1541 /* For ODM + window MPO, in 3 plane case, if we already have a MPO window on 1542 * the right side, then we will invalidate a 2nd one on the right side 1543 */ 1544 if (head_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) { 1545 dc_plane_state_release(plane_state); 1546 return false; 1547 } 1548 1549 DC_LOG_SCALER("%s - ODM + window MPO(right). free_pipe:%d tail_pipe->next_odm_pipe:%d\n", 1550 __func__, 1551 free_pipe->pipe_idx, 1552 tail_pipe->next_odm_pipe ? tail_pipe->next_odm_pipe->pipe_idx : -1); 1553 1554 /* 1555 * We want to avoid the case where the right side already has a pipe assigned to 1556 * it and is different from free_pipe ( which would cause trigger a pipe 1557 * reallocation ). 1558 * Check the old context to see if the right side already has a pipe allocated 1559 * - If not, continue to use free_pipe 1560 * - If the right side already has a pipe, use that pipe instead if its available 1561 */ 1562 1563 /* 1564 * We also want to avoid the case where with three plane ( 2 MPO videos ), we have 1565 * both videos on the left side so one of the videos is invalidated. Then we 1566 * move the invalidated video back to the right side. If the order of the plane 1567 * states is such that the right MPO plane is processed first, the free pipe 1568 * selected by the head will be the left MPO pipe. But since there was no right 1569 * MPO pipe, it will assign the free pipe to the right MPO pipe instead and 1570 * a pipe reallocation will occur. 1571 * Check the old context to see if the left side already has a pipe allocated 1572 * - If not, continue to use free_pipe 1573 * - If the left side is already using this pipe, then pick another pipe for right 1574 */ 1575 1576 prev_right_head = &dc->current_state->res_ctx.pipe_ctx[tail_pipe->next_odm_pipe->pipe_idx]; 1577 if ((prev_right_head->bottom_pipe) && 1578 (free_pipe->pipe_idx != prev_right_head->bottom_pipe->pipe_idx)) { 1579 free_right_pipe = acquire_free_pipe_for_head(context, pool, tail_pipe->next_odm_pipe); 1580 } else { 1581 prev_left_head = &dc->current_state->res_ctx.pipe_ctx[head_pipe->pipe_idx]; 1582 if ((prev_left_head->bottom_pipe) && 1583 (free_pipe->pipe_idx == prev_left_head->bottom_pipe->pipe_idx)) { 1584 free_right_pipe = acquire_free_pipe_for_head(context, pool, head_pipe); 1585 } 1586 } 1587 1588 if (free_right_pipe) { 1589 free_pipe->stream = NULL; 1590 memset(&free_pipe->stream_res, 0, sizeof(struct stream_resource)); 1591 memset(&free_pipe->plane_res, 0, sizeof(struct plane_resource)); 1592 free_pipe->plane_state = NULL; 1593 free_pipe->pipe_idx = 0; 1594 free_right_pipe->plane_state = plane_state; 1595 free_pipe = free_right_pipe; 1596 } 1597 1598 free_pipe->stream_res.tg = tail_pipe->next_odm_pipe->stream_res.tg; 1599 free_pipe->stream_res.abm = tail_pipe->next_odm_pipe->stream_res.abm; 1600 free_pipe->stream_res.opp = tail_pipe->next_odm_pipe->stream_res.opp; 1601 free_pipe->stream_res.stream_enc = tail_pipe->next_odm_pipe->stream_res.stream_enc; 1602 free_pipe->stream_res.audio = tail_pipe->next_odm_pipe->stream_res.audio; 1603 free_pipe->clock_source = tail_pipe->next_odm_pipe->clock_source; 1604 1605 free_pipe->top_pipe = tail_pipe->next_odm_pipe; 1606 tail_pipe->next_odm_pipe->bottom_pipe = free_pipe; 1607 } else if (free_pipe->plane_state && 1608 (free_pipe->plane_state->clip_rect.x >= free_pipe->stream->src.x + free_pipe->stream->src.width/2) 1609 && head_pipe->next_odm_pipe) { 1610 1611 /* For ODM + window MPO, support 3 plane ( 2 MPO ) case. 1612 * Here we have a desktop ODM + left window MPO and a new MPO window appears 1613 * on the right side only. It fails the first case, because tail_pipe is the 1614 * left window MPO, so it has no next_odm_pipe. So in this scenario, we check 1615 * for head_pipe->next_odm_pipe instead 1616 */ 1617 DC_LOG_SCALER("%s - ODM + win MPO (left) + win MPO (right). free_pipe:%d head_pipe->next_odm:%d\n", 1618 __func__, 1619 free_pipe->pipe_idx, 1620 head_pipe->next_odm_pipe ? head_pipe->next_odm_pipe->pipe_idx : -1); 1621 1622 /* 1623 * We want to avoid the case where the right side already has a pipe assigned to 1624 * it and is different from free_pipe ( which would cause trigger a pipe 1625 * reallocation ). 1626 * Check the old context to see if the right side already has a pipe allocated 1627 * - If not, continue to use free_pipe 1628 * - If the right side already has a pipe, use that pipe instead if its available 1629 */ 1630 prev_right_head = &dc->current_state->res_ctx.pipe_ctx[head_pipe->next_odm_pipe->pipe_idx]; 1631 if ((prev_right_head->bottom_pipe) && 1632 (free_pipe->pipe_idx != prev_right_head->bottom_pipe->pipe_idx)) { 1633 free_right_pipe = acquire_free_pipe_for_head(context, pool, head_pipe->next_odm_pipe); 1634 if (free_right_pipe) { 1635 free_pipe->stream = NULL; 1636 memset(&free_pipe->stream_res, 0, sizeof(struct stream_resource)); 1637 memset(&free_pipe->plane_res, 0, sizeof(struct plane_resource)); 1638 free_pipe->plane_state = NULL; 1639 free_pipe->pipe_idx = 0; 1640 free_right_pipe->plane_state = plane_state; 1641 free_pipe = free_right_pipe; 1642 } 1643 } 1644 1645 free_pipe->stream_res.tg = head_pipe->next_odm_pipe->stream_res.tg; 1646 free_pipe->stream_res.abm = head_pipe->next_odm_pipe->stream_res.abm; 1647 free_pipe->stream_res.opp = head_pipe->next_odm_pipe->stream_res.opp; 1648 free_pipe->stream_res.stream_enc = head_pipe->next_odm_pipe->stream_res.stream_enc; 1649 free_pipe->stream_res.audio = head_pipe->next_odm_pipe->stream_res.audio; 1650 free_pipe->clock_source = head_pipe->next_odm_pipe->clock_source; 1651 1652 free_pipe->top_pipe = head_pipe->next_odm_pipe; 1653 head_pipe->next_odm_pipe->bottom_pipe = free_pipe; 1654 } else { 1655 1656 /* For ODM + window MPO, in 3 plane case, if we already have a MPO window on 1657 * the left side, then we will invalidate a 2nd one on the left side 1658 */ 1659 if (head_pipe->next_odm_pipe && tail_pipe->top_pipe) { 1660 dc_plane_state_release(plane_state); 1661 return false; 1662 } 1663 1664 free_pipe->stream_res.tg = tail_pipe->stream_res.tg; 1665 free_pipe->stream_res.abm = tail_pipe->stream_res.abm; 1666 free_pipe->stream_res.opp = tail_pipe->stream_res.opp; 1667 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; 1668 free_pipe->stream_res.audio = tail_pipe->stream_res.audio; 1669 free_pipe->clock_source = tail_pipe->clock_source; 1670 1671 free_pipe->top_pipe = tail_pipe; 1672 tail_pipe->bottom_pipe = free_pipe; 1673 1674 /* Connect MPO pipes together if MPO window is in the centre */ 1675 if (!(free_pipe->plane_state && 1676 (free_pipe->plane_state->clip_rect.x + free_pipe->plane_state->clip_rect.width <= 1677 free_pipe->stream->src.x + free_pipe->stream->src.width/2))) { 1678 if (!free_pipe->next_odm_pipe && 1679 tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) { 1680 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe; 1681 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe; 1682 } 1683 if (!free_pipe->prev_odm_pipe && 1684 tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) { 1685 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe; 1686 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe; 1687 } 1688 } 1689 } 1690 } 1691 1692 /* ODM + window MPO, where MPO window is on left half only */ 1693 if (free_pipe->plane_state && 1694 (free_pipe->plane_state->clip_rect.x + free_pipe->plane_state->clip_rect.width <= 1695 free_pipe->stream->src.x + free_pipe->stream->src.width/2)) { 1696 DC_LOG_SCALER("%s - ODM + window MPO(left). free_pipe:%d\n", 1697 __func__, 1698 free_pipe->pipe_idx); 1699 break; 1700 } 1701 /* ODM + window MPO, where MPO window is on right half only */ 1702 if (free_pipe->plane_state && 1703 (free_pipe->plane_state->clip_rect.x >= free_pipe->stream->src.x + free_pipe->stream->src.width/2)) { 1704 DC_LOG_SCALER("%s - ODM + window MPO(right). free_pipe:%d\n", 1705 __func__, 1706 free_pipe->pipe_idx); 1707 break; 1708 } 1709 1710 head_pipe = head_pipe->next_odm_pipe; 1711 } 1712 /* assign new surfaces*/ 1713 stream_status->plane_states[stream_status->plane_count] = plane_state; 1714 1715 stream_status->plane_count++; 1716 1717 return true; 1718 } 1719 1720 bool dc_remove_plane_from_context( 1721 const struct dc *dc, 1722 struct dc_stream_state *stream, 1723 struct dc_plane_state *plane_state, 1724 struct dc_state *context) 1725 { 1726 int i; 1727 struct dc_stream_status *stream_status = NULL; 1728 struct resource_pool *pool = dc->res_pool; 1729 1730 if (!plane_state) 1731 return true; 1732 1733 for (i = 0; i < context->stream_count; i++) 1734 if (context->streams[i] == stream) { 1735 stream_status = &context->stream_status[i]; 1736 break; 1737 } 1738 1739 if (stream_status == NULL) { 1740 dm_error("Existing stream not found; failed to remove plane.\n"); 1741 return false; 1742 } 1743 1744 /* release pipe for plane*/ 1745 for (i = pool->pipe_count - 1; i >= 0; i--) { 1746 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1747 1748 if (pipe_ctx->plane_state == plane_state) { 1749 if (pipe_ctx->top_pipe) 1750 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1751 1752 /* Second condition is to avoid setting NULL to top pipe 1753 * of tail pipe making it look like head pipe in subsequent 1754 * deletes 1755 */ 1756 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) 1757 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1758 1759 /* 1760 * For head pipe detach surfaces from pipe for tail 1761 * pipe just zero it out 1762 */ 1763 if (!pipe_ctx->top_pipe) 1764 pipe_ctx->plane_state = NULL; 1765 else 1766 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1767 } 1768 } 1769 1770 1771 for (i = 0; i < stream_status->plane_count; i++) { 1772 if (stream_status->plane_states[i] == plane_state) { 1773 dc_plane_state_release(stream_status->plane_states[i]); 1774 break; 1775 } 1776 } 1777 1778 if (i == stream_status->plane_count) { 1779 dm_error("Existing plane_state not found; failed to detach it!\n"); 1780 return false; 1781 } 1782 1783 stream_status->plane_count--; 1784 1785 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */ 1786 for (; i < stream_status->plane_count; i++) 1787 stream_status->plane_states[i] = stream_status->plane_states[i + 1]; 1788 1789 stream_status->plane_states[stream_status->plane_count] = NULL; 1790 1791 return true; 1792 } 1793 1794 /** 1795 * dc_rem_all_planes_for_stream - Remove planes attached to the target stream. 1796 * 1797 * @dc: Current dc state. 1798 * @stream: Target stream, which we want to remove the attached plans. 1799 * @context: New context. 1800 * 1801 * Return: 1802 * Return true if DC was able to remove all planes from the target 1803 * stream, otherwise, return false. 1804 */ 1805 bool dc_rem_all_planes_for_stream( 1806 const struct dc *dc, 1807 struct dc_stream_state *stream, 1808 struct dc_state *context) 1809 { 1810 int i, old_plane_count; 1811 struct dc_stream_status *stream_status = NULL; 1812 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; 1813 1814 for (i = 0; i < context->stream_count; i++) 1815 if (context->streams[i] == stream) { 1816 stream_status = &context->stream_status[i]; 1817 break; 1818 } 1819 1820 if (stream_status == NULL) { 1821 dm_error("Existing stream %p not found!\n", stream); 1822 return false; 1823 } 1824 1825 old_plane_count = stream_status->plane_count; 1826 1827 for (i = 0; i < old_plane_count; i++) 1828 del_planes[i] = stream_status->plane_states[i]; 1829 1830 for (i = 0; i < old_plane_count; i++) 1831 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) 1832 return false; 1833 1834 return true; 1835 } 1836 1837 static bool add_all_planes_for_stream( 1838 const struct dc *dc, 1839 struct dc_stream_state *stream, 1840 const struct dc_validation_set set[], 1841 int set_count, 1842 struct dc_state *context) 1843 { 1844 int i, j; 1845 1846 for (i = 0; i < set_count; i++) 1847 if (set[i].stream == stream) 1848 break; 1849 1850 if (i == set_count) { 1851 dm_error("Stream %p not found in set!\n", stream); 1852 return false; 1853 } 1854 1855 for (j = 0; j < set[i].plane_count; j++) 1856 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) 1857 return false; 1858 1859 return true; 1860 } 1861 1862 bool dc_add_all_planes_for_stream( 1863 const struct dc *dc, 1864 struct dc_stream_state *stream, 1865 struct dc_plane_state * const *plane_states, 1866 int plane_count, 1867 struct dc_state *context) 1868 { 1869 struct dc_validation_set set; 1870 int i; 1871 1872 set.stream = stream; 1873 set.plane_count = plane_count; 1874 1875 for (i = 0; i < plane_count; i++) 1876 set.plane_states[i] = plane_states[i]; 1877 1878 return add_all_planes_for_stream(dc, stream, &set, 1, context); 1879 } 1880 1881 bool is_timing_changed(struct dc_stream_state *cur_stream, 1882 struct dc_stream_state *new_stream) 1883 { 1884 if (cur_stream == NULL) 1885 return true; 1886 1887 /* If output color space is changed, need to reprogram info frames */ 1888 if (cur_stream->output_color_space != new_stream->output_color_space) 1889 return true; 1890 1891 return memcmp( 1892 &cur_stream->timing, 1893 &new_stream->timing, 1894 sizeof(struct dc_crtc_timing)) != 0; 1895 } 1896 1897 static bool are_stream_backends_same( 1898 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) 1899 { 1900 if (stream_a == stream_b) 1901 return true; 1902 1903 if (stream_a == NULL || stream_b == NULL) 1904 return false; 1905 1906 if (is_timing_changed(stream_a, stream_b)) 1907 return false; 1908 1909 if (stream_a->signal != stream_b->signal) 1910 return false; 1911 1912 if (stream_a->dpms_off != stream_b->dpms_off) 1913 return false; 1914 1915 return true; 1916 } 1917 1918 /* 1919 * dc_is_stream_unchanged() - Compare two stream states for equivalence. 1920 * 1921 * Checks if there a difference between the two states 1922 * that would require a mode change. 1923 * 1924 * Does not compare cursor position or attributes. 1925 */ 1926 bool dc_is_stream_unchanged( 1927 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1928 { 1929 1930 if (!are_stream_backends_same(old_stream, stream)) 1931 return false; 1932 1933 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param) 1934 return false; 1935 1936 /*compare audio info*/ 1937 if (memcmp(&old_stream->audio_info, &stream->audio_info, sizeof(stream->audio_info)) != 0) 1938 return false; 1939 1940 return true; 1941 } 1942 1943 /* 1944 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams. 1945 */ 1946 bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream, 1947 struct dc_stream_state *stream) 1948 { 1949 if (old_stream == stream) 1950 return true; 1951 1952 if (old_stream == NULL || stream == NULL) 1953 return false; 1954 1955 if (memcmp(&old_stream->src, 1956 &stream->src, 1957 sizeof(struct rect)) != 0) 1958 return false; 1959 1960 if (memcmp(&old_stream->dst, 1961 &stream->dst, 1962 sizeof(struct rect)) != 0) 1963 return false; 1964 1965 return true; 1966 } 1967 1968 static void update_stream_engine_usage( 1969 struct resource_context *res_ctx, 1970 const struct resource_pool *pool, 1971 struct stream_encoder *stream_enc, 1972 bool acquired) 1973 { 1974 int i; 1975 1976 for (i = 0; i < pool->stream_enc_count; i++) { 1977 if (pool->stream_enc[i] == stream_enc) 1978 res_ctx->is_stream_enc_acquired[i] = acquired; 1979 } 1980 } 1981 1982 static void update_hpo_dp_stream_engine_usage( 1983 struct resource_context *res_ctx, 1984 const struct resource_pool *pool, 1985 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, 1986 bool acquired) 1987 { 1988 int i; 1989 1990 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { 1991 if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc) 1992 res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired; 1993 } 1994 } 1995 1996 static inline int find_acquired_hpo_dp_link_enc_for_link( 1997 const struct resource_context *res_ctx, 1998 const struct dc_link *link) 1999 { 2000 int i; 2001 2002 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++) 2003 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 && 2004 res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index) 2005 return i; 2006 2007 return -1; 2008 } 2009 2010 static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx, 2011 const struct resource_pool *pool) 2012 { 2013 int i; 2014 2015 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++) 2016 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0) 2017 break; 2018 2019 return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) && 2020 i < pool->hpo_dp_link_enc_count) ? i : -1; 2021 } 2022 2023 static inline void acquire_hpo_dp_link_enc( 2024 struct resource_context *res_ctx, 2025 unsigned int link_index, 2026 int enc_index) 2027 { 2028 res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index; 2029 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1; 2030 } 2031 2032 static inline void retain_hpo_dp_link_enc( 2033 struct resource_context *res_ctx, 2034 int enc_index) 2035 { 2036 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++; 2037 } 2038 2039 static inline void release_hpo_dp_link_enc( 2040 struct resource_context *res_ctx, 2041 int enc_index) 2042 { 2043 ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0); 2044 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--; 2045 } 2046 2047 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx, 2048 const struct resource_pool *pool, 2049 struct pipe_ctx *pipe_ctx, 2050 struct dc_stream_state *stream) 2051 { 2052 int enc_index; 2053 2054 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link); 2055 2056 if (enc_index >= 0) { 2057 retain_hpo_dp_link_enc(res_ctx, enc_index); 2058 } else { 2059 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool); 2060 if (enc_index >= 0) 2061 acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index); 2062 } 2063 2064 if (enc_index >= 0) 2065 pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index]; 2066 2067 return pipe_ctx->link_res.hpo_dp_link_enc != NULL; 2068 } 2069 2070 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx, 2071 struct pipe_ctx *pipe_ctx, 2072 struct dc_stream_state *stream) 2073 { 2074 int enc_index; 2075 2076 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link); 2077 2078 if (enc_index >= 0) { 2079 release_hpo_dp_link_enc(res_ctx, enc_index); 2080 pipe_ctx->link_res.hpo_dp_link_enc = NULL; 2081 } 2082 } 2083 2084 /* TODO: release audio object */ 2085 void update_audio_usage( 2086 struct resource_context *res_ctx, 2087 const struct resource_pool *pool, 2088 struct audio *audio, 2089 bool acquired) 2090 { 2091 int i; 2092 for (i = 0; i < pool->audio_count; i++) { 2093 if (pool->audios[i] == audio) 2094 res_ctx->is_audio_acquired[i] = acquired; 2095 } 2096 } 2097 2098 static int acquire_first_free_pipe( 2099 struct resource_context *res_ctx, 2100 const struct resource_pool *pool, 2101 struct dc_stream_state *stream) 2102 { 2103 int i; 2104 2105 for (i = 0; i < pool->pipe_count; i++) { 2106 if (!res_ctx->pipe_ctx[i].stream) { 2107 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 2108 2109 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 2110 pipe_ctx->plane_res.mi = pool->mis[i]; 2111 pipe_ctx->plane_res.hubp = pool->hubps[i]; 2112 pipe_ctx->plane_res.ipp = pool->ipps[i]; 2113 pipe_ctx->plane_res.xfm = pool->transforms[i]; 2114 pipe_ctx->plane_res.dpp = pool->dpps[i]; 2115 pipe_ctx->stream_res.opp = pool->opps[i]; 2116 if (pool->dpps[i]) 2117 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; 2118 pipe_ctx->pipe_idx = i; 2119 2120 if (i >= pool->timing_generator_count) { 2121 int tg_inst = pool->timing_generator_count - 1; 2122 2123 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 2124 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; 2125 } 2126 2127 pipe_ctx->stream = stream; 2128 return i; 2129 } 2130 } 2131 return -1; 2132 } 2133 2134 static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link( 2135 struct resource_context *res_ctx, 2136 const struct resource_pool *pool, 2137 struct dc_stream_state *stream) 2138 { 2139 int i; 2140 2141 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { 2142 if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] && 2143 pool->hpo_dp_stream_enc[i]) { 2144 2145 return pool->hpo_dp_stream_enc[i]; 2146 } 2147 } 2148 2149 return NULL; 2150 } 2151 2152 static struct audio *find_first_free_audio( 2153 struct resource_context *res_ctx, 2154 const struct resource_pool *pool, 2155 enum engine_id id, 2156 enum dce_version dc_version) 2157 { 2158 int i, available_audio_count; 2159 2160 available_audio_count = pool->audio_count; 2161 2162 for (i = 0; i < available_audio_count; i++) { 2163 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { 2164 /*we have enough audio endpoint, find the matching inst*/ 2165 if (id != i) 2166 continue; 2167 return pool->audios[i]; 2168 } 2169 } 2170 2171 /* use engine id to find free audio */ 2172 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) { 2173 return pool->audios[id]; 2174 } 2175 /*not found the matching one, first come first serve*/ 2176 for (i = 0; i < available_audio_count; i++) { 2177 if (res_ctx->is_audio_acquired[i] == false) { 2178 return pool->audios[i]; 2179 } 2180 } 2181 return NULL; 2182 } 2183 2184 /* 2185 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state. 2186 */ 2187 enum dc_status dc_add_stream_to_ctx( 2188 struct dc *dc, 2189 struct dc_state *new_ctx, 2190 struct dc_stream_state *stream) 2191 { 2192 enum dc_status res; 2193 DC_LOGGER_INIT(dc->ctx->logger); 2194 2195 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) { 2196 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream); 2197 return DC_ERROR_UNEXPECTED; 2198 } 2199 2200 new_ctx->streams[new_ctx->stream_count] = stream; 2201 dc_stream_retain(stream); 2202 new_ctx->stream_count++; 2203 2204 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); 2205 if (res != DC_OK) 2206 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res); 2207 2208 return res; 2209 } 2210 2211 /* 2212 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state. 2213 */ 2214 enum dc_status dc_remove_stream_from_ctx( 2215 struct dc *dc, 2216 struct dc_state *new_ctx, 2217 struct dc_stream_state *stream) 2218 { 2219 int i; 2220 struct dc_context *dc_ctx = dc->ctx; 2221 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream); 2222 struct pipe_ctx *odm_pipe; 2223 2224 if (!del_pipe) { 2225 DC_ERROR("Pipe not found for stream %p !\n", stream); 2226 return DC_ERROR_UNEXPECTED; 2227 } 2228 2229 odm_pipe = del_pipe->next_odm_pipe; 2230 2231 /* Release primary pipe */ 2232 ASSERT(del_pipe->stream_res.stream_enc); 2233 update_stream_engine_usage( 2234 &new_ctx->res_ctx, 2235 dc->res_pool, 2236 del_pipe->stream_res.stream_enc, 2237 false); 2238 2239 if (dc->link_srv->dp_is_128b_132b_signal(del_pipe)) { 2240 update_hpo_dp_stream_engine_usage( 2241 &new_ctx->res_ctx, dc->res_pool, 2242 del_pipe->stream_res.hpo_dp_stream_enc, 2243 false); 2244 remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream); 2245 } 2246 2247 if (del_pipe->stream_res.audio) 2248 update_audio_usage( 2249 &new_ctx->res_ctx, 2250 dc->res_pool, 2251 del_pipe->stream_res.audio, 2252 false); 2253 2254 resource_unreference_clock_source(&new_ctx->res_ctx, 2255 dc->res_pool, 2256 del_pipe->clock_source); 2257 2258 if (dc->res_pool->funcs->remove_stream_from_ctx) 2259 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream); 2260 2261 while (odm_pipe) { 2262 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 2263 2264 memset(odm_pipe, 0, sizeof(*odm_pipe)); 2265 odm_pipe = next_odm_pipe; 2266 } 2267 memset(del_pipe, 0, sizeof(*del_pipe)); 2268 2269 for (i = 0; i < new_ctx->stream_count; i++) 2270 if (new_ctx->streams[i] == stream) 2271 break; 2272 2273 if (new_ctx->streams[i] != stream) { 2274 DC_ERROR("Context doesn't have stream %p !\n", stream); 2275 return DC_ERROR_UNEXPECTED; 2276 } 2277 2278 dc_stream_release(new_ctx->streams[i]); 2279 new_ctx->stream_count--; 2280 2281 /* Trim back arrays */ 2282 for (; i < new_ctx->stream_count; i++) { 2283 new_ctx->streams[i] = new_ctx->streams[i + 1]; 2284 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; 2285 } 2286 2287 new_ctx->streams[new_ctx->stream_count] = NULL; 2288 memset( 2289 &new_ctx->stream_status[new_ctx->stream_count], 2290 0, 2291 sizeof(new_ctx->stream_status[0])); 2292 2293 return DC_OK; 2294 } 2295 2296 static struct dc_stream_state *find_pll_sharable_stream( 2297 struct dc_stream_state *stream_needs_pll, 2298 struct dc_state *context) 2299 { 2300 int i; 2301 2302 for (i = 0; i < context->stream_count; i++) { 2303 struct dc_stream_state *stream_has_pll = context->streams[i]; 2304 2305 /* We are looking for non dp, non virtual stream */ 2306 if (resource_are_streams_timing_synchronizable( 2307 stream_needs_pll, stream_has_pll) 2308 && !dc_is_dp_signal(stream_has_pll->signal) 2309 && stream_has_pll->link->connector_signal 2310 != SIGNAL_TYPE_VIRTUAL) 2311 return stream_has_pll; 2312 2313 } 2314 2315 return NULL; 2316 } 2317 2318 static int get_norm_pix_clk(const struct dc_crtc_timing *timing) 2319 { 2320 uint32_t pix_clk = timing->pix_clk_100hz; 2321 uint32_t normalized_pix_clk = pix_clk; 2322 2323 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 2324 pix_clk /= 2; 2325 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 2326 switch (timing->display_color_depth) { 2327 case COLOR_DEPTH_666: 2328 case COLOR_DEPTH_888: 2329 normalized_pix_clk = pix_clk; 2330 break; 2331 case COLOR_DEPTH_101010: 2332 normalized_pix_clk = (pix_clk * 30) / 24; 2333 break; 2334 case COLOR_DEPTH_121212: 2335 normalized_pix_clk = (pix_clk * 36) / 24; 2336 break; 2337 case COLOR_DEPTH_161616: 2338 normalized_pix_clk = (pix_clk * 48) / 24; 2339 break; 2340 default: 2341 ASSERT(0); 2342 break; 2343 } 2344 } 2345 return normalized_pix_clk; 2346 } 2347 2348 static void calculate_phy_pix_clks(struct dc_stream_state *stream) 2349 { 2350 /* update actual pixel clock on all streams */ 2351 if (dc_is_hdmi_signal(stream->signal)) 2352 stream->phy_pix_clk = get_norm_pix_clk( 2353 &stream->timing) / 10; 2354 else 2355 stream->phy_pix_clk = 2356 stream->timing.pix_clk_100hz / 10; 2357 2358 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 2359 stream->phy_pix_clk *= 2; 2360 } 2361 2362 static int acquire_resource_from_hw_enabled_state( 2363 struct resource_context *res_ctx, 2364 const struct resource_pool *pool, 2365 struct dc_stream_state *stream) 2366 { 2367 struct dc_link *link = stream->link; 2368 unsigned int i, inst, tg_inst = 0; 2369 uint32_t numPipes = 1; 2370 uint32_t id_src[4] = {0}; 2371 2372 /* Check for enabled DIG to identify enabled display */ 2373 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) 2374 return -1; 2375 2376 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); 2377 2378 if (inst == ENGINE_ID_UNKNOWN) 2379 return -1; 2380 2381 for (i = 0; i < pool->stream_enc_count; i++) { 2382 if (pool->stream_enc[i]->id == inst) { 2383 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( 2384 pool->stream_enc[i]); 2385 break; 2386 } 2387 } 2388 2389 // tg_inst not found 2390 if (i == pool->stream_enc_count) 2391 return -1; 2392 2393 if (tg_inst >= pool->timing_generator_count) 2394 return -1; 2395 2396 if (!res_ctx->pipe_ctx[tg_inst].stream) { 2397 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; 2398 2399 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 2400 id_src[0] = tg_inst; 2401 2402 if (pipe_ctx->stream_res.tg->funcs->get_optc_source) 2403 pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg, 2404 &numPipes, &id_src[0], &id_src[1]); 2405 2406 if (id_src[0] == 0xf && id_src[1] == 0xf) { 2407 id_src[0] = tg_inst; 2408 numPipes = 1; 2409 } 2410 2411 for (i = 0; i < numPipes; i++) { 2412 //Check if src id invalid 2413 if (id_src[i] == 0xf) 2414 return -1; 2415 2416 pipe_ctx = &res_ctx->pipe_ctx[id_src[i]]; 2417 2418 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 2419 pipe_ctx->plane_res.mi = pool->mis[id_src[i]]; 2420 pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]]; 2421 pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]]; 2422 pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]]; 2423 pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]]; 2424 pipe_ctx->stream_res.opp = pool->opps[id_src[i]]; 2425 2426 if (pool->dpps[id_src[i]]) { 2427 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst; 2428 2429 if (pool->mpc->funcs->read_mpcc_state) { 2430 struct mpcc_state s = {0}; 2431 2432 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); 2433 2434 if (s.dpp_id < MAX_MPCC) 2435 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = 2436 s.dpp_id; 2437 2438 if (s.bot_mpcc_id < MAX_MPCC) 2439 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = 2440 &pool->mpc->mpcc_array[s.bot_mpcc_id]; 2441 2442 if (s.opp_id < MAX_OPP) 2443 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; 2444 } 2445 } 2446 pipe_ctx->pipe_idx = id_src[i]; 2447 2448 if (id_src[i] >= pool->timing_generator_count) { 2449 id_src[i] = pool->timing_generator_count - 1; 2450 2451 pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]]; 2452 pipe_ctx->stream_res.opp = pool->opps[id_src[i]]; 2453 } 2454 2455 pipe_ctx->stream = stream; 2456 } 2457 2458 if (numPipes == 2) { 2459 stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1; 2460 res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]]; 2461 res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL; 2462 res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL; 2463 res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]]; 2464 } else 2465 stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled; 2466 2467 return id_src[0]; 2468 } 2469 2470 return -1; 2471 } 2472 2473 static void mark_seamless_boot_stream( 2474 const struct dc *dc, 2475 struct dc_stream_state *stream) 2476 { 2477 struct dc_bios *dcb = dc->ctx->dc_bios; 2478 2479 if (dc->config.allow_seamless_boot_optimization && 2480 !dcb->funcs->is_accelerated_mode(dcb)) { 2481 if (dc_validate_boot_timing(dc, stream->sink, &stream->timing)) 2482 stream->apply_seamless_boot_optimization = true; 2483 } 2484 } 2485 2486 enum dc_status resource_map_pool_resources( 2487 const struct dc *dc, 2488 struct dc_state *context, 2489 struct dc_stream_state *stream) 2490 { 2491 const struct resource_pool *pool = dc->res_pool; 2492 int i; 2493 struct dc_context *dc_ctx = dc->ctx; 2494 struct pipe_ctx *pipe_ctx = NULL; 2495 int pipe_idx = -1; 2496 2497 calculate_phy_pix_clks(stream); 2498 2499 mark_seamless_boot_stream(dc, stream); 2500 2501 if (stream->apply_seamless_boot_optimization) { 2502 pipe_idx = acquire_resource_from_hw_enabled_state( 2503 &context->res_ctx, 2504 pool, 2505 stream); 2506 if (pipe_idx < 0) 2507 /* hw resource was assigned to other stream */ 2508 stream->apply_seamless_boot_optimization = false; 2509 } 2510 2511 if (pipe_idx < 0) 2512 /* acquire new resources */ 2513 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); 2514 2515 if (pipe_idx < 0) 2516 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 2517 2518 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL) 2519 return DC_NO_CONTROLLER_RESOURCE; 2520 2521 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2522 2523 pipe_ctx->stream_res.stream_enc = 2524 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link( 2525 &context->res_ctx, pool, stream); 2526 2527 if (!pipe_ctx->stream_res.stream_enc) 2528 return DC_NO_STREAM_ENC_RESOURCE; 2529 2530 update_stream_engine_usage( 2531 &context->res_ctx, pool, 2532 pipe_ctx->stream_res.stream_enc, 2533 true); 2534 2535 /* Allocate DP HPO Stream Encoder based on signal, hw capabilities 2536 * and link settings 2537 */ 2538 if (dc_is_dp_signal(stream->signal)) { 2539 if (!dc->link_srv->dp_decide_link_settings(stream, &pipe_ctx->link_config.dp_link_settings)) 2540 return DC_FAIL_DP_LINK_BANDWIDTH; 2541 if (dc->link_srv->dp_get_encoding_format( 2542 &pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) { 2543 pipe_ctx->stream_res.hpo_dp_stream_enc = 2544 find_first_free_match_hpo_dp_stream_enc_for_link( 2545 &context->res_ctx, pool, stream); 2546 2547 if (!pipe_ctx->stream_res.hpo_dp_stream_enc) 2548 return DC_NO_STREAM_ENC_RESOURCE; 2549 2550 update_hpo_dp_stream_engine_usage( 2551 &context->res_ctx, pool, 2552 pipe_ctx->stream_res.hpo_dp_stream_enc, 2553 true); 2554 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream)) 2555 return DC_NO_LINK_ENC_RESOURCE; 2556 } 2557 } 2558 2559 /* TODO: Add check if ASIC support and EDID audio */ 2560 if (!stream->converter_disable_audio && 2561 dc_is_audio_capable_signal(pipe_ctx->stream->signal) && 2562 stream->audio_info.mode_count && stream->audio_info.flags.all) { 2563 pipe_ctx->stream_res.audio = find_first_free_audio( 2564 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version); 2565 2566 /* 2567 * Audio assigned in order first come first get. 2568 * There are asics which has number of audio 2569 * resources less then number of pipes 2570 */ 2571 if (pipe_ctx->stream_res.audio) 2572 update_audio_usage(&context->res_ctx, pool, 2573 pipe_ctx->stream_res.audio, true); 2574 } 2575 2576 /* Add ABM to the resource if on EDP */ 2577 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) { 2578 if (pool->abm) 2579 pipe_ctx->stream_res.abm = pool->abm; 2580 else 2581 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst]; 2582 } 2583 2584 for (i = 0; i < context->stream_count; i++) 2585 if (context->streams[i] == stream) { 2586 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; 2587 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst; 2588 context->stream_status[i].audio_inst = 2589 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; 2590 2591 return DC_OK; 2592 } 2593 2594 DC_ERROR("Stream %p not found in new ctx!\n", stream); 2595 return DC_ERROR_UNEXPECTED; 2596 } 2597 2598 /** 2599 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state 2600 * 2601 * @dc: copy out of dc->current_state 2602 * @dst_ctx: copy into this 2603 * 2604 * This function makes a shallow copy of the current DC state and increments 2605 * refcounts on existing streams and planes. 2606 */ 2607 void dc_resource_state_copy_construct_current( 2608 const struct dc *dc, 2609 struct dc_state *dst_ctx) 2610 { 2611 dc_resource_state_copy_construct(dc->current_state, dst_ctx); 2612 } 2613 2614 2615 void dc_resource_state_construct( 2616 const struct dc *dc, 2617 struct dc_state *dst_ctx) 2618 { 2619 dst_ctx->clk_mgr = dc->clk_mgr; 2620 2621 /* Initialise DIG link encoder resource tracking variables. */ 2622 link_enc_cfg_init(dc, dst_ctx); 2623 } 2624 2625 2626 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) 2627 { 2628 if (dc->res_pool == NULL) 2629 return false; 2630 2631 return dc->res_pool->res_cap->num_dsc > 0; 2632 } 2633 2634 static bool planes_changed_for_existing_stream(struct dc_state *context, 2635 struct dc_stream_state *stream, 2636 const struct dc_validation_set set[], 2637 int set_count) 2638 { 2639 int i, j; 2640 struct dc_stream_status *stream_status = NULL; 2641 2642 for (i = 0; i < context->stream_count; i++) { 2643 if (context->streams[i] == stream) { 2644 stream_status = &context->stream_status[i]; 2645 break; 2646 } 2647 } 2648 2649 if (!stream_status) 2650 ASSERT(0); 2651 2652 for (i = 0; i < set_count; i++) 2653 if (set[i].stream == stream) 2654 break; 2655 2656 if (i == set_count) 2657 ASSERT(0); 2658 2659 if (set[i].plane_count != stream_status->plane_count) 2660 return true; 2661 2662 for (j = 0; j < set[i].plane_count; j++) 2663 if (set[i].plane_states[j] != stream_status->plane_states[j]) 2664 return true; 2665 2666 return false; 2667 } 2668 2669 /** 2670 * dc_validate_with_context - Validate and update the potential new stream in the context object 2671 * 2672 * @dc: Used to get the current state status 2673 * @set: An array of dc_validation_set with all the current streams reference 2674 * @set_count: Total of streams 2675 * @context: New context 2676 * @fast_validate: Enable or disable fast validation 2677 * 2678 * This function updates the potential new stream in the context object. It 2679 * creates multiple lists for the add, remove, and unchanged streams. In 2680 * particular, if the unchanged streams have a plane that changed, it is 2681 * necessary to remove all planes from the unchanged streams. In summary, this 2682 * function is responsible for validating the new context. 2683 * 2684 * Return: 2685 * In case of success, return DC_OK (1), otherwise, return a DC error. 2686 */ 2687 enum dc_status dc_validate_with_context(struct dc *dc, 2688 const struct dc_validation_set set[], 2689 int set_count, 2690 struct dc_state *context, 2691 bool fast_validate) 2692 { 2693 struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 }; 2694 struct dc_stream_state *del_streams[MAX_PIPES] = { 0 }; 2695 struct dc_stream_state *add_streams[MAX_PIPES] = { 0 }; 2696 int old_stream_count = context->stream_count; 2697 enum dc_status res = DC_ERROR_UNEXPECTED; 2698 int unchanged_streams_count = 0; 2699 int del_streams_count = 0; 2700 int add_streams_count = 0; 2701 bool found = false; 2702 int i, j, k; 2703 2704 DC_LOGGER_INIT(dc->ctx->logger); 2705 2706 /* First build a list of streams to be remove from current context */ 2707 for (i = 0; i < old_stream_count; i++) { 2708 struct dc_stream_state *stream = context->streams[i]; 2709 2710 for (j = 0; j < set_count; j++) { 2711 if (stream == set[j].stream) { 2712 found = true; 2713 break; 2714 } 2715 } 2716 2717 if (!found) 2718 del_streams[del_streams_count++] = stream; 2719 2720 found = false; 2721 } 2722 2723 /* Second, build a list of new streams */ 2724 for (i = 0; i < set_count; i++) { 2725 struct dc_stream_state *stream = set[i].stream; 2726 2727 for (j = 0; j < old_stream_count; j++) { 2728 if (stream == context->streams[j]) { 2729 found = true; 2730 break; 2731 } 2732 } 2733 2734 if (!found) 2735 add_streams[add_streams_count++] = stream; 2736 2737 found = false; 2738 } 2739 2740 /* Build a list of unchanged streams which is necessary for handling 2741 * planes change such as added, removed, and updated. 2742 */ 2743 for (i = 0; i < set_count; i++) { 2744 /* Check if stream is part of the delete list */ 2745 for (j = 0; j < del_streams_count; j++) { 2746 if (set[i].stream == del_streams[j]) { 2747 found = true; 2748 break; 2749 } 2750 } 2751 2752 if (!found) { 2753 /* Check if stream is part of the add list */ 2754 for (j = 0; j < add_streams_count; j++) { 2755 if (set[i].stream == add_streams[j]) { 2756 found = true; 2757 break; 2758 } 2759 } 2760 } 2761 2762 if (!found) 2763 unchanged_streams[unchanged_streams_count++] = set[i].stream; 2764 2765 found = false; 2766 } 2767 2768 /* Remove all planes for unchanged streams if planes changed */ 2769 for (i = 0; i < unchanged_streams_count; i++) { 2770 if (planes_changed_for_existing_stream(context, 2771 unchanged_streams[i], 2772 set, 2773 set_count)) { 2774 if (!dc_rem_all_planes_for_stream(dc, 2775 unchanged_streams[i], 2776 context)) { 2777 res = DC_FAIL_DETACH_SURFACES; 2778 goto fail; 2779 } 2780 } 2781 } 2782 2783 /* Remove all planes for removed streams and then remove the streams */ 2784 for (i = 0; i < del_streams_count; i++) { 2785 /* Need to cpy the dwb data from the old stream in order to efc to work */ 2786 if (del_streams[i]->num_wb_info > 0) { 2787 for (j = 0; j < add_streams_count; j++) { 2788 if (del_streams[i]->sink == add_streams[j]->sink) { 2789 add_streams[j]->num_wb_info = del_streams[i]->num_wb_info; 2790 for (k = 0; k < del_streams[i]->num_wb_info; k++) 2791 add_streams[j]->writeback_info[k] = del_streams[i]->writeback_info[k]; 2792 } 2793 } 2794 } 2795 2796 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { 2797 res = DC_FAIL_DETACH_SURFACES; 2798 goto fail; 2799 } 2800 2801 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); 2802 if (res != DC_OK) 2803 goto fail; 2804 } 2805 2806 /* Swap seamless boot stream to pipe 0 (if needed) to ensure pipe_ctx 2807 * matches. This may change in the future if seamless_boot_stream can be 2808 * multiple. 2809 */ 2810 for (i = 0; i < add_streams_count; i++) { 2811 mark_seamless_boot_stream(dc, add_streams[i]); 2812 if (add_streams[i]->apply_seamless_boot_optimization && i != 0) { 2813 struct dc_stream_state *temp = add_streams[0]; 2814 2815 add_streams[0] = add_streams[i]; 2816 add_streams[i] = temp; 2817 break; 2818 } 2819 } 2820 2821 /* Add new streams and then add all planes for the new stream */ 2822 for (i = 0; i < add_streams_count; i++) { 2823 calculate_phy_pix_clks(add_streams[i]); 2824 res = dc_add_stream_to_ctx(dc, context, add_streams[i]); 2825 if (res != DC_OK) 2826 goto fail; 2827 2828 if (!add_all_planes_for_stream(dc, add_streams[i], set, set_count, context)) { 2829 res = DC_FAIL_ATTACH_SURFACES; 2830 goto fail; 2831 } 2832 } 2833 2834 /* Add all planes for unchanged streams if planes changed */ 2835 for (i = 0; i < unchanged_streams_count; i++) { 2836 if (planes_changed_for_existing_stream(context, 2837 unchanged_streams[i], 2838 set, 2839 set_count)) { 2840 if (!add_all_planes_for_stream(dc, unchanged_streams[i], set, set_count, context)) { 2841 res = DC_FAIL_ATTACH_SURFACES; 2842 goto fail; 2843 } 2844 } 2845 } 2846 2847 res = dc_validate_global_state(dc, context, fast_validate); 2848 2849 fail: 2850 if (res != DC_OK) 2851 DC_LOG_WARNING("%s:resource validation failed, dc_status:%d\n", 2852 __func__, 2853 res); 2854 2855 return res; 2856 } 2857 2858 /** 2859 * dc_validate_global_state() - Determine if hardware can support a given state 2860 * 2861 * @dc: dc struct for this driver 2862 * @new_ctx: state to be validated 2863 * @fast_validate: set to true if only yes/no to support matters 2864 * 2865 * Checks hardware resource availability and bandwidth requirement. 2866 * 2867 * Return: 2868 * DC_OK if the result can be programmed. Otherwise, an error code. 2869 */ 2870 enum dc_status dc_validate_global_state( 2871 struct dc *dc, 2872 struct dc_state *new_ctx, 2873 bool fast_validate) 2874 { 2875 enum dc_status result = DC_ERROR_UNEXPECTED; 2876 int i, j; 2877 2878 if (!new_ctx) 2879 return DC_ERROR_UNEXPECTED; 2880 2881 if (dc->res_pool->funcs->validate_global) { 2882 result = dc->res_pool->funcs->validate_global(dc, new_ctx); 2883 if (result != DC_OK) 2884 return result; 2885 } 2886 2887 for (i = 0; i < new_ctx->stream_count; i++) { 2888 struct dc_stream_state *stream = new_ctx->streams[i]; 2889 2890 for (j = 0; j < dc->res_pool->pipe_count; j++) { 2891 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; 2892 2893 if (pipe_ctx->stream != stream) 2894 continue; 2895 2896 if (dc->res_pool->funcs->patch_unknown_plane_state && 2897 pipe_ctx->plane_state && 2898 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { 2899 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); 2900 if (result != DC_OK) 2901 return result; 2902 } 2903 2904 /* Switch to dp clock source only if there is 2905 * no non dp stream that shares the same timing 2906 * with the dp stream. 2907 */ 2908 if (dc_is_dp_signal(pipe_ctx->stream->signal) && 2909 !find_pll_sharable_stream(stream, new_ctx)) { 2910 2911 resource_unreference_clock_source( 2912 &new_ctx->res_ctx, 2913 dc->res_pool, 2914 pipe_ctx->clock_source); 2915 2916 pipe_ctx->clock_source = dc->res_pool->dp_clock_source; 2917 resource_reference_clock_source( 2918 &new_ctx->res_ctx, 2919 dc->res_pool, 2920 pipe_ctx->clock_source); 2921 } 2922 } 2923 } 2924 2925 result = resource_build_scaling_params_for_context(dc, new_ctx); 2926 2927 if (result == DC_OK) 2928 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate)) 2929 result = DC_FAIL_BANDWIDTH_VALIDATE; 2930 2931 /* 2932 * Only update link encoder to stream assignment after bandwidth validation passed. 2933 * TODO: Split out assignment and validation. 2934 */ 2935 if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false) 2936 dc->res_pool->funcs->link_encs_assign( 2937 dc, new_ctx, new_ctx->streams, new_ctx->stream_count); 2938 2939 return result; 2940 } 2941 2942 static void patch_gamut_packet_checksum( 2943 struct dc_info_packet *gamut_packet) 2944 { 2945 /* For gamut we recalc checksum */ 2946 if (gamut_packet->valid) { 2947 uint8_t chk_sum = 0; 2948 uint8_t *ptr; 2949 uint8_t i; 2950 2951 /*start of the Gamut data. */ 2952 ptr = &gamut_packet->sb[3]; 2953 2954 for (i = 0; i <= gamut_packet->sb[1]; i++) 2955 chk_sum += ptr[i]; 2956 2957 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); 2958 } 2959 } 2960 2961 static void set_avi_info_frame( 2962 struct dc_info_packet *info_packet, 2963 struct pipe_ctx *pipe_ctx) 2964 { 2965 struct dc_stream_state *stream = pipe_ctx->stream; 2966 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; 2967 uint32_t pixel_encoding = 0; 2968 enum scanning_type scan_type = SCANNING_TYPE_NODATA; 2969 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA; 2970 bool itc = false; 2971 uint8_t itc_value = 0; 2972 uint8_t cn0_cn1 = 0; 2973 unsigned int cn0_cn1_value = 0; 2974 uint8_t *check_sum = NULL; 2975 uint8_t byte_index = 0; 2976 union hdmi_info_packet hdmi_info; 2977 union display_content_support support = {0}; 2978 unsigned int vic = pipe_ctx->stream->timing.vic; 2979 unsigned int rid = pipe_ctx->stream->timing.rid; 2980 unsigned int fr_ind = pipe_ctx->stream->timing.fr_index; 2981 enum dc_timing_3d_format format; 2982 2983 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet)); 2984 2985 color_space = pipe_ctx->stream->output_color_space; 2986 if (color_space == COLOR_SPACE_UNKNOWN) 2987 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? 2988 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; 2989 2990 /* Initialize header */ 2991 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI; 2992 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall 2993 * not be used in HDMI 2.0 (Section 10.1) */ 2994 hdmi_info.bits.header.version = 2; 2995 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE; 2996 2997 /* 2998 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built 2999 * according to HDMI 2.0 spec (Section 10.1) 3000 */ 3001 3002 switch (stream->timing.pixel_encoding) { 3003 case PIXEL_ENCODING_YCBCR422: 3004 pixel_encoding = 1; 3005 break; 3006 3007 case PIXEL_ENCODING_YCBCR444: 3008 pixel_encoding = 2; 3009 break; 3010 case PIXEL_ENCODING_YCBCR420: 3011 pixel_encoding = 3; 3012 break; 3013 3014 case PIXEL_ENCODING_RGB: 3015 default: 3016 pixel_encoding = 0; 3017 } 3018 3019 /* Y0_Y1_Y2 : The pixel encoding */ 3020 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ 3021 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding; 3022 3023 /* A0 = 1 Active Format Information valid */ 3024 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID; 3025 3026 /* B0, B1 = 3; Bar info data is valid */ 3027 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID; 3028 3029 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM; 3030 3031 /* S0, S1 : Underscan / Overscan */ 3032 /* TODO: un-hardcode scan type */ 3033 scan_type = SCANNING_TYPE_UNDERSCAN; 3034 hdmi_info.bits.S0_S1 = scan_type; 3035 3036 /* C0, C1 : Colorimetry */ 3037 if (color_space == COLOR_SPACE_YCBCR709 || 3038 color_space == COLOR_SPACE_YCBCR709_LIMITED) 3039 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709; 3040 else if (color_space == COLOR_SPACE_YCBCR601 || 3041 color_space == COLOR_SPACE_YCBCR601_LIMITED) 3042 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601; 3043 else { 3044 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA; 3045 } 3046 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE || 3047 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE || 3048 color_space == COLOR_SPACE_2020_YCBCR) { 3049 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR; 3050 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 3051 } else if (color_space == COLOR_SPACE_ADOBERGB) { 3052 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB; 3053 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 3054 } 3055 3056 if (pixel_encoding && color_space == COLOR_SPACE_2020_YCBCR && 3057 stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) { 3058 hdmi_info.bits.EC0_EC2 = 0; 3059 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709; 3060 } 3061 3062 /* TODO: un-hardcode aspect ratio */ 3063 aspect = stream->timing.aspect_ratio; 3064 3065 switch (aspect) { 3066 case ASPECT_RATIO_4_3: 3067 case ASPECT_RATIO_16_9: 3068 hdmi_info.bits.M0_M1 = aspect; 3069 break; 3070 3071 case ASPECT_RATIO_NO_DATA: 3072 case ASPECT_RATIO_64_27: 3073 case ASPECT_RATIO_256_135: 3074 default: 3075 hdmi_info.bits.M0_M1 = 0; 3076 } 3077 3078 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */ 3079 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE; 3080 3081 /* TODO: un-hardcode cn0_cn1 and itc */ 3082 3083 cn0_cn1 = 0; 3084 cn0_cn1_value = 0; 3085 3086 itc = true; 3087 itc_value = 1; 3088 3089 support = stream->content_support; 3090 3091 if (itc) { 3092 if (!support.bits.valid_content_type) { 3093 cn0_cn1_value = 0; 3094 } else { 3095 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) { 3096 if (support.bits.graphics_content == 1) { 3097 cn0_cn1_value = 0; 3098 } 3099 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) { 3100 if (support.bits.photo_content == 1) { 3101 cn0_cn1_value = 1; 3102 } else { 3103 cn0_cn1_value = 0; 3104 itc_value = 0; 3105 } 3106 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) { 3107 if (support.bits.cinema_content == 1) { 3108 cn0_cn1_value = 2; 3109 } else { 3110 cn0_cn1_value = 0; 3111 itc_value = 0; 3112 } 3113 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) { 3114 if (support.bits.game_content == 1) { 3115 cn0_cn1_value = 3; 3116 } else { 3117 cn0_cn1_value = 0; 3118 itc_value = 0; 3119 } 3120 } 3121 } 3122 hdmi_info.bits.CN0_CN1 = cn0_cn1_value; 3123 hdmi_info.bits.ITC = itc_value; 3124 } 3125 3126 if (stream->qs_bit == 1) { 3127 if (color_space == COLOR_SPACE_SRGB || 3128 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) 3129 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; 3130 else if (color_space == COLOR_SPACE_SRGB_LIMITED || 3131 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) 3132 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE; 3133 else 3134 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 3135 } else 3136 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 3137 3138 /* TODO : We should handle YCC quantization */ 3139 /* but we do not have matrix calculation */ 3140 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 3141 3142 ///VIC 3143 if (pipe_ctx->stream->timing.hdmi_vic != 0) 3144 vic = 0; 3145 format = stream->timing.timing_3d_format; 3146 /*todo, add 3DStereo support*/ 3147 if (format != TIMING_3D_FORMAT_NONE) { 3148 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled 3149 switch (pipe_ctx->stream->timing.hdmi_vic) { 3150 case 1: 3151 vic = 95; 3152 break; 3153 case 2: 3154 vic = 94; 3155 break; 3156 case 3: 3157 vic = 93; 3158 break; 3159 case 4: 3160 vic = 98; 3161 break; 3162 default: 3163 break; 3164 } 3165 } 3166 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/ 3167 hdmi_info.bits.VIC0_VIC7 = vic; 3168 if (vic >= 128) 3169 hdmi_info.bits.header.version = 3; 3170 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1), 3171 * the Source shall use 20 AVI InfoFrame Version 4 3172 */ 3173 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED && 3174 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) { 3175 hdmi_info.bits.header.version = 4; 3176 hdmi_info.bits.header.length = 14; 3177 } 3178 3179 if (rid != 0 && fr_ind != 0) { 3180 hdmi_info.bits.header.version = 5; 3181 hdmi_info.bits.header.length = 15; 3182 3183 hdmi_info.bits.FR0_FR3 = fr_ind & 0xF; 3184 hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1; 3185 hdmi_info.bits.RID0_RID5 = rid; 3186 } 3187 3188 /* pixel repetition 3189 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel 3190 * repetition start from 1 */ 3191 hdmi_info.bits.PR0_PR3 = 0; 3192 3193 /* Bar Info 3194 * barTop: Line Number of End of Top Bar. 3195 * barBottom: Line Number of Start of Bottom Bar. 3196 * barLeft: Pixel Number of End of Left Bar. 3197 * barRight: Pixel Number of Start of Right Bar. */ 3198 hdmi_info.bits.bar_top = stream->timing.v_border_top; 3199 hdmi_info.bits.bar_bottom = (stream->timing.v_total 3200 - stream->timing.v_border_bottom + 1); 3201 hdmi_info.bits.bar_left = stream->timing.h_border_left; 3202 hdmi_info.bits.bar_right = (stream->timing.h_total 3203 - stream->timing.h_border_right + 1); 3204 3205 /* Additional Colorimetry Extension 3206 * Used in conduction with C0-C1 and EC0-EC2 3207 * 0 = DCI-P3 RGB (D65) 3208 * 1 = DCI-P3 RGB (theater) 3209 */ 3210 hdmi_info.bits.ACE0_ACE3 = 0; 3211 3212 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ 3213 check_sum = &hdmi_info.packet_raw_data.sb[0]; 3214 3215 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version; 3216 3217 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++) 3218 *check_sum += hdmi_info.packet_raw_data.sb[byte_index]; 3219 3220 /* one byte complement */ 3221 *check_sum = (uint8_t) (0x100 - *check_sum); 3222 3223 /* Store in hw_path_mode */ 3224 info_packet->hb0 = hdmi_info.packet_raw_data.hb0; 3225 info_packet->hb1 = hdmi_info.packet_raw_data.hb1; 3226 info_packet->hb2 = hdmi_info.packet_raw_data.hb2; 3227 3228 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++) 3229 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index]; 3230 3231 info_packet->valid = true; 3232 } 3233 3234 static void set_vendor_info_packet( 3235 struct dc_info_packet *info_packet, 3236 struct dc_stream_state *stream) 3237 { 3238 /* SPD info packet for FreeSync */ 3239 3240 /* Check if Freesync is supported. Return if false. If true, 3241 * set the corresponding bit in the info packet 3242 */ 3243 if (!stream->vsp_infopacket.valid) 3244 return; 3245 3246 *info_packet = stream->vsp_infopacket; 3247 } 3248 3249 static void set_spd_info_packet( 3250 struct dc_info_packet *info_packet, 3251 struct dc_stream_state *stream) 3252 { 3253 /* SPD info packet for FreeSync */ 3254 3255 /* Check if Freesync is supported. Return if false. If true, 3256 * set the corresponding bit in the info packet 3257 */ 3258 if (!stream->vrr_infopacket.valid) 3259 return; 3260 3261 *info_packet = stream->vrr_infopacket; 3262 } 3263 3264 static void set_hdr_static_info_packet( 3265 struct dc_info_packet *info_packet, 3266 struct dc_stream_state *stream) 3267 { 3268 /* HDR Static Metadata info packet for HDR10 */ 3269 3270 if (!stream->hdr_static_metadata.valid || 3271 stream->use_dynamic_meta) 3272 return; 3273 3274 *info_packet = stream->hdr_static_metadata; 3275 } 3276 3277 static void set_vsc_info_packet( 3278 struct dc_info_packet *info_packet, 3279 struct dc_stream_state *stream) 3280 { 3281 if (!stream->vsc_infopacket.valid) 3282 return; 3283 3284 *info_packet = stream->vsc_infopacket; 3285 } 3286 static void set_hfvs_info_packet( 3287 struct dc_info_packet *info_packet, 3288 struct dc_stream_state *stream) 3289 { 3290 if (!stream->hfvsif_infopacket.valid) 3291 return; 3292 3293 *info_packet = stream->hfvsif_infopacket; 3294 } 3295 3296 static void adaptive_sync_override_dp_info_packets_sdp_line_num( 3297 const struct dc_crtc_timing *timing, 3298 struct enc_sdp_line_num *sdp_line_num, 3299 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param) 3300 { 3301 uint32_t asic_blank_start = 0; 3302 uint32_t asic_blank_end = 0; 3303 uint32_t v_update = 0; 3304 3305 const struct dc_crtc_timing *tg = timing; 3306 3307 /* blank_start = frame end - front porch */ 3308 asic_blank_start = tg->v_total - tg->v_front_porch; 3309 3310 /* blank_end = blank_start - active */ 3311 asic_blank_end = (asic_blank_start - tg->v_border_bottom - 3312 tg->v_addressable - tg->v_border_top); 3313 3314 if (pipe_dlg_param->vstartup_start > asic_blank_end) { 3315 v_update = (tg->v_total - (pipe_dlg_param->vstartup_start - asic_blank_end)); 3316 sdp_line_num->adaptive_sync_line_num_valid = true; 3317 sdp_line_num->adaptive_sync_line_num = (tg->v_total - v_update - 1); 3318 } else { 3319 sdp_line_num->adaptive_sync_line_num_valid = false; 3320 sdp_line_num->adaptive_sync_line_num = 0; 3321 } 3322 } 3323 3324 static void set_adaptive_sync_info_packet( 3325 struct dc_info_packet *info_packet, 3326 const struct dc_stream_state *stream, 3327 struct encoder_info_frame *info_frame, 3328 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param) 3329 { 3330 if (!stream->adaptive_sync_infopacket.valid) 3331 return; 3332 3333 adaptive_sync_override_dp_info_packets_sdp_line_num( 3334 &stream->timing, 3335 &info_frame->sdp_line_num, 3336 pipe_dlg_param); 3337 3338 *info_packet = stream->adaptive_sync_infopacket; 3339 } 3340 3341 static void set_vtem_info_packet( 3342 struct dc_info_packet *info_packet, 3343 struct dc_stream_state *stream) 3344 { 3345 if (!stream->vtem_infopacket.valid) 3346 return; 3347 3348 *info_packet = stream->vtem_infopacket; 3349 } 3350 3351 void dc_resource_state_destruct(struct dc_state *context) 3352 { 3353 int i, j; 3354 3355 for (i = 0; i < context->stream_count; i++) { 3356 for (j = 0; j < context->stream_status[i].plane_count; j++) 3357 dc_plane_state_release( 3358 context->stream_status[i].plane_states[j]); 3359 3360 context->stream_status[i].plane_count = 0; 3361 dc_stream_release(context->streams[i]); 3362 context->streams[i] = NULL; 3363 } 3364 context->stream_count = 0; 3365 } 3366 3367 void dc_resource_state_copy_construct( 3368 const struct dc_state *src_ctx, 3369 struct dc_state *dst_ctx) 3370 { 3371 int i, j; 3372 struct kref refcount = dst_ctx->refcount; 3373 3374 *dst_ctx = *src_ctx; 3375 3376 for (i = 0; i < MAX_PIPES; i++) { 3377 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; 3378 3379 if (cur_pipe->top_pipe) 3380 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; 3381 3382 if (cur_pipe->bottom_pipe) 3383 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; 3384 3385 if (cur_pipe->next_odm_pipe) 3386 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; 3387 3388 if (cur_pipe->prev_odm_pipe) 3389 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; 3390 } 3391 3392 for (i = 0; i < dst_ctx->stream_count; i++) { 3393 dc_stream_retain(dst_ctx->streams[i]); 3394 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) 3395 dc_plane_state_retain( 3396 dst_ctx->stream_status[i].plane_states[j]); 3397 } 3398 3399 /* context refcount should not be overridden */ 3400 dst_ctx->refcount = refcount; 3401 3402 } 3403 3404 struct clock_source *dc_resource_find_first_free_pll( 3405 struct resource_context *res_ctx, 3406 const struct resource_pool *pool) 3407 { 3408 int i; 3409 3410 for (i = 0; i < pool->clk_src_count; ++i) { 3411 if (res_ctx->clock_source_ref_count[i] == 0) 3412 return pool->clock_sources[i]; 3413 } 3414 3415 return NULL; 3416 } 3417 3418 void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 3419 { 3420 enum signal_type signal = SIGNAL_TYPE_NONE; 3421 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; 3422 3423 /* default all packets to invalid */ 3424 info->avi.valid = false; 3425 info->gamut.valid = false; 3426 info->vendor.valid = false; 3427 info->spd.valid = false; 3428 info->hdrsmd.valid = false; 3429 info->vsc.valid = false; 3430 info->hfvsif.valid = false; 3431 info->vtem.valid = false; 3432 info->adaptive_sync.valid = false; 3433 signal = pipe_ctx->stream->signal; 3434 3435 /* HDMi and DP have different info packets*/ 3436 if (dc_is_hdmi_signal(signal)) { 3437 set_avi_info_frame(&info->avi, pipe_ctx); 3438 3439 set_vendor_info_packet(&info->vendor, pipe_ctx->stream); 3440 set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream); 3441 set_vtem_info_packet(&info->vtem, pipe_ctx->stream); 3442 3443 set_spd_info_packet(&info->spd, pipe_ctx->stream); 3444 3445 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 3446 3447 } else if (dc_is_dp_signal(signal)) { 3448 set_vsc_info_packet(&info->vsc, pipe_ctx->stream); 3449 3450 set_spd_info_packet(&info->spd, pipe_ctx->stream); 3451 3452 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 3453 set_adaptive_sync_info_packet(&info->adaptive_sync, 3454 pipe_ctx->stream, 3455 info, 3456 &pipe_ctx->pipe_dlg_param); 3457 } 3458 3459 patch_gamut_packet_checksum(&info->gamut); 3460 } 3461 3462 enum dc_status resource_map_clock_resources( 3463 const struct dc *dc, 3464 struct dc_state *context, 3465 struct dc_stream_state *stream) 3466 { 3467 /* acquire new resources */ 3468 const struct resource_pool *pool = dc->res_pool; 3469 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 3470 &context->res_ctx, stream); 3471 3472 if (!pipe_ctx) 3473 return DC_ERROR_UNEXPECTED; 3474 3475 if (dc_is_dp_signal(pipe_ctx->stream->signal) 3476 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 3477 pipe_ctx->clock_source = pool->dp_clock_source; 3478 else { 3479 pipe_ctx->clock_source = NULL; 3480 3481 if (!dc->config.disable_disp_pll_sharing) 3482 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing( 3483 &context->res_ctx, 3484 pipe_ctx); 3485 3486 if (pipe_ctx->clock_source == NULL) 3487 pipe_ctx->clock_source = 3488 dc_resource_find_first_free_pll( 3489 &context->res_ctx, 3490 pool); 3491 } 3492 3493 if (pipe_ctx->clock_source == NULL) 3494 return DC_NO_CLOCK_SOURCE_RESOURCE; 3495 3496 resource_reference_clock_source( 3497 &context->res_ctx, pool, 3498 pipe_ctx->clock_source); 3499 3500 return DC_OK; 3501 } 3502 3503 /* 3504 * Note: We need to disable output if clock sources change, 3505 * since bios does optimization and doesn't apply if changing 3506 * PHY when not already disabled. 3507 */ 3508 bool pipe_need_reprogram( 3509 struct pipe_ctx *pipe_ctx_old, 3510 struct pipe_ctx *pipe_ctx) 3511 { 3512 if (!pipe_ctx_old->stream) 3513 return false; 3514 3515 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) 3516 return true; 3517 3518 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) 3519 return true; 3520 3521 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) 3522 return true; 3523 3524 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source 3525 && pipe_ctx_old->stream != pipe_ctx->stream) 3526 return true; 3527 3528 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) 3529 return true; 3530 3531 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) 3532 return true; 3533 3534 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off) 3535 return true; 3536 3537 if (false == pipe_ctx_old->stream->link->link_state_valid && 3538 false == pipe_ctx_old->stream->dpms_off) 3539 return true; 3540 3541 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) 3542 return true; 3543 3544 if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) 3545 return true; 3546 if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc) 3547 return true; 3548 3549 /* DIG link encoder resource assignment for stream changed. */ 3550 if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) { 3551 bool need_reprogram = false; 3552 struct dc *dc = pipe_ctx_old->stream->ctx->dc; 3553 struct link_encoder *link_enc_prev = 3554 link_enc_cfg_get_link_enc_used_by_stream_current(dc, pipe_ctx_old->stream); 3555 3556 if (link_enc_prev != pipe_ctx->stream->link_enc) 3557 need_reprogram = true; 3558 3559 return need_reprogram; 3560 } 3561 3562 return false; 3563 } 3564 3565 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 3566 struct bit_depth_reduction_params *fmt_bit_depth) 3567 { 3568 enum dc_dither_option option = stream->dither_option; 3569 enum dc_pixel_encoding pixel_encoding = 3570 stream->timing.pixel_encoding; 3571 3572 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); 3573 3574 if (option == DITHER_OPTION_DEFAULT) { 3575 switch (stream->timing.display_color_depth) { 3576 case COLOR_DEPTH_666: 3577 option = DITHER_OPTION_SPATIAL6; 3578 break; 3579 case COLOR_DEPTH_888: 3580 option = DITHER_OPTION_SPATIAL8; 3581 break; 3582 case COLOR_DEPTH_101010: 3583 option = DITHER_OPTION_SPATIAL10; 3584 break; 3585 default: 3586 option = DITHER_OPTION_DISABLE; 3587 } 3588 } 3589 3590 if (option == DITHER_OPTION_DISABLE) 3591 return; 3592 3593 if (option == DITHER_OPTION_TRUN6) { 3594 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 3595 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; 3596 } else if (option == DITHER_OPTION_TRUN8 || 3597 option == DITHER_OPTION_TRUN8_SPATIAL6 || 3598 option == DITHER_OPTION_TRUN8_FM6) { 3599 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 3600 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; 3601 } else if (option == DITHER_OPTION_TRUN10 || 3602 option == DITHER_OPTION_TRUN10_SPATIAL6 || 3603 option == DITHER_OPTION_TRUN10_SPATIAL8 || 3604 option == DITHER_OPTION_TRUN10_FM8 || 3605 option == DITHER_OPTION_TRUN10_FM6 || 3606 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 3607 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 3608 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 3609 } 3610 3611 /* special case - Formatter can only reduce by 4 bits at most. 3612 * When reducing from 12 to 6 bits, 3613 * HW recommends we use trunc with round mode 3614 * (if we did nothing, trunc to 10 bits would be used) 3615 * note that any 12->10 bit reduction is ignored prior to DCE8, 3616 * as the input was 10 bits. 3617 */ 3618 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 3619 option == DITHER_OPTION_SPATIAL6 || 3620 option == DITHER_OPTION_FM6) { 3621 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 3622 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 3623 fmt_bit_depth->flags.TRUNCATE_MODE = 1; 3624 } 3625 3626 /* spatial dither 3627 * note that spatial modes 1-3 are never used 3628 */ 3629 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 3630 option == DITHER_OPTION_SPATIAL6 || 3631 option == DITHER_OPTION_TRUN10_SPATIAL6 || 3632 option == DITHER_OPTION_TRUN8_SPATIAL6) { 3633 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 3634 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; 3635 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 3636 fmt_bit_depth->flags.RGB_RANDOM = 3637 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 3638 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || 3639 option == DITHER_OPTION_SPATIAL8 || 3640 option == DITHER_OPTION_SPATIAL8_FM6 || 3641 option == DITHER_OPTION_TRUN10_SPATIAL8 || 3642 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 3643 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 3644 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; 3645 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 3646 fmt_bit_depth->flags.RGB_RANDOM = 3647 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 3648 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || 3649 option == DITHER_OPTION_SPATIAL10 || 3650 option == DITHER_OPTION_SPATIAL10_FM8 || 3651 option == DITHER_OPTION_SPATIAL10_FM6) { 3652 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 3653 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; 3654 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 3655 fmt_bit_depth->flags.RGB_RANDOM = 3656 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 3657 } 3658 3659 if (option == DITHER_OPTION_SPATIAL6 || 3660 option == DITHER_OPTION_SPATIAL8 || 3661 option == DITHER_OPTION_SPATIAL10) { 3662 fmt_bit_depth->flags.FRAME_RANDOM = 0; 3663 } else { 3664 fmt_bit_depth->flags.FRAME_RANDOM = 1; 3665 } 3666 3667 ////////////////////// 3668 //// temporal dither 3669 ////////////////////// 3670 if (option == DITHER_OPTION_FM6 || 3671 option == DITHER_OPTION_SPATIAL8_FM6 || 3672 option == DITHER_OPTION_SPATIAL10_FM6 || 3673 option == DITHER_OPTION_TRUN10_FM6 || 3674 option == DITHER_OPTION_TRUN8_FM6 || 3675 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 3676 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 3677 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; 3678 } else if (option == DITHER_OPTION_FM8 || 3679 option == DITHER_OPTION_SPATIAL10_FM8 || 3680 option == DITHER_OPTION_TRUN10_FM8) { 3681 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 3682 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; 3683 } else if (option == DITHER_OPTION_FM10) { 3684 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 3685 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; 3686 } 3687 3688 fmt_bit_depth->pixel_encoding = pixel_encoding; 3689 } 3690 3691 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) 3692 { 3693 struct dc_link *link = stream->link; 3694 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 3695 enum dc_status res = DC_OK; 3696 3697 calculate_phy_pix_clks(stream); 3698 3699 if (!tg->funcs->validate_timing(tg, &stream->timing)) 3700 res = DC_FAIL_CONTROLLER_VALIDATE; 3701 3702 if (res == DC_OK) { 3703 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 3704 !link->link_enc->funcs->validate_output_with_stream( 3705 link->link_enc, stream)) 3706 res = DC_FAIL_ENC_VALIDATE; 3707 } 3708 3709 /* TODO: validate audio ASIC caps, encoder */ 3710 3711 if (res == DC_OK) 3712 res = dc->link_srv->validate_mode_timing(stream, 3713 link, 3714 &stream->timing); 3715 3716 return res; 3717 } 3718 3719 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) 3720 { 3721 enum dc_status res = DC_OK; 3722 3723 /* check if surface has invalid dimensions */ 3724 if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 || 3725 plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0) 3726 return DC_FAIL_SURFACE_VALIDATE; 3727 3728 /* TODO For now validates pixel format only */ 3729 if (dc->res_pool->funcs->validate_plane) 3730 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps); 3731 3732 return res; 3733 } 3734 3735 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format) 3736 { 3737 switch (format) { 3738 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 3739 return 8; 3740 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 3741 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 3742 return 12; 3743 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 3744 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 3745 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 3746 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 3747 return 16; 3748 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 3749 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 3750 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 3751 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 3752 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 3753 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 3754 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 3755 return 32; 3756 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 3757 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 3758 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 3759 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 3760 return 64; 3761 default: 3762 ASSERT_CRITICAL(false); 3763 return -1; 3764 } 3765 } 3766 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes) 3767 { 3768 if (modes) { 3769 if (modes->sample_rates.rate.RATE_192) 3770 return 192000; 3771 if (modes->sample_rates.rate.RATE_176_4) 3772 return 176400; 3773 if (modes->sample_rates.rate.RATE_96) 3774 return 96000; 3775 if (modes->sample_rates.rate.RATE_88_2) 3776 return 88200; 3777 if (modes->sample_rates.rate.RATE_48) 3778 return 48000; 3779 if (modes->sample_rates.rate.RATE_44_1) 3780 return 44100; 3781 if (modes->sample_rates.rate.RATE_32) 3782 return 32000; 3783 } 3784 /*original logic when no audio info*/ 3785 return 441000; 3786 } 3787 3788 void get_audio_check(struct audio_info *aud_modes, 3789 struct audio_check *audio_chk) 3790 { 3791 unsigned int i; 3792 unsigned int max_sample_rate = 0; 3793 3794 if (aud_modes) { 3795 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/ 3796 3797 audio_chk->max_audiosample_rate = 0; 3798 for (i = 0; i < aud_modes->mode_count; i++) { 3799 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]); 3800 if (audio_chk->max_audiosample_rate < max_sample_rate) 3801 audio_chk->max_audiosample_rate = max_sample_rate; 3802 /*dts takes the same as type 2: AP = 0.25*/ 3803 } 3804 /*check which one take more bandwidth*/ 3805 if (audio_chk->max_audiosample_rate > 192000) 3806 audio_chk->audio_packet_type = 0x9;/*AP =1*/ 3807 audio_chk->acat = 0;/*not support*/ 3808 } 3809 } 3810 3811 static struct hpo_dp_link_encoder *get_temp_hpo_dp_link_enc( 3812 const struct resource_context *res_ctx, 3813 const struct resource_pool *const pool, 3814 const struct dc_link *link) 3815 { 3816 struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL; 3817 int enc_index; 3818 3819 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link); 3820 3821 if (enc_index < 0) 3822 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool); 3823 3824 if (enc_index >= 0) 3825 hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index]; 3826 3827 return hpo_dp_link_enc; 3828 } 3829 3830 bool get_temp_dp_link_res(struct dc_link *link, 3831 struct link_resource *link_res, 3832 struct dc_link_settings *link_settings) 3833 { 3834 const struct dc *dc = link->dc; 3835 const struct resource_context *res_ctx = &dc->current_state->res_ctx; 3836 3837 memset(link_res, 0, sizeof(*link_res)); 3838 3839 if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 3840 link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx, 3841 dc->res_pool, link); 3842 if (!link_res->hpo_dp_link_enc) 3843 return false; 3844 } 3845 return true; 3846 } 3847 3848 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc, 3849 struct dc_state *context) 3850 { 3851 int i, j; 3852 struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd; 3853 3854 /* If pipe backend is reset, need to reset pipe syncd status */ 3855 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3856 pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i]; 3857 pipe_ctx = &context->res_ctx.pipe_ctx[i]; 3858 3859 if (!pipe_ctx_old->stream) 3860 continue; 3861 3862 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 3863 continue; 3864 3865 if (!pipe_ctx->stream || 3866 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 3867 3868 /* Reset all the syncd pipes from the disabled pipe */ 3869 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3870 pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j]; 3871 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) || 3872 !IS_PIPE_SYNCD_VALID(pipe_ctx_syncd)) 3873 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j); 3874 } 3875 } 3876 } 3877 } 3878 3879 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc, 3880 struct dc_state *context, 3881 uint8_t disabled_master_pipe_idx) 3882 { 3883 int i; 3884 struct pipe_ctx *pipe_ctx, *pipe_ctx_check; 3885 3886 pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx]; 3887 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) || 3888 !IS_PIPE_SYNCD_VALID(pipe_ctx)) 3889 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx); 3890 3891 /* for the pipe disabled, check if any slave pipe exists and assert */ 3892 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3893 pipe_ctx_check = &context->res_ctx.pipe_ctx[i]; 3894 3895 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) && 3896 IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx)) { 3897 struct pipe_ctx *first_pipe = pipe_ctx_check; 3898 3899 while (first_pipe->prev_odm_pipe) 3900 first_pipe = first_pipe->prev_odm_pipe; 3901 /* When ODM combine is enabled, this case is expected. If the disabled pipe 3902 * is part of the ODM tree, then we should not print an error. 3903 * */ 3904 if (first_pipe->pipe_idx == disabled_master_pipe_idx) 3905 continue; 3906 3907 DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n", 3908 i, disabled_master_pipe_idx); 3909 } 3910 } 3911 } 3912 3913 void reset_sync_context_for_pipe(const struct dc *dc, 3914 struct dc_state *context, 3915 uint8_t pipe_idx) 3916 { 3917 int i; 3918 struct pipe_ctx *pipe_ctx_reset; 3919 3920 /* reset the otg sync context for the pipe and its slave pipes if any */ 3921 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3922 pipe_ctx_reset = &context->res_ctx.pipe_ctx[i]; 3923 3924 if (((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_reset) == pipe_idx) && 3925 IS_PIPE_SYNCD_VALID(pipe_ctx_reset)) || (i == pipe_idx)) 3926 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_reset, i); 3927 } 3928 } 3929 3930 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter) 3931 { 3932 /* TODO - get transmitter to phy idx mapping from DMUB */ 3933 uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A; 3934 3935 if (dc->ctx->dce_version == DCN_VERSION_3_1 && 3936 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 3937 switch (transmitter) { 3938 case TRANSMITTER_UNIPHY_A: 3939 phy_idx = 0; 3940 break; 3941 case TRANSMITTER_UNIPHY_B: 3942 phy_idx = 1; 3943 break; 3944 case TRANSMITTER_UNIPHY_C: 3945 phy_idx = 5; 3946 break; 3947 case TRANSMITTER_UNIPHY_D: 3948 phy_idx = 6; 3949 break; 3950 case TRANSMITTER_UNIPHY_E: 3951 phy_idx = 4; 3952 break; 3953 default: 3954 phy_idx = 0; 3955 break; 3956 } 3957 } 3958 3959 return phy_idx; 3960 } 3961 3962 const struct link_hwss *get_link_hwss(const struct dc_link *link, 3963 const struct link_resource *link_res) 3964 { 3965 /* Link_hwss is only accessible by getter function instead of accessing 3966 * by pointers in dc with the intent to protect against breaking polymorphism. 3967 */ 3968 if (can_use_hpo_dp_link_hwss(link, link_res)) 3969 /* TODO: some assumes that if decided link settings is 128b/132b 3970 * channel coding format hpo_dp_link_enc should be used. 3971 * Others believe that if hpo_dp_link_enc is available in link 3972 * resource then hpo_dp_link_enc must be used. This bound between 3973 * hpo_dp_link_enc != NULL and decided link settings is loosely coupled 3974 * with a premise that both hpo_dp_link_enc pointer and decided link 3975 * settings are determined based on single policy function like 3976 * "decide_link_settings" from upper layer. This "convention" 3977 * cannot be maintained and enforced at current level. 3978 * Therefore a refactor is due so we can enforce a strong bound 3979 * between those two parameters at this level. 3980 * 3981 * To put it simple, we want to make enforcement at low level so that 3982 * we will not return link hwss if caller plans to do 8b/10b 3983 * with an hpo encoder. Or we can return a very dummy one that doesn't 3984 * do work for all functions 3985 */ 3986 return get_hpo_dp_link_hwss(); 3987 else if (can_use_dpia_link_hwss(link, link_res)) 3988 return get_dpia_link_hwss(); 3989 else if (can_use_dio_link_hwss(link, link_res)) 3990 return get_dio_link_hwss(); 3991 else 3992 return get_virtual_link_hwss(); 3993 } 3994 3995 bool is_h_timing_divisible_by_2(struct dc_stream_state *stream) 3996 { 3997 bool divisible = false; 3998 uint16_t h_blank_start = 0; 3999 uint16_t h_blank_end = 0; 4000 4001 if (stream) { 4002 h_blank_start = stream->timing.h_total - stream->timing.h_front_porch; 4003 h_blank_end = h_blank_start - stream->timing.h_addressable; 4004 4005 /* HTOTAL, Hblank start/end, and Hsync start/end all must be 4006 * divisible by 2 in order for the horizontal timing params 4007 * to be considered divisible by 2. Hsync start is always 0. 4008 */ 4009 divisible = (stream->timing.h_total % 2 == 0) && 4010 (h_blank_start % 2 == 0) && 4011 (h_blank_end % 2 == 0) && 4012 (stream->timing.h_sync_width % 2 == 0); 4013 } 4014 return divisible; 4015 } 4016 4017 bool dc_resource_acquire_secondary_pipe_for_mpc_odm( 4018 const struct dc *dc, 4019 struct dc_state *state, 4020 struct pipe_ctx *pri_pipe, 4021 struct pipe_ctx *sec_pipe, 4022 bool odm) 4023 { 4024 int pipe_idx = sec_pipe->pipe_idx; 4025 struct pipe_ctx *sec_top, *sec_bottom, *sec_next, *sec_prev; 4026 const struct resource_pool *pool = dc->res_pool; 4027 4028 sec_top = sec_pipe->top_pipe; 4029 sec_bottom = sec_pipe->bottom_pipe; 4030 sec_next = sec_pipe->next_odm_pipe; 4031 sec_prev = sec_pipe->prev_odm_pipe; 4032 4033 *sec_pipe = *pri_pipe; 4034 4035 sec_pipe->top_pipe = sec_top; 4036 sec_pipe->bottom_pipe = sec_bottom; 4037 sec_pipe->next_odm_pipe = sec_next; 4038 sec_pipe->prev_odm_pipe = sec_prev; 4039 4040 sec_pipe->pipe_idx = pipe_idx; 4041 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; 4042 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; 4043 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; 4044 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; 4045 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; 4046 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; 4047 sec_pipe->stream_res.dsc = NULL; 4048 if (odm) { 4049 if (!sec_pipe->top_pipe) 4050 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; 4051 else 4052 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; 4053 if (sec_pipe->stream->timing.flags.DSC == 1) { 4054 #if defined(CONFIG_DRM_AMD_DC_FP) 4055 dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); 4056 #endif 4057 ASSERT(sec_pipe->stream_res.dsc); 4058 if (sec_pipe->stream_res.dsc == NULL) 4059 return false; 4060 } 4061 #if defined(CONFIG_DRM_AMD_DC_FP) 4062 dcn20_build_mapped_resource(dc, state, sec_pipe->stream); 4063 #endif 4064 } 4065 4066 return true; 4067 } 4068 4069 enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc, 4070 struct dc_state *context, 4071 struct pipe_ctx *pipe_ctx) 4072 { 4073 if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) { 4074 if (pipe_ctx->stream_res.hpo_dp_stream_enc == NULL) { 4075 pipe_ctx->stream_res.hpo_dp_stream_enc = 4076 find_first_free_match_hpo_dp_stream_enc_for_link( 4077 &context->res_ctx, dc->res_pool, pipe_ctx->stream); 4078 4079 if (!pipe_ctx->stream_res.hpo_dp_stream_enc) 4080 return DC_NO_STREAM_ENC_RESOURCE; 4081 4082 update_hpo_dp_stream_engine_usage( 4083 &context->res_ctx, dc->res_pool, 4084 pipe_ctx->stream_res.hpo_dp_stream_enc, 4085 true); 4086 } 4087 4088 if (pipe_ctx->link_res.hpo_dp_link_enc == NULL) { 4089 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream)) 4090 return DC_NO_LINK_ENC_RESOURCE; 4091 } 4092 } else { 4093 if (pipe_ctx->stream_res.hpo_dp_stream_enc) { 4094 update_hpo_dp_stream_engine_usage( 4095 &context->res_ctx, dc->res_pool, 4096 pipe_ctx->stream_res.hpo_dp_stream_enc, 4097 false); 4098 pipe_ctx->stream_res.hpo_dp_stream_enc = NULL; 4099 } 4100 if (pipe_ctx->link_res.hpo_dp_link_enc) 4101 remove_hpo_dp_link_enc_from_ctx(&context->res_ctx, pipe_ctx, pipe_ctx->stream); 4102 } 4103 4104 return DC_OK; 4105 } 4106 4107