1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "link_encoder.h" 33 #include "stream_encoder.h" 34 #include "opp.h" 35 #include "timing_generator.h" 36 #include "transform.h" 37 #include "dccg.h" 38 #include "dchubbub.h" 39 #include "dpp.h" 40 #include "core_types.h" 41 #include "set_mode_types.h" 42 #include "virtual/virtual_stream_encoder.h" 43 #include "dpcd_defs.h" 44 45 #if defined(CONFIG_DRM_AMD_DC_SI) 46 #include "dce60/dce60_resource.h" 47 #endif 48 #include "dce80/dce80_resource.h" 49 #include "dce100/dce100_resource.h" 50 #include "dce110/dce110_resource.h" 51 #include "dce112/dce112_resource.h" 52 #include "dce120/dce120_resource.h" 53 #if defined(CONFIG_DRM_AMD_DC_DCN) 54 #include "dcn10/dcn10_resource.h" 55 #include "dcn20/dcn20_resource.h" 56 #include "dcn21/dcn21_resource.h" 57 #include "dcn30/dcn30_resource.h" 58 #include "dcn301/dcn301_resource.h" 59 #include "dcn302/dcn302_resource.h" 60 #endif 61 62 #define DC_LOGGER_INIT(logger) 63 64 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 65 { 66 enum dce_version dc_version = DCE_VERSION_UNKNOWN; 67 switch (asic_id.chip_family) { 68 69 #if defined(CONFIG_DRM_AMD_DC_SI) 70 case FAMILY_SI: 71 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) || 72 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) || 73 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev)) 74 dc_version = DCE_VERSION_6_0; 75 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev)) 76 dc_version = DCE_VERSION_6_4; 77 else 78 dc_version = DCE_VERSION_6_1; 79 break; 80 #endif 81 case FAMILY_CI: 82 dc_version = DCE_VERSION_8_0; 83 break; 84 case FAMILY_KV: 85 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) || 86 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) || 87 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev)) 88 dc_version = DCE_VERSION_8_3; 89 else 90 dc_version = DCE_VERSION_8_1; 91 break; 92 case FAMILY_CZ: 93 dc_version = DCE_VERSION_11_0; 94 break; 95 96 case FAMILY_VI: 97 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || 98 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { 99 dc_version = DCE_VERSION_10_0; 100 break; 101 } 102 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || 103 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || 104 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { 105 dc_version = DCE_VERSION_11_2; 106 } 107 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) 108 dc_version = DCE_VERSION_11_22; 109 break; 110 case FAMILY_AI: 111 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev)) 112 dc_version = DCE_VERSION_12_1; 113 else 114 dc_version = DCE_VERSION_12_0; 115 break; 116 #if defined(CONFIG_DRM_AMD_DC_DCN) 117 case FAMILY_RV: 118 dc_version = DCN_VERSION_1_0; 119 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) 120 dc_version = DCN_VERSION_1_01; 121 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) 122 dc_version = DCN_VERSION_2_1; 123 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) 124 dc_version = DCN_VERSION_2_1; 125 break; 126 127 case FAMILY_NV: 128 dc_version = DCN_VERSION_2_0; 129 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) 130 dc_version = DCN_VERSION_3_0; 131 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) 132 dc_version = DCN_VERSION_3_02; 133 break; 134 135 case FAMILY_VGH: 136 dc_version = DCN_VERSION_3_01; 137 break; 138 #endif 139 default: 140 dc_version = DCE_VERSION_UNKNOWN; 141 break; 142 } 143 return dc_version; 144 } 145 146 struct resource_pool *dc_create_resource_pool(struct dc *dc, 147 const struct dc_init_data *init_data, 148 enum dce_version dc_version) 149 { 150 struct resource_pool *res_pool = NULL; 151 152 switch (dc_version) { 153 #if defined(CONFIG_DRM_AMD_DC_SI) 154 case DCE_VERSION_6_0: 155 res_pool = dce60_create_resource_pool( 156 init_data->num_virtual_links, dc); 157 break; 158 case DCE_VERSION_6_1: 159 res_pool = dce61_create_resource_pool( 160 init_data->num_virtual_links, dc); 161 break; 162 case DCE_VERSION_6_4: 163 res_pool = dce64_create_resource_pool( 164 init_data->num_virtual_links, dc); 165 break; 166 #endif 167 case DCE_VERSION_8_0: 168 res_pool = dce80_create_resource_pool( 169 init_data->num_virtual_links, dc); 170 break; 171 case DCE_VERSION_8_1: 172 res_pool = dce81_create_resource_pool( 173 init_data->num_virtual_links, dc); 174 break; 175 case DCE_VERSION_8_3: 176 res_pool = dce83_create_resource_pool( 177 init_data->num_virtual_links, dc); 178 break; 179 case DCE_VERSION_10_0: 180 res_pool = dce100_create_resource_pool( 181 init_data->num_virtual_links, dc); 182 break; 183 case DCE_VERSION_11_0: 184 res_pool = dce110_create_resource_pool( 185 init_data->num_virtual_links, dc, 186 init_data->asic_id); 187 break; 188 case DCE_VERSION_11_2: 189 case DCE_VERSION_11_22: 190 res_pool = dce112_create_resource_pool( 191 init_data->num_virtual_links, dc); 192 break; 193 case DCE_VERSION_12_0: 194 case DCE_VERSION_12_1: 195 res_pool = dce120_create_resource_pool( 196 init_data->num_virtual_links, dc); 197 break; 198 199 #if defined(CONFIG_DRM_AMD_DC_DCN) 200 case DCN_VERSION_1_0: 201 case DCN_VERSION_1_01: 202 res_pool = dcn10_create_resource_pool(init_data, dc); 203 break; 204 case DCN_VERSION_2_0: 205 res_pool = dcn20_create_resource_pool(init_data, dc); 206 break; 207 case DCN_VERSION_2_1: 208 res_pool = dcn21_create_resource_pool(init_data, dc); 209 break; 210 case DCN_VERSION_3_0: 211 res_pool = dcn30_create_resource_pool(init_data, dc); 212 break; 213 case DCN_VERSION_3_01: 214 res_pool = dcn301_create_resource_pool(init_data, dc); 215 break; 216 case DCN_VERSION_3_02: 217 res_pool = dcn302_create_resource_pool(init_data, dc); 218 break; 219 #endif 220 default: 221 break; 222 } 223 224 if (res_pool != NULL) { 225 if (dc->ctx->dc_bios->fw_info_valid) { 226 res_pool->ref_clocks.xtalin_clock_inKhz = 227 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 228 /* initialize with firmware data first, no all 229 * ASIC have DCCG SW component. FPGA or 230 * simulation need initialization of 231 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz 232 * with xtalin_clock_inKhz 233 */ 234 res_pool->ref_clocks.dccg_ref_clock_inKhz = 235 res_pool->ref_clocks.xtalin_clock_inKhz; 236 res_pool->ref_clocks.dchub_ref_clock_inKhz = 237 res_pool->ref_clocks.xtalin_clock_inKhz; 238 } else 239 ASSERT_CRITICAL(false); 240 } 241 242 return res_pool; 243 } 244 245 void dc_destroy_resource_pool(struct dc *dc) 246 { 247 if (dc) { 248 if (dc->res_pool) 249 dc->res_pool->funcs->destroy(&dc->res_pool); 250 251 kfree(dc->hwseq); 252 } 253 } 254 255 static void update_num_audio( 256 const struct resource_straps *straps, 257 unsigned int *num_audio, 258 struct audio_support *aud_support) 259 { 260 aud_support->dp_audio = true; 261 aud_support->hdmi_audio_native = false; 262 aud_support->hdmi_audio_on_dongle = false; 263 264 if (straps->hdmi_disable == 0) { 265 if (straps->dc_pinstraps_audio & 0x2) { 266 aud_support->hdmi_audio_on_dongle = true; 267 aud_support->hdmi_audio_native = true; 268 } 269 } 270 271 switch (straps->audio_stream_number) { 272 case 0: /* multi streams supported */ 273 break; 274 case 1: /* multi streams not supported */ 275 *num_audio = 1; 276 break; 277 default: 278 DC_ERR("DC: unexpected audio fuse!\n"); 279 } 280 } 281 282 bool resource_construct( 283 unsigned int num_virtual_links, 284 struct dc *dc, 285 struct resource_pool *pool, 286 const struct resource_create_funcs *create_funcs) 287 { 288 struct dc_context *ctx = dc->ctx; 289 const struct resource_caps *caps = pool->res_cap; 290 int i; 291 unsigned int num_audio = caps->num_audio; 292 struct resource_straps straps = {0}; 293 294 if (create_funcs->read_dce_straps) 295 create_funcs->read_dce_straps(dc->ctx, &straps); 296 297 pool->audio_count = 0; 298 if (create_funcs->create_audio) { 299 /* find the total number of streams available via the 300 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 301 * registers (one for each pin) starting from pin 1 302 * up to the max number of audio pins. 303 * We stop on the first pin where 304 * PORT_CONNECTIVITY == 1 (as instructed by HW team). 305 */ 306 update_num_audio(&straps, &num_audio, &pool->audio_support); 307 for (i = 0; i < caps->num_audio; i++) { 308 struct audio *aud = create_funcs->create_audio(ctx, i); 309 310 if (aud == NULL) { 311 DC_ERR("DC: failed to create audio!\n"); 312 return false; 313 } 314 if (!aud->funcs->endpoint_valid(aud)) { 315 aud->funcs->destroy(&aud); 316 break; 317 } 318 pool->audios[i] = aud; 319 pool->audio_count++; 320 } 321 } 322 323 pool->stream_enc_count = 0; 324 if (create_funcs->create_stream_encoder) { 325 for (i = 0; i < caps->num_stream_encoder; i++) { 326 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); 327 if (pool->stream_enc[i] == NULL) 328 DC_ERR("DC: failed to create stream_encoder!\n"); 329 pool->stream_enc_count++; 330 } 331 } 332 333 #if defined(CONFIG_DRM_AMD_DC_DCN) 334 for (i = 0; i < caps->num_mpc_3dlut; i++) { 335 pool->mpc_lut[i] = dc_create_3dlut_func(); 336 if (pool->mpc_lut[i] == NULL) 337 DC_ERR("DC: failed to create MPC 3dlut!\n"); 338 pool->mpc_shaper[i] = dc_create_transfer_func(); 339 if (pool->mpc_shaper[i] == NULL) 340 DC_ERR("DC: failed to create MPC shaper!\n"); 341 } 342 #endif 343 dc->caps.dynamic_audio = false; 344 if (pool->audio_count < pool->stream_enc_count) { 345 dc->caps.dynamic_audio = true; 346 } 347 for (i = 0; i < num_virtual_links; i++) { 348 pool->stream_enc[pool->stream_enc_count] = 349 virtual_stream_encoder_create( 350 ctx, ctx->dc_bios); 351 if (pool->stream_enc[pool->stream_enc_count] == NULL) { 352 DC_ERR("DC: failed to create stream_encoder!\n"); 353 return false; 354 } 355 pool->stream_enc_count++; 356 } 357 358 dc->hwseq = create_funcs->create_hwseq(ctx); 359 360 return true; 361 } 362 static int find_matching_clock_source( 363 const struct resource_pool *pool, 364 struct clock_source *clock_source) 365 { 366 367 int i; 368 369 for (i = 0; i < pool->clk_src_count; i++) { 370 if (pool->clock_sources[i] == clock_source) 371 return i; 372 } 373 return -1; 374 } 375 376 void resource_unreference_clock_source( 377 struct resource_context *res_ctx, 378 const struct resource_pool *pool, 379 struct clock_source *clock_source) 380 { 381 int i = find_matching_clock_source(pool, clock_source); 382 383 if (i > -1) 384 res_ctx->clock_source_ref_count[i]--; 385 386 if (pool->dp_clock_source == clock_source) 387 res_ctx->dp_clock_source_ref_count--; 388 } 389 390 void resource_reference_clock_source( 391 struct resource_context *res_ctx, 392 const struct resource_pool *pool, 393 struct clock_source *clock_source) 394 { 395 int i = find_matching_clock_source(pool, clock_source); 396 397 if (i > -1) 398 res_ctx->clock_source_ref_count[i]++; 399 400 if (pool->dp_clock_source == clock_source) 401 res_ctx->dp_clock_source_ref_count++; 402 } 403 404 int resource_get_clock_source_reference( 405 struct resource_context *res_ctx, 406 const struct resource_pool *pool, 407 struct clock_source *clock_source) 408 { 409 int i = find_matching_clock_source(pool, clock_source); 410 411 if (i > -1) 412 return res_ctx->clock_source_ref_count[i]; 413 414 if (pool->dp_clock_source == clock_source) 415 return res_ctx->dp_clock_source_ref_count; 416 417 return -1; 418 } 419 420 bool resource_are_streams_timing_synchronizable( 421 struct dc_stream_state *stream1, 422 struct dc_stream_state *stream2) 423 { 424 if (stream1->timing.h_total != stream2->timing.h_total) 425 return false; 426 427 if (stream1->timing.v_total != stream2->timing.v_total) 428 return false; 429 430 if (stream1->timing.h_addressable 431 != stream2->timing.h_addressable) 432 return false; 433 434 if (stream1->timing.v_addressable 435 != stream2->timing.v_addressable) 436 return false; 437 438 if (stream1->timing.v_front_porch 439 != stream2->timing.v_front_porch) 440 return false; 441 442 if (stream1->timing.pix_clk_100hz 443 != stream2->timing.pix_clk_100hz) 444 return false; 445 446 if (stream1->clamping.c_depth != stream2->clamping.c_depth) 447 return false; 448 449 if (stream1->phy_pix_clk != stream2->phy_pix_clk 450 && (!dc_is_dp_signal(stream1->signal) 451 || !dc_is_dp_signal(stream2->signal))) 452 return false; 453 454 if (stream1->view_format != stream2->view_format) 455 return false; 456 457 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param) 458 return false; 459 460 return true; 461 } 462 static bool is_dp_and_hdmi_sharable( 463 struct dc_stream_state *stream1, 464 struct dc_stream_state *stream2) 465 { 466 if (stream1->ctx->dc->caps.disable_dp_clk_share) 467 return false; 468 469 if (stream1->clamping.c_depth != COLOR_DEPTH_888 || 470 stream2->clamping.c_depth != COLOR_DEPTH_888) 471 return false; 472 473 return true; 474 475 } 476 477 static bool is_sharable_clk_src( 478 const struct pipe_ctx *pipe_with_clk_src, 479 const struct pipe_ctx *pipe) 480 { 481 if (pipe_with_clk_src->clock_source == NULL) 482 return false; 483 484 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) 485 return false; 486 487 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) || 488 (dc_is_dp_signal(pipe->stream->signal) && 489 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream, 490 pipe->stream))) 491 return false; 492 493 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) 494 && dc_is_dual_link_signal(pipe->stream->signal)) 495 return false; 496 497 if (dc_is_hdmi_signal(pipe->stream->signal) 498 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal)) 499 return false; 500 501 if (!resource_are_streams_timing_synchronizable( 502 pipe_with_clk_src->stream, pipe->stream)) 503 return false; 504 505 return true; 506 } 507 508 struct clock_source *resource_find_used_clk_src_for_sharing( 509 struct resource_context *res_ctx, 510 struct pipe_ctx *pipe_ctx) 511 { 512 int i; 513 514 for (i = 0; i < MAX_PIPES; i++) { 515 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) 516 return res_ctx->pipe_ctx[i].clock_source; 517 } 518 519 return NULL; 520 } 521 522 static enum pixel_format convert_pixel_format_to_dalsurface( 523 enum surface_pixel_format surface_pixel_format) 524 { 525 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 526 527 switch (surface_pixel_format) { 528 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 529 dal_pixel_format = PIXEL_FORMAT_INDEX8; 530 break; 531 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 532 dal_pixel_format = PIXEL_FORMAT_RGB565; 533 break; 534 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 535 dal_pixel_format = PIXEL_FORMAT_RGB565; 536 break; 537 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 538 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 539 break; 540 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 541 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 542 break; 543 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 544 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 545 break; 546 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 547 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 548 break; 549 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 550 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS; 551 break; 552 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 553 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 554 dal_pixel_format = PIXEL_FORMAT_FP16; 555 break; 556 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 557 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 558 dal_pixel_format = PIXEL_FORMAT_420BPP8; 559 break; 560 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 561 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 562 dal_pixel_format = PIXEL_FORMAT_420BPP10; 563 break; 564 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 565 default: 566 dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 567 break; 568 } 569 return dal_pixel_format; 570 } 571 572 static inline void get_vp_scan_direction( 573 enum dc_rotation_angle rotation, 574 bool horizontal_mirror, 575 bool *orthogonal_rotation, 576 bool *flip_vert_scan_dir, 577 bool *flip_horz_scan_dir) 578 { 579 *orthogonal_rotation = false; 580 *flip_vert_scan_dir = false; 581 *flip_horz_scan_dir = false; 582 if (rotation == ROTATION_ANGLE_180) { 583 *flip_vert_scan_dir = true; 584 *flip_horz_scan_dir = true; 585 } else if (rotation == ROTATION_ANGLE_90) { 586 *orthogonal_rotation = true; 587 *flip_horz_scan_dir = true; 588 } else if (rotation == ROTATION_ANGLE_270) { 589 *orthogonal_rotation = true; 590 *flip_vert_scan_dir = true; 591 } 592 593 if (horizontal_mirror) 594 *flip_horz_scan_dir = !*flip_horz_scan_dir; 595 } 596 597 int get_num_mpc_splits(struct pipe_ctx *pipe) 598 { 599 int mpc_split_count = 0; 600 struct pipe_ctx *other_pipe = pipe->bottom_pipe; 601 602 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 603 mpc_split_count++; 604 other_pipe = other_pipe->bottom_pipe; 605 } 606 other_pipe = pipe->top_pipe; 607 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 608 mpc_split_count++; 609 other_pipe = other_pipe->top_pipe; 610 } 611 612 return mpc_split_count; 613 } 614 615 int get_num_odm_splits(struct pipe_ctx *pipe) 616 { 617 int odm_split_count = 0; 618 struct pipe_ctx *next_pipe = pipe->next_odm_pipe; 619 while (next_pipe) { 620 odm_split_count++; 621 next_pipe = next_pipe->next_odm_pipe; 622 } 623 pipe = pipe->prev_odm_pipe; 624 while (pipe) { 625 odm_split_count++; 626 pipe = pipe->prev_odm_pipe; 627 } 628 return odm_split_count; 629 } 630 631 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx) 632 { 633 *split_count = get_num_odm_splits(pipe_ctx); 634 *split_idx = 0; 635 if (*split_count == 0) { 636 /*Check for mpc split*/ 637 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe; 638 639 *split_count = get_num_mpc_splits(pipe_ctx); 640 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) { 641 (*split_idx)++; 642 split_pipe = split_pipe->top_pipe; 643 } 644 } else { 645 /*Get odm split index*/ 646 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe; 647 648 while (split_pipe) { 649 (*split_idx)++; 650 split_pipe = split_pipe->prev_odm_pipe; 651 } 652 } 653 } 654 655 static void calculate_viewport(struct pipe_ctx *pipe_ctx) 656 { 657 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 658 const struct dc_stream_state *stream = pipe_ctx->stream; 659 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 660 struct rect surf_src = plane_state->src_rect; 661 struct rect clip, dest; 662 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 663 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 664 int split_count = 0; 665 int split_idx = 0; 666 bool orthogonal_rotation, flip_y_start, flip_x_start; 667 668 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 669 670 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || 671 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { 672 split_count = 0; 673 split_idx = 0; 674 } 675 676 /* The actual clip is an intersection between stream 677 * source and surface clip 678 */ 679 dest = plane_state->dst_rect; 680 clip.x = stream->src.x > plane_state->clip_rect.x ? 681 stream->src.x : plane_state->clip_rect.x; 682 683 clip.width = stream->src.x + stream->src.width < 684 plane_state->clip_rect.x + plane_state->clip_rect.width ? 685 stream->src.x + stream->src.width - clip.x : 686 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ; 687 688 clip.y = stream->src.y > plane_state->clip_rect.y ? 689 stream->src.y : plane_state->clip_rect.y; 690 691 clip.height = stream->src.y + stream->src.height < 692 plane_state->clip_rect.y + plane_state->clip_rect.height ? 693 stream->src.y + stream->src.height - clip.y : 694 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ; 695 696 /* 697 * Need to calculate how scan origin is shifted in vp space 698 * to correctly rotate clip and dst 699 */ 700 get_vp_scan_direction( 701 plane_state->rotation, 702 plane_state->horizontal_mirror, 703 &orthogonal_rotation, 704 &flip_y_start, 705 &flip_x_start); 706 707 if (orthogonal_rotation) { 708 swap(clip.x, clip.y); 709 swap(clip.width, clip.height); 710 swap(dest.x, dest.y); 711 swap(dest.width, dest.height); 712 } 713 if (flip_x_start) { 714 clip.x = dest.x + dest.width - clip.x - clip.width; 715 dest.x = 0; 716 } 717 if (flip_y_start) { 718 clip.y = dest.y + dest.height - clip.y - clip.height; 719 dest.y = 0; 720 } 721 722 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio 723 * num_pixels = clip.num_pix * scl_ratio 724 */ 725 data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width; 726 data->viewport.width = clip.width * surf_src.width / dest.width; 727 728 data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height; 729 data->viewport.height = clip.height * surf_src.height / dest.height; 730 731 /* Handle split */ 732 if (split_count) { 733 /* extra pixels in the division remainder need to go to pipes after 734 * the extra pixel index minus one(epimo) defined here as: 735 */ 736 int epimo = 0; 737 738 if (orthogonal_rotation) { 739 if (flip_y_start) 740 split_idx = split_count - split_idx; 741 742 epimo = split_count - data->viewport.height % (split_count + 1); 743 744 data->viewport.y += (data->viewport.height / (split_count + 1)) * split_idx; 745 if (split_idx > epimo) 746 data->viewport.y += split_idx - epimo - 1; 747 data->viewport.height = data->viewport.height / (split_count + 1) + (split_idx > epimo ? 1 : 0); 748 } else { 749 if (flip_x_start) 750 split_idx = split_count - split_idx; 751 752 epimo = split_count - data->viewport.width % (split_count + 1); 753 754 data->viewport.x += (data->viewport.width / (split_count + 1)) * split_idx; 755 if (split_idx > epimo) 756 data->viewport.x += split_idx - epimo - 1; 757 data->viewport.width = data->viewport.width / (split_count + 1) + (split_idx > epimo ? 1 : 0); 758 } 759 } 760 761 /* Round down, compensate in init */ 762 data->viewport_c.x = data->viewport.x / vpc_div; 763 data->viewport_c.y = data->viewport.y / vpc_div; 764 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero; 765 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero; 766 767 /* Round up, assume original video size always even dimensions */ 768 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div; 769 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div; 770 771 data->viewport_unadjusted = data->viewport; 772 data->viewport_c_unadjusted = data->viewport_c; 773 } 774 775 static void calculate_recout(struct pipe_ctx *pipe_ctx) 776 { 777 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 778 const struct dc_stream_state *stream = pipe_ctx->stream; 779 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 780 struct rect surf_clip = plane_state->clip_rect; 781 bool pri_split_tb = pipe_ctx->bottom_pipe && 782 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state && 783 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; 784 bool sec_split_tb = pipe_ctx->top_pipe && 785 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state && 786 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; 787 int split_count = 0; 788 int split_idx = 0; 789 790 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 791 792 /* 793 * Only the leftmost ODM pipe should be offset by a nonzero distance 794 */ 795 if (!pipe_ctx->prev_odm_pipe) { 796 data->recout.x = stream->dst.x; 797 if (stream->src.x < surf_clip.x) 798 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width 799 / stream->src.width; 800 801 } else 802 data->recout.x = 0; 803 804 if (stream->src.x > surf_clip.x) 805 surf_clip.width -= stream->src.x - surf_clip.x; 806 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width; 807 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width) 808 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x; 809 810 data->recout.y = stream->dst.y; 811 if (stream->src.y < surf_clip.y) 812 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height 813 / stream->src.height; 814 else if (stream->src.y > surf_clip.y) 815 surf_clip.height -= stream->src.y - surf_clip.y; 816 817 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height; 818 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height) 819 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y; 820 821 /* Handle h & v split, handle rotation using viewport */ 822 if (sec_split_tb) { 823 data->recout.y += data->recout.height / 2; 824 /* Floor primary pipe, ceil 2ndary pipe */ 825 data->recout.height = (data->recout.height + 1) / 2; 826 } else if (pri_split_tb) 827 data->recout.height /= 2; 828 else if (split_count) { 829 /* extra pixels in the division remainder need to go to pipes after 830 * the extra pixel index minus one(epimo) defined here as: 831 */ 832 int epimo = split_count - data->recout.width % (split_count + 1); 833 834 /*no recout offset due to odm */ 835 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) { 836 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx; 837 if (split_idx > epimo) 838 data->recout.x += split_idx - epimo - 1; 839 } 840 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0); 841 } 842 } 843 844 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) 845 { 846 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 847 const struct dc_stream_state *stream = pipe_ctx->stream; 848 struct rect surf_src = plane_state->src_rect; 849 const int in_w = stream->src.width; 850 const int in_h = stream->src.height; 851 const int out_w = stream->dst.width; 852 const int out_h = stream->dst.height; 853 854 /*Swap surf_src height and width since scaling ratios are in recout rotation*/ 855 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 856 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 857 swap(surf_src.height, surf_src.width); 858 859 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( 860 surf_src.width, 861 plane_state->dst_rect.width); 862 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( 863 surf_src.height, 864 plane_state->dst_rect.height); 865 866 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 867 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; 868 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 869 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; 870 871 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( 872 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); 873 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( 874 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); 875 876 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; 877 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; 878 879 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 880 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { 881 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; 882 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; 883 } 884 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate( 885 pipe_ctx->plane_res.scl_data.ratios.horz, 19); 886 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( 887 pipe_ctx->plane_res.scl_data.ratios.vert, 19); 888 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate( 889 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19); 890 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate( 891 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); 892 } 893 894 static inline void adjust_vp_and_init_for_seamless_clip( 895 bool flip_scan_dir, 896 int recout_skip, 897 int src_size, 898 int taps, 899 struct fixed31_32 ratio, 900 struct fixed31_32 *init, 901 int *vp_offset, 902 int *vp_size) 903 { 904 if (!flip_scan_dir) { 905 /* Adjust for viewport end clip-off */ 906 if ((*vp_offset + *vp_size) < src_size) { 907 int vp_clip = src_size - *vp_size - *vp_offset; 908 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio)); 909 910 int_part = int_part > 0 ? int_part : 0; 911 *vp_size += int_part < vp_clip ? int_part : vp_clip; 912 } 913 914 /* Adjust for non-0 viewport offset */ 915 if (*vp_offset) { 916 int int_part; 917 918 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip)); 919 int_part = dc_fixpt_floor(*init) - *vp_offset; 920 if (int_part < taps) { 921 int int_adj = *vp_offset >= (taps - int_part) ? 922 (taps - int_part) : *vp_offset; 923 *vp_offset -= int_adj; 924 *vp_size += int_adj; 925 int_part += int_adj; 926 } else if (int_part > taps) { 927 *vp_offset += int_part - taps; 928 *vp_size -= int_part - taps; 929 int_part = taps; 930 } 931 init->value &= 0xffffffff; 932 *init = dc_fixpt_add_int(*init, int_part); 933 } 934 } else { 935 /* Adjust for non-0 viewport offset */ 936 if (*vp_offset) { 937 int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio)); 938 939 int_part = int_part > 0 ? int_part : 0; 940 *vp_size += int_part < *vp_offset ? int_part : *vp_offset; 941 *vp_offset -= int_part < *vp_offset ? int_part : *vp_offset; 942 } 943 944 /* Adjust for viewport end clip-off */ 945 if ((*vp_offset + *vp_size) < src_size) { 946 int int_part; 947 int end_offset = src_size - *vp_offset - *vp_size; 948 949 /* 950 * this is init if vp had no offset, keep in mind this is from the 951 * right side of vp due to scan direction 952 */ 953 *init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip)); 954 /* 955 * this is the difference between first pixel of viewport available to read 956 * and init position, takning into account scan direction 957 */ 958 int_part = dc_fixpt_floor(*init) - end_offset; 959 if (int_part < taps) { 960 int int_adj = end_offset >= (taps - int_part) ? 961 (taps - int_part) : end_offset; 962 *vp_size += int_adj; 963 int_part += int_adj; 964 } else if (int_part > taps) { 965 *vp_size += int_part - taps; 966 int_part = taps; 967 } 968 init->value &= 0xffffffff; 969 *init = dc_fixpt_add_int(*init, int_part); 970 } 971 } 972 } 973 974 static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx) 975 { 976 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 977 const struct dc_stream_state *stream = pipe_ctx->stream; 978 struct pipe_ctx *odm_pipe = pipe_ctx; 979 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 980 struct rect src = pipe_ctx->plane_state->src_rect; 981 int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v; 982 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 983 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 984 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; 985 int odm_idx = 0; 986 987 /* 988 * Need to calculate the scan direction for viewport to make adjustments 989 */ 990 get_vp_scan_direction( 991 plane_state->rotation, 992 plane_state->horizontal_mirror, 993 &orthogonal_rotation, 994 &flip_vert_scan_dir, 995 &flip_horz_scan_dir); 996 997 /* Calculate src rect rotation adjusted to recout space */ 998 surf_size_h = src.x + src.width; 999 surf_size_v = src.y + src.height; 1000 if (flip_horz_scan_dir) 1001 src.x = 0; 1002 if (flip_vert_scan_dir) 1003 src.y = 0; 1004 if (orthogonal_rotation) { 1005 swap(src.x, src.y); 1006 swap(src.width, src.height); 1007 } 1008 1009 /*modified recout_skip_h calculation due to odm having no recout offset*/ 1010 while (odm_pipe->prev_odm_pipe) { 1011 odm_idx++; 1012 odm_pipe = odm_pipe->prev_odm_pipe; 1013 } 1014 /*odm_pipe is the leftmost pipe in the ODM group*/ 1015 recout_skip_h = odm_idx * data->recout.width; 1016 1017 /* Recout matching initial vp offset = recout_offset - (stream dst offset + 1018 * ((surf dst offset - stream src offset) * 1/ stream scaling ratio) 1019 * - (surf surf_src offset * 1/ full scl ratio)) 1020 */ 1021 recout_skip_h += odm_pipe->plane_res.scl_data.recout.x 1022 - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x) 1023 * stream->dst.width / stream->src.width - 1024 src.x * plane_state->dst_rect.width / src.width 1025 * stream->dst.width / stream->src.width); 1026 1027 1028 recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y) 1029 * stream->dst.height / stream->src.height - 1030 src.y * plane_state->dst_rect.height / src.height 1031 * stream->dst.height / stream->src.height); 1032 if (orthogonal_rotation) 1033 swap(recout_skip_h, recout_skip_v); 1034 /* 1035 * Init calculated according to formula: 1036 * init = (scaling_ratio + number_of_taps + 1) / 2 1037 * init_bot = init + scaling_ratio 1038 * init_c = init + truncated_vp_c_offset(from calculate viewport) 1039 */ 1040 data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int( 1041 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19); 1042 1043 data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int( 1044 dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19); 1045 1046 data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int( 1047 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19); 1048 1049 data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int( 1050 dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19); 1051 1052 /* 1053 * Taps, inits and scaling ratios are in recout space need to rotate 1054 * to viewport rotation before adjustment 1055 */ 1056 adjust_vp_and_init_for_seamless_clip( 1057 flip_horz_scan_dir, 1058 recout_skip_h, 1059 surf_size_h, 1060 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps, 1061 orthogonal_rotation ? data->ratios.vert : data->ratios.horz, 1062 orthogonal_rotation ? &data->inits.v : &data->inits.h, 1063 &data->viewport.x, 1064 &data->viewport.width); 1065 adjust_vp_and_init_for_seamless_clip( 1066 flip_horz_scan_dir, 1067 recout_skip_h, 1068 surf_size_h / vpc_div, 1069 orthogonal_rotation ? data->taps.v_taps_c : data->taps.h_taps_c, 1070 orthogonal_rotation ? data->ratios.vert_c : data->ratios.horz_c, 1071 orthogonal_rotation ? &data->inits.v_c : &data->inits.h_c, 1072 &data->viewport_c.x, 1073 &data->viewport_c.width); 1074 adjust_vp_and_init_for_seamless_clip( 1075 flip_vert_scan_dir, 1076 recout_skip_v, 1077 surf_size_v, 1078 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps, 1079 orthogonal_rotation ? data->ratios.horz : data->ratios.vert, 1080 orthogonal_rotation ? &data->inits.h : &data->inits.v, 1081 &data->viewport.y, 1082 &data->viewport.height); 1083 adjust_vp_and_init_for_seamless_clip( 1084 flip_vert_scan_dir, 1085 recout_skip_v, 1086 surf_size_v / vpc_div, 1087 orthogonal_rotation ? data->taps.h_taps_c : data->taps.v_taps_c, 1088 orthogonal_rotation ? data->ratios.horz_c : data->ratios.vert_c, 1089 orthogonal_rotation ? &data->inits.h_c : &data->inits.v_c, 1090 &data->viewport_c.y, 1091 &data->viewport_c.height); 1092 1093 /* Interlaced inits based on final vert inits */ 1094 data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert); 1095 data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c); 1096 1097 } 1098 1099 /* 1100 * When handling 270 rotation in mixed SLS mode, we have 1101 * stream->timing.h_border_left that is non zero. If we are doing 1102 * pipe-splitting, this h_border_left value gets added to recout.x and when it 1103 * calls calculate_inits_and_adj_vp() and 1104 * adjust_vp_and_init_for_seamless_clip(), it can cause viewport.height for a 1105 * pipe to be incorrect. 1106 * 1107 * To fix this, instead of using stream->timing.h_border_left, we can use 1108 * stream->dst.x to represent the border instead. So we will set h_border_left 1109 * to 0 and shift the appropriate amount in stream->dst.x. We will then 1110 * perform all calculations in resource_build_scaling_params() based on this 1111 * and then restore the h_border_left and stream->dst.x to their original 1112 * values. 1113 * 1114 * shift_border_left_to_dst() will shift the amount of h_border_left to 1115 * stream->dst.x and set h_border_left to 0. restore_border_left_from_dst() 1116 * will restore h_border_left and stream->dst.x back to their original values 1117 * We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the 1118 * original h_border_left value in its calculation. 1119 */ 1120 static int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx) 1121 { 1122 int store_h_border_left = pipe_ctx->stream->timing.h_border_left; 1123 1124 if (store_h_border_left) { 1125 pipe_ctx->stream->timing.h_border_left = 0; 1126 pipe_ctx->stream->dst.x += store_h_border_left; 1127 } 1128 return store_h_border_left; 1129 } 1130 1131 static void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx, 1132 int store_h_border_left) 1133 { 1134 pipe_ctx->stream->dst.x -= store_h_border_left; 1135 pipe_ctx->stream->timing.h_border_left = store_h_border_left; 1136 } 1137 1138 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 1139 { 1140 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1141 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 1142 bool res = false; 1143 int store_h_border_left = shift_border_left_to_dst(pipe_ctx); 1144 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 1145 /* Important: scaling ratio calculation requires pixel format, 1146 * lb depth calculation requires recout and taps require scaling ratios. 1147 * Inits require viewport, taps, ratios and recout of split pipe 1148 */ 1149 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( 1150 pipe_ctx->plane_state->format); 1151 1152 calculate_scaling_ratios(pipe_ctx); 1153 1154 calculate_viewport(pipe_ctx); 1155 1156 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE || 1157 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) { 1158 if (store_h_border_left) { 1159 restore_border_left_from_dst(pipe_ctx, 1160 store_h_border_left); 1161 } 1162 return false; 1163 } 1164 1165 calculate_recout(pipe_ctx); 1166 1167 /** 1168 * Setting line buffer pixel depth to 24bpp yields banding 1169 * on certain displays, such as the Sharp 4k 1170 */ 1171 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; 1172 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; 1173 1174 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left; 1175 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top; 1176 1177 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + 1178 store_h_border_left + timing->h_border_right; 1179 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + 1180 timing->v_border_top + timing->v_border_bottom; 1181 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe) 1182 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1; 1183 1184 /* Taps calculations */ 1185 if (pipe_ctx->plane_res.xfm != NULL) 1186 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1187 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1188 1189 if (pipe_ctx->plane_res.dpp != NULL) 1190 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1191 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1192 1193 1194 if (!res) { 1195 /* Try 24 bpp linebuffer */ 1196 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; 1197 1198 if (pipe_ctx->plane_res.xfm != NULL) 1199 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1200 pipe_ctx->plane_res.xfm, 1201 &pipe_ctx->plane_res.scl_data, 1202 &plane_state->scaling_quality); 1203 1204 if (pipe_ctx->plane_res.dpp != NULL) 1205 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1206 pipe_ctx->plane_res.dpp, 1207 &pipe_ctx->plane_res.scl_data, 1208 &plane_state->scaling_quality); 1209 } 1210 1211 if (res) 1212 /* May need to re-check lb size after this in some obscure scenario */ 1213 calculate_inits_and_adj_vp(pipe_ctx); 1214 1215 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n" 1216 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n", 1217 __func__, 1218 pipe_ctx->pipe_idx, 1219 pipe_ctx->plane_res.scl_data.viewport.height, 1220 pipe_ctx->plane_res.scl_data.viewport.width, 1221 pipe_ctx->plane_res.scl_data.viewport.x, 1222 pipe_ctx->plane_res.scl_data.viewport.y, 1223 pipe_ctx->plane_res.scl_data.recout.height, 1224 pipe_ctx->plane_res.scl_data.recout.width, 1225 pipe_ctx->plane_res.scl_data.recout.x, 1226 pipe_ctx->plane_res.scl_data.recout.y, 1227 pipe_ctx->plane_res.scl_data.h_active, 1228 pipe_ctx->plane_res.scl_data.v_active, 1229 plane_state->src_rect.height, 1230 plane_state->src_rect.width, 1231 plane_state->src_rect.x, 1232 plane_state->src_rect.y, 1233 plane_state->dst_rect.height, 1234 plane_state->dst_rect.width, 1235 plane_state->dst_rect.x, 1236 plane_state->dst_rect.y, 1237 plane_state->clip_rect.height, 1238 plane_state->clip_rect.width, 1239 plane_state->clip_rect.x, 1240 plane_state->clip_rect.y); 1241 1242 if (store_h_border_left) 1243 restore_border_left_from_dst(pipe_ctx, store_h_border_left); 1244 1245 return res; 1246 } 1247 1248 1249 enum dc_status resource_build_scaling_params_for_context( 1250 const struct dc *dc, 1251 struct dc_state *context) 1252 { 1253 int i; 1254 1255 for (i = 0; i < MAX_PIPES; i++) { 1256 if (context->res_ctx.pipe_ctx[i].plane_state != NULL && 1257 context->res_ctx.pipe_ctx[i].stream != NULL) 1258 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) 1259 return DC_FAIL_SCALING; 1260 } 1261 1262 return DC_OK; 1263 } 1264 1265 struct pipe_ctx *find_idle_secondary_pipe( 1266 struct resource_context *res_ctx, 1267 const struct resource_pool *pool, 1268 const struct pipe_ctx *primary_pipe) 1269 { 1270 int i; 1271 struct pipe_ctx *secondary_pipe = NULL; 1272 1273 /* 1274 * We add a preferred pipe mapping to avoid the chance that 1275 * MPCCs already in use will need to be reassigned to other trees. 1276 * For example, if we went with the strict, assign backwards logic: 1277 * 1278 * (State 1) 1279 * Display A on, no surface, top pipe = 0 1280 * Display B on, no surface, top pipe = 1 1281 * 1282 * (State 2) 1283 * Display A on, no surface, top pipe = 0 1284 * Display B on, surface enable, top pipe = 1, bottom pipe = 5 1285 * 1286 * (State 3) 1287 * Display A on, surface enable, top pipe = 0, bottom pipe = 5 1288 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1289 * 1290 * The state 2->3 transition requires remapping MPCC 5 from display B 1291 * to display A. 1292 * 1293 * However, with the preferred pipe logic, state 2 would look like: 1294 * 1295 * (State 2) 1296 * Display A on, no surface, top pipe = 0 1297 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1298 * 1299 * This would then cause 2->3 to not require remapping any MPCCs. 1300 */ 1301 if (primary_pipe) { 1302 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 1303 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1304 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1305 secondary_pipe->pipe_idx = preferred_pipe_idx; 1306 } 1307 } 1308 1309 /* 1310 * search backwards for the second pipe to keep pipe 1311 * assignment more consistent 1312 */ 1313 if (!secondary_pipe) 1314 for (i = pool->pipe_count - 1; i >= 0; i--) { 1315 if (res_ctx->pipe_ctx[i].stream == NULL) { 1316 secondary_pipe = &res_ctx->pipe_ctx[i]; 1317 secondary_pipe->pipe_idx = i; 1318 break; 1319 } 1320 } 1321 1322 return secondary_pipe; 1323 } 1324 1325 struct pipe_ctx *resource_get_head_pipe_for_stream( 1326 struct resource_context *res_ctx, 1327 struct dc_stream_state *stream) 1328 { 1329 int i; 1330 1331 for (i = 0; i < MAX_PIPES; i++) { 1332 if (res_ctx->pipe_ctx[i].stream == stream 1333 && !res_ctx->pipe_ctx[i].top_pipe 1334 && !res_ctx->pipe_ctx[i].prev_odm_pipe) 1335 return &res_ctx->pipe_ctx[i]; 1336 } 1337 return NULL; 1338 } 1339 1340 static struct pipe_ctx *resource_get_tail_pipe( 1341 struct resource_context *res_ctx, 1342 struct pipe_ctx *head_pipe) 1343 { 1344 struct pipe_ctx *tail_pipe; 1345 1346 tail_pipe = head_pipe->bottom_pipe; 1347 1348 while (tail_pipe) { 1349 head_pipe = tail_pipe; 1350 tail_pipe = tail_pipe->bottom_pipe; 1351 } 1352 1353 return head_pipe; 1354 } 1355 1356 /* 1357 * A free_pipe for a stream is defined here as a pipe 1358 * that has no surface attached yet 1359 */ 1360 static struct pipe_ctx *acquire_free_pipe_for_head( 1361 struct dc_state *context, 1362 const struct resource_pool *pool, 1363 struct pipe_ctx *head_pipe) 1364 { 1365 int i; 1366 struct resource_context *res_ctx = &context->res_ctx; 1367 1368 if (!head_pipe->plane_state) 1369 return head_pipe; 1370 1371 /* Re-use pipe already acquired for this stream if available*/ 1372 for (i = pool->pipe_count - 1; i >= 0; i--) { 1373 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream && 1374 !res_ctx->pipe_ctx[i].plane_state) { 1375 return &res_ctx->pipe_ctx[i]; 1376 } 1377 } 1378 1379 /* 1380 * At this point we have no re-useable pipe for this stream and we need 1381 * to acquire an idle one to satisfy the request 1382 */ 1383 1384 if (!pool->funcs->acquire_idle_pipe_for_layer) 1385 return NULL; 1386 1387 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream); 1388 } 1389 1390 #if defined(CONFIG_DRM_AMD_DC_DCN) 1391 static int acquire_first_split_pipe( 1392 struct resource_context *res_ctx, 1393 const struct resource_pool *pool, 1394 struct dc_stream_state *stream) 1395 { 1396 int i; 1397 1398 for (i = 0; i < pool->pipe_count; i++) { 1399 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; 1400 1401 if (split_pipe->top_pipe && 1402 split_pipe->top_pipe->plane_state == split_pipe->plane_state) { 1403 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; 1404 if (split_pipe->bottom_pipe) 1405 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; 1406 1407 if (split_pipe->top_pipe->plane_state) 1408 resource_build_scaling_params(split_pipe->top_pipe); 1409 1410 memset(split_pipe, 0, sizeof(*split_pipe)); 1411 split_pipe->stream_res.tg = pool->timing_generators[i]; 1412 split_pipe->plane_res.hubp = pool->hubps[i]; 1413 split_pipe->plane_res.ipp = pool->ipps[i]; 1414 split_pipe->plane_res.dpp = pool->dpps[i]; 1415 split_pipe->stream_res.opp = pool->opps[i]; 1416 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; 1417 split_pipe->pipe_idx = i; 1418 1419 split_pipe->stream = stream; 1420 return i; 1421 } 1422 } 1423 return -1; 1424 } 1425 #endif 1426 1427 bool dc_add_plane_to_context( 1428 const struct dc *dc, 1429 struct dc_stream_state *stream, 1430 struct dc_plane_state *plane_state, 1431 struct dc_state *context) 1432 { 1433 int i; 1434 struct resource_pool *pool = dc->res_pool; 1435 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; 1436 struct dc_stream_status *stream_status = NULL; 1437 1438 for (i = 0; i < context->stream_count; i++) 1439 if (context->streams[i] == stream) { 1440 stream_status = &context->stream_status[i]; 1441 break; 1442 } 1443 if (stream_status == NULL) { 1444 dm_error("Existing stream not found; failed to attach surface!\n"); 1445 return false; 1446 } 1447 1448 1449 if (stream_status->plane_count == MAX_SURFACE_NUM) { 1450 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", 1451 plane_state, MAX_SURFACE_NUM); 1452 return false; 1453 } 1454 1455 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1456 1457 if (!head_pipe) { 1458 dm_error("Head pipe not found for stream_state %p !\n", stream); 1459 return false; 1460 } 1461 1462 /* retain new surface, but only once per stream */ 1463 dc_plane_state_retain(plane_state); 1464 1465 while (head_pipe) { 1466 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe); 1467 1468 #if defined(CONFIG_DRM_AMD_DC_DCN) 1469 if (!free_pipe) { 1470 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 1471 if (pipe_idx >= 0) 1472 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; 1473 } 1474 #endif 1475 if (!free_pipe) { 1476 dc_plane_state_release(plane_state); 1477 return false; 1478 } 1479 1480 free_pipe->plane_state = plane_state; 1481 1482 if (head_pipe != free_pipe) { 1483 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe); 1484 ASSERT(tail_pipe); 1485 free_pipe->stream_res.tg = tail_pipe->stream_res.tg; 1486 free_pipe->stream_res.abm = tail_pipe->stream_res.abm; 1487 free_pipe->stream_res.opp = tail_pipe->stream_res.opp; 1488 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; 1489 free_pipe->stream_res.audio = tail_pipe->stream_res.audio; 1490 free_pipe->clock_source = tail_pipe->clock_source; 1491 free_pipe->top_pipe = tail_pipe; 1492 tail_pipe->bottom_pipe = free_pipe; 1493 if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) { 1494 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe; 1495 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe; 1496 } 1497 if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) { 1498 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe; 1499 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe; 1500 } 1501 } 1502 head_pipe = head_pipe->next_odm_pipe; 1503 } 1504 /* assign new surfaces*/ 1505 stream_status->plane_states[stream_status->plane_count] = plane_state; 1506 1507 stream_status->plane_count++; 1508 1509 return true; 1510 } 1511 1512 bool dc_remove_plane_from_context( 1513 const struct dc *dc, 1514 struct dc_stream_state *stream, 1515 struct dc_plane_state *plane_state, 1516 struct dc_state *context) 1517 { 1518 int i; 1519 struct dc_stream_status *stream_status = NULL; 1520 struct resource_pool *pool = dc->res_pool; 1521 1522 for (i = 0; i < context->stream_count; i++) 1523 if (context->streams[i] == stream) { 1524 stream_status = &context->stream_status[i]; 1525 break; 1526 } 1527 1528 if (stream_status == NULL) { 1529 dm_error("Existing stream not found; failed to remove plane.\n"); 1530 return false; 1531 } 1532 1533 /* release pipe for plane*/ 1534 for (i = pool->pipe_count - 1; i >= 0; i--) { 1535 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1536 1537 if (pipe_ctx->plane_state == plane_state) { 1538 if (pipe_ctx->top_pipe) 1539 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1540 1541 /* Second condition is to avoid setting NULL to top pipe 1542 * of tail pipe making it look like head pipe in subsequent 1543 * deletes 1544 */ 1545 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) 1546 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1547 1548 /* 1549 * For head pipe detach surfaces from pipe for tail 1550 * pipe just zero it out 1551 */ 1552 if (!pipe_ctx->top_pipe) 1553 pipe_ctx->plane_state = NULL; 1554 else 1555 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1556 } 1557 } 1558 1559 1560 for (i = 0; i < stream_status->plane_count; i++) { 1561 if (stream_status->plane_states[i] == plane_state) { 1562 1563 dc_plane_state_release(stream_status->plane_states[i]); 1564 break; 1565 } 1566 } 1567 1568 if (i == stream_status->plane_count) { 1569 dm_error("Existing plane_state not found; failed to detach it!\n"); 1570 return false; 1571 } 1572 1573 stream_status->plane_count--; 1574 1575 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */ 1576 for (; i < stream_status->plane_count; i++) 1577 stream_status->plane_states[i] = stream_status->plane_states[i + 1]; 1578 1579 stream_status->plane_states[stream_status->plane_count] = NULL; 1580 1581 return true; 1582 } 1583 1584 bool dc_rem_all_planes_for_stream( 1585 const struct dc *dc, 1586 struct dc_stream_state *stream, 1587 struct dc_state *context) 1588 { 1589 int i, old_plane_count; 1590 struct dc_stream_status *stream_status = NULL; 1591 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; 1592 1593 for (i = 0; i < context->stream_count; i++) 1594 if (context->streams[i] == stream) { 1595 stream_status = &context->stream_status[i]; 1596 break; 1597 } 1598 1599 if (stream_status == NULL) { 1600 dm_error("Existing stream %p not found!\n", stream); 1601 return false; 1602 } 1603 1604 old_plane_count = stream_status->plane_count; 1605 1606 for (i = 0; i < old_plane_count; i++) 1607 del_planes[i] = stream_status->plane_states[i]; 1608 1609 for (i = 0; i < old_plane_count; i++) 1610 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) 1611 return false; 1612 1613 return true; 1614 } 1615 1616 static bool add_all_planes_for_stream( 1617 const struct dc *dc, 1618 struct dc_stream_state *stream, 1619 const struct dc_validation_set set[], 1620 int set_count, 1621 struct dc_state *context) 1622 { 1623 int i, j; 1624 1625 for (i = 0; i < set_count; i++) 1626 if (set[i].stream == stream) 1627 break; 1628 1629 if (i == set_count) { 1630 dm_error("Stream %p not found in set!\n", stream); 1631 return false; 1632 } 1633 1634 for (j = 0; j < set[i].plane_count; j++) 1635 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) 1636 return false; 1637 1638 return true; 1639 } 1640 1641 bool dc_add_all_planes_for_stream( 1642 const struct dc *dc, 1643 struct dc_stream_state *stream, 1644 struct dc_plane_state * const *plane_states, 1645 int plane_count, 1646 struct dc_state *context) 1647 { 1648 struct dc_validation_set set; 1649 int i; 1650 1651 set.stream = stream; 1652 set.plane_count = plane_count; 1653 1654 for (i = 0; i < plane_count; i++) 1655 set.plane_states[i] = plane_states[i]; 1656 1657 return add_all_planes_for_stream(dc, stream, &set, 1, context); 1658 } 1659 1660 static bool is_timing_changed(struct dc_stream_state *cur_stream, 1661 struct dc_stream_state *new_stream) 1662 { 1663 if (cur_stream == NULL) 1664 return true; 1665 1666 /* If sink pointer changed, it means this is a hotplug, we should do 1667 * full hw setting. 1668 */ 1669 if (cur_stream->sink != new_stream->sink) 1670 return true; 1671 1672 /* If output color space is changed, need to reprogram info frames */ 1673 if (cur_stream->output_color_space != new_stream->output_color_space) 1674 return true; 1675 1676 return memcmp( 1677 &cur_stream->timing, 1678 &new_stream->timing, 1679 sizeof(struct dc_crtc_timing)) != 0; 1680 } 1681 1682 static bool are_stream_backends_same( 1683 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) 1684 { 1685 if (stream_a == stream_b) 1686 return true; 1687 1688 if (stream_a == NULL || stream_b == NULL) 1689 return false; 1690 1691 if (is_timing_changed(stream_a, stream_b)) 1692 return false; 1693 1694 if (stream_a->dpms_off != stream_b->dpms_off) 1695 return false; 1696 1697 return true; 1698 } 1699 1700 /* 1701 * dc_is_stream_unchanged() - Compare two stream states for equivalence. 1702 * 1703 * Checks if there a difference between the two states 1704 * that would require a mode change. 1705 * 1706 * Does not compare cursor position or attributes. 1707 */ 1708 bool dc_is_stream_unchanged( 1709 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1710 { 1711 1712 if (!are_stream_backends_same(old_stream, stream)) 1713 return false; 1714 1715 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param) 1716 return false; 1717 1718 return true; 1719 } 1720 1721 /* 1722 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams. 1723 */ 1724 bool dc_is_stream_scaling_unchanged( 1725 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1726 { 1727 if (old_stream == stream) 1728 return true; 1729 1730 if (old_stream == NULL || stream == NULL) 1731 return false; 1732 1733 if (memcmp(&old_stream->src, 1734 &stream->src, 1735 sizeof(struct rect)) != 0) 1736 return false; 1737 1738 if (memcmp(&old_stream->dst, 1739 &stream->dst, 1740 sizeof(struct rect)) != 0) 1741 return false; 1742 1743 return true; 1744 } 1745 1746 static void update_stream_engine_usage( 1747 struct resource_context *res_ctx, 1748 const struct resource_pool *pool, 1749 struct stream_encoder *stream_enc, 1750 bool acquired) 1751 { 1752 int i; 1753 1754 for (i = 0; i < pool->stream_enc_count; i++) { 1755 if (pool->stream_enc[i] == stream_enc) 1756 res_ctx->is_stream_enc_acquired[i] = acquired; 1757 } 1758 } 1759 1760 /* TODO: release audio object */ 1761 void update_audio_usage( 1762 struct resource_context *res_ctx, 1763 const struct resource_pool *pool, 1764 struct audio *audio, 1765 bool acquired) 1766 { 1767 int i; 1768 for (i = 0; i < pool->audio_count; i++) { 1769 if (pool->audios[i] == audio) 1770 res_ctx->is_audio_acquired[i] = acquired; 1771 } 1772 } 1773 1774 static int acquire_first_free_pipe( 1775 struct resource_context *res_ctx, 1776 const struct resource_pool *pool, 1777 struct dc_stream_state *stream) 1778 { 1779 int i; 1780 1781 for (i = 0; i < pool->pipe_count; i++) { 1782 if (!res_ctx->pipe_ctx[i].stream) { 1783 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 1784 1785 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 1786 pipe_ctx->plane_res.mi = pool->mis[i]; 1787 pipe_ctx->plane_res.hubp = pool->hubps[i]; 1788 pipe_ctx->plane_res.ipp = pool->ipps[i]; 1789 pipe_ctx->plane_res.xfm = pool->transforms[i]; 1790 pipe_ctx->plane_res.dpp = pool->dpps[i]; 1791 pipe_ctx->stream_res.opp = pool->opps[i]; 1792 if (pool->dpps[i]) 1793 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; 1794 pipe_ctx->pipe_idx = i; 1795 1796 1797 pipe_ctx->stream = stream; 1798 return i; 1799 } 1800 } 1801 return -1; 1802 } 1803 1804 static struct audio *find_first_free_audio( 1805 struct resource_context *res_ctx, 1806 const struct resource_pool *pool, 1807 enum engine_id id, 1808 enum dce_version dc_version) 1809 { 1810 int i, available_audio_count; 1811 1812 available_audio_count = pool->audio_count; 1813 1814 for (i = 0; i < available_audio_count; i++) { 1815 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { 1816 /*we have enough audio endpoint, find the matching inst*/ 1817 if (id != i) 1818 continue; 1819 return pool->audios[i]; 1820 } 1821 } 1822 1823 /* use engine id to find free audio */ 1824 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) { 1825 return pool->audios[id]; 1826 } 1827 /*not found the matching one, first come first serve*/ 1828 for (i = 0; i < available_audio_count; i++) { 1829 if (res_ctx->is_audio_acquired[i] == false) { 1830 return pool->audios[i]; 1831 } 1832 } 1833 return 0; 1834 } 1835 1836 /* 1837 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state. 1838 */ 1839 enum dc_status dc_add_stream_to_ctx( 1840 struct dc *dc, 1841 struct dc_state *new_ctx, 1842 struct dc_stream_state *stream) 1843 { 1844 enum dc_status res; 1845 DC_LOGGER_INIT(dc->ctx->logger); 1846 1847 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) { 1848 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream); 1849 return DC_ERROR_UNEXPECTED; 1850 } 1851 1852 new_ctx->streams[new_ctx->stream_count] = stream; 1853 dc_stream_retain(stream); 1854 new_ctx->stream_count++; 1855 1856 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); 1857 if (res != DC_OK) 1858 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res); 1859 1860 return res; 1861 } 1862 1863 /* 1864 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state. 1865 */ 1866 enum dc_status dc_remove_stream_from_ctx( 1867 struct dc *dc, 1868 struct dc_state *new_ctx, 1869 struct dc_stream_state *stream) 1870 { 1871 int i; 1872 struct dc_context *dc_ctx = dc->ctx; 1873 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream); 1874 struct pipe_ctx *odm_pipe; 1875 1876 if (!del_pipe) { 1877 DC_ERROR("Pipe not found for stream %p !\n", stream); 1878 return DC_ERROR_UNEXPECTED; 1879 } 1880 1881 odm_pipe = del_pipe->next_odm_pipe; 1882 1883 /* Release primary pipe */ 1884 ASSERT(del_pipe->stream_res.stream_enc); 1885 update_stream_engine_usage( 1886 &new_ctx->res_ctx, 1887 dc->res_pool, 1888 del_pipe->stream_res.stream_enc, 1889 false); 1890 1891 if (del_pipe->stream_res.audio) 1892 update_audio_usage( 1893 &new_ctx->res_ctx, 1894 dc->res_pool, 1895 del_pipe->stream_res.audio, 1896 false); 1897 1898 resource_unreference_clock_source(&new_ctx->res_ctx, 1899 dc->res_pool, 1900 del_pipe->clock_source); 1901 1902 if (dc->res_pool->funcs->remove_stream_from_ctx) 1903 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream); 1904 1905 while (odm_pipe) { 1906 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 1907 1908 memset(odm_pipe, 0, sizeof(*odm_pipe)); 1909 odm_pipe = next_odm_pipe; 1910 } 1911 memset(del_pipe, 0, sizeof(*del_pipe)); 1912 1913 for (i = 0; i < new_ctx->stream_count; i++) 1914 if (new_ctx->streams[i] == stream) 1915 break; 1916 1917 if (new_ctx->streams[i] != stream) { 1918 DC_ERROR("Context doesn't have stream %p !\n", stream); 1919 return DC_ERROR_UNEXPECTED; 1920 } 1921 1922 dc_stream_release(new_ctx->streams[i]); 1923 new_ctx->stream_count--; 1924 1925 /* Trim back arrays */ 1926 for (; i < new_ctx->stream_count; i++) { 1927 new_ctx->streams[i] = new_ctx->streams[i + 1]; 1928 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; 1929 } 1930 1931 new_ctx->streams[new_ctx->stream_count] = NULL; 1932 memset( 1933 &new_ctx->stream_status[new_ctx->stream_count], 1934 0, 1935 sizeof(new_ctx->stream_status[0])); 1936 1937 return DC_OK; 1938 } 1939 1940 static struct dc_stream_state *find_pll_sharable_stream( 1941 struct dc_stream_state *stream_needs_pll, 1942 struct dc_state *context) 1943 { 1944 int i; 1945 1946 for (i = 0; i < context->stream_count; i++) { 1947 struct dc_stream_state *stream_has_pll = context->streams[i]; 1948 1949 /* We are looking for non dp, non virtual stream */ 1950 if (resource_are_streams_timing_synchronizable( 1951 stream_needs_pll, stream_has_pll) 1952 && !dc_is_dp_signal(stream_has_pll->signal) 1953 && stream_has_pll->link->connector_signal 1954 != SIGNAL_TYPE_VIRTUAL) 1955 return stream_has_pll; 1956 1957 } 1958 1959 return NULL; 1960 } 1961 1962 static int get_norm_pix_clk(const struct dc_crtc_timing *timing) 1963 { 1964 uint32_t pix_clk = timing->pix_clk_100hz; 1965 uint32_t normalized_pix_clk = pix_clk; 1966 1967 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 1968 pix_clk /= 2; 1969 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 1970 switch (timing->display_color_depth) { 1971 case COLOR_DEPTH_666: 1972 case COLOR_DEPTH_888: 1973 normalized_pix_clk = pix_clk; 1974 break; 1975 case COLOR_DEPTH_101010: 1976 normalized_pix_clk = (pix_clk * 30) / 24; 1977 break; 1978 case COLOR_DEPTH_121212: 1979 normalized_pix_clk = (pix_clk * 36) / 24; 1980 break; 1981 case COLOR_DEPTH_161616: 1982 normalized_pix_clk = (pix_clk * 48) / 24; 1983 break; 1984 default: 1985 ASSERT(0); 1986 break; 1987 } 1988 } 1989 return normalized_pix_clk; 1990 } 1991 1992 static void calculate_phy_pix_clks(struct dc_stream_state *stream) 1993 { 1994 /* update actual pixel clock on all streams */ 1995 if (dc_is_hdmi_signal(stream->signal)) 1996 stream->phy_pix_clk = get_norm_pix_clk( 1997 &stream->timing) / 10; 1998 else 1999 stream->phy_pix_clk = 2000 stream->timing.pix_clk_100hz / 10; 2001 2002 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 2003 stream->phy_pix_clk *= 2; 2004 } 2005 2006 static int acquire_resource_from_hw_enabled_state( 2007 struct resource_context *res_ctx, 2008 const struct resource_pool *pool, 2009 struct dc_stream_state *stream) 2010 { 2011 struct dc_link *link = stream->link; 2012 unsigned int i, inst, tg_inst = 0; 2013 2014 /* Check for enabled DIG to identify enabled display */ 2015 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) 2016 return -1; 2017 2018 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); 2019 2020 if (inst == ENGINE_ID_UNKNOWN) 2021 return -1; 2022 2023 for (i = 0; i < pool->stream_enc_count; i++) { 2024 if (pool->stream_enc[i]->id == inst) { 2025 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( 2026 pool->stream_enc[i]); 2027 break; 2028 } 2029 } 2030 2031 // tg_inst not found 2032 if (i == pool->stream_enc_count) 2033 return -1; 2034 2035 if (tg_inst >= pool->timing_generator_count) 2036 return -1; 2037 2038 if (!res_ctx->pipe_ctx[tg_inst].stream) { 2039 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; 2040 2041 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 2042 pipe_ctx->plane_res.mi = pool->mis[tg_inst]; 2043 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; 2044 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; 2045 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; 2046 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst]; 2047 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; 2048 2049 if (pool->dpps[tg_inst]) { 2050 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; 2051 2052 // Read DPP->MPCC->OPP Pipe from HW State 2053 if (pool->mpc->funcs->read_mpcc_state) { 2054 struct mpcc_state s = {0}; 2055 2056 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); 2057 2058 if (s.dpp_id < MAX_MPCC) 2059 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id; 2060 2061 if (s.bot_mpcc_id < MAX_MPCC) 2062 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = 2063 &pool->mpc->mpcc_array[s.bot_mpcc_id]; 2064 2065 if (s.opp_id < MAX_OPP) 2066 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; 2067 } 2068 } 2069 pipe_ctx->pipe_idx = tg_inst; 2070 2071 pipe_ctx->stream = stream; 2072 return tg_inst; 2073 } 2074 2075 return -1; 2076 } 2077 2078 static void mark_seamless_boot_stream( 2079 const struct dc *dc, 2080 struct dc_stream_state *stream) 2081 { 2082 struct dc_bios *dcb = dc->ctx->dc_bios; 2083 2084 /* TODO: Check Linux */ 2085 if (dc->config.allow_seamless_boot_optimization && 2086 !dcb->funcs->is_accelerated_mode(dcb)) { 2087 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing)) 2088 stream->apply_seamless_boot_optimization = true; 2089 } 2090 } 2091 2092 enum dc_status resource_map_pool_resources( 2093 const struct dc *dc, 2094 struct dc_state *context, 2095 struct dc_stream_state *stream) 2096 { 2097 const struct resource_pool *pool = dc->res_pool; 2098 int i; 2099 struct dc_context *dc_ctx = dc->ctx; 2100 struct pipe_ctx *pipe_ctx = NULL; 2101 int pipe_idx = -1; 2102 2103 calculate_phy_pix_clks(stream); 2104 2105 mark_seamless_boot_stream(dc, stream); 2106 2107 if (stream->apply_seamless_boot_optimization) { 2108 pipe_idx = acquire_resource_from_hw_enabled_state( 2109 &context->res_ctx, 2110 pool, 2111 stream); 2112 if (pipe_idx < 0) 2113 /* hw resource was assigned to other stream */ 2114 stream->apply_seamless_boot_optimization = false; 2115 } 2116 2117 if (pipe_idx < 0) 2118 /* acquire new resources */ 2119 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); 2120 2121 #ifdef CONFIG_DRM_AMD_DC_DCN 2122 if (pipe_idx < 0) 2123 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 2124 #endif 2125 2126 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL) 2127 return DC_NO_CONTROLLER_RESOURCE; 2128 2129 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2130 2131 pipe_ctx->stream_res.stream_enc = 2132 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link( 2133 &context->res_ctx, pool, stream); 2134 2135 if (!pipe_ctx->stream_res.stream_enc) 2136 return DC_NO_STREAM_ENC_RESOURCE; 2137 2138 update_stream_engine_usage( 2139 &context->res_ctx, pool, 2140 pipe_ctx->stream_res.stream_enc, 2141 true); 2142 2143 /* TODO: Add check if ASIC support and EDID audio */ 2144 if (!stream->converter_disable_audio && 2145 dc_is_audio_capable_signal(pipe_ctx->stream->signal) && 2146 stream->audio_info.mode_count && stream->audio_info.flags.all) { 2147 pipe_ctx->stream_res.audio = find_first_free_audio( 2148 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version); 2149 2150 /* 2151 * Audio assigned in order first come first get. 2152 * There are asics which has number of audio 2153 * resources less then number of pipes 2154 */ 2155 if (pipe_ctx->stream_res.audio) 2156 update_audio_usage(&context->res_ctx, pool, 2157 pipe_ctx->stream_res.audio, true); 2158 } 2159 2160 /* Add ABM to the resource if on EDP */ 2161 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) { 2162 #if defined(CONFIG_DRM_AMD_DC_DCN) 2163 if (pool->abm) 2164 pipe_ctx->stream_res.abm = pool->abm; 2165 else 2166 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst]; 2167 #else 2168 pipe_ctx->stream_res.abm = pool->abm; 2169 #endif 2170 } 2171 2172 for (i = 0; i < context->stream_count; i++) 2173 if (context->streams[i] == stream) { 2174 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; 2175 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst; 2176 context->stream_status[i].audio_inst = 2177 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; 2178 2179 return DC_OK; 2180 } 2181 2182 DC_ERROR("Stream %p not found in new ctx!\n", stream); 2183 return DC_ERROR_UNEXPECTED; 2184 } 2185 2186 /** 2187 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state 2188 * Is a shallow copy. Increments refcounts on existing streams and planes. 2189 * @dc: copy out of dc->current_state 2190 * @dst_ctx: copy into this 2191 */ 2192 void dc_resource_state_copy_construct_current( 2193 const struct dc *dc, 2194 struct dc_state *dst_ctx) 2195 { 2196 dc_resource_state_copy_construct(dc->current_state, dst_ctx); 2197 } 2198 2199 2200 void dc_resource_state_construct( 2201 const struct dc *dc, 2202 struct dc_state *dst_ctx) 2203 { 2204 dst_ctx->clk_mgr = dc->clk_mgr; 2205 } 2206 2207 2208 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) 2209 { 2210 return dc->res_pool->res_cap->num_dsc > 0; 2211 } 2212 2213 2214 /** 2215 * dc_validate_global_state() - Determine if HW can support a given state 2216 * Checks HW resource availability and bandwidth requirement. 2217 * @dc: dc struct for this driver 2218 * @new_ctx: state to be validated 2219 * @fast_validate: set to true if only yes/no to support matters 2220 * 2221 * Return: DC_OK if the result can be programmed. Otherwise, an error code. 2222 */ 2223 enum dc_status dc_validate_global_state( 2224 struct dc *dc, 2225 struct dc_state *new_ctx, 2226 bool fast_validate) 2227 { 2228 enum dc_status result = DC_ERROR_UNEXPECTED; 2229 int i, j; 2230 2231 if (!new_ctx) 2232 return DC_ERROR_UNEXPECTED; 2233 2234 if (dc->res_pool->funcs->validate_global) { 2235 result = dc->res_pool->funcs->validate_global(dc, new_ctx); 2236 if (result != DC_OK) 2237 return result; 2238 } 2239 2240 for (i = 0; i < new_ctx->stream_count; i++) { 2241 struct dc_stream_state *stream = new_ctx->streams[i]; 2242 2243 for (j = 0; j < dc->res_pool->pipe_count; j++) { 2244 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; 2245 2246 if (pipe_ctx->stream != stream) 2247 continue; 2248 2249 if (dc->res_pool->funcs->patch_unknown_plane_state && 2250 pipe_ctx->plane_state && 2251 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { 2252 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); 2253 if (result != DC_OK) 2254 return result; 2255 } 2256 2257 /* Switch to dp clock source only if there is 2258 * no non dp stream that shares the same timing 2259 * with the dp stream. 2260 */ 2261 if (dc_is_dp_signal(pipe_ctx->stream->signal) && 2262 !find_pll_sharable_stream(stream, new_ctx)) { 2263 2264 resource_unreference_clock_source( 2265 &new_ctx->res_ctx, 2266 dc->res_pool, 2267 pipe_ctx->clock_source); 2268 2269 pipe_ctx->clock_source = dc->res_pool->dp_clock_source; 2270 resource_reference_clock_source( 2271 &new_ctx->res_ctx, 2272 dc->res_pool, 2273 pipe_ctx->clock_source); 2274 } 2275 } 2276 } 2277 2278 result = resource_build_scaling_params_for_context(dc, new_ctx); 2279 2280 if (result == DC_OK) 2281 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate)) 2282 result = DC_FAIL_BANDWIDTH_VALIDATE; 2283 2284 return result; 2285 } 2286 2287 static void patch_gamut_packet_checksum( 2288 struct dc_info_packet *gamut_packet) 2289 { 2290 /* For gamut we recalc checksum */ 2291 if (gamut_packet->valid) { 2292 uint8_t chk_sum = 0; 2293 uint8_t *ptr; 2294 uint8_t i; 2295 2296 /*start of the Gamut data. */ 2297 ptr = &gamut_packet->sb[3]; 2298 2299 for (i = 0; i <= gamut_packet->sb[1]; i++) 2300 chk_sum += ptr[i]; 2301 2302 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); 2303 } 2304 } 2305 2306 static void set_avi_info_frame( 2307 struct dc_info_packet *info_packet, 2308 struct pipe_ctx *pipe_ctx) 2309 { 2310 struct dc_stream_state *stream = pipe_ctx->stream; 2311 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; 2312 uint32_t pixel_encoding = 0; 2313 enum scanning_type scan_type = SCANNING_TYPE_NODATA; 2314 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA; 2315 bool itc = false; 2316 uint8_t itc_value = 0; 2317 uint8_t cn0_cn1 = 0; 2318 unsigned int cn0_cn1_value = 0; 2319 uint8_t *check_sum = NULL; 2320 uint8_t byte_index = 0; 2321 union hdmi_info_packet hdmi_info; 2322 union display_content_support support = {0}; 2323 unsigned int vic = pipe_ctx->stream->timing.vic; 2324 enum dc_timing_3d_format format; 2325 2326 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet)); 2327 2328 color_space = pipe_ctx->stream->output_color_space; 2329 if (color_space == COLOR_SPACE_UNKNOWN) 2330 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? 2331 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; 2332 2333 /* Initialize header */ 2334 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI; 2335 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall 2336 * not be used in HDMI 2.0 (Section 10.1) */ 2337 hdmi_info.bits.header.version = 2; 2338 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE; 2339 2340 /* 2341 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built 2342 * according to HDMI 2.0 spec (Section 10.1) 2343 */ 2344 2345 switch (stream->timing.pixel_encoding) { 2346 case PIXEL_ENCODING_YCBCR422: 2347 pixel_encoding = 1; 2348 break; 2349 2350 case PIXEL_ENCODING_YCBCR444: 2351 pixel_encoding = 2; 2352 break; 2353 case PIXEL_ENCODING_YCBCR420: 2354 pixel_encoding = 3; 2355 break; 2356 2357 case PIXEL_ENCODING_RGB: 2358 default: 2359 pixel_encoding = 0; 2360 } 2361 2362 /* Y0_Y1_Y2 : The pixel encoding */ 2363 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ 2364 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding; 2365 2366 /* A0 = 1 Active Format Information valid */ 2367 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID; 2368 2369 /* B0, B1 = 3; Bar info data is valid */ 2370 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID; 2371 2372 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM; 2373 2374 /* S0, S1 : Underscan / Overscan */ 2375 /* TODO: un-hardcode scan type */ 2376 scan_type = SCANNING_TYPE_UNDERSCAN; 2377 hdmi_info.bits.S0_S1 = scan_type; 2378 2379 /* C0, C1 : Colorimetry */ 2380 if (color_space == COLOR_SPACE_YCBCR709 || 2381 color_space == COLOR_SPACE_YCBCR709_LIMITED) 2382 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709; 2383 else if (color_space == COLOR_SPACE_YCBCR601 || 2384 color_space == COLOR_SPACE_YCBCR601_LIMITED) 2385 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601; 2386 else { 2387 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA; 2388 } 2389 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE || 2390 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE || 2391 color_space == COLOR_SPACE_2020_YCBCR) { 2392 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR; 2393 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 2394 } else if (color_space == COLOR_SPACE_ADOBERGB) { 2395 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB; 2396 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 2397 } 2398 2399 /* TODO: un-hardcode aspect ratio */ 2400 aspect = stream->timing.aspect_ratio; 2401 2402 switch (aspect) { 2403 case ASPECT_RATIO_4_3: 2404 case ASPECT_RATIO_16_9: 2405 hdmi_info.bits.M0_M1 = aspect; 2406 break; 2407 2408 case ASPECT_RATIO_NO_DATA: 2409 case ASPECT_RATIO_64_27: 2410 case ASPECT_RATIO_256_135: 2411 default: 2412 hdmi_info.bits.M0_M1 = 0; 2413 } 2414 2415 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */ 2416 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE; 2417 2418 /* TODO: un-hardcode cn0_cn1 and itc */ 2419 2420 cn0_cn1 = 0; 2421 cn0_cn1_value = 0; 2422 2423 itc = true; 2424 itc_value = 1; 2425 2426 support = stream->content_support; 2427 2428 if (itc) { 2429 if (!support.bits.valid_content_type) { 2430 cn0_cn1_value = 0; 2431 } else { 2432 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) { 2433 if (support.bits.graphics_content == 1) { 2434 cn0_cn1_value = 0; 2435 } 2436 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) { 2437 if (support.bits.photo_content == 1) { 2438 cn0_cn1_value = 1; 2439 } else { 2440 cn0_cn1_value = 0; 2441 itc_value = 0; 2442 } 2443 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) { 2444 if (support.bits.cinema_content == 1) { 2445 cn0_cn1_value = 2; 2446 } else { 2447 cn0_cn1_value = 0; 2448 itc_value = 0; 2449 } 2450 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) { 2451 if (support.bits.game_content == 1) { 2452 cn0_cn1_value = 3; 2453 } else { 2454 cn0_cn1_value = 0; 2455 itc_value = 0; 2456 } 2457 } 2458 } 2459 hdmi_info.bits.CN0_CN1 = cn0_cn1_value; 2460 hdmi_info.bits.ITC = itc_value; 2461 } 2462 2463 /* TODO : We should handle YCC quantization */ 2464 /* but we do not have matrix calculation */ 2465 if (stream->qs_bit == 1 && 2466 stream->qy_bit == 1) { 2467 if (color_space == COLOR_SPACE_SRGB || 2468 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) { 2469 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; 2470 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2471 } else if (color_space == COLOR_SPACE_SRGB_LIMITED || 2472 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) { 2473 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE; 2474 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2475 } else { 2476 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2477 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2478 } 2479 } else { 2480 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2481 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2482 } 2483 2484 ///VIC 2485 format = stream->timing.timing_3d_format; 2486 /*todo, add 3DStereo support*/ 2487 if (format != TIMING_3D_FORMAT_NONE) { 2488 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled 2489 switch (pipe_ctx->stream->timing.hdmi_vic) { 2490 case 1: 2491 vic = 95; 2492 break; 2493 case 2: 2494 vic = 94; 2495 break; 2496 case 3: 2497 vic = 93; 2498 break; 2499 case 4: 2500 vic = 98; 2501 break; 2502 default: 2503 break; 2504 } 2505 } 2506 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/ 2507 hdmi_info.bits.VIC0_VIC7 = vic; 2508 if (vic >= 128) 2509 hdmi_info.bits.header.version = 3; 2510 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1), 2511 * the Source shall use 20 AVI InfoFrame Version 4 2512 */ 2513 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED && 2514 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) { 2515 hdmi_info.bits.header.version = 4; 2516 hdmi_info.bits.header.length = 14; 2517 } 2518 2519 /* pixel repetition 2520 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel 2521 * repetition start from 1 */ 2522 hdmi_info.bits.PR0_PR3 = 0; 2523 2524 /* Bar Info 2525 * barTop: Line Number of End of Top Bar. 2526 * barBottom: Line Number of Start of Bottom Bar. 2527 * barLeft: Pixel Number of End of Left Bar. 2528 * barRight: Pixel Number of Start of Right Bar. */ 2529 hdmi_info.bits.bar_top = stream->timing.v_border_top; 2530 hdmi_info.bits.bar_bottom = (stream->timing.v_total 2531 - stream->timing.v_border_bottom + 1); 2532 hdmi_info.bits.bar_left = stream->timing.h_border_left; 2533 hdmi_info.bits.bar_right = (stream->timing.h_total 2534 - stream->timing.h_border_right + 1); 2535 2536 /* Additional Colorimetry Extension 2537 * Used in conduction with C0-C1 and EC0-EC2 2538 * 0 = DCI-P3 RGB (D65) 2539 * 1 = DCI-P3 RGB (theater) 2540 */ 2541 hdmi_info.bits.ACE0_ACE3 = 0; 2542 2543 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ 2544 check_sum = &hdmi_info.packet_raw_data.sb[0]; 2545 2546 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version; 2547 2548 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++) 2549 *check_sum += hdmi_info.packet_raw_data.sb[byte_index]; 2550 2551 /* one byte complement */ 2552 *check_sum = (uint8_t) (0x100 - *check_sum); 2553 2554 /* Store in hw_path_mode */ 2555 info_packet->hb0 = hdmi_info.packet_raw_data.hb0; 2556 info_packet->hb1 = hdmi_info.packet_raw_data.hb1; 2557 info_packet->hb2 = hdmi_info.packet_raw_data.hb2; 2558 2559 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++) 2560 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index]; 2561 2562 info_packet->valid = true; 2563 } 2564 2565 static void set_vendor_info_packet( 2566 struct dc_info_packet *info_packet, 2567 struct dc_stream_state *stream) 2568 { 2569 /* SPD info packet for FreeSync */ 2570 2571 /* Check if Freesync is supported. Return if false. If true, 2572 * set the corresponding bit in the info packet 2573 */ 2574 if (!stream->vsp_infopacket.valid) 2575 return; 2576 2577 *info_packet = stream->vsp_infopacket; 2578 } 2579 2580 static void set_spd_info_packet( 2581 struct dc_info_packet *info_packet, 2582 struct dc_stream_state *stream) 2583 { 2584 /* SPD info packet for FreeSync */ 2585 2586 /* Check if Freesync is supported. Return if false. If true, 2587 * set the corresponding bit in the info packet 2588 */ 2589 if (!stream->vrr_infopacket.valid) 2590 return; 2591 2592 *info_packet = stream->vrr_infopacket; 2593 } 2594 2595 static void set_hdr_static_info_packet( 2596 struct dc_info_packet *info_packet, 2597 struct dc_stream_state *stream) 2598 { 2599 /* HDR Static Metadata info packet for HDR10 */ 2600 2601 if (!stream->hdr_static_metadata.valid || 2602 stream->use_dynamic_meta) 2603 return; 2604 2605 *info_packet = stream->hdr_static_metadata; 2606 } 2607 2608 static void set_vsc_info_packet( 2609 struct dc_info_packet *info_packet, 2610 struct dc_stream_state *stream) 2611 { 2612 if (!stream->vsc_infopacket.valid) 2613 return; 2614 2615 *info_packet = stream->vsc_infopacket; 2616 } 2617 2618 void dc_resource_state_destruct(struct dc_state *context) 2619 { 2620 int i, j; 2621 2622 for (i = 0; i < context->stream_count; i++) { 2623 for (j = 0; j < context->stream_status[i].plane_count; j++) 2624 dc_plane_state_release( 2625 context->stream_status[i].plane_states[j]); 2626 2627 context->stream_status[i].plane_count = 0; 2628 dc_stream_release(context->streams[i]); 2629 context->streams[i] = NULL; 2630 } 2631 } 2632 2633 void dc_resource_state_copy_construct( 2634 const struct dc_state *src_ctx, 2635 struct dc_state *dst_ctx) 2636 { 2637 int i, j; 2638 struct kref refcount = dst_ctx->refcount; 2639 2640 *dst_ctx = *src_ctx; 2641 2642 for (i = 0; i < MAX_PIPES; i++) { 2643 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; 2644 2645 if (cur_pipe->top_pipe) 2646 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; 2647 2648 if (cur_pipe->bottom_pipe) 2649 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; 2650 2651 if (cur_pipe->next_odm_pipe) 2652 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; 2653 2654 if (cur_pipe->prev_odm_pipe) 2655 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; 2656 } 2657 2658 for (i = 0; i < dst_ctx->stream_count; i++) { 2659 dc_stream_retain(dst_ctx->streams[i]); 2660 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) 2661 dc_plane_state_retain( 2662 dst_ctx->stream_status[i].plane_states[j]); 2663 } 2664 2665 /* context refcount should not be overridden */ 2666 dst_ctx->refcount = refcount; 2667 2668 } 2669 2670 struct clock_source *dc_resource_find_first_free_pll( 2671 struct resource_context *res_ctx, 2672 const struct resource_pool *pool) 2673 { 2674 int i; 2675 2676 for (i = 0; i < pool->clk_src_count; ++i) { 2677 if (res_ctx->clock_source_ref_count[i] == 0) 2678 return pool->clock_sources[i]; 2679 } 2680 2681 return NULL; 2682 } 2683 2684 void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 2685 { 2686 enum signal_type signal = SIGNAL_TYPE_NONE; 2687 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; 2688 2689 /* default all packets to invalid */ 2690 info->avi.valid = false; 2691 info->gamut.valid = false; 2692 info->vendor.valid = false; 2693 info->spd.valid = false; 2694 info->hdrsmd.valid = false; 2695 info->vsc.valid = false; 2696 2697 signal = pipe_ctx->stream->signal; 2698 2699 /* HDMi and DP have different info packets*/ 2700 if (dc_is_hdmi_signal(signal)) { 2701 set_avi_info_frame(&info->avi, pipe_ctx); 2702 2703 set_vendor_info_packet(&info->vendor, pipe_ctx->stream); 2704 2705 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2706 2707 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 2708 2709 } else if (dc_is_dp_signal(signal)) { 2710 set_vsc_info_packet(&info->vsc, pipe_ctx->stream); 2711 2712 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2713 2714 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 2715 } 2716 2717 patch_gamut_packet_checksum(&info->gamut); 2718 } 2719 2720 enum dc_status resource_map_clock_resources( 2721 const struct dc *dc, 2722 struct dc_state *context, 2723 struct dc_stream_state *stream) 2724 { 2725 /* acquire new resources */ 2726 const struct resource_pool *pool = dc->res_pool; 2727 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 2728 &context->res_ctx, stream); 2729 2730 if (!pipe_ctx) 2731 return DC_ERROR_UNEXPECTED; 2732 2733 if (dc_is_dp_signal(pipe_ctx->stream->signal) 2734 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 2735 pipe_ctx->clock_source = pool->dp_clock_source; 2736 else { 2737 pipe_ctx->clock_source = NULL; 2738 2739 if (!dc->config.disable_disp_pll_sharing) 2740 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing( 2741 &context->res_ctx, 2742 pipe_ctx); 2743 2744 if (pipe_ctx->clock_source == NULL) 2745 pipe_ctx->clock_source = 2746 dc_resource_find_first_free_pll( 2747 &context->res_ctx, 2748 pool); 2749 } 2750 2751 if (pipe_ctx->clock_source == NULL) 2752 return DC_NO_CLOCK_SOURCE_RESOURCE; 2753 2754 resource_reference_clock_source( 2755 &context->res_ctx, pool, 2756 pipe_ctx->clock_source); 2757 2758 return DC_OK; 2759 } 2760 2761 /* 2762 * Note: We need to disable output if clock sources change, 2763 * since bios does optimization and doesn't apply if changing 2764 * PHY when not already disabled. 2765 */ 2766 bool pipe_need_reprogram( 2767 struct pipe_ctx *pipe_ctx_old, 2768 struct pipe_ctx *pipe_ctx) 2769 { 2770 if (!pipe_ctx_old->stream) 2771 return false; 2772 2773 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) 2774 return true; 2775 2776 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) 2777 return true; 2778 2779 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) 2780 return true; 2781 2782 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source 2783 && pipe_ctx_old->stream != pipe_ctx->stream) 2784 return true; 2785 2786 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) 2787 return true; 2788 2789 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) 2790 return true; 2791 2792 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off) 2793 return true; 2794 2795 if (false == pipe_ctx_old->stream->link->link_state_valid && 2796 false == pipe_ctx_old->stream->dpms_off) 2797 return true; 2798 2799 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) 2800 return true; 2801 2802 return false; 2803 } 2804 2805 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 2806 struct bit_depth_reduction_params *fmt_bit_depth) 2807 { 2808 enum dc_dither_option option = stream->dither_option; 2809 enum dc_pixel_encoding pixel_encoding = 2810 stream->timing.pixel_encoding; 2811 2812 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); 2813 2814 if (option == DITHER_OPTION_DEFAULT) { 2815 switch (stream->timing.display_color_depth) { 2816 case COLOR_DEPTH_666: 2817 option = DITHER_OPTION_SPATIAL6; 2818 break; 2819 case COLOR_DEPTH_888: 2820 option = DITHER_OPTION_SPATIAL8; 2821 break; 2822 case COLOR_DEPTH_101010: 2823 option = DITHER_OPTION_SPATIAL10; 2824 break; 2825 default: 2826 option = DITHER_OPTION_DISABLE; 2827 } 2828 } 2829 2830 if (option == DITHER_OPTION_DISABLE) 2831 return; 2832 2833 if (option == DITHER_OPTION_TRUN6) { 2834 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2835 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; 2836 } else if (option == DITHER_OPTION_TRUN8 || 2837 option == DITHER_OPTION_TRUN8_SPATIAL6 || 2838 option == DITHER_OPTION_TRUN8_FM6) { 2839 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2840 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; 2841 } else if (option == DITHER_OPTION_TRUN10 || 2842 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2843 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2844 option == DITHER_OPTION_TRUN10_FM8 || 2845 option == DITHER_OPTION_TRUN10_FM6 || 2846 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2847 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2848 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2849 } 2850 2851 /* special case - Formatter can only reduce by 4 bits at most. 2852 * When reducing from 12 to 6 bits, 2853 * HW recommends we use trunc with round mode 2854 * (if we did nothing, trunc to 10 bits would be used) 2855 * note that any 12->10 bit reduction is ignored prior to DCE8, 2856 * as the input was 10 bits. 2857 */ 2858 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2859 option == DITHER_OPTION_SPATIAL6 || 2860 option == DITHER_OPTION_FM6) { 2861 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2862 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2863 fmt_bit_depth->flags.TRUNCATE_MODE = 1; 2864 } 2865 2866 /* spatial dither 2867 * note that spatial modes 1-3 are never used 2868 */ 2869 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2870 option == DITHER_OPTION_SPATIAL6 || 2871 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2872 option == DITHER_OPTION_TRUN8_SPATIAL6) { 2873 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2874 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; 2875 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2876 fmt_bit_depth->flags.RGB_RANDOM = 2877 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2878 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || 2879 option == DITHER_OPTION_SPATIAL8 || 2880 option == DITHER_OPTION_SPATIAL8_FM6 || 2881 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2882 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2883 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2884 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; 2885 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2886 fmt_bit_depth->flags.RGB_RANDOM = 2887 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2888 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || 2889 option == DITHER_OPTION_SPATIAL10 || 2890 option == DITHER_OPTION_SPATIAL10_FM8 || 2891 option == DITHER_OPTION_SPATIAL10_FM6) { 2892 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2893 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; 2894 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2895 fmt_bit_depth->flags.RGB_RANDOM = 2896 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2897 } 2898 2899 if (option == DITHER_OPTION_SPATIAL6 || 2900 option == DITHER_OPTION_SPATIAL8 || 2901 option == DITHER_OPTION_SPATIAL10) { 2902 fmt_bit_depth->flags.FRAME_RANDOM = 0; 2903 } else { 2904 fmt_bit_depth->flags.FRAME_RANDOM = 1; 2905 } 2906 2907 ////////////////////// 2908 //// temporal dither 2909 ////////////////////// 2910 if (option == DITHER_OPTION_FM6 || 2911 option == DITHER_OPTION_SPATIAL8_FM6 || 2912 option == DITHER_OPTION_SPATIAL10_FM6 || 2913 option == DITHER_OPTION_TRUN10_FM6 || 2914 option == DITHER_OPTION_TRUN8_FM6 || 2915 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2916 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2917 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; 2918 } else if (option == DITHER_OPTION_FM8 || 2919 option == DITHER_OPTION_SPATIAL10_FM8 || 2920 option == DITHER_OPTION_TRUN10_FM8) { 2921 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2922 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; 2923 } else if (option == DITHER_OPTION_FM10) { 2924 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2925 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; 2926 } 2927 2928 fmt_bit_depth->pixel_encoding = pixel_encoding; 2929 } 2930 2931 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) 2932 { 2933 struct dc_link *link = stream->link; 2934 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 2935 enum dc_status res = DC_OK; 2936 2937 calculate_phy_pix_clks(stream); 2938 2939 if (!tg->funcs->validate_timing(tg, &stream->timing)) 2940 res = DC_FAIL_CONTROLLER_VALIDATE; 2941 2942 if (res == DC_OK) { 2943 if (!link->link_enc->funcs->validate_output_with_stream( 2944 link->link_enc, stream)) 2945 res = DC_FAIL_ENC_VALIDATE; 2946 } 2947 2948 /* TODO: validate audio ASIC caps, encoder */ 2949 2950 if (res == DC_OK) 2951 res = dc_link_validate_mode_timing(stream, 2952 link, 2953 &stream->timing); 2954 2955 return res; 2956 } 2957 2958 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) 2959 { 2960 enum dc_status res = DC_OK; 2961 2962 /* TODO For now validates pixel format only */ 2963 if (dc->res_pool->funcs->validate_plane) 2964 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps); 2965 2966 return res; 2967 } 2968 2969 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format) 2970 { 2971 switch (format) { 2972 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 2973 return 8; 2974 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 2975 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 2976 return 12; 2977 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 2978 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2979 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 2980 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 2981 return 16; 2982 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2983 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2984 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2985 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2986 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 2987 #if defined(CONFIG_DRM_AMD_DC_DCN) 2988 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 2989 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 2990 #endif 2991 return 32; 2992 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2993 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 2994 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2995 return 64; 2996 default: 2997 ASSERT_CRITICAL(false); 2998 return -1; 2999 } 3000 } 3001 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes) 3002 { 3003 if (modes) { 3004 if (modes->sample_rates.rate.RATE_192) 3005 return 192000; 3006 if (modes->sample_rates.rate.RATE_176_4) 3007 return 176400; 3008 if (modes->sample_rates.rate.RATE_96) 3009 return 96000; 3010 if (modes->sample_rates.rate.RATE_88_2) 3011 return 88200; 3012 if (modes->sample_rates.rate.RATE_48) 3013 return 48000; 3014 if (modes->sample_rates.rate.RATE_44_1) 3015 return 44100; 3016 if (modes->sample_rates.rate.RATE_32) 3017 return 32000; 3018 } 3019 /*original logic when no audio info*/ 3020 return 441000; 3021 } 3022 3023 void get_audio_check(struct audio_info *aud_modes, 3024 struct audio_check *audio_chk) 3025 { 3026 unsigned int i; 3027 unsigned int max_sample_rate = 0; 3028 3029 if (aud_modes) { 3030 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/ 3031 3032 audio_chk->max_audiosample_rate = 0; 3033 for (i = 0; i < aud_modes->mode_count; i++) { 3034 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]); 3035 if (audio_chk->max_audiosample_rate < max_sample_rate) 3036 audio_chk->max_audiosample_rate = max_sample_rate; 3037 /*dts takes the same as type 2: AP = 0.25*/ 3038 } 3039 /*check which one take more bandwidth*/ 3040 if (audio_chk->max_audiosample_rate > 192000) 3041 audio_chk->audio_packet_type = 0x9;/*AP =1*/ 3042 audio_chk->acat = 0;/*not support*/ 3043 } 3044 } 3045 3046