1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "resource.h" 31 #include "include/irq_service_interface.h" 32 #include "link_encoder.h" 33 #include "stream_encoder.h" 34 #include "opp.h" 35 #include "timing_generator.h" 36 #include "transform.h" 37 #include "dccg.h" 38 #include "dchubbub.h" 39 #include "dpp.h" 40 #include "core_types.h" 41 #include "set_mode_types.h" 42 #include "virtual/virtual_stream_encoder.h" 43 #include "dpcd_defs.h" 44 45 #if defined(CONFIG_DRM_AMD_DC_SI) 46 #include "dce60/dce60_resource.h" 47 #endif 48 #include "dce80/dce80_resource.h" 49 #include "dce100/dce100_resource.h" 50 #include "dce110/dce110_resource.h" 51 #include "dce112/dce112_resource.h" 52 #include "dce120/dce120_resource.h" 53 #if defined(CONFIG_DRM_AMD_DC_DCN) 54 #include "dcn10/dcn10_resource.h" 55 #include "dcn20/dcn20_resource.h" 56 #include "dcn21/dcn21_resource.h" 57 #include "dcn30/dcn30_resource.h" 58 #include "dcn301/dcn301_resource.h" 59 #include "dcn302/dcn302_resource.h" 60 #include "dcn303/dcn303_resource.h" 61 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 62 #include "../dcn31/dcn31_resource.h" 63 #endif 64 #endif 65 66 #define DC_LOGGER_INIT(logger) 67 68 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 69 { 70 enum dce_version dc_version = DCE_VERSION_UNKNOWN; 71 switch (asic_id.chip_family) { 72 73 #if defined(CONFIG_DRM_AMD_DC_SI) 74 case FAMILY_SI: 75 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) || 76 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) || 77 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev)) 78 dc_version = DCE_VERSION_6_0; 79 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev)) 80 dc_version = DCE_VERSION_6_4; 81 else 82 dc_version = DCE_VERSION_6_1; 83 break; 84 #endif 85 case FAMILY_CI: 86 dc_version = DCE_VERSION_8_0; 87 break; 88 case FAMILY_KV: 89 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) || 90 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) || 91 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev)) 92 dc_version = DCE_VERSION_8_3; 93 else 94 dc_version = DCE_VERSION_8_1; 95 break; 96 case FAMILY_CZ: 97 dc_version = DCE_VERSION_11_0; 98 break; 99 100 case FAMILY_VI: 101 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || 102 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { 103 dc_version = DCE_VERSION_10_0; 104 break; 105 } 106 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || 107 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || 108 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { 109 dc_version = DCE_VERSION_11_2; 110 } 111 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) 112 dc_version = DCE_VERSION_11_22; 113 break; 114 case FAMILY_AI: 115 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev)) 116 dc_version = DCE_VERSION_12_1; 117 else 118 dc_version = DCE_VERSION_12_0; 119 break; 120 #if defined(CONFIG_DRM_AMD_DC_DCN) 121 case FAMILY_RV: 122 dc_version = DCN_VERSION_1_0; 123 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) 124 dc_version = DCN_VERSION_1_01; 125 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) 126 dc_version = DCN_VERSION_2_1; 127 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) 128 dc_version = DCN_VERSION_2_1; 129 break; 130 131 case FAMILY_NV: 132 dc_version = DCN_VERSION_2_0; 133 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) 134 dc_version = DCN_VERSION_3_0; 135 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) 136 dc_version = DCN_VERSION_3_02; 137 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) 138 dc_version = DCN_VERSION_3_03; 139 break; 140 141 case FAMILY_VGH: 142 dc_version = DCN_VERSION_3_01; 143 break; 144 #endif 145 146 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 147 case FAMILY_YELLOW_CARP: 148 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) 149 dc_version = DCN_VERSION_3_1; 150 break; 151 #endif 152 153 default: 154 dc_version = DCE_VERSION_UNKNOWN; 155 break; 156 } 157 return dc_version; 158 } 159 160 struct resource_pool *dc_create_resource_pool(struct dc *dc, 161 const struct dc_init_data *init_data, 162 enum dce_version dc_version) 163 { 164 struct resource_pool *res_pool = NULL; 165 166 switch (dc_version) { 167 #if defined(CONFIG_DRM_AMD_DC_SI) 168 case DCE_VERSION_6_0: 169 res_pool = dce60_create_resource_pool( 170 init_data->num_virtual_links, dc); 171 break; 172 case DCE_VERSION_6_1: 173 res_pool = dce61_create_resource_pool( 174 init_data->num_virtual_links, dc); 175 break; 176 case DCE_VERSION_6_4: 177 res_pool = dce64_create_resource_pool( 178 init_data->num_virtual_links, dc); 179 break; 180 #endif 181 case DCE_VERSION_8_0: 182 res_pool = dce80_create_resource_pool( 183 init_data->num_virtual_links, dc); 184 break; 185 case DCE_VERSION_8_1: 186 res_pool = dce81_create_resource_pool( 187 init_data->num_virtual_links, dc); 188 break; 189 case DCE_VERSION_8_3: 190 res_pool = dce83_create_resource_pool( 191 init_data->num_virtual_links, dc); 192 break; 193 case DCE_VERSION_10_0: 194 res_pool = dce100_create_resource_pool( 195 init_data->num_virtual_links, dc); 196 break; 197 case DCE_VERSION_11_0: 198 res_pool = dce110_create_resource_pool( 199 init_data->num_virtual_links, dc, 200 init_data->asic_id); 201 break; 202 case DCE_VERSION_11_2: 203 case DCE_VERSION_11_22: 204 res_pool = dce112_create_resource_pool( 205 init_data->num_virtual_links, dc); 206 break; 207 case DCE_VERSION_12_0: 208 case DCE_VERSION_12_1: 209 res_pool = dce120_create_resource_pool( 210 init_data->num_virtual_links, dc); 211 break; 212 213 #if defined(CONFIG_DRM_AMD_DC_DCN) 214 case DCN_VERSION_1_0: 215 case DCN_VERSION_1_01: 216 res_pool = dcn10_create_resource_pool(init_data, dc); 217 break; 218 case DCN_VERSION_2_0: 219 res_pool = dcn20_create_resource_pool(init_data, dc); 220 break; 221 case DCN_VERSION_2_1: 222 res_pool = dcn21_create_resource_pool(init_data, dc); 223 break; 224 case DCN_VERSION_3_0: 225 res_pool = dcn30_create_resource_pool(init_data, dc); 226 break; 227 case DCN_VERSION_3_01: 228 res_pool = dcn301_create_resource_pool(init_data, dc); 229 break; 230 case DCN_VERSION_3_02: 231 res_pool = dcn302_create_resource_pool(init_data, dc); 232 break; 233 case DCN_VERSION_3_03: 234 res_pool = dcn303_create_resource_pool(init_data, dc); 235 break; 236 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 237 case DCN_VERSION_3_1: 238 res_pool = dcn31_create_resource_pool(init_data, dc); 239 break; 240 #endif 241 #endif 242 default: 243 break; 244 } 245 246 if (res_pool != NULL) { 247 if (dc->ctx->dc_bios->fw_info_valid) { 248 res_pool->ref_clocks.xtalin_clock_inKhz = 249 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 250 /* initialize with firmware data first, no all 251 * ASIC have DCCG SW component. FPGA or 252 * simulation need initialization of 253 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz 254 * with xtalin_clock_inKhz 255 */ 256 res_pool->ref_clocks.dccg_ref_clock_inKhz = 257 res_pool->ref_clocks.xtalin_clock_inKhz; 258 res_pool->ref_clocks.dchub_ref_clock_inKhz = 259 res_pool->ref_clocks.xtalin_clock_inKhz; 260 } else 261 ASSERT_CRITICAL(false); 262 } 263 264 return res_pool; 265 } 266 267 void dc_destroy_resource_pool(struct dc *dc) 268 { 269 if (dc) { 270 if (dc->res_pool) 271 dc->res_pool->funcs->destroy(&dc->res_pool); 272 273 kfree(dc->hwseq); 274 } 275 } 276 277 static void update_num_audio( 278 const struct resource_straps *straps, 279 unsigned int *num_audio, 280 struct audio_support *aud_support) 281 { 282 aud_support->dp_audio = true; 283 aud_support->hdmi_audio_native = false; 284 aud_support->hdmi_audio_on_dongle = false; 285 286 if (straps->hdmi_disable == 0) { 287 if (straps->dc_pinstraps_audio & 0x2) { 288 aud_support->hdmi_audio_on_dongle = true; 289 aud_support->hdmi_audio_native = true; 290 } 291 } 292 293 switch (straps->audio_stream_number) { 294 case 0: /* multi streams supported */ 295 break; 296 case 1: /* multi streams not supported */ 297 *num_audio = 1; 298 break; 299 default: 300 DC_ERR("DC: unexpected audio fuse!\n"); 301 } 302 } 303 304 bool resource_construct( 305 unsigned int num_virtual_links, 306 struct dc *dc, 307 struct resource_pool *pool, 308 const struct resource_create_funcs *create_funcs) 309 { 310 struct dc_context *ctx = dc->ctx; 311 const struct resource_caps *caps = pool->res_cap; 312 int i; 313 unsigned int num_audio = caps->num_audio; 314 struct resource_straps straps = {0}; 315 316 if (create_funcs->read_dce_straps) 317 create_funcs->read_dce_straps(dc->ctx, &straps); 318 319 pool->audio_count = 0; 320 if (create_funcs->create_audio) { 321 /* find the total number of streams available via the 322 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 323 * registers (one for each pin) starting from pin 1 324 * up to the max number of audio pins. 325 * We stop on the first pin where 326 * PORT_CONNECTIVITY == 1 (as instructed by HW team). 327 */ 328 update_num_audio(&straps, &num_audio, &pool->audio_support); 329 for (i = 0; i < caps->num_audio; i++) { 330 struct audio *aud = create_funcs->create_audio(ctx, i); 331 332 if (aud == NULL) { 333 DC_ERR("DC: failed to create audio!\n"); 334 return false; 335 } 336 if (!aud->funcs->endpoint_valid(aud)) { 337 aud->funcs->destroy(&aud); 338 break; 339 } 340 pool->audios[i] = aud; 341 pool->audio_count++; 342 } 343 } 344 345 pool->stream_enc_count = 0; 346 if (create_funcs->create_stream_encoder) { 347 for (i = 0; i < caps->num_stream_encoder; i++) { 348 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); 349 if (pool->stream_enc[i] == NULL) 350 DC_ERR("DC: failed to create stream_encoder!\n"); 351 pool->stream_enc_count++; 352 } 353 } 354 355 #if defined(CONFIG_DRM_AMD_DC_DCN) 356 for (i = 0; i < caps->num_mpc_3dlut; i++) { 357 pool->mpc_lut[i] = dc_create_3dlut_func(); 358 if (pool->mpc_lut[i] == NULL) 359 DC_ERR("DC: failed to create MPC 3dlut!\n"); 360 pool->mpc_shaper[i] = dc_create_transfer_func(); 361 if (pool->mpc_shaper[i] == NULL) 362 DC_ERR("DC: failed to create MPC shaper!\n"); 363 } 364 #endif 365 dc->caps.dynamic_audio = false; 366 if (pool->audio_count < pool->stream_enc_count) { 367 dc->caps.dynamic_audio = true; 368 } 369 for (i = 0; i < num_virtual_links; i++) { 370 pool->stream_enc[pool->stream_enc_count] = 371 virtual_stream_encoder_create( 372 ctx, ctx->dc_bios); 373 if (pool->stream_enc[pool->stream_enc_count] == NULL) { 374 DC_ERR("DC: failed to create stream_encoder!\n"); 375 return false; 376 } 377 pool->stream_enc_count++; 378 } 379 380 dc->hwseq = create_funcs->create_hwseq(ctx); 381 382 return true; 383 } 384 static int find_matching_clock_source( 385 const struct resource_pool *pool, 386 struct clock_source *clock_source) 387 { 388 389 int i; 390 391 for (i = 0; i < pool->clk_src_count; i++) { 392 if (pool->clock_sources[i] == clock_source) 393 return i; 394 } 395 return -1; 396 } 397 398 void resource_unreference_clock_source( 399 struct resource_context *res_ctx, 400 const struct resource_pool *pool, 401 struct clock_source *clock_source) 402 { 403 int i = find_matching_clock_source(pool, clock_source); 404 405 if (i > -1) 406 res_ctx->clock_source_ref_count[i]--; 407 408 if (pool->dp_clock_source == clock_source) 409 res_ctx->dp_clock_source_ref_count--; 410 } 411 412 void resource_reference_clock_source( 413 struct resource_context *res_ctx, 414 const struct resource_pool *pool, 415 struct clock_source *clock_source) 416 { 417 int i = find_matching_clock_source(pool, clock_source); 418 419 if (i > -1) 420 res_ctx->clock_source_ref_count[i]++; 421 422 if (pool->dp_clock_source == clock_source) 423 res_ctx->dp_clock_source_ref_count++; 424 } 425 426 int resource_get_clock_source_reference( 427 struct resource_context *res_ctx, 428 const struct resource_pool *pool, 429 struct clock_source *clock_source) 430 { 431 int i = find_matching_clock_source(pool, clock_source); 432 433 if (i > -1) 434 return res_ctx->clock_source_ref_count[i]; 435 436 if (pool->dp_clock_source == clock_source) 437 return res_ctx->dp_clock_source_ref_count; 438 439 return -1; 440 } 441 442 bool resource_are_vblanks_synchronizable( 443 struct dc_stream_state *stream1, 444 struct dc_stream_state *stream2) 445 { 446 uint32_t base60_refresh_rates[] = {10, 20, 5}; 447 uint8_t i; 448 uint8_t rr_count = sizeof(base60_refresh_rates)/sizeof(base60_refresh_rates[0]); 449 uint64_t frame_time_diff; 450 451 if (stream1->ctx->dc->config.vblank_alignment_dto_params && 452 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 && 453 dc_is_dp_signal(stream1->signal) && 454 dc_is_dp_signal(stream2->signal) && 455 false == stream1->has_non_synchronizable_pclk && 456 false == stream2->has_non_synchronizable_pclk && 457 stream1->timing.flags.VBLANK_SYNCHRONIZABLE && 458 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) { 459 /* disable refresh rates higher than 60Hz for now */ 460 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/ 461 stream1->timing.v_total > 60) 462 return false; 463 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/ 464 stream2->timing.v_total > 60) 465 return false; 466 frame_time_diff = (uint64_t)10000 * 467 stream1->timing.h_total * 468 stream1->timing.v_total * 469 stream2->timing.pix_clk_100hz; 470 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz); 471 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total); 472 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total); 473 for (i = 0; i < rr_count; i++) { 474 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000; 475 476 if (diff < 0) 477 diff = -diff; 478 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff) 479 return true; 480 } 481 } 482 return false; 483 } 484 485 bool resource_are_streams_timing_synchronizable( 486 struct dc_stream_state *stream1, 487 struct dc_stream_state *stream2) 488 { 489 if (stream1->timing.h_total != stream2->timing.h_total) 490 return false; 491 492 if (stream1->timing.v_total != stream2->timing.v_total) 493 return false; 494 495 if (stream1->timing.h_addressable 496 != stream2->timing.h_addressable) 497 return false; 498 499 if (stream1->timing.v_addressable 500 != stream2->timing.v_addressable) 501 return false; 502 503 if (stream1->timing.v_front_porch 504 != stream2->timing.v_front_porch) 505 return false; 506 507 if (stream1->timing.pix_clk_100hz 508 != stream2->timing.pix_clk_100hz) 509 return false; 510 511 if (stream1->clamping.c_depth != stream2->clamping.c_depth) 512 return false; 513 514 if (stream1->phy_pix_clk != stream2->phy_pix_clk 515 && (!dc_is_dp_signal(stream1->signal) 516 || !dc_is_dp_signal(stream2->signal))) 517 return false; 518 519 if (stream1->view_format != stream2->view_format) 520 return false; 521 522 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param) 523 return false; 524 525 return true; 526 } 527 static bool is_dp_and_hdmi_sharable( 528 struct dc_stream_state *stream1, 529 struct dc_stream_state *stream2) 530 { 531 if (stream1->ctx->dc->caps.disable_dp_clk_share) 532 return false; 533 534 if (stream1->clamping.c_depth != COLOR_DEPTH_888 || 535 stream2->clamping.c_depth != COLOR_DEPTH_888) 536 return false; 537 538 return true; 539 540 } 541 542 static bool is_sharable_clk_src( 543 const struct pipe_ctx *pipe_with_clk_src, 544 const struct pipe_ctx *pipe) 545 { 546 if (pipe_with_clk_src->clock_source == NULL) 547 return false; 548 549 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) 550 return false; 551 552 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) || 553 (dc_is_dp_signal(pipe->stream->signal) && 554 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream, 555 pipe->stream))) 556 return false; 557 558 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) 559 && dc_is_dual_link_signal(pipe->stream->signal)) 560 return false; 561 562 if (dc_is_hdmi_signal(pipe->stream->signal) 563 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal)) 564 return false; 565 566 if (!resource_are_streams_timing_synchronizable( 567 pipe_with_clk_src->stream, pipe->stream)) 568 return false; 569 570 return true; 571 } 572 573 struct clock_source *resource_find_used_clk_src_for_sharing( 574 struct resource_context *res_ctx, 575 struct pipe_ctx *pipe_ctx) 576 { 577 int i; 578 579 for (i = 0; i < MAX_PIPES; i++) { 580 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) 581 return res_ctx->pipe_ctx[i].clock_source; 582 } 583 584 return NULL; 585 } 586 587 static enum pixel_format convert_pixel_format_to_dalsurface( 588 enum surface_pixel_format surface_pixel_format) 589 { 590 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 591 592 switch (surface_pixel_format) { 593 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 594 dal_pixel_format = PIXEL_FORMAT_INDEX8; 595 break; 596 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 597 dal_pixel_format = PIXEL_FORMAT_RGB565; 598 break; 599 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 600 dal_pixel_format = PIXEL_FORMAT_RGB565; 601 break; 602 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 603 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 604 break; 605 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 606 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 607 break; 608 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 609 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 610 break; 611 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 612 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 613 break; 614 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 615 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS; 616 break; 617 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 618 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 619 dal_pixel_format = PIXEL_FORMAT_FP16; 620 break; 621 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 622 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 623 dal_pixel_format = PIXEL_FORMAT_420BPP8; 624 break; 625 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 626 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 627 dal_pixel_format = PIXEL_FORMAT_420BPP10; 628 break; 629 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 630 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 631 default: 632 dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 633 break; 634 } 635 return dal_pixel_format; 636 } 637 638 static inline void get_vp_scan_direction( 639 enum dc_rotation_angle rotation, 640 bool horizontal_mirror, 641 bool *orthogonal_rotation, 642 bool *flip_vert_scan_dir, 643 bool *flip_horz_scan_dir) 644 { 645 *orthogonal_rotation = false; 646 *flip_vert_scan_dir = false; 647 *flip_horz_scan_dir = false; 648 if (rotation == ROTATION_ANGLE_180) { 649 *flip_vert_scan_dir = true; 650 *flip_horz_scan_dir = true; 651 } else if (rotation == ROTATION_ANGLE_90) { 652 *orthogonal_rotation = true; 653 *flip_horz_scan_dir = true; 654 } else if (rotation == ROTATION_ANGLE_270) { 655 *orthogonal_rotation = true; 656 *flip_vert_scan_dir = true; 657 } 658 659 if (horizontal_mirror) 660 *flip_horz_scan_dir = !*flip_horz_scan_dir; 661 } 662 663 int get_num_mpc_splits(struct pipe_ctx *pipe) 664 { 665 int mpc_split_count = 0; 666 struct pipe_ctx *other_pipe = pipe->bottom_pipe; 667 668 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 669 mpc_split_count++; 670 other_pipe = other_pipe->bottom_pipe; 671 } 672 other_pipe = pipe->top_pipe; 673 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 674 mpc_split_count++; 675 other_pipe = other_pipe->top_pipe; 676 } 677 678 return mpc_split_count; 679 } 680 681 int get_num_odm_splits(struct pipe_ctx *pipe) 682 { 683 int odm_split_count = 0; 684 struct pipe_ctx *next_pipe = pipe->next_odm_pipe; 685 while (next_pipe) { 686 odm_split_count++; 687 next_pipe = next_pipe->next_odm_pipe; 688 } 689 pipe = pipe->prev_odm_pipe; 690 while (pipe) { 691 odm_split_count++; 692 pipe = pipe->prev_odm_pipe; 693 } 694 return odm_split_count; 695 } 696 697 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx) 698 { 699 *split_count = get_num_odm_splits(pipe_ctx); 700 *split_idx = 0; 701 if (*split_count == 0) { 702 /*Check for mpc split*/ 703 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe; 704 705 *split_count = get_num_mpc_splits(pipe_ctx); 706 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) { 707 (*split_idx)++; 708 split_pipe = split_pipe->top_pipe; 709 } 710 } else { 711 /*Get odm split index*/ 712 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe; 713 714 while (split_pipe) { 715 (*split_idx)++; 716 split_pipe = split_pipe->prev_odm_pipe; 717 } 718 } 719 } 720 721 /* 722 * This is a preliminary vp size calculation to allow us to check taps support. 723 * The result is completely overridden afterwards. 724 */ 725 static void calculate_viewport_size(struct pipe_ctx *pipe_ctx) 726 { 727 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 728 729 data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width)); 730 data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height)); 731 data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width)); 732 data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height)); 733 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 734 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { 735 swap(data->viewport.width, data->viewport.height); 736 swap(data->viewport_c.width, data->viewport_c.height); 737 } 738 } 739 740 static void calculate_recout(struct pipe_ctx *pipe_ctx) 741 { 742 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 743 const struct dc_stream_state *stream = pipe_ctx->stream; 744 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 745 struct rect surf_clip = plane_state->clip_rect; 746 bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; 747 int split_count, split_idx; 748 749 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 750 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 751 split_idx = 0; 752 753 /* 754 * Only the leftmost ODM pipe should be offset by a nonzero distance 755 */ 756 if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) { 757 data->recout.x = stream->dst.x; 758 if (stream->src.x < surf_clip.x) 759 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width 760 / stream->src.width; 761 } else 762 data->recout.x = 0; 763 764 if (stream->src.x > surf_clip.x) 765 surf_clip.width -= stream->src.x - surf_clip.x; 766 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width; 767 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width) 768 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x; 769 770 data->recout.y = stream->dst.y; 771 if (stream->src.y < surf_clip.y) 772 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height 773 / stream->src.height; 774 else if (stream->src.y > surf_clip.y) 775 surf_clip.height -= stream->src.y - surf_clip.y; 776 777 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height; 778 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height) 779 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y; 780 781 /* Handle h & v split */ 782 if (split_tb) { 783 ASSERT(data->recout.height % 2 == 0); 784 data->recout.height /= 2; 785 } else if (split_count) { 786 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) { 787 /* extra pixels in the division remainder need to go to pipes after 788 * the extra pixel index minus one(epimo) defined here as: 789 */ 790 int epimo = split_count - data->recout.width % (split_count + 1); 791 792 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx; 793 if (split_idx > epimo) 794 data->recout.x += split_idx - epimo - 1; 795 ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0); 796 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0); 797 } else { 798 /* odm */ 799 if (split_idx == split_count) { 800 /* rightmost pipe is the remainder recout */ 801 data->recout.width -= data->h_active * split_count - data->recout.x; 802 data->recout.x = 0; 803 } else 804 data->recout.width = data->h_active - data->recout.x; 805 } 806 } 807 } 808 809 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) 810 { 811 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 812 const struct dc_stream_state *stream = pipe_ctx->stream; 813 struct rect surf_src = plane_state->src_rect; 814 const int in_w = stream->src.width; 815 const int in_h = stream->src.height; 816 const int out_w = stream->dst.width; 817 const int out_h = stream->dst.height; 818 819 /*Swap surf_src height and width since scaling ratios are in recout rotation*/ 820 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 821 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 822 swap(surf_src.height, surf_src.width); 823 824 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( 825 surf_src.width, 826 plane_state->dst_rect.width); 827 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( 828 surf_src.height, 829 plane_state->dst_rect.height); 830 831 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 832 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; 833 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 834 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; 835 836 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( 837 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); 838 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( 839 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); 840 841 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; 842 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; 843 844 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 845 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { 846 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; 847 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; 848 } 849 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate( 850 pipe_ctx->plane_res.scl_data.ratios.horz, 19); 851 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( 852 pipe_ctx->plane_res.scl_data.ratios.vert, 19); 853 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate( 854 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19); 855 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate( 856 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); 857 } 858 859 860 /* 861 * We completely calculate vp offset, size and inits here based entirely on scaling 862 * ratios and recout for pixel perfect pipe combine. 863 */ 864 static void calculate_init_and_vp( 865 bool flip_scan_dir, 866 int recout_offset_within_recout_full, 867 int recout_size, 868 int src_size, 869 int taps, 870 struct fixed31_32 ratio, 871 struct fixed31_32 *init, 872 int *vp_offset, 873 int *vp_size) 874 { 875 struct fixed31_32 temp; 876 int int_part; 877 878 /* 879 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout 880 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on. 881 * All following calculations are based on this logic. 882 * 883 * Init calculated according to formula: 884 * init = (scaling_ratio + number_of_taps + 1) / 2 885 * init_bot = init + scaling_ratio 886 * to get pixel perfect combine add the fraction from calculating vp offset 887 */ 888 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full); 889 *vp_offset = dc_fixpt_floor(temp); 890 temp.value &= 0xffffffff; 891 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int( 892 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19); 893 /* 894 * If viewport has non 0 offset and there are more taps than covered by init then 895 * we should decrease the offset and increase init so we are never sampling 896 * outside of viewport. 897 */ 898 int_part = dc_fixpt_floor(*init); 899 if (int_part < taps) { 900 int_part = taps - int_part; 901 if (int_part > *vp_offset) 902 int_part = *vp_offset; 903 *vp_offset -= int_part; 904 *init = dc_fixpt_add_int(*init, int_part); 905 } 906 /* 907 * If taps are sampling outside of viewport at end of recout and there are more pixels 908 * available in the surface we should increase the viewport size, regardless set vp to 909 * only what is used. 910 */ 911 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1)); 912 *vp_size = dc_fixpt_floor(temp); 913 if (*vp_size + *vp_offset > src_size) 914 *vp_size = src_size - *vp_offset; 915 916 /* We did all the math assuming we are scanning same direction as display does, 917 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction 918 * is flipped we simply need to calculate offset from the other side of plane. 919 * Note that outside of viewport all scaling hardware works in recout space. 920 */ 921 if (flip_scan_dir) 922 *vp_offset = src_size - *vp_offset - *vp_size; 923 } 924 925 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx) 926 { 927 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 928 const struct dc_stream_state *stream = pipe_ctx->stream; 929 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 930 struct rect src = plane_state->src_rect; 931 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 932 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 933 int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y; 934 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; 935 936 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); 937 /* 938 * recout full is what the recout would have been if we didnt clip 939 * the source plane at all. We only care about left(ro_lb) and top(ro_tb) 940 * offsets of recout within recout full because those are the directions 941 * we scan from and therefore the only ones that affect inits. 942 */ 943 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) 944 * stream->dst.width / stream->src.width; 945 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) 946 * stream->dst.height / stream->src.height; 947 if (pipe_ctx->prev_odm_pipe && split_idx) 948 ro_lb = data->h_active * split_idx - recout_full_x; 949 else 950 ro_lb = data->recout.x - recout_full_x; 951 ro_tb = data->recout.y - recout_full_y; 952 ASSERT(ro_lb >= 0 && ro_tb >= 0); 953 954 /* 955 * Work in recout rotation since that requires less transformations 956 */ 957 get_vp_scan_direction( 958 plane_state->rotation, 959 plane_state->horizontal_mirror, 960 &orthogonal_rotation, 961 &flip_vert_scan_dir, 962 &flip_horz_scan_dir); 963 964 if (orthogonal_rotation) { 965 swap(src.width, src.height); 966 swap(flip_vert_scan_dir, flip_horz_scan_dir); 967 } 968 969 calculate_init_and_vp( 970 flip_horz_scan_dir, 971 ro_lb, 972 data->recout.width, 973 src.width, 974 data->taps.h_taps, 975 data->ratios.horz, 976 &data->inits.h, 977 &data->viewport.x, 978 &data->viewport.width); 979 calculate_init_and_vp( 980 flip_horz_scan_dir, 981 ro_lb, 982 data->recout.width, 983 src.width / vpc_div, 984 data->taps.h_taps_c, 985 data->ratios.horz_c, 986 &data->inits.h_c, 987 &data->viewport_c.x, 988 &data->viewport_c.width); 989 calculate_init_and_vp( 990 flip_vert_scan_dir, 991 ro_tb, 992 data->recout.height, 993 src.height, 994 data->taps.v_taps, 995 data->ratios.vert, 996 &data->inits.v, 997 &data->viewport.y, 998 &data->viewport.height); 999 calculate_init_and_vp( 1000 flip_vert_scan_dir, 1001 ro_tb, 1002 data->recout.height, 1003 src.height / vpc_div, 1004 data->taps.v_taps_c, 1005 data->ratios.vert_c, 1006 &data->inits.v_c, 1007 &data->viewport_c.y, 1008 &data->viewport_c.height); 1009 if (orthogonal_rotation) { 1010 swap(data->viewport.x, data->viewport.y); 1011 swap(data->viewport.width, data->viewport.height); 1012 swap(data->viewport_c.x, data->viewport_c.y); 1013 swap(data->viewport_c.width, data->viewport_c.height); 1014 } 1015 data->viewport.x += src.x; 1016 data->viewport.y += src.y; 1017 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); 1018 data->viewport_c.x += src.x / vpc_div; 1019 data->viewport_c.y += src.y / vpc_div; 1020 } 1021 1022 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 1023 { 1024 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1025 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 1026 bool res = false; 1027 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 1028 1029 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( 1030 pipe_ctx->plane_state->format); 1031 1032 /* Timing borders are part of vactive that we are also supposed to skip in addition 1033 * to any stream dst offset. Since dm logic assumes dst is in addressable 1034 * space we need to add the the left and top borders to dst offsets temporarily. 1035 * TODO: fix in DM, stream dst is supposed to be in vactive 1036 */ 1037 pipe_ctx->stream->dst.x += timing->h_border_left; 1038 pipe_ctx->stream->dst.y += timing->v_border_top; 1039 1040 /* Calculate H and V active size */ 1041 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + 1042 timing->h_border_left + timing->h_border_right; 1043 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + 1044 timing->v_border_top + timing->v_border_bottom; 1045 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe) 1046 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1; 1047 1048 /* depends on h_active */ 1049 calculate_recout(pipe_ctx); 1050 /* depends on pixel format */ 1051 calculate_scaling_ratios(pipe_ctx); 1052 /* depends on scaling ratios and recout, does not calculate offset yet */ 1053 calculate_viewport_size(pipe_ctx); 1054 1055 /* 1056 * LB calculations depend on vp size, h/v_active and scaling ratios 1057 * Setting line buffer pixel depth to 24bpp yields banding 1058 * on certain displays, such as the Sharp 4k. 36bpp is needed 1059 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and 1060 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc 1061 * precision on at least DCN display engines. However, at least 1062 * Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth, 1063 * so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3 1064 * did not show such problems, so this seems to be the exception. 1065 */ 1066 if (plane_state->ctx->dce_version != DCE_VERSION_11_0) 1067 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; 1068 else 1069 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; 1070 1071 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; 1072 1073 if (pipe_ctx->plane_res.xfm != NULL) 1074 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1075 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1076 1077 if (pipe_ctx->plane_res.dpp != NULL) 1078 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1079 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1080 1081 1082 if (!res) { 1083 /* Try 24 bpp linebuffer */ 1084 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; 1085 1086 if (pipe_ctx->plane_res.xfm != NULL) 1087 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1088 pipe_ctx->plane_res.xfm, 1089 &pipe_ctx->plane_res.scl_data, 1090 &plane_state->scaling_quality); 1091 1092 if (pipe_ctx->plane_res.dpp != NULL) 1093 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1094 pipe_ctx->plane_res.dpp, 1095 &pipe_ctx->plane_res.scl_data, 1096 &plane_state->scaling_quality); 1097 } 1098 1099 /* 1100 * Depends on recout, scaling ratios, h_active and taps 1101 * May need to re-check lb size after this in some obscure scenario 1102 */ 1103 if (res) 1104 calculate_inits_and_viewports(pipe_ctx); 1105 1106 /* 1107 * Handle side by side and top bottom 3d recout offsets after vp calculation 1108 * since 3d is special and needs to calculate vp as if there is no recout offset 1109 * This may break with rotation, good thing we aren't mixing hw rotation and 3d 1110 */ 1111 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) { 1112 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 || 1113 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM && 1114 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE)); 1115 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 1116 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; 1117 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 1118 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; 1119 } 1120 1121 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE || 1122 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) 1123 res = false; 1124 1125 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n" 1126 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n", 1127 __func__, 1128 pipe_ctx->pipe_idx, 1129 pipe_ctx->plane_res.scl_data.viewport.height, 1130 pipe_ctx->plane_res.scl_data.viewport.width, 1131 pipe_ctx->plane_res.scl_data.viewport.x, 1132 pipe_ctx->plane_res.scl_data.viewport.y, 1133 pipe_ctx->plane_res.scl_data.recout.height, 1134 pipe_ctx->plane_res.scl_data.recout.width, 1135 pipe_ctx->plane_res.scl_data.recout.x, 1136 pipe_ctx->plane_res.scl_data.recout.y, 1137 pipe_ctx->plane_res.scl_data.h_active, 1138 pipe_ctx->plane_res.scl_data.v_active, 1139 plane_state->src_rect.height, 1140 plane_state->src_rect.width, 1141 plane_state->src_rect.x, 1142 plane_state->src_rect.y, 1143 plane_state->dst_rect.height, 1144 plane_state->dst_rect.width, 1145 plane_state->dst_rect.x, 1146 plane_state->dst_rect.y, 1147 plane_state->clip_rect.height, 1148 plane_state->clip_rect.width, 1149 plane_state->clip_rect.x, 1150 plane_state->clip_rect.y); 1151 1152 pipe_ctx->stream->dst.x -= timing->h_border_left; 1153 pipe_ctx->stream->dst.y -= timing->v_border_top; 1154 1155 return res; 1156 } 1157 1158 1159 enum dc_status resource_build_scaling_params_for_context( 1160 const struct dc *dc, 1161 struct dc_state *context) 1162 { 1163 int i; 1164 1165 for (i = 0; i < MAX_PIPES; i++) { 1166 if (context->res_ctx.pipe_ctx[i].plane_state != NULL && 1167 context->res_ctx.pipe_ctx[i].stream != NULL) 1168 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) 1169 return DC_FAIL_SCALING; 1170 } 1171 1172 return DC_OK; 1173 } 1174 1175 struct pipe_ctx *find_idle_secondary_pipe( 1176 struct resource_context *res_ctx, 1177 const struct resource_pool *pool, 1178 const struct pipe_ctx *primary_pipe) 1179 { 1180 int i; 1181 struct pipe_ctx *secondary_pipe = NULL; 1182 1183 /* 1184 * We add a preferred pipe mapping to avoid the chance that 1185 * MPCCs already in use will need to be reassigned to other trees. 1186 * For example, if we went with the strict, assign backwards logic: 1187 * 1188 * (State 1) 1189 * Display A on, no surface, top pipe = 0 1190 * Display B on, no surface, top pipe = 1 1191 * 1192 * (State 2) 1193 * Display A on, no surface, top pipe = 0 1194 * Display B on, surface enable, top pipe = 1, bottom pipe = 5 1195 * 1196 * (State 3) 1197 * Display A on, surface enable, top pipe = 0, bottom pipe = 5 1198 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1199 * 1200 * The state 2->3 transition requires remapping MPCC 5 from display B 1201 * to display A. 1202 * 1203 * However, with the preferred pipe logic, state 2 would look like: 1204 * 1205 * (State 2) 1206 * Display A on, no surface, top pipe = 0 1207 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1208 * 1209 * This would then cause 2->3 to not require remapping any MPCCs. 1210 */ 1211 if (primary_pipe) { 1212 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 1213 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1214 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1215 secondary_pipe->pipe_idx = preferred_pipe_idx; 1216 } 1217 } 1218 1219 /* 1220 * search backwards for the second pipe to keep pipe 1221 * assignment more consistent 1222 */ 1223 if (!secondary_pipe) 1224 for (i = pool->pipe_count - 1; i >= 0; i--) { 1225 if (res_ctx->pipe_ctx[i].stream == NULL) { 1226 secondary_pipe = &res_ctx->pipe_ctx[i]; 1227 secondary_pipe->pipe_idx = i; 1228 break; 1229 } 1230 } 1231 1232 return secondary_pipe; 1233 } 1234 1235 struct pipe_ctx *resource_get_head_pipe_for_stream( 1236 struct resource_context *res_ctx, 1237 struct dc_stream_state *stream) 1238 { 1239 int i; 1240 1241 for (i = 0; i < MAX_PIPES; i++) { 1242 if (res_ctx->pipe_ctx[i].stream == stream 1243 && !res_ctx->pipe_ctx[i].top_pipe 1244 && !res_ctx->pipe_ctx[i].prev_odm_pipe) 1245 return &res_ctx->pipe_ctx[i]; 1246 } 1247 return NULL; 1248 } 1249 1250 static struct pipe_ctx *resource_get_tail_pipe( 1251 struct resource_context *res_ctx, 1252 struct pipe_ctx *head_pipe) 1253 { 1254 struct pipe_ctx *tail_pipe; 1255 1256 tail_pipe = head_pipe->bottom_pipe; 1257 1258 while (tail_pipe) { 1259 head_pipe = tail_pipe; 1260 tail_pipe = tail_pipe->bottom_pipe; 1261 } 1262 1263 return head_pipe; 1264 } 1265 1266 /* 1267 * A free_pipe for a stream is defined here as a pipe 1268 * that has no surface attached yet 1269 */ 1270 static struct pipe_ctx *acquire_free_pipe_for_head( 1271 struct dc_state *context, 1272 const struct resource_pool *pool, 1273 struct pipe_ctx *head_pipe) 1274 { 1275 int i; 1276 struct resource_context *res_ctx = &context->res_ctx; 1277 1278 if (!head_pipe->plane_state) 1279 return head_pipe; 1280 1281 /* Re-use pipe already acquired for this stream if available*/ 1282 for (i = pool->pipe_count - 1; i >= 0; i--) { 1283 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream && 1284 !res_ctx->pipe_ctx[i].plane_state) { 1285 return &res_ctx->pipe_ctx[i]; 1286 } 1287 } 1288 1289 /* 1290 * At this point we have no re-useable pipe for this stream and we need 1291 * to acquire an idle one to satisfy the request 1292 */ 1293 1294 if (!pool->funcs->acquire_idle_pipe_for_layer) 1295 return NULL; 1296 1297 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream); 1298 } 1299 1300 #if defined(CONFIG_DRM_AMD_DC_DCN) 1301 static int acquire_first_split_pipe( 1302 struct resource_context *res_ctx, 1303 const struct resource_pool *pool, 1304 struct dc_stream_state *stream) 1305 { 1306 int i; 1307 1308 for (i = 0; i < pool->pipe_count; i++) { 1309 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; 1310 1311 if (split_pipe->top_pipe && 1312 split_pipe->top_pipe->plane_state == split_pipe->plane_state) { 1313 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; 1314 if (split_pipe->bottom_pipe) 1315 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; 1316 1317 if (split_pipe->top_pipe->plane_state) 1318 resource_build_scaling_params(split_pipe->top_pipe); 1319 1320 memset(split_pipe, 0, sizeof(*split_pipe)); 1321 split_pipe->stream_res.tg = pool->timing_generators[i]; 1322 split_pipe->plane_res.hubp = pool->hubps[i]; 1323 split_pipe->plane_res.ipp = pool->ipps[i]; 1324 split_pipe->plane_res.dpp = pool->dpps[i]; 1325 split_pipe->stream_res.opp = pool->opps[i]; 1326 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; 1327 split_pipe->pipe_idx = i; 1328 1329 split_pipe->stream = stream; 1330 return i; 1331 } 1332 } 1333 return -1; 1334 } 1335 #endif 1336 1337 bool dc_add_plane_to_context( 1338 const struct dc *dc, 1339 struct dc_stream_state *stream, 1340 struct dc_plane_state *plane_state, 1341 struct dc_state *context) 1342 { 1343 int i; 1344 struct resource_pool *pool = dc->res_pool; 1345 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; 1346 struct dc_stream_status *stream_status = NULL; 1347 1348 for (i = 0; i < context->stream_count; i++) 1349 if (context->streams[i] == stream) { 1350 stream_status = &context->stream_status[i]; 1351 break; 1352 } 1353 if (stream_status == NULL) { 1354 dm_error("Existing stream not found; failed to attach surface!\n"); 1355 return false; 1356 } 1357 1358 1359 if (stream_status->plane_count == MAX_SURFACE_NUM) { 1360 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", 1361 plane_state, MAX_SURFACE_NUM); 1362 return false; 1363 } 1364 1365 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1366 1367 if (!head_pipe) { 1368 dm_error("Head pipe not found for stream_state %p !\n", stream); 1369 return false; 1370 } 1371 1372 /* retain new surface, but only once per stream */ 1373 dc_plane_state_retain(plane_state); 1374 1375 while (head_pipe) { 1376 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe); 1377 1378 #if defined(CONFIG_DRM_AMD_DC_DCN) 1379 if (!free_pipe) { 1380 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 1381 if (pipe_idx >= 0) 1382 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; 1383 } 1384 #endif 1385 if (!free_pipe) { 1386 dc_plane_state_release(plane_state); 1387 return false; 1388 } 1389 1390 free_pipe->plane_state = plane_state; 1391 1392 if (head_pipe != free_pipe) { 1393 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe); 1394 ASSERT(tail_pipe); 1395 free_pipe->stream_res.tg = tail_pipe->stream_res.tg; 1396 free_pipe->stream_res.abm = tail_pipe->stream_res.abm; 1397 free_pipe->stream_res.opp = tail_pipe->stream_res.opp; 1398 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; 1399 free_pipe->stream_res.audio = tail_pipe->stream_res.audio; 1400 free_pipe->clock_source = tail_pipe->clock_source; 1401 free_pipe->top_pipe = tail_pipe; 1402 tail_pipe->bottom_pipe = free_pipe; 1403 if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) { 1404 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe; 1405 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe; 1406 } 1407 if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) { 1408 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe; 1409 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe; 1410 } 1411 } 1412 head_pipe = head_pipe->next_odm_pipe; 1413 } 1414 /* assign new surfaces*/ 1415 stream_status->plane_states[stream_status->plane_count] = plane_state; 1416 1417 stream_status->plane_count++; 1418 1419 return true; 1420 } 1421 1422 bool dc_remove_plane_from_context( 1423 const struct dc *dc, 1424 struct dc_stream_state *stream, 1425 struct dc_plane_state *plane_state, 1426 struct dc_state *context) 1427 { 1428 int i; 1429 struct dc_stream_status *stream_status = NULL; 1430 struct resource_pool *pool = dc->res_pool; 1431 1432 for (i = 0; i < context->stream_count; i++) 1433 if (context->streams[i] == stream) { 1434 stream_status = &context->stream_status[i]; 1435 break; 1436 } 1437 1438 if (stream_status == NULL) { 1439 dm_error("Existing stream not found; failed to remove plane.\n"); 1440 return false; 1441 } 1442 1443 /* release pipe for plane*/ 1444 for (i = pool->pipe_count - 1; i >= 0; i--) { 1445 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1446 1447 if (pipe_ctx->plane_state == plane_state) { 1448 if (pipe_ctx->top_pipe) 1449 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1450 1451 /* Second condition is to avoid setting NULL to top pipe 1452 * of tail pipe making it look like head pipe in subsequent 1453 * deletes 1454 */ 1455 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) 1456 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1457 1458 /* 1459 * For head pipe detach surfaces from pipe for tail 1460 * pipe just zero it out 1461 */ 1462 if (!pipe_ctx->top_pipe) 1463 pipe_ctx->plane_state = NULL; 1464 else 1465 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1466 } 1467 } 1468 1469 1470 for (i = 0; i < stream_status->plane_count; i++) { 1471 if (stream_status->plane_states[i] == plane_state) { 1472 1473 dc_plane_state_release(stream_status->plane_states[i]); 1474 break; 1475 } 1476 } 1477 1478 if (i == stream_status->plane_count) { 1479 dm_error("Existing plane_state not found; failed to detach it!\n"); 1480 return false; 1481 } 1482 1483 stream_status->plane_count--; 1484 1485 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */ 1486 for (; i < stream_status->plane_count; i++) 1487 stream_status->plane_states[i] = stream_status->plane_states[i + 1]; 1488 1489 stream_status->plane_states[stream_status->plane_count] = NULL; 1490 1491 return true; 1492 } 1493 1494 bool dc_rem_all_planes_for_stream( 1495 const struct dc *dc, 1496 struct dc_stream_state *stream, 1497 struct dc_state *context) 1498 { 1499 int i, old_plane_count; 1500 struct dc_stream_status *stream_status = NULL; 1501 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; 1502 1503 for (i = 0; i < context->stream_count; i++) 1504 if (context->streams[i] == stream) { 1505 stream_status = &context->stream_status[i]; 1506 break; 1507 } 1508 1509 if (stream_status == NULL) { 1510 dm_error("Existing stream %p not found!\n", stream); 1511 return false; 1512 } 1513 1514 old_plane_count = stream_status->plane_count; 1515 1516 for (i = 0; i < old_plane_count; i++) 1517 del_planes[i] = stream_status->plane_states[i]; 1518 1519 for (i = 0; i < old_plane_count; i++) 1520 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) 1521 return false; 1522 1523 return true; 1524 } 1525 1526 static bool add_all_planes_for_stream( 1527 const struct dc *dc, 1528 struct dc_stream_state *stream, 1529 const struct dc_validation_set set[], 1530 int set_count, 1531 struct dc_state *context) 1532 { 1533 int i, j; 1534 1535 for (i = 0; i < set_count; i++) 1536 if (set[i].stream == stream) 1537 break; 1538 1539 if (i == set_count) { 1540 dm_error("Stream %p not found in set!\n", stream); 1541 return false; 1542 } 1543 1544 for (j = 0; j < set[i].plane_count; j++) 1545 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) 1546 return false; 1547 1548 return true; 1549 } 1550 1551 bool dc_add_all_planes_for_stream( 1552 const struct dc *dc, 1553 struct dc_stream_state *stream, 1554 struct dc_plane_state * const *plane_states, 1555 int plane_count, 1556 struct dc_state *context) 1557 { 1558 struct dc_validation_set set; 1559 int i; 1560 1561 set.stream = stream; 1562 set.plane_count = plane_count; 1563 1564 for (i = 0; i < plane_count; i++) 1565 set.plane_states[i] = plane_states[i]; 1566 1567 return add_all_planes_for_stream(dc, stream, &set, 1, context); 1568 } 1569 1570 static bool is_timing_changed(struct dc_stream_state *cur_stream, 1571 struct dc_stream_state *new_stream) 1572 { 1573 if (cur_stream == NULL) 1574 return true; 1575 1576 /* If output color space is changed, need to reprogram info frames */ 1577 if (cur_stream->output_color_space != new_stream->output_color_space) 1578 return true; 1579 1580 return memcmp( 1581 &cur_stream->timing, 1582 &new_stream->timing, 1583 sizeof(struct dc_crtc_timing)) != 0; 1584 } 1585 1586 static bool are_stream_backends_same( 1587 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) 1588 { 1589 if (stream_a == stream_b) 1590 return true; 1591 1592 if (stream_a == NULL || stream_b == NULL) 1593 return false; 1594 1595 if (is_timing_changed(stream_a, stream_b)) 1596 return false; 1597 1598 if (stream_a->dpms_off != stream_b->dpms_off) 1599 return false; 1600 1601 return true; 1602 } 1603 1604 /* 1605 * dc_is_stream_unchanged() - Compare two stream states for equivalence. 1606 * 1607 * Checks if there a difference between the two states 1608 * that would require a mode change. 1609 * 1610 * Does not compare cursor position or attributes. 1611 */ 1612 bool dc_is_stream_unchanged( 1613 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1614 { 1615 1616 if (!are_stream_backends_same(old_stream, stream)) 1617 return false; 1618 1619 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param) 1620 return false; 1621 1622 return true; 1623 } 1624 1625 /* 1626 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams. 1627 */ 1628 bool dc_is_stream_scaling_unchanged( 1629 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1630 { 1631 if (old_stream == stream) 1632 return true; 1633 1634 if (old_stream == NULL || stream == NULL) 1635 return false; 1636 1637 if (memcmp(&old_stream->src, 1638 &stream->src, 1639 sizeof(struct rect)) != 0) 1640 return false; 1641 1642 if (memcmp(&old_stream->dst, 1643 &stream->dst, 1644 sizeof(struct rect)) != 0) 1645 return false; 1646 1647 return true; 1648 } 1649 1650 static void update_stream_engine_usage( 1651 struct resource_context *res_ctx, 1652 const struct resource_pool *pool, 1653 struct stream_encoder *stream_enc, 1654 bool acquired) 1655 { 1656 int i; 1657 1658 for (i = 0; i < pool->stream_enc_count; i++) { 1659 if (pool->stream_enc[i] == stream_enc) 1660 res_ctx->is_stream_enc_acquired[i] = acquired; 1661 } 1662 } 1663 1664 /* TODO: release audio object */ 1665 void update_audio_usage( 1666 struct resource_context *res_ctx, 1667 const struct resource_pool *pool, 1668 struct audio *audio, 1669 bool acquired) 1670 { 1671 int i; 1672 for (i = 0; i < pool->audio_count; i++) { 1673 if (pool->audios[i] == audio) 1674 res_ctx->is_audio_acquired[i] = acquired; 1675 } 1676 } 1677 1678 static int acquire_first_free_pipe( 1679 struct resource_context *res_ctx, 1680 const struct resource_pool *pool, 1681 struct dc_stream_state *stream) 1682 { 1683 int i; 1684 1685 for (i = 0; i < pool->pipe_count; i++) { 1686 if (!res_ctx->pipe_ctx[i].stream) { 1687 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 1688 1689 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 1690 pipe_ctx->plane_res.mi = pool->mis[i]; 1691 pipe_ctx->plane_res.hubp = pool->hubps[i]; 1692 pipe_ctx->plane_res.ipp = pool->ipps[i]; 1693 pipe_ctx->plane_res.xfm = pool->transforms[i]; 1694 pipe_ctx->plane_res.dpp = pool->dpps[i]; 1695 pipe_ctx->stream_res.opp = pool->opps[i]; 1696 if (pool->dpps[i]) 1697 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; 1698 pipe_ctx->pipe_idx = i; 1699 1700 1701 pipe_ctx->stream = stream; 1702 return i; 1703 } 1704 } 1705 return -1; 1706 } 1707 1708 static struct audio *find_first_free_audio( 1709 struct resource_context *res_ctx, 1710 const struct resource_pool *pool, 1711 enum engine_id id, 1712 enum dce_version dc_version) 1713 { 1714 int i, available_audio_count; 1715 1716 available_audio_count = pool->audio_count; 1717 1718 for (i = 0; i < available_audio_count; i++) { 1719 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { 1720 /*we have enough audio endpoint, find the matching inst*/ 1721 if (id != i) 1722 continue; 1723 return pool->audios[i]; 1724 } 1725 } 1726 1727 /* use engine id to find free audio */ 1728 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) { 1729 return pool->audios[id]; 1730 } 1731 /*not found the matching one, first come first serve*/ 1732 for (i = 0; i < available_audio_count; i++) { 1733 if (res_ctx->is_audio_acquired[i] == false) { 1734 return pool->audios[i]; 1735 } 1736 } 1737 return 0; 1738 } 1739 1740 /* 1741 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state. 1742 */ 1743 enum dc_status dc_add_stream_to_ctx( 1744 struct dc *dc, 1745 struct dc_state *new_ctx, 1746 struct dc_stream_state *stream) 1747 { 1748 enum dc_status res; 1749 DC_LOGGER_INIT(dc->ctx->logger); 1750 1751 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) { 1752 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream); 1753 return DC_ERROR_UNEXPECTED; 1754 } 1755 1756 new_ctx->streams[new_ctx->stream_count] = stream; 1757 dc_stream_retain(stream); 1758 new_ctx->stream_count++; 1759 1760 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); 1761 if (res != DC_OK) 1762 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res); 1763 1764 return res; 1765 } 1766 1767 /* 1768 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state. 1769 */ 1770 enum dc_status dc_remove_stream_from_ctx( 1771 struct dc *dc, 1772 struct dc_state *new_ctx, 1773 struct dc_stream_state *stream) 1774 { 1775 int i; 1776 struct dc_context *dc_ctx = dc->ctx; 1777 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream); 1778 struct pipe_ctx *odm_pipe; 1779 1780 if (!del_pipe) { 1781 DC_ERROR("Pipe not found for stream %p !\n", stream); 1782 return DC_ERROR_UNEXPECTED; 1783 } 1784 1785 odm_pipe = del_pipe->next_odm_pipe; 1786 1787 /* Release primary pipe */ 1788 ASSERT(del_pipe->stream_res.stream_enc); 1789 update_stream_engine_usage( 1790 &new_ctx->res_ctx, 1791 dc->res_pool, 1792 del_pipe->stream_res.stream_enc, 1793 false); 1794 /* Release link encoder from stream in new dc_state. */ 1795 if (dc->res_pool->funcs->link_enc_unassign) 1796 dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream); 1797 1798 if (del_pipe->stream_res.audio) 1799 update_audio_usage( 1800 &new_ctx->res_ctx, 1801 dc->res_pool, 1802 del_pipe->stream_res.audio, 1803 false); 1804 1805 resource_unreference_clock_source(&new_ctx->res_ctx, 1806 dc->res_pool, 1807 del_pipe->clock_source); 1808 1809 if (dc->res_pool->funcs->remove_stream_from_ctx) 1810 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream); 1811 1812 while (odm_pipe) { 1813 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 1814 1815 memset(odm_pipe, 0, sizeof(*odm_pipe)); 1816 odm_pipe = next_odm_pipe; 1817 } 1818 memset(del_pipe, 0, sizeof(*del_pipe)); 1819 1820 for (i = 0; i < new_ctx->stream_count; i++) 1821 if (new_ctx->streams[i] == stream) 1822 break; 1823 1824 if (new_ctx->streams[i] != stream) { 1825 DC_ERROR("Context doesn't have stream %p !\n", stream); 1826 return DC_ERROR_UNEXPECTED; 1827 } 1828 1829 dc_stream_release(new_ctx->streams[i]); 1830 new_ctx->stream_count--; 1831 1832 /* Trim back arrays */ 1833 for (; i < new_ctx->stream_count; i++) { 1834 new_ctx->streams[i] = new_ctx->streams[i + 1]; 1835 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; 1836 } 1837 1838 new_ctx->streams[new_ctx->stream_count] = NULL; 1839 memset( 1840 &new_ctx->stream_status[new_ctx->stream_count], 1841 0, 1842 sizeof(new_ctx->stream_status[0])); 1843 1844 return DC_OK; 1845 } 1846 1847 static struct dc_stream_state *find_pll_sharable_stream( 1848 struct dc_stream_state *stream_needs_pll, 1849 struct dc_state *context) 1850 { 1851 int i; 1852 1853 for (i = 0; i < context->stream_count; i++) { 1854 struct dc_stream_state *stream_has_pll = context->streams[i]; 1855 1856 /* We are looking for non dp, non virtual stream */ 1857 if (resource_are_streams_timing_synchronizable( 1858 stream_needs_pll, stream_has_pll) 1859 && !dc_is_dp_signal(stream_has_pll->signal) 1860 && stream_has_pll->link->connector_signal 1861 != SIGNAL_TYPE_VIRTUAL) 1862 return stream_has_pll; 1863 1864 } 1865 1866 return NULL; 1867 } 1868 1869 static int get_norm_pix_clk(const struct dc_crtc_timing *timing) 1870 { 1871 uint32_t pix_clk = timing->pix_clk_100hz; 1872 uint32_t normalized_pix_clk = pix_clk; 1873 1874 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 1875 pix_clk /= 2; 1876 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 1877 switch (timing->display_color_depth) { 1878 case COLOR_DEPTH_666: 1879 case COLOR_DEPTH_888: 1880 normalized_pix_clk = pix_clk; 1881 break; 1882 case COLOR_DEPTH_101010: 1883 normalized_pix_clk = (pix_clk * 30) / 24; 1884 break; 1885 case COLOR_DEPTH_121212: 1886 normalized_pix_clk = (pix_clk * 36) / 24; 1887 break; 1888 case COLOR_DEPTH_161616: 1889 normalized_pix_clk = (pix_clk * 48) / 24; 1890 break; 1891 default: 1892 ASSERT(0); 1893 break; 1894 } 1895 } 1896 return normalized_pix_clk; 1897 } 1898 1899 static void calculate_phy_pix_clks(struct dc_stream_state *stream) 1900 { 1901 /* update actual pixel clock on all streams */ 1902 if (dc_is_hdmi_signal(stream->signal)) 1903 stream->phy_pix_clk = get_norm_pix_clk( 1904 &stream->timing) / 10; 1905 else 1906 stream->phy_pix_clk = 1907 stream->timing.pix_clk_100hz / 10; 1908 1909 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1910 stream->phy_pix_clk *= 2; 1911 } 1912 1913 static int acquire_resource_from_hw_enabled_state( 1914 struct resource_context *res_ctx, 1915 const struct resource_pool *pool, 1916 struct dc_stream_state *stream) 1917 { 1918 struct dc_link *link = stream->link; 1919 unsigned int i, inst, tg_inst = 0; 1920 1921 /* Check for enabled DIG to identify enabled display */ 1922 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) 1923 return -1; 1924 1925 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); 1926 1927 if (inst == ENGINE_ID_UNKNOWN) 1928 return -1; 1929 1930 for (i = 0; i < pool->stream_enc_count; i++) { 1931 if (pool->stream_enc[i]->id == inst) { 1932 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( 1933 pool->stream_enc[i]); 1934 break; 1935 } 1936 } 1937 1938 // tg_inst not found 1939 if (i == pool->stream_enc_count) 1940 return -1; 1941 1942 if (tg_inst >= pool->timing_generator_count) 1943 return -1; 1944 1945 if (!res_ctx->pipe_ctx[tg_inst].stream) { 1946 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; 1947 1948 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 1949 pipe_ctx->plane_res.mi = pool->mis[tg_inst]; 1950 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; 1951 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; 1952 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; 1953 pipe_ctx->plane_res.dpp = pool->dpps[tg_inst]; 1954 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; 1955 1956 if (pool->dpps[tg_inst]) { 1957 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; 1958 1959 // Read DPP->MPCC->OPP Pipe from HW State 1960 if (pool->mpc->funcs->read_mpcc_state) { 1961 struct mpcc_state s = {0}; 1962 1963 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); 1964 1965 if (s.dpp_id < MAX_MPCC) 1966 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id; 1967 1968 if (s.bot_mpcc_id < MAX_MPCC) 1969 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = 1970 &pool->mpc->mpcc_array[s.bot_mpcc_id]; 1971 1972 if (s.opp_id < MAX_OPP) 1973 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; 1974 } 1975 } 1976 pipe_ctx->pipe_idx = tg_inst; 1977 1978 pipe_ctx->stream = stream; 1979 return tg_inst; 1980 } 1981 1982 return -1; 1983 } 1984 1985 static void mark_seamless_boot_stream( 1986 const struct dc *dc, 1987 struct dc_stream_state *stream) 1988 { 1989 struct dc_bios *dcb = dc->ctx->dc_bios; 1990 1991 /* TODO: Check Linux */ 1992 if (dc->config.allow_seamless_boot_optimization && 1993 !dcb->funcs->is_accelerated_mode(dcb)) { 1994 if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing)) 1995 stream->apply_seamless_boot_optimization = true; 1996 } 1997 } 1998 1999 enum dc_status resource_map_pool_resources( 2000 const struct dc *dc, 2001 struct dc_state *context, 2002 struct dc_stream_state *stream) 2003 { 2004 const struct resource_pool *pool = dc->res_pool; 2005 int i; 2006 struct dc_context *dc_ctx = dc->ctx; 2007 struct pipe_ctx *pipe_ctx = NULL; 2008 int pipe_idx = -1; 2009 2010 calculate_phy_pix_clks(stream); 2011 2012 mark_seamless_boot_stream(dc, stream); 2013 2014 if (stream->apply_seamless_boot_optimization) { 2015 pipe_idx = acquire_resource_from_hw_enabled_state( 2016 &context->res_ctx, 2017 pool, 2018 stream); 2019 if (pipe_idx < 0) 2020 /* hw resource was assigned to other stream */ 2021 stream->apply_seamless_boot_optimization = false; 2022 } 2023 2024 if (pipe_idx < 0) 2025 /* acquire new resources */ 2026 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); 2027 2028 #ifdef CONFIG_DRM_AMD_DC_DCN 2029 if (pipe_idx < 0) 2030 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 2031 #endif 2032 2033 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL) 2034 return DC_NO_CONTROLLER_RESOURCE; 2035 2036 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2037 2038 pipe_ctx->stream_res.stream_enc = 2039 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link( 2040 &context->res_ctx, pool, stream); 2041 2042 if (!pipe_ctx->stream_res.stream_enc) 2043 return DC_NO_STREAM_ENC_RESOURCE; 2044 2045 update_stream_engine_usage( 2046 &context->res_ctx, pool, 2047 pipe_ctx->stream_res.stream_enc, 2048 true); 2049 2050 /* TODO: Add check if ASIC support and EDID audio */ 2051 if (!stream->converter_disable_audio && 2052 dc_is_audio_capable_signal(pipe_ctx->stream->signal) && 2053 stream->audio_info.mode_count && stream->audio_info.flags.all) { 2054 pipe_ctx->stream_res.audio = find_first_free_audio( 2055 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version); 2056 2057 /* 2058 * Audio assigned in order first come first get. 2059 * There are asics which has number of audio 2060 * resources less then number of pipes 2061 */ 2062 if (pipe_ctx->stream_res.audio) 2063 update_audio_usage(&context->res_ctx, pool, 2064 pipe_ctx->stream_res.audio, true); 2065 } 2066 2067 /* Add ABM to the resource if on EDP */ 2068 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) { 2069 #if defined(CONFIG_DRM_AMD_DC_DCN) 2070 if (pool->abm) 2071 pipe_ctx->stream_res.abm = pool->abm; 2072 else 2073 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst]; 2074 #else 2075 pipe_ctx->stream_res.abm = pool->abm; 2076 #endif 2077 } 2078 2079 for (i = 0; i < context->stream_count; i++) 2080 if (context->streams[i] == stream) { 2081 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; 2082 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst; 2083 context->stream_status[i].audio_inst = 2084 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; 2085 2086 return DC_OK; 2087 } 2088 2089 DC_ERROR("Stream %p not found in new ctx!\n", stream); 2090 return DC_ERROR_UNEXPECTED; 2091 } 2092 2093 /** 2094 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state 2095 * Is a shallow copy. Increments refcounts on existing streams and planes. 2096 * @dc: copy out of dc->current_state 2097 * @dst_ctx: copy into this 2098 */ 2099 void dc_resource_state_copy_construct_current( 2100 const struct dc *dc, 2101 struct dc_state *dst_ctx) 2102 { 2103 dc_resource_state_copy_construct(dc->current_state, dst_ctx); 2104 } 2105 2106 2107 void dc_resource_state_construct( 2108 const struct dc *dc, 2109 struct dc_state *dst_ctx) 2110 { 2111 dst_ctx->clk_mgr = dc->clk_mgr; 2112 } 2113 2114 2115 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) 2116 { 2117 return dc->res_pool->res_cap->num_dsc > 0; 2118 } 2119 2120 2121 /** 2122 * dc_validate_global_state() - Determine if HW can support a given state 2123 * Checks HW resource availability and bandwidth requirement. 2124 * @dc: dc struct for this driver 2125 * @new_ctx: state to be validated 2126 * @fast_validate: set to true if only yes/no to support matters 2127 * 2128 * Return: DC_OK if the result can be programmed. Otherwise, an error code. 2129 */ 2130 enum dc_status dc_validate_global_state( 2131 struct dc *dc, 2132 struct dc_state *new_ctx, 2133 bool fast_validate) 2134 { 2135 enum dc_status result = DC_ERROR_UNEXPECTED; 2136 int i, j; 2137 2138 if (!new_ctx) 2139 return DC_ERROR_UNEXPECTED; 2140 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2141 2142 /* 2143 * Update link encoder to stream assignment. 2144 * TODO: Split out reason allocation from validation. 2145 */ 2146 if (dc->res_pool->funcs->link_encs_assign) 2147 dc->res_pool->funcs->link_encs_assign( 2148 dc, new_ctx, new_ctx->streams, new_ctx->stream_count); 2149 #endif 2150 2151 if (dc->res_pool->funcs->validate_global) { 2152 result = dc->res_pool->funcs->validate_global(dc, new_ctx); 2153 if (result != DC_OK) 2154 return result; 2155 } 2156 2157 for (i = 0; i < new_ctx->stream_count; i++) { 2158 struct dc_stream_state *stream = new_ctx->streams[i]; 2159 2160 for (j = 0; j < dc->res_pool->pipe_count; j++) { 2161 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; 2162 2163 if (pipe_ctx->stream != stream) 2164 continue; 2165 2166 if (dc->res_pool->funcs->patch_unknown_plane_state && 2167 pipe_ctx->plane_state && 2168 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { 2169 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); 2170 if (result != DC_OK) 2171 return result; 2172 } 2173 2174 /* Switch to dp clock source only if there is 2175 * no non dp stream that shares the same timing 2176 * with the dp stream. 2177 */ 2178 if (dc_is_dp_signal(pipe_ctx->stream->signal) && 2179 !find_pll_sharable_stream(stream, new_ctx)) { 2180 2181 resource_unreference_clock_source( 2182 &new_ctx->res_ctx, 2183 dc->res_pool, 2184 pipe_ctx->clock_source); 2185 2186 pipe_ctx->clock_source = dc->res_pool->dp_clock_source; 2187 resource_reference_clock_source( 2188 &new_ctx->res_ctx, 2189 dc->res_pool, 2190 pipe_ctx->clock_source); 2191 } 2192 } 2193 } 2194 2195 result = resource_build_scaling_params_for_context(dc, new_ctx); 2196 2197 if (result == DC_OK) 2198 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate)) 2199 result = DC_FAIL_BANDWIDTH_VALIDATE; 2200 2201 return result; 2202 } 2203 2204 static void patch_gamut_packet_checksum( 2205 struct dc_info_packet *gamut_packet) 2206 { 2207 /* For gamut we recalc checksum */ 2208 if (gamut_packet->valid) { 2209 uint8_t chk_sum = 0; 2210 uint8_t *ptr; 2211 uint8_t i; 2212 2213 /*start of the Gamut data. */ 2214 ptr = &gamut_packet->sb[3]; 2215 2216 for (i = 0; i <= gamut_packet->sb[1]; i++) 2217 chk_sum += ptr[i]; 2218 2219 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); 2220 } 2221 } 2222 2223 static void set_avi_info_frame( 2224 struct dc_info_packet *info_packet, 2225 struct pipe_ctx *pipe_ctx) 2226 { 2227 struct dc_stream_state *stream = pipe_ctx->stream; 2228 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; 2229 uint32_t pixel_encoding = 0; 2230 enum scanning_type scan_type = SCANNING_TYPE_NODATA; 2231 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA; 2232 bool itc = false; 2233 uint8_t itc_value = 0; 2234 uint8_t cn0_cn1 = 0; 2235 unsigned int cn0_cn1_value = 0; 2236 uint8_t *check_sum = NULL; 2237 uint8_t byte_index = 0; 2238 union hdmi_info_packet hdmi_info; 2239 union display_content_support support = {0}; 2240 unsigned int vic = pipe_ctx->stream->timing.vic; 2241 enum dc_timing_3d_format format; 2242 2243 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet)); 2244 2245 color_space = pipe_ctx->stream->output_color_space; 2246 if (color_space == COLOR_SPACE_UNKNOWN) 2247 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? 2248 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; 2249 2250 /* Initialize header */ 2251 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI; 2252 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall 2253 * not be used in HDMI 2.0 (Section 10.1) */ 2254 hdmi_info.bits.header.version = 2; 2255 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE; 2256 2257 /* 2258 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built 2259 * according to HDMI 2.0 spec (Section 10.1) 2260 */ 2261 2262 switch (stream->timing.pixel_encoding) { 2263 case PIXEL_ENCODING_YCBCR422: 2264 pixel_encoding = 1; 2265 break; 2266 2267 case PIXEL_ENCODING_YCBCR444: 2268 pixel_encoding = 2; 2269 break; 2270 case PIXEL_ENCODING_YCBCR420: 2271 pixel_encoding = 3; 2272 break; 2273 2274 case PIXEL_ENCODING_RGB: 2275 default: 2276 pixel_encoding = 0; 2277 } 2278 2279 /* Y0_Y1_Y2 : The pixel encoding */ 2280 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ 2281 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding; 2282 2283 /* A0 = 1 Active Format Information valid */ 2284 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID; 2285 2286 /* B0, B1 = 3; Bar info data is valid */ 2287 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID; 2288 2289 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM; 2290 2291 /* S0, S1 : Underscan / Overscan */ 2292 /* TODO: un-hardcode scan type */ 2293 scan_type = SCANNING_TYPE_UNDERSCAN; 2294 hdmi_info.bits.S0_S1 = scan_type; 2295 2296 /* C0, C1 : Colorimetry */ 2297 if (color_space == COLOR_SPACE_YCBCR709 || 2298 color_space == COLOR_SPACE_YCBCR709_LIMITED) 2299 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709; 2300 else if (color_space == COLOR_SPACE_YCBCR601 || 2301 color_space == COLOR_SPACE_YCBCR601_LIMITED) 2302 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601; 2303 else { 2304 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA; 2305 } 2306 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE || 2307 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE || 2308 color_space == COLOR_SPACE_2020_YCBCR) { 2309 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR; 2310 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 2311 } else if (color_space == COLOR_SPACE_ADOBERGB) { 2312 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB; 2313 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 2314 } 2315 2316 /* TODO: un-hardcode aspect ratio */ 2317 aspect = stream->timing.aspect_ratio; 2318 2319 switch (aspect) { 2320 case ASPECT_RATIO_4_3: 2321 case ASPECT_RATIO_16_9: 2322 hdmi_info.bits.M0_M1 = aspect; 2323 break; 2324 2325 case ASPECT_RATIO_NO_DATA: 2326 case ASPECT_RATIO_64_27: 2327 case ASPECT_RATIO_256_135: 2328 default: 2329 hdmi_info.bits.M0_M1 = 0; 2330 } 2331 2332 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */ 2333 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE; 2334 2335 /* TODO: un-hardcode cn0_cn1 and itc */ 2336 2337 cn0_cn1 = 0; 2338 cn0_cn1_value = 0; 2339 2340 itc = true; 2341 itc_value = 1; 2342 2343 support = stream->content_support; 2344 2345 if (itc) { 2346 if (!support.bits.valid_content_type) { 2347 cn0_cn1_value = 0; 2348 } else { 2349 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) { 2350 if (support.bits.graphics_content == 1) { 2351 cn0_cn1_value = 0; 2352 } 2353 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) { 2354 if (support.bits.photo_content == 1) { 2355 cn0_cn1_value = 1; 2356 } else { 2357 cn0_cn1_value = 0; 2358 itc_value = 0; 2359 } 2360 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) { 2361 if (support.bits.cinema_content == 1) { 2362 cn0_cn1_value = 2; 2363 } else { 2364 cn0_cn1_value = 0; 2365 itc_value = 0; 2366 } 2367 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) { 2368 if (support.bits.game_content == 1) { 2369 cn0_cn1_value = 3; 2370 } else { 2371 cn0_cn1_value = 0; 2372 itc_value = 0; 2373 } 2374 } 2375 } 2376 hdmi_info.bits.CN0_CN1 = cn0_cn1_value; 2377 hdmi_info.bits.ITC = itc_value; 2378 } 2379 2380 if (stream->qs_bit == 1) { 2381 if (color_space == COLOR_SPACE_SRGB || 2382 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) 2383 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; 2384 else if (color_space == COLOR_SPACE_SRGB_LIMITED || 2385 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) 2386 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE; 2387 else 2388 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2389 } else 2390 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2391 2392 /* TODO : We should handle YCC quantization */ 2393 /* but we do not have matrix calculation */ 2394 if (stream->qy_bit == 1) { 2395 if (color_space == COLOR_SPACE_SRGB || 2396 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) 2397 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2398 else if (color_space == COLOR_SPACE_SRGB_LIMITED || 2399 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) 2400 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2401 else 2402 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2403 } else 2404 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2405 2406 ///VIC 2407 format = stream->timing.timing_3d_format; 2408 /*todo, add 3DStereo support*/ 2409 if (format != TIMING_3D_FORMAT_NONE) { 2410 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled 2411 switch (pipe_ctx->stream->timing.hdmi_vic) { 2412 case 1: 2413 vic = 95; 2414 break; 2415 case 2: 2416 vic = 94; 2417 break; 2418 case 3: 2419 vic = 93; 2420 break; 2421 case 4: 2422 vic = 98; 2423 break; 2424 default: 2425 break; 2426 } 2427 } 2428 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/ 2429 hdmi_info.bits.VIC0_VIC7 = vic; 2430 if (vic >= 128) 2431 hdmi_info.bits.header.version = 3; 2432 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1), 2433 * the Source shall use 20 AVI InfoFrame Version 4 2434 */ 2435 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED && 2436 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) { 2437 hdmi_info.bits.header.version = 4; 2438 hdmi_info.bits.header.length = 14; 2439 } 2440 2441 /* pixel repetition 2442 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel 2443 * repetition start from 1 */ 2444 hdmi_info.bits.PR0_PR3 = 0; 2445 2446 /* Bar Info 2447 * barTop: Line Number of End of Top Bar. 2448 * barBottom: Line Number of Start of Bottom Bar. 2449 * barLeft: Pixel Number of End of Left Bar. 2450 * barRight: Pixel Number of Start of Right Bar. */ 2451 hdmi_info.bits.bar_top = stream->timing.v_border_top; 2452 hdmi_info.bits.bar_bottom = (stream->timing.v_total 2453 - stream->timing.v_border_bottom + 1); 2454 hdmi_info.bits.bar_left = stream->timing.h_border_left; 2455 hdmi_info.bits.bar_right = (stream->timing.h_total 2456 - stream->timing.h_border_right + 1); 2457 2458 /* Additional Colorimetry Extension 2459 * Used in conduction with C0-C1 and EC0-EC2 2460 * 0 = DCI-P3 RGB (D65) 2461 * 1 = DCI-P3 RGB (theater) 2462 */ 2463 hdmi_info.bits.ACE0_ACE3 = 0; 2464 2465 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ 2466 check_sum = &hdmi_info.packet_raw_data.sb[0]; 2467 2468 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version; 2469 2470 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++) 2471 *check_sum += hdmi_info.packet_raw_data.sb[byte_index]; 2472 2473 /* one byte complement */ 2474 *check_sum = (uint8_t) (0x100 - *check_sum); 2475 2476 /* Store in hw_path_mode */ 2477 info_packet->hb0 = hdmi_info.packet_raw_data.hb0; 2478 info_packet->hb1 = hdmi_info.packet_raw_data.hb1; 2479 info_packet->hb2 = hdmi_info.packet_raw_data.hb2; 2480 2481 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++) 2482 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index]; 2483 2484 info_packet->valid = true; 2485 } 2486 2487 static void set_vendor_info_packet( 2488 struct dc_info_packet *info_packet, 2489 struct dc_stream_state *stream) 2490 { 2491 /* SPD info packet for FreeSync */ 2492 2493 /* Check if Freesync is supported. Return if false. If true, 2494 * set the corresponding bit in the info packet 2495 */ 2496 if (!stream->vsp_infopacket.valid) 2497 return; 2498 2499 *info_packet = stream->vsp_infopacket; 2500 } 2501 2502 static void set_spd_info_packet( 2503 struct dc_info_packet *info_packet, 2504 struct dc_stream_state *stream) 2505 { 2506 /* SPD info packet for FreeSync */ 2507 2508 /* Check if Freesync is supported. Return if false. If true, 2509 * set the corresponding bit in the info packet 2510 */ 2511 if (!stream->vrr_infopacket.valid) 2512 return; 2513 2514 *info_packet = stream->vrr_infopacket; 2515 } 2516 2517 static void set_hdr_static_info_packet( 2518 struct dc_info_packet *info_packet, 2519 struct dc_stream_state *stream) 2520 { 2521 /* HDR Static Metadata info packet for HDR10 */ 2522 2523 if (!stream->hdr_static_metadata.valid || 2524 stream->use_dynamic_meta) 2525 return; 2526 2527 *info_packet = stream->hdr_static_metadata; 2528 } 2529 2530 static void set_vsc_info_packet( 2531 struct dc_info_packet *info_packet, 2532 struct dc_stream_state *stream) 2533 { 2534 if (!stream->vsc_infopacket.valid) 2535 return; 2536 2537 *info_packet = stream->vsc_infopacket; 2538 } 2539 2540 void dc_resource_state_destruct(struct dc_state *context) 2541 { 2542 int i, j; 2543 2544 for (i = 0; i < context->stream_count; i++) { 2545 for (j = 0; j < context->stream_status[i].plane_count; j++) 2546 dc_plane_state_release( 2547 context->stream_status[i].plane_states[j]); 2548 2549 context->stream_status[i].plane_count = 0; 2550 dc_stream_release(context->streams[i]); 2551 context->streams[i] = NULL; 2552 } 2553 context->stream_count = 0; 2554 } 2555 2556 void dc_resource_state_copy_construct( 2557 const struct dc_state *src_ctx, 2558 struct dc_state *dst_ctx) 2559 { 2560 int i, j; 2561 struct kref refcount = dst_ctx->refcount; 2562 2563 *dst_ctx = *src_ctx; 2564 2565 for (i = 0; i < MAX_PIPES; i++) { 2566 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; 2567 2568 if (cur_pipe->top_pipe) 2569 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; 2570 2571 if (cur_pipe->bottom_pipe) 2572 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; 2573 2574 if (cur_pipe->next_odm_pipe) 2575 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; 2576 2577 if (cur_pipe->prev_odm_pipe) 2578 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; 2579 } 2580 2581 for (i = 0; i < dst_ctx->stream_count; i++) { 2582 dc_stream_retain(dst_ctx->streams[i]); 2583 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) 2584 dc_plane_state_retain( 2585 dst_ctx->stream_status[i].plane_states[j]); 2586 } 2587 2588 /* context refcount should not be overridden */ 2589 dst_ctx->refcount = refcount; 2590 2591 } 2592 2593 struct clock_source *dc_resource_find_first_free_pll( 2594 struct resource_context *res_ctx, 2595 const struct resource_pool *pool) 2596 { 2597 int i; 2598 2599 for (i = 0; i < pool->clk_src_count; ++i) { 2600 if (res_ctx->clock_source_ref_count[i] == 0) 2601 return pool->clock_sources[i]; 2602 } 2603 2604 return NULL; 2605 } 2606 2607 void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 2608 { 2609 enum signal_type signal = SIGNAL_TYPE_NONE; 2610 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; 2611 2612 /* default all packets to invalid */ 2613 info->avi.valid = false; 2614 info->gamut.valid = false; 2615 info->vendor.valid = false; 2616 info->spd.valid = false; 2617 info->hdrsmd.valid = false; 2618 info->vsc.valid = false; 2619 2620 signal = pipe_ctx->stream->signal; 2621 2622 /* HDMi and DP have different info packets*/ 2623 if (dc_is_hdmi_signal(signal)) { 2624 set_avi_info_frame(&info->avi, pipe_ctx); 2625 2626 set_vendor_info_packet(&info->vendor, pipe_ctx->stream); 2627 2628 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2629 2630 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 2631 2632 } else if (dc_is_dp_signal(signal)) { 2633 set_vsc_info_packet(&info->vsc, pipe_ctx->stream); 2634 2635 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2636 2637 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 2638 } 2639 2640 patch_gamut_packet_checksum(&info->gamut); 2641 } 2642 2643 enum dc_status resource_map_clock_resources( 2644 const struct dc *dc, 2645 struct dc_state *context, 2646 struct dc_stream_state *stream) 2647 { 2648 /* acquire new resources */ 2649 const struct resource_pool *pool = dc->res_pool; 2650 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 2651 &context->res_ctx, stream); 2652 2653 if (!pipe_ctx) 2654 return DC_ERROR_UNEXPECTED; 2655 2656 if (dc_is_dp_signal(pipe_ctx->stream->signal) 2657 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 2658 pipe_ctx->clock_source = pool->dp_clock_source; 2659 else { 2660 pipe_ctx->clock_source = NULL; 2661 2662 if (!dc->config.disable_disp_pll_sharing) 2663 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing( 2664 &context->res_ctx, 2665 pipe_ctx); 2666 2667 if (pipe_ctx->clock_source == NULL) 2668 pipe_ctx->clock_source = 2669 dc_resource_find_first_free_pll( 2670 &context->res_ctx, 2671 pool); 2672 } 2673 2674 if (pipe_ctx->clock_source == NULL) 2675 return DC_NO_CLOCK_SOURCE_RESOURCE; 2676 2677 resource_reference_clock_source( 2678 &context->res_ctx, pool, 2679 pipe_ctx->clock_source); 2680 2681 return DC_OK; 2682 } 2683 2684 /* 2685 * Note: We need to disable output if clock sources change, 2686 * since bios does optimization and doesn't apply if changing 2687 * PHY when not already disabled. 2688 */ 2689 bool pipe_need_reprogram( 2690 struct pipe_ctx *pipe_ctx_old, 2691 struct pipe_ctx *pipe_ctx) 2692 { 2693 if (!pipe_ctx_old->stream) 2694 return false; 2695 2696 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) 2697 return true; 2698 2699 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) 2700 return true; 2701 2702 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) 2703 return true; 2704 2705 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source 2706 && pipe_ctx_old->stream != pipe_ctx->stream) 2707 return true; 2708 2709 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) 2710 return true; 2711 2712 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) 2713 return true; 2714 2715 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off) 2716 return true; 2717 2718 if (false == pipe_ctx_old->stream->link->link_state_valid && 2719 false == pipe_ctx_old->stream->dpms_off) 2720 return true; 2721 2722 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) 2723 return true; 2724 2725 /* DIG link encoder resource assignment for stream changed. */ 2726 if (pipe_ctx_old->stream->link_enc != pipe_ctx->stream->link_enc) 2727 return true; 2728 2729 return false; 2730 } 2731 2732 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 2733 struct bit_depth_reduction_params *fmt_bit_depth) 2734 { 2735 enum dc_dither_option option = stream->dither_option; 2736 enum dc_pixel_encoding pixel_encoding = 2737 stream->timing.pixel_encoding; 2738 2739 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); 2740 2741 if (option == DITHER_OPTION_DEFAULT) { 2742 switch (stream->timing.display_color_depth) { 2743 case COLOR_DEPTH_666: 2744 option = DITHER_OPTION_SPATIAL6; 2745 break; 2746 case COLOR_DEPTH_888: 2747 option = DITHER_OPTION_SPATIAL8; 2748 break; 2749 case COLOR_DEPTH_101010: 2750 option = DITHER_OPTION_SPATIAL10; 2751 break; 2752 default: 2753 option = DITHER_OPTION_DISABLE; 2754 } 2755 } 2756 2757 if (option == DITHER_OPTION_DISABLE) 2758 return; 2759 2760 if (option == DITHER_OPTION_TRUN6) { 2761 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2762 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; 2763 } else if (option == DITHER_OPTION_TRUN8 || 2764 option == DITHER_OPTION_TRUN8_SPATIAL6 || 2765 option == DITHER_OPTION_TRUN8_FM6) { 2766 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2767 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; 2768 } else if (option == DITHER_OPTION_TRUN10 || 2769 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2770 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2771 option == DITHER_OPTION_TRUN10_FM8 || 2772 option == DITHER_OPTION_TRUN10_FM6 || 2773 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2774 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2775 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2776 } 2777 2778 /* special case - Formatter can only reduce by 4 bits at most. 2779 * When reducing from 12 to 6 bits, 2780 * HW recommends we use trunc with round mode 2781 * (if we did nothing, trunc to 10 bits would be used) 2782 * note that any 12->10 bit reduction is ignored prior to DCE8, 2783 * as the input was 10 bits. 2784 */ 2785 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2786 option == DITHER_OPTION_SPATIAL6 || 2787 option == DITHER_OPTION_FM6) { 2788 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2789 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2790 fmt_bit_depth->flags.TRUNCATE_MODE = 1; 2791 } 2792 2793 /* spatial dither 2794 * note that spatial modes 1-3 are never used 2795 */ 2796 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2797 option == DITHER_OPTION_SPATIAL6 || 2798 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2799 option == DITHER_OPTION_TRUN8_SPATIAL6) { 2800 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2801 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; 2802 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2803 fmt_bit_depth->flags.RGB_RANDOM = 2804 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2805 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || 2806 option == DITHER_OPTION_SPATIAL8 || 2807 option == DITHER_OPTION_SPATIAL8_FM6 || 2808 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2809 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2810 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2811 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; 2812 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2813 fmt_bit_depth->flags.RGB_RANDOM = 2814 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2815 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || 2816 option == DITHER_OPTION_SPATIAL10 || 2817 option == DITHER_OPTION_SPATIAL10_FM8 || 2818 option == DITHER_OPTION_SPATIAL10_FM6) { 2819 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2820 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; 2821 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2822 fmt_bit_depth->flags.RGB_RANDOM = 2823 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2824 } 2825 2826 if (option == DITHER_OPTION_SPATIAL6 || 2827 option == DITHER_OPTION_SPATIAL8 || 2828 option == DITHER_OPTION_SPATIAL10) { 2829 fmt_bit_depth->flags.FRAME_RANDOM = 0; 2830 } else { 2831 fmt_bit_depth->flags.FRAME_RANDOM = 1; 2832 } 2833 2834 ////////////////////// 2835 //// temporal dither 2836 ////////////////////// 2837 if (option == DITHER_OPTION_FM6 || 2838 option == DITHER_OPTION_SPATIAL8_FM6 || 2839 option == DITHER_OPTION_SPATIAL10_FM6 || 2840 option == DITHER_OPTION_TRUN10_FM6 || 2841 option == DITHER_OPTION_TRUN8_FM6 || 2842 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2843 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2844 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; 2845 } else if (option == DITHER_OPTION_FM8 || 2846 option == DITHER_OPTION_SPATIAL10_FM8 || 2847 option == DITHER_OPTION_TRUN10_FM8) { 2848 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2849 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; 2850 } else if (option == DITHER_OPTION_FM10) { 2851 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2852 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; 2853 } 2854 2855 fmt_bit_depth->pixel_encoding = pixel_encoding; 2856 } 2857 2858 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) 2859 { 2860 struct dc_link *link = stream->link; 2861 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 2862 enum dc_status res = DC_OK; 2863 2864 calculate_phy_pix_clks(stream); 2865 2866 if (!tg->funcs->validate_timing(tg, &stream->timing)) 2867 res = DC_FAIL_CONTROLLER_VALIDATE; 2868 2869 if (res == DC_OK) { 2870 if (!link->link_enc->funcs->validate_output_with_stream( 2871 link->link_enc, stream)) 2872 res = DC_FAIL_ENC_VALIDATE; 2873 } 2874 2875 /* TODO: validate audio ASIC caps, encoder */ 2876 2877 if (res == DC_OK) 2878 res = dc_link_validate_mode_timing(stream, 2879 link, 2880 &stream->timing); 2881 2882 return res; 2883 } 2884 2885 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) 2886 { 2887 enum dc_status res = DC_OK; 2888 2889 /* TODO For now validates pixel format only */ 2890 if (dc->res_pool->funcs->validate_plane) 2891 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps); 2892 2893 return res; 2894 } 2895 2896 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format) 2897 { 2898 switch (format) { 2899 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 2900 return 8; 2901 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 2902 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 2903 return 12; 2904 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 2905 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 2906 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 2907 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 2908 return 16; 2909 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 2910 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 2911 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 2912 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 2913 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 2914 #if defined(CONFIG_DRM_AMD_DC_DCN) 2915 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 2916 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 2917 #endif 2918 return 32; 2919 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 2920 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 2921 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 2922 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 2923 return 64; 2924 default: 2925 ASSERT_CRITICAL(false); 2926 return -1; 2927 } 2928 } 2929 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes) 2930 { 2931 if (modes) { 2932 if (modes->sample_rates.rate.RATE_192) 2933 return 192000; 2934 if (modes->sample_rates.rate.RATE_176_4) 2935 return 176400; 2936 if (modes->sample_rates.rate.RATE_96) 2937 return 96000; 2938 if (modes->sample_rates.rate.RATE_88_2) 2939 return 88200; 2940 if (modes->sample_rates.rate.RATE_48) 2941 return 48000; 2942 if (modes->sample_rates.rate.RATE_44_1) 2943 return 44100; 2944 if (modes->sample_rates.rate.RATE_32) 2945 return 32000; 2946 } 2947 /*original logic when no audio info*/ 2948 return 441000; 2949 } 2950 2951 void get_audio_check(struct audio_info *aud_modes, 2952 struct audio_check *audio_chk) 2953 { 2954 unsigned int i; 2955 unsigned int max_sample_rate = 0; 2956 2957 if (aud_modes) { 2958 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/ 2959 2960 audio_chk->max_audiosample_rate = 0; 2961 for (i = 0; i < aud_modes->mode_count; i++) { 2962 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]); 2963 if (audio_chk->max_audiosample_rate < max_sample_rate) 2964 audio_chk->max_audiosample_rate = max_sample_rate; 2965 /*dts takes the same as type 2: AP = 0.25*/ 2966 } 2967 /*check which one take more bandwidth*/ 2968 if (audio_chk->max_audiosample_rate > 192000) 2969 audio_chk->audio_packet_type = 0x9;/*AP =1*/ 2970 audio_chk->acat = 0;/*not support*/ 2971 } 2972 } 2973 2974