1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include "dm_services.h" 26 27 #include "resource.h" 28 #include "include/irq_service_interface.h" 29 #include "link_encoder.h" 30 #include "stream_encoder.h" 31 #include "opp.h" 32 #include "timing_generator.h" 33 #include "transform.h" 34 #include "dpp.h" 35 #include "core_types.h" 36 #include "set_mode_types.h" 37 #include "virtual/virtual_stream_encoder.h" 38 39 #include "dce80/dce80_resource.h" 40 #include "dce100/dce100_resource.h" 41 #include "dce110/dce110_resource.h" 42 #include "dce112/dce112_resource.h" 43 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 44 #include "dcn10/dcn10_resource.h" 45 #endif 46 #include "dce120/dce120_resource.h" 47 48 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 49 { 50 enum dce_version dc_version = DCE_VERSION_UNKNOWN; 51 switch (asic_id.chip_family) { 52 53 case FAMILY_CI: 54 dc_version = DCE_VERSION_8_0; 55 break; 56 case FAMILY_KV: 57 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) || 58 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) || 59 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev)) 60 dc_version = DCE_VERSION_8_3; 61 else 62 dc_version = DCE_VERSION_8_1; 63 break; 64 case FAMILY_CZ: 65 dc_version = DCE_VERSION_11_0; 66 break; 67 68 case FAMILY_VI: 69 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || 70 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { 71 dc_version = DCE_VERSION_10_0; 72 break; 73 } 74 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || 75 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || 76 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { 77 dc_version = DCE_VERSION_11_2; 78 } 79 break; 80 case FAMILY_AI: 81 dc_version = DCE_VERSION_12_0; 82 break; 83 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 84 case FAMILY_RV: 85 dc_version = DCN_VERSION_1_0; 86 break; 87 #endif 88 default: 89 dc_version = DCE_VERSION_UNKNOWN; 90 break; 91 } 92 return dc_version; 93 } 94 95 struct resource_pool *dc_create_resource_pool( 96 struct dc *dc, 97 int num_virtual_links, 98 enum dce_version dc_version, 99 struct hw_asic_id asic_id) 100 { 101 struct resource_pool *res_pool = NULL; 102 103 switch (dc_version) { 104 case DCE_VERSION_8_0: 105 res_pool = dce80_create_resource_pool( 106 num_virtual_links, dc); 107 break; 108 case DCE_VERSION_8_1: 109 res_pool = dce81_create_resource_pool( 110 num_virtual_links, dc); 111 break; 112 case DCE_VERSION_8_3: 113 res_pool = dce83_create_resource_pool( 114 num_virtual_links, dc); 115 break; 116 case DCE_VERSION_10_0: 117 res_pool = dce100_create_resource_pool( 118 num_virtual_links, dc); 119 break; 120 case DCE_VERSION_11_0: 121 res_pool = dce110_create_resource_pool( 122 num_virtual_links, dc, asic_id); 123 break; 124 case DCE_VERSION_11_2: 125 res_pool = dce112_create_resource_pool( 126 num_virtual_links, dc); 127 break; 128 case DCE_VERSION_12_0: 129 res_pool = dce120_create_resource_pool( 130 num_virtual_links, dc); 131 break; 132 133 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 134 case DCN_VERSION_1_0: 135 res_pool = dcn10_create_resource_pool( 136 num_virtual_links, dc); 137 break; 138 #endif 139 140 141 default: 142 break; 143 } 144 if (res_pool != NULL) { 145 struct dc_firmware_info fw_info = { { 0 } }; 146 147 if (dc->ctx->dc_bios->funcs->get_firmware_info( 148 dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) { 149 res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency; 150 } else 151 ASSERT_CRITICAL(false); 152 } 153 154 return res_pool; 155 } 156 157 void dc_destroy_resource_pool(struct dc *dc) 158 { 159 if (dc) { 160 if (dc->res_pool) 161 dc->res_pool->funcs->destroy(&dc->res_pool); 162 163 kfree(dc->hwseq); 164 } 165 } 166 167 static void update_num_audio( 168 const struct resource_straps *straps, 169 unsigned int *num_audio, 170 struct audio_support *aud_support) 171 { 172 aud_support->dp_audio = true; 173 aud_support->hdmi_audio_native = false; 174 aud_support->hdmi_audio_on_dongle = false; 175 176 if (straps->hdmi_disable == 0) { 177 if (straps->dc_pinstraps_audio & 0x2) { 178 aud_support->hdmi_audio_on_dongle = true; 179 aud_support->hdmi_audio_native = true; 180 } 181 } 182 183 switch (straps->audio_stream_number) { 184 case 0: /* multi streams supported */ 185 break; 186 case 1: /* multi streams not supported */ 187 *num_audio = 1; 188 break; 189 default: 190 DC_ERR("DC: unexpected audio fuse!\n"); 191 } 192 } 193 194 bool resource_construct( 195 unsigned int num_virtual_links, 196 struct dc *dc, 197 struct resource_pool *pool, 198 const struct resource_create_funcs *create_funcs) 199 { 200 struct dc_context *ctx = dc->ctx; 201 const struct resource_caps *caps = pool->res_cap; 202 int i; 203 unsigned int num_audio = caps->num_audio; 204 struct resource_straps straps = {0}; 205 206 if (create_funcs->read_dce_straps) 207 create_funcs->read_dce_straps(dc->ctx, &straps); 208 209 pool->audio_count = 0; 210 if (create_funcs->create_audio) { 211 /* find the total number of streams available via the 212 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 213 * registers (one for each pin) starting from pin 1 214 * up to the max number of audio pins. 215 * We stop on the first pin where 216 * PORT_CONNECTIVITY == 1 (as instructed by HW team). 217 */ 218 update_num_audio(&straps, &num_audio, &pool->audio_support); 219 for (i = 0; i < pool->pipe_count && i < num_audio; i++) { 220 struct audio *aud = create_funcs->create_audio(ctx, i); 221 222 if (aud == NULL) { 223 DC_ERR("DC: failed to create audio!\n"); 224 return false; 225 } 226 227 if (!aud->funcs->endpoint_valid(aud)) { 228 aud->funcs->destroy(&aud); 229 break; 230 } 231 232 pool->audios[i] = aud; 233 pool->audio_count++; 234 } 235 } 236 237 pool->stream_enc_count = 0; 238 if (create_funcs->create_stream_encoder) { 239 for (i = 0; i < caps->num_stream_encoder; i++) { 240 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); 241 if (pool->stream_enc[i] == NULL) 242 DC_ERR("DC: failed to create stream_encoder!\n"); 243 pool->stream_enc_count++; 244 } 245 } 246 dc->caps.dynamic_audio = false; 247 if (pool->audio_count < pool->stream_enc_count) { 248 dc->caps.dynamic_audio = true; 249 } 250 for (i = 0; i < num_virtual_links; i++) { 251 pool->stream_enc[pool->stream_enc_count] = 252 virtual_stream_encoder_create( 253 ctx, ctx->dc_bios); 254 if (pool->stream_enc[pool->stream_enc_count] == NULL) { 255 DC_ERR("DC: failed to create stream_encoder!\n"); 256 return false; 257 } 258 pool->stream_enc_count++; 259 } 260 261 dc->hwseq = create_funcs->create_hwseq(ctx); 262 263 return true; 264 } 265 266 267 void resource_unreference_clock_source( 268 struct resource_context *res_ctx, 269 const struct resource_pool *pool, 270 struct clock_source *clock_source) 271 { 272 int i; 273 274 for (i = 0; i < pool->clk_src_count; i++) { 275 if (pool->clock_sources[i] != clock_source) 276 continue; 277 278 res_ctx->clock_source_ref_count[i]--; 279 280 break; 281 } 282 283 if (pool->dp_clock_source == clock_source) 284 res_ctx->dp_clock_source_ref_count--; 285 } 286 287 void resource_reference_clock_source( 288 struct resource_context *res_ctx, 289 const struct resource_pool *pool, 290 struct clock_source *clock_source) 291 { 292 int i; 293 for (i = 0; i < pool->clk_src_count; i++) { 294 if (pool->clock_sources[i] != clock_source) 295 continue; 296 297 res_ctx->clock_source_ref_count[i]++; 298 break; 299 } 300 301 if (pool->dp_clock_source == clock_source) 302 res_ctx->dp_clock_source_ref_count++; 303 } 304 305 bool resource_are_streams_timing_synchronizable( 306 struct dc_stream_state *stream1, 307 struct dc_stream_state *stream2) 308 { 309 if (stream1->timing.h_total != stream2->timing.h_total) 310 return false; 311 312 if (stream1->timing.v_total != stream2->timing.v_total) 313 return false; 314 315 if (stream1->timing.h_addressable 316 != stream2->timing.h_addressable) 317 return false; 318 319 if (stream1->timing.v_addressable 320 != stream2->timing.v_addressable) 321 return false; 322 323 if (stream1->timing.pix_clk_khz 324 != stream2->timing.pix_clk_khz) 325 return false; 326 327 if (stream1->phy_pix_clk != stream2->phy_pix_clk 328 && (!dc_is_dp_signal(stream1->signal) 329 || !dc_is_dp_signal(stream2->signal))) 330 return false; 331 332 return true; 333 } 334 335 static bool is_sharable_clk_src( 336 const struct pipe_ctx *pipe_with_clk_src, 337 const struct pipe_ctx *pipe) 338 { 339 if (pipe_with_clk_src->clock_source == NULL) 340 return false; 341 342 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) 343 return false; 344 345 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal)) 346 return false; 347 348 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) 349 && dc_is_dvi_signal(pipe->stream->signal)) 350 return false; 351 352 if (dc_is_hdmi_signal(pipe->stream->signal) 353 && dc_is_dvi_signal(pipe_with_clk_src->stream->signal)) 354 return false; 355 356 if (!resource_are_streams_timing_synchronizable( 357 pipe_with_clk_src->stream, pipe->stream)) 358 return false; 359 360 return true; 361 } 362 363 struct clock_source *resource_find_used_clk_src_for_sharing( 364 struct resource_context *res_ctx, 365 struct pipe_ctx *pipe_ctx) 366 { 367 int i; 368 369 for (i = 0; i < MAX_PIPES; i++) { 370 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) 371 return res_ctx->pipe_ctx[i].clock_source; 372 } 373 374 return NULL; 375 } 376 377 static enum pixel_format convert_pixel_format_to_dalsurface( 378 enum surface_pixel_format surface_pixel_format) 379 { 380 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 381 382 switch (surface_pixel_format) { 383 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 384 dal_pixel_format = PIXEL_FORMAT_INDEX8; 385 break; 386 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 387 dal_pixel_format = PIXEL_FORMAT_RGB565; 388 break; 389 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 390 dal_pixel_format = PIXEL_FORMAT_RGB565; 391 break; 392 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 393 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 394 break; 395 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 396 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 397 break; 398 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 399 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 400 break; 401 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 402 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 403 break; 404 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 405 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS; 406 break; 407 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 408 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 409 dal_pixel_format = PIXEL_FORMAT_FP16; 410 break; 411 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 412 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 413 dal_pixel_format = PIXEL_FORMAT_420BPP8; 414 break; 415 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 416 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 417 dal_pixel_format = PIXEL_FORMAT_420BPP10; 418 break; 419 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 420 default: 421 dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 422 break; 423 } 424 return dal_pixel_format; 425 } 426 427 static void rect_swap_helper(struct rect *rect) 428 { 429 uint32_t temp = 0; 430 431 temp = rect->height; 432 rect->height = rect->width; 433 rect->width = temp; 434 435 temp = rect->x; 436 rect->x = rect->y; 437 rect->y = temp; 438 } 439 440 static void calculate_viewport(struct pipe_ctx *pipe_ctx) 441 { 442 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 443 const struct dc_stream_state *stream = pipe_ctx->stream; 444 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 445 struct rect surf_src = plane_state->src_rect; 446 struct rect clip = { 0 }; 447 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 448 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 449 bool pri_split = pipe_ctx->bottom_pipe && 450 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state; 451 bool sec_split = pipe_ctx->top_pipe && 452 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 453 454 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || 455 stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { 456 pri_split = false; 457 sec_split = false; 458 } 459 460 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 461 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 462 rect_swap_helper(&surf_src); 463 464 /* The actual clip is an intersection between stream 465 * source and surface clip 466 */ 467 clip.x = stream->src.x > plane_state->clip_rect.x ? 468 stream->src.x : plane_state->clip_rect.x; 469 470 clip.width = stream->src.x + stream->src.width < 471 plane_state->clip_rect.x + plane_state->clip_rect.width ? 472 stream->src.x + stream->src.width - clip.x : 473 plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ; 474 475 clip.y = stream->src.y > plane_state->clip_rect.y ? 476 stream->src.y : plane_state->clip_rect.y; 477 478 clip.height = stream->src.y + stream->src.height < 479 plane_state->clip_rect.y + plane_state->clip_rect.height ? 480 stream->src.y + stream->src.height - clip.y : 481 plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ; 482 483 /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio 484 * num_pixels = clip.num_pix * scl_ratio 485 */ 486 data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) * 487 surf_src.width / plane_state->dst_rect.width; 488 data->viewport.width = clip.width * 489 surf_src.width / plane_state->dst_rect.width; 490 491 data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) * 492 surf_src.height / plane_state->dst_rect.height; 493 data->viewport.height = clip.height * 494 surf_src.height / plane_state->dst_rect.height; 495 496 /* Round down, compensate in init */ 497 data->viewport_c.x = data->viewport.x / vpc_div; 498 data->viewport_c.y = data->viewport.y / vpc_div; 499 data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? 500 dal_fixed31_32_half : dal_fixed31_32_zero; 501 data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? 502 dal_fixed31_32_half : dal_fixed31_32_zero; 503 /* Round up, assume original video size always even dimensions */ 504 data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div; 505 data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div; 506 507 /* Handle hsplit */ 508 if (pri_split || sec_split) { 509 /* HMirror XOR Secondary_pipe XOR Rotation_180 */ 510 bool right_view = (sec_split != plane_state->horizontal_mirror) != 511 (plane_state->rotation == ROTATION_ANGLE_180); 512 513 if (plane_state->rotation == ROTATION_ANGLE_90 514 || plane_state->rotation == ROTATION_ANGLE_270) 515 /* Secondary_pipe XOR Rotation_270 */ 516 right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split; 517 518 if (right_view) { 519 data->viewport.width /= 2; 520 data->viewport_c.width /= 2; 521 data->viewport.x += data->viewport.width; 522 data->viewport_c.x += data->viewport_c.width; 523 /* Ceil offset pipe */ 524 data->viewport.width += data->viewport.width % 2; 525 data->viewport_c.width += data->viewport_c.width % 2; 526 } else { 527 data->viewport.width /= 2; 528 data->viewport_c.width /= 2; 529 } 530 } 531 532 if (plane_state->rotation == ROTATION_ANGLE_90 || 533 plane_state->rotation == ROTATION_ANGLE_270) { 534 rect_swap_helper(&data->viewport_c); 535 rect_swap_helper(&data->viewport); 536 } 537 } 538 539 static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) 540 { 541 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 542 const struct dc_stream_state *stream = pipe_ctx->stream; 543 struct rect surf_src = plane_state->src_rect; 544 struct rect surf_clip = plane_state->clip_rect; 545 int recout_full_x, recout_full_y; 546 547 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 548 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 549 rect_swap_helper(&surf_src); 550 551 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x; 552 if (stream->src.x < surf_clip.x) 553 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x 554 - stream->src.x) * stream->dst.width 555 / stream->src.width; 556 557 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width * 558 stream->dst.width / stream->src.width; 559 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x > 560 stream->dst.x + stream->dst.width) 561 pipe_ctx->plane_res.scl_data.recout.width = 562 stream->dst.x + stream->dst.width 563 - pipe_ctx->plane_res.scl_data.recout.x; 564 565 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y; 566 if (stream->src.y < surf_clip.y) 567 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y 568 - stream->src.y) * stream->dst.height 569 / stream->src.height; 570 571 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height * 572 stream->dst.height / stream->src.height; 573 if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y > 574 stream->dst.y + stream->dst.height) 575 pipe_ctx->plane_res.scl_data.recout.height = 576 stream->dst.y + stream->dst.height 577 - pipe_ctx->plane_res.scl_data.recout.y; 578 579 /* Handle h & vsplit */ 580 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == 581 pipe_ctx->plane_state) { 582 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { 583 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height / 2; 584 /* Floor primary pipe, ceil 2ndary pipe */ 585 pipe_ctx->plane_res.scl_data.recout.height = (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2; 586 } else { 587 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width / 2; 588 pipe_ctx->plane_res.scl_data.recout.width = (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2; 589 } 590 } else if (pipe_ctx->bottom_pipe && 591 pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) { 592 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 593 pipe_ctx->plane_res.scl_data.recout.height /= 2; 594 else 595 pipe_ctx->plane_res.scl_data.recout.width /= 2; 596 } 597 598 /* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset) 599 * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl 600 * ratio) 601 */ 602 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) 603 * stream->dst.width / stream->src.width - 604 surf_src.x * plane_state->dst_rect.width / surf_src.width 605 * stream->dst.width / stream->src.width; 606 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) 607 * stream->dst.height / stream->src.height - 608 surf_src.y * plane_state->dst_rect.height / surf_src.height 609 * stream->dst.height / stream->src.height; 610 611 recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x; 612 recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y; 613 } 614 615 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) 616 { 617 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 618 const struct dc_stream_state *stream = pipe_ctx->stream; 619 struct rect surf_src = plane_state->src_rect; 620 const int in_w = stream->src.width; 621 const int in_h = stream->src.height; 622 const int out_w = stream->dst.width; 623 const int out_h = stream->dst.height; 624 625 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 626 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 627 rect_swap_helper(&surf_src); 628 629 pipe_ctx->plane_res.scl_data.ratios.horz = dal_fixed31_32_from_fraction( 630 surf_src.width, 631 plane_state->dst_rect.width); 632 pipe_ctx->plane_res.scl_data.ratios.vert = dal_fixed31_32_from_fraction( 633 surf_src.height, 634 plane_state->dst_rect.height); 635 636 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 637 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; 638 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 639 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; 640 641 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( 642 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); 643 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( 644 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); 645 646 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; 647 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; 648 649 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 650 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { 651 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; 652 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; 653 } 654 } 655 656 static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip) 657 { 658 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 659 struct rect src = pipe_ctx->plane_state->src_rect; 660 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 661 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 662 663 664 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 665 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { 666 rect_swap_helper(&src); 667 rect_swap_helper(&data->viewport_c); 668 rect_swap_helper(&data->viewport); 669 } 670 671 /* 672 * Init calculated according to formula: 673 * init = (scaling_ratio + number_of_taps + 1) / 2 674 * init_bot = init + scaling_ratio 675 * init_c = init + truncated_vp_c_offset(from calculate viewport) 676 */ 677 data->inits.h = dal_fixed31_32_div_int( 678 dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2); 679 680 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int( 681 dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)); 682 683 data->inits.v = dal_fixed31_32_div_int( 684 dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2); 685 686 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int( 687 dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)); 688 689 690 /* Adjust for viewport end clip-off */ 691 if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) { 692 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x; 693 int int_part = dal_fixed31_32_floor( 694 dal_fixed31_32_sub(data->inits.h, data->ratios.horz)); 695 696 int_part = int_part > 0 ? int_part : 0; 697 data->viewport.width += int_part < vp_clip ? int_part : vp_clip; 698 } 699 if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) { 700 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y; 701 int int_part = dal_fixed31_32_floor( 702 dal_fixed31_32_sub(data->inits.v, data->ratios.vert)); 703 704 int_part = int_part > 0 ? int_part : 0; 705 data->viewport.height += int_part < vp_clip ? int_part : vp_clip; 706 } 707 if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) { 708 int vp_clip = (src.x + src.width) / vpc_div - 709 data->viewport_c.width - data->viewport_c.x; 710 int int_part = dal_fixed31_32_floor( 711 dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c)); 712 713 int_part = int_part > 0 ? int_part : 0; 714 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip; 715 } 716 if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) { 717 int vp_clip = (src.y + src.height) / vpc_div - 718 data->viewport_c.height - data->viewport_c.y; 719 int int_part = dal_fixed31_32_floor( 720 dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c)); 721 722 int_part = int_part > 0 ? int_part : 0; 723 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip; 724 } 725 726 /* Adjust for non-0 viewport offset */ 727 if (data->viewport.x) { 728 int int_part; 729 730 data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int( 731 data->ratios.horz, recout_skip->width)); 732 int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x; 733 if (int_part < data->taps.h_taps) { 734 int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ? 735 (data->taps.h_taps - int_part) : data->viewport.x; 736 data->viewport.x -= int_adj; 737 data->viewport.width += int_adj; 738 int_part += int_adj; 739 } else if (int_part > data->taps.h_taps) { 740 data->viewport.x += int_part - data->taps.h_taps; 741 data->viewport.width -= int_part - data->taps.h_taps; 742 int_part = data->taps.h_taps; 743 } 744 data->inits.h.value &= 0xffffffff; 745 data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part); 746 } 747 748 if (data->viewport_c.x) { 749 int int_part; 750 751 data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int( 752 data->ratios.horz_c, recout_skip->width)); 753 int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x; 754 if (int_part < data->taps.h_taps_c) { 755 int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ? 756 (data->taps.h_taps_c - int_part) : data->viewport_c.x; 757 data->viewport_c.x -= int_adj; 758 data->viewport_c.width += int_adj; 759 int_part += int_adj; 760 } else if (int_part > data->taps.h_taps_c) { 761 data->viewport_c.x += int_part - data->taps.h_taps_c; 762 data->viewport_c.width -= int_part - data->taps.h_taps_c; 763 int_part = data->taps.h_taps_c; 764 } 765 data->inits.h_c.value &= 0xffffffff; 766 data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part); 767 } 768 769 if (data->viewport.y) { 770 int int_part; 771 772 data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int( 773 data->ratios.vert, recout_skip->height)); 774 int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y; 775 if (int_part < data->taps.v_taps) { 776 int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ? 777 (data->taps.v_taps - int_part) : data->viewport.y; 778 data->viewport.y -= int_adj; 779 data->viewport.height += int_adj; 780 int_part += int_adj; 781 } else if (int_part > data->taps.v_taps) { 782 data->viewport.y += int_part - data->taps.v_taps; 783 data->viewport.height -= int_part - data->taps.v_taps; 784 int_part = data->taps.v_taps; 785 } 786 data->inits.v.value &= 0xffffffff; 787 data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part); 788 } 789 790 if (data->viewport_c.y) { 791 int int_part; 792 793 data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int( 794 data->ratios.vert_c, recout_skip->height)); 795 int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y; 796 if (int_part < data->taps.v_taps_c) { 797 int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ? 798 (data->taps.v_taps_c - int_part) : data->viewport_c.y; 799 data->viewport_c.y -= int_adj; 800 data->viewport_c.height += int_adj; 801 int_part += int_adj; 802 } else if (int_part > data->taps.v_taps_c) { 803 data->viewport_c.y += int_part - data->taps.v_taps_c; 804 data->viewport_c.height -= int_part - data->taps.v_taps_c; 805 int_part = data->taps.v_taps_c; 806 } 807 data->inits.v_c.value &= 0xffffffff; 808 data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part); 809 } 810 811 /* Interlaced inits based on final vert inits */ 812 data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert); 813 data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c); 814 815 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 816 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { 817 rect_swap_helper(&data->viewport_c); 818 rect_swap_helper(&data->viewport); 819 } 820 } 821 822 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 823 { 824 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 825 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 826 struct view recout_skip = { 0 }; 827 bool res = false; 828 829 /* Important: scaling ratio calculation requires pixel format, 830 * lb depth calculation requires recout and taps require scaling ratios. 831 * Inits require viewport, taps, ratios and recout of split pipe 832 */ 833 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( 834 pipe_ctx->plane_state->format); 835 836 calculate_scaling_ratios(pipe_ctx); 837 838 calculate_viewport(pipe_ctx); 839 840 if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16) 841 return false; 842 843 calculate_recout(pipe_ctx, &recout_skip); 844 845 /** 846 * Setting line buffer pixel depth to 24bpp yields banding 847 * on certain displays, such as the Sharp 4k 848 */ 849 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; 850 851 pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left; 852 pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top; 853 854 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; 855 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; 856 857 858 /* Taps calculations */ 859 if (pipe_ctx->plane_res.xfm != NULL) 860 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 861 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 862 863 if (pipe_ctx->plane_res.dpp != NULL) 864 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 865 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 866 if (!res) { 867 /* Try 24 bpp linebuffer */ 868 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; 869 870 if (pipe_ctx->plane_res.xfm != NULL) 871 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 872 pipe_ctx->plane_res.xfm, 873 &pipe_ctx->plane_res.scl_data, 874 &plane_state->scaling_quality); 875 876 if (pipe_ctx->plane_res.dpp != NULL) 877 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 878 pipe_ctx->plane_res.dpp, 879 &pipe_ctx->plane_res.scl_data, 880 &plane_state->scaling_quality); 881 } 882 883 if (res) 884 /* May need to re-check lb size after this in some obscure scenario */ 885 calculate_inits_and_adj_vp(pipe_ctx, &recout_skip); 886 887 dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER, 888 "%s: Viewport:\nheight:%d width:%d x:%d " 889 "y:%d\n dst_rect:\nheight:%d width:%d x:%d " 890 "y:%d\n", 891 __func__, 892 pipe_ctx->plane_res.scl_data.viewport.height, 893 pipe_ctx->plane_res.scl_data.viewport.width, 894 pipe_ctx->plane_res.scl_data.viewport.x, 895 pipe_ctx->plane_res.scl_data.viewport.y, 896 plane_state->dst_rect.height, 897 plane_state->dst_rect.width, 898 plane_state->dst_rect.x, 899 plane_state->dst_rect.y); 900 901 return res; 902 } 903 904 905 enum dc_status resource_build_scaling_params_for_context( 906 const struct dc *dc, 907 struct dc_state *context) 908 { 909 int i; 910 911 for (i = 0; i < MAX_PIPES; i++) { 912 if (context->res_ctx.pipe_ctx[i].plane_state != NULL && 913 context->res_ctx.pipe_ctx[i].stream != NULL) 914 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) 915 return DC_FAIL_SCALING; 916 } 917 918 return DC_OK; 919 } 920 921 struct pipe_ctx *find_idle_secondary_pipe( 922 struct resource_context *res_ctx, 923 const struct resource_pool *pool) 924 { 925 int i; 926 struct pipe_ctx *secondary_pipe = NULL; 927 928 /* 929 * search backwards for the second pipe to keep pipe 930 * assignment more consistent 931 */ 932 933 for (i = pool->pipe_count - 1; i >= 0; i--) { 934 if (res_ctx->pipe_ctx[i].stream == NULL) { 935 secondary_pipe = &res_ctx->pipe_ctx[i]; 936 secondary_pipe->pipe_idx = i; 937 break; 938 } 939 } 940 941 942 return secondary_pipe; 943 } 944 945 struct pipe_ctx *resource_get_head_pipe_for_stream( 946 struct resource_context *res_ctx, 947 struct dc_stream_state *stream) 948 { 949 int i; 950 for (i = 0; i < MAX_PIPES; i++) { 951 if (res_ctx->pipe_ctx[i].stream == stream && 952 !res_ctx->pipe_ctx[i].top_pipe) { 953 return &res_ctx->pipe_ctx[i]; 954 break; 955 } 956 } 957 return NULL; 958 } 959 960 static struct pipe_ctx *resource_get_tail_pipe_for_stream( 961 struct resource_context *res_ctx, 962 struct dc_stream_state *stream) 963 { 964 struct pipe_ctx *head_pipe, *tail_pipe; 965 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 966 967 if (!head_pipe) 968 return NULL; 969 970 tail_pipe = head_pipe->bottom_pipe; 971 972 while (tail_pipe) { 973 head_pipe = tail_pipe; 974 tail_pipe = tail_pipe->bottom_pipe; 975 } 976 977 return head_pipe; 978 } 979 980 /* 981 * A free_pipe for a stream is defined here as a pipe 982 * that has no surface attached yet 983 */ 984 static struct pipe_ctx *acquire_free_pipe_for_stream( 985 struct dc_state *context, 986 const struct resource_pool *pool, 987 struct dc_stream_state *stream) 988 { 989 int i; 990 struct resource_context *res_ctx = &context->res_ctx; 991 992 struct pipe_ctx *head_pipe = NULL; 993 994 /* Find head pipe, which has the back end set up*/ 995 996 head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 997 998 if (!head_pipe) 999 ASSERT(0); 1000 1001 if (!head_pipe->plane_state) 1002 return head_pipe; 1003 1004 /* Re-use pipe already acquired for this stream if available*/ 1005 for (i = pool->pipe_count - 1; i >= 0; i--) { 1006 if (res_ctx->pipe_ctx[i].stream == stream && 1007 !res_ctx->pipe_ctx[i].plane_state) { 1008 return &res_ctx->pipe_ctx[i]; 1009 } 1010 } 1011 1012 /* 1013 * At this point we have no re-useable pipe for this stream and we need 1014 * to acquire an idle one to satisfy the request 1015 */ 1016 1017 if (!pool->funcs->acquire_idle_pipe_for_layer) 1018 return NULL; 1019 1020 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream); 1021 1022 } 1023 1024 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1025 static int acquire_first_split_pipe( 1026 struct resource_context *res_ctx, 1027 const struct resource_pool *pool, 1028 struct dc_stream_state *stream) 1029 { 1030 int i; 1031 1032 for (i = 0; i < pool->pipe_count; i++) { 1033 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 1034 1035 if (pipe_ctx->top_pipe && 1036 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) { 1037 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1038 if (pipe_ctx->bottom_pipe) 1039 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1040 1041 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1042 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 1043 pipe_ctx->plane_res.hubp = pool->hubps[i]; 1044 pipe_ctx->plane_res.ipp = pool->ipps[i]; 1045 pipe_ctx->plane_res.dpp = pool->dpps[i]; 1046 pipe_ctx->stream_res.opp = pool->opps[i]; 1047 pipe_ctx->pipe_idx = i; 1048 1049 pipe_ctx->stream = stream; 1050 return i; 1051 } 1052 } 1053 return -1; 1054 } 1055 #endif 1056 1057 bool dc_add_plane_to_context( 1058 const struct dc *dc, 1059 struct dc_stream_state *stream, 1060 struct dc_plane_state *plane_state, 1061 struct dc_state *context) 1062 { 1063 int i; 1064 struct resource_pool *pool = dc->res_pool; 1065 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; 1066 struct dc_stream_status *stream_status = NULL; 1067 1068 for (i = 0; i < context->stream_count; i++) 1069 if (context->streams[i] == stream) { 1070 stream_status = &context->stream_status[i]; 1071 break; 1072 } 1073 if (stream_status == NULL) { 1074 dm_error("Existing stream not found; failed to attach surface!\n"); 1075 return false; 1076 } 1077 1078 1079 if (stream_status->plane_count == MAX_SURFACE_NUM) { 1080 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", 1081 plane_state, MAX_SURFACE_NUM); 1082 return false; 1083 } 1084 1085 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1086 1087 if (!head_pipe) { 1088 dm_error("Head pipe not found for stream_state %p !\n", stream); 1089 return false; 1090 } 1091 1092 free_pipe = acquire_free_pipe_for_stream(context, pool, stream); 1093 1094 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 1095 if (!free_pipe) { 1096 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 1097 if (pipe_idx >= 0) 1098 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; 1099 } 1100 #endif 1101 if (!free_pipe) 1102 return false; 1103 1104 /* retain new surfaces */ 1105 dc_plane_state_retain(plane_state); 1106 free_pipe->plane_state = plane_state; 1107 1108 if (head_pipe != free_pipe) { 1109 1110 tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream); 1111 ASSERT(tail_pipe); 1112 1113 free_pipe->stream_res.tg = tail_pipe->stream_res.tg; 1114 free_pipe->stream_res.opp = tail_pipe->stream_res.opp; 1115 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; 1116 free_pipe->stream_res.audio = tail_pipe->stream_res.audio; 1117 free_pipe->clock_source = tail_pipe->clock_source; 1118 free_pipe->top_pipe = tail_pipe; 1119 tail_pipe->bottom_pipe = free_pipe; 1120 } 1121 1122 /* assign new surfaces*/ 1123 stream_status->plane_states[stream_status->plane_count] = plane_state; 1124 1125 stream_status->plane_count++; 1126 1127 return true; 1128 } 1129 1130 bool dc_remove_plane_from_context( 1131 const struct dc *dc, 1132 struct dc_stream_state *stream, 1133 struct dc_plane_state *plane_state, 1134 struct dc_state *context) 1135 { 1136 int i; 1137 struct dc_stream_status *stream_status = NULL; 1138 struct resource_pool *pool = dc->res_pool; 1139 1140 for (i = 0; i < context->stream_count; i++) 1141 if (context->streams[i] == stream) { 1142 stream_status = &context->stream_status[i]; 1143 break; 1144 } 1145 1146 if (stream_status == NULL) { 1147 dm_error("Existing stream not found; failed to remove plane.\n"); 1148 return false; 1149 } 1150 1151 /* release pipe for plane*/ 1152 for (i = pool->pipe_count - 1; i >= 0; i--) { 1153 struct pipe_ctx *pipe_ctx; 1154 1155 if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) { 1156 pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1157 1158 if (pipe_ctx->top_pipe) 1159 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1160 1161 /* Second condition is to avoid setting NULL to top pipe 1162 * of tail pipe making it look like head pipe in subsequent 1163 * deletes 1164 */ 1165 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) 1166 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1167 1168 /* 1169 * For head pipe detach surfaces from pipe for tail 1170 * pipe just zero it out 1171 */ 1172 if (!pipe_ctx->top_pipe) { 1173 pipe_ctx->plane_state = NULL; 1174 pipe_ctx->bottom_pipe = NULL; 1175 } else { 1176 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1177 } 1178 } 1179 } 1180 1181 1182 for (i = 0; i < stream_status->plane_count; i++) { 1183 if (stream_status->plane_states[i] == plane_state) { 1184 1185 dc_plane_state_release(stream_status->plane_states[i]); 1186 break; 1187 } 1188 } 1189 1190 if (i == stream_status->plane_count) { 1191 dm_error("Existing plane_state not found; failed to detach it!\n"); 1192 return false; 1193 } 1194 1195 stream_status->plane_count--; 1196 1197 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */ 1198 for (; i < stream_status->plane_count; i++) 1199 stream_status->plane_states[i] = stream_status->plane_states[i + 1]; 1200 1201 stream_status->plane_states[stream_status->plane_count] = NULL; 1202 1203 return true; 1204 } 1205 1206 bool dc_rem_all_planes_for_stream( 1207 const struct dc *dc, 1208 struct dc_stream_state *stream, 1209 struct dc_state *context) 1210 { 1211 int i, old_plane_count; 1212 struct dc_stream_status *stream_status = NULL; 1213 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; 1214 1215 for (i = 0; i < context->stream_count; i++) 1216 if (context->streams[i] == stream) { 1217 stream_status = &context->stream_status[i]; 1218 break; 1219 } 1220 1221 if (stream_status == NULL) { 1222 dm_error("Existing stream %p not found!\n", stream); 1223 return false; 1224 } 1225 1226 old_plane_count = stream_status->plane_count; 1227 1228 for (i = 0; i < old_plane_count; i++) 1229 del_planes[i] = stream_status->plane_states[i]; 1230 1231 for (i = 0; i < old_plane_count; i++) 1232 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) 1233 return false; 1234 1235 return true; 1236 } 1237 1238 static bool add_all_planes_for_stream( 1239 const struct dc *dc, 1240 struct dc_stream_state *stream, 1241 const struct dc_validation_set set[], 1242 int set_count, 1243 struct dc_state *context) 1244 { 1245 int i, j; 1246 1247 for (i = 0; i < set_count; i++) 1248 if (set[i].stream == stream) 1249 break; 1250 1251 if (i == set_count) { 1252 dm_error("Stream %p not found in set!\n", stream); 1253 return false; 1254 } 1255 1256 for (j = 0; j < set[i].plane_count; j++) 1257 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) 1258 return false; 1259 1260 return true; 1261 } 1262 1263 bool dc_add_all_planes_for_stream( 1264 const struct dc *dc, 1265 struct dc_stream_state *stream, 1266 struct dc_plane_state * const *plane_states, 1267 int plane_count, 1268 struct dc_state *context) 1269 { 1270 struct dc_validation_set set; 1271 int i; 1272 1273 set.stream = stream; 1274 set.plane_count = plane_count; 1275 1276 for (i = 0; i < plane_count; i++) 1277 set.plane_states[i] = plane_states[i]; 1278 1279 return add_all_planes_for_stream(dc, stream, &set, 1, context); 1280 } 1281 1282 1283 1284 static bool is_timing_changed(struct dc_stream_state *cur_stream, 1285 struct dc_stream_state *new_stream) 1286 { 1287 if (cur_stream == NULL) 1288 return true; 1289 1290 /* If sink pointer changed, it means this is a hotplug, we should do 1291 * full hw setting. 1292 */ 1293 if (cur_stream->sink != new_stream->sink) 1294 return true; 1295 1296 /* If output color space is changed, need to reprogram info frames */ 1297 if (cur_stream->output_color_space != new_stream->output_color_space) 1298 return true; 1299 1300 return memcmp( 1301 &cur_stream->timing, 1302 &new_stream->timing, 1303 sizeof(struct dc_crtc_timing)) != 0; 1304 } 1305 1306 static bool are_stream_backends_same( 1307 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) 1308 { 1309 if (stream_a == stream_b) 1310 return true; 1311 1312 if (stream_a == NULL || stream_b == NULL) 1313 return false; 1314 1315 if (is_timing_changed(stream_a, stream_b)) 1316 return false; 1317 1318 return true; 1319 } 1320 1321 bool dc_is_stream_unchanged( 1322 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1323 { 1324 1325 if (!are_stream_backends_same(old_stream, stream)) 1326 return false; 1327 1328 return true; 1329 } 1330 1331 bool dc_is_stream_scaling_unchanged( 1332 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 1333 { 1334 if (old_stream == stream) 1335 return true; 1336 1337 if (old_stream == NULL || stream == NULL) 1338 return false; 1339 1340 if (memcmp(&old_stream->src, 1341 &stream->src, 1342 sizeof(struct rect)) != 0) 1343 return false; 1344 1345 if (memcmp(&old_stream->dst, 1346 &stream->dst, 1347 sizeof(struct rect)) != 0) 1348 return false; 1349 1350 return true; 1351 } 1352 1353 /* Maximum TMDS single link pixel clock 165MHz */ 1354 #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000 1355 1356 static void update_stream_engine_usage( 1357 struct resource_context *res_ctx, 1358 const struct resource_pool *pool, 1359 struct stream_encoder *stream_enc, 1360 bool acquired) 1361 { 1362 int i; 1363 1364 for (i = 0; i < pool->stream_enc_count; i++) { 1365 if (pool->stream_enc[i] == stream_enc) 1366 res_ctx->is_stream_enc_acquired[i] = acquired; 1367 } 1368 } 1369 1370 /* TODO: release audio object */ 1371 void update_audio_usage( 1372 struct resource_context *res_ctx, 1373 const struct resource_pool *pool, 1374 struct audio *audio, 1375 bool acquired) 1376 { 1377 int i; 1378 for (i = 0; i < pool->audio_count; i++) { 1379 if (pool->audios[i] == audio) 1380 res_ctx->is_audio_acquired[i] = acquired; 1381 } 1382 } 1383 1384 static int acquire_first_free_pipe( 1385 struct resource_context *res_ctx, 1386 const struct resource_pool *pool, 1387 struct dc_stream_state *stream) 1388 { 1389 int i; 1390 1391 for (i = 0; i < pool->pipe_count; i++) { 1392 if (!res_ctx->pipe_ctx[i].stream) { 1393 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 1394 1395 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 1396 pipe_ctx->plane_res.mi = pool->mis[i]; 1397 pipe_ctx->plane_res.hubp = pool->hubps[i]; 1398 pipe_ctx->plane_res.ipp = pool->ipps[i]; 1399 pipe_ctx->plane_res.xfm = pool->transforms[i]; 1400 pipe_ctx->plane_res.dpp = pool->dpps[i]; 1401 pipe_ctx->stream_res.opp = pool->opps[i]; 1402 pipe_ctx->pipe_idx = i; 1403 1404 1405 pipe_ctx->stream = stream; 1406 return i; 1407 } 1408 } 1409 return -1; 1410 } 1411 1412 static struct stream_encoder *find_first_free_match_stream_enc_for_link( 1413 struct resource_context *res_ctx, 1414 const struct resource_pool *pool, 1415 struct dc_stream_state *stream) 1416 { 1417 int i; 1418 int j = -1; 1419 struct dc_link *link = stream->sink->link; 1420 1421 for (i = 0; i < pool->stream_enc_count; i++) { 1422 if (!res_ctx->is_stream_enc_acquired[i] && 1423 pool->stream_enc[i]) { 1424 /* Store first available for MST second display 1425 * in daisy chain use case */ 1426 j = i; 1427 if (pool->stream_enc[i]->id == 1428 link->link_enc->preferred_engine) 1429 return pool->stream_enc[i]; 1430 } 1431 } 1432 1433 /* 1434 * below can happen in cases when stream encoder is acquired: 1435 * 1) for second MST display in chain, so preferred engine already 1436 * acquired; 1437 * 2) for another link, which preferred engine already acquired by any 1438 * MST configuration. 1439 * 1440 * If signal is of DP type and preferred engine not found, return last available 1441 * 1442 * TODO - This is just a patch up and a generic solution is 1443 * required for non DP connectors. 1444 */ 1445 1446 if (j >= 0 && dc_is_dp_signal(stream->signal)) 1447 return pool->stream_enc[j]; 1448 1449 return NULL; 1450 } 1451 1452 static struct audio *find_first_free_audio( 1453 struct resource_context *res_ctx, 1454 const struct resource_pool *pool) 1455 { 1456 int i; 1457 for (i = 0; i < pool->audio_count; i++) { 1458 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { 1459 return pool->audios[i]; 1460 } 1461 } 1462 /*not found the matching one, first come first serve*/ 1463 for (i = 0; i < pool->audio_count; i++) { 1464 if (res_ctx->is_audio_acquired[i] == false) { 1465 return pool->audios[i]; 1466 } 1467 } 1468 return 0; 1469 } 1470 1471 bool resource_is_stream_unchanged( 1472 struct dc_state *old_context, struct dc_stream_state *stream) 1473 { 1474 int i; 1475 1476 for (i = 0; i < old_context->stream_count; i++) { 1477 struct dc_stream_state *old_stream = old_context->streams[i]; 1478 1479 if (are_stream_backends_same(old_stream, stream)) 1480 return true; 1481 } 1482 1483 return false; 1484 } 1485 1486 enum dc_status dc_add_stream_to_ctx( 1487 struct dc *dc, 1488 struct dc_state *new_ctx, 1489 struct dc_stream_state *stream) 1490 { 1491 struct dc_context *dc_ctx = dc->ctx; 1492 enum dc_status res; 1493 1494 if (new_ctx->stream_count >= dc->res_pool->pipe_count) { 1495 DC_ERROR("Max streams reached, can add stream %p !\n", stream); 1496 return DC_ERROR_UNEXPECTED; 1497 } 1498 1499 new_ctx->streams[new_ctx->stream_count] = stream; 1500 dc_stream_retain(stream); 1501 new_ctx->stream_count++; 1502 1503 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); 1504 if (res != DC_OK) 1505 DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res); 1506 1507 return res; 1508 } 1509 1510 enum dc_status dc_remove_stream_from_ctx( 1511 struct dc *dc, 1512 struct dc_state *new_ctx, 1513 struct dc_stream_state *stream) 1514 { 1515 int i; 1516 struct dc_context *dc_ctx = dc->ctx; 1517 struct pipe_ctx *del_pipe = NULL; 1518 1519 /* Release primary pipe */ 1520 for (i = 0; i < MAX_PIPES; i++) { 1521 if (new_ctx->res_ctx.pipe_ctx[i].stream == stream && 1522 !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { 1523 del_pipe = &new_ctx->res_ctx.pipe_ctx[i]; 1524 1525 ASSERT(del_pipe->stream_res.stream_enc); 1526 update_stream_engine_usage( 1527 &new_ctx->res_ctx, 1528 dc->res_pool, 1529 del_pipe->stream_res.stream_enc, 1530 false); 1531 1532 if (del_pipe->stream_res.audio) 1533 update_audio_usage( 1534 &new_ctx->res_ctx, 1535 dc->res_pool, 1536 del_pipe->stream_res.audio, 1537 false); 1538 1539 resource_unreference_clock_source(&new_ctx->res_ctx, 1540 dc->res_pool, 1541 del_pipe->clock_source); 1542 1543 memset(del_pipe, 0, sizeof(*del_pipe)); 1544 1545 break; 1546 } 1547 } 1548 1549 if (!del_pipe) { 1550 DC_ERROR("Pipe not found for stream %p !\n", stream); 1551 return DC_ERROR_UNEXPECTED; 1552 } 1553 1554 for (i = 0; i < new_ctx->stream_count; i++) 1555 if (new_ctx->streams[i] == stream) 1556 break; 1557 1558 if (new_ctx->streams[i] != stream) { 1559 DC_ERROR("Context doesn't have stream %p !\n", stream); 1560 return DC_ERROR_UNEXPECTED; 1561 } 1562 1563 dc_stream_release(new_ctx->streams[i]); 1564 new_ctx->stream_count--; 1565 1566 /* Trim back arrays */ 1567 for (; i < new_ctx->stream_count; i++) { 1568 new_ctx->streams[i] = new_ctx->streams[i + 1]; 1569 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; 1570 } 1571 1572 new_ctx->streams[new_ctx->stream_count] = NULL; 1573 memset( 1574 &new_ctx->stream_status[new_ctx->stream_count], 1575 0, 1576 sizeof(new_ctx->stream_status[0])); 1577 1578 return DC_OK; 1579 } 1580 1581 static void copy_pipe_ctx( 1582 const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) 1583 { 1584 struct dc_plane_state *plane_state = to_pipe_ctx->plane_state; 1585 struct dc_stream_state *stream = to_pipe_ctx->stream; 1586 1587 *to_pipe_ctx = *from_pipe_ctx; 1588 to_pipe_ctx->stream = stream; 1589 if (plane_state != NULL) 1590 to_pipe_ctx->plane_state = plane_state; 1591 } 1592 1593 static struct dc_stream_state *find_pll_sharable_stream( 1594 struct dc_stream_state *stream_needs_pll, 1595 struct dc_state *context) 1596 { 1597 int i; 1598 1599 for (i = 0; i < context->stream_count; i++) { 1600 struct dc_stream_state *stream_has_pll = context->streams[i]; 1601 1602 /* We are looking for non dp, non virtual stream */ 1603 if (resource_are_streams_timing_synchronizable( 1604 stream_needs_pll, stream_has_pll) 1605 && !dc_is_dp_signal(stream_has_pll->signal) 1606 && stream_has_pll->sink->link->connector_signal 1607 != SIGNAL_TYPE_VIRTUAL) 1608 return stream_has_pll; 1609 1610 } 1611 1612 return NULL; 1613 } 1614 1615 static int get_norm_pix_clk(const struct dc_crtc_timing *timing) 1616 { 1617 uint32_t pix_clk = timing->pix_clk_khz; 1618 uint32_t normalized_pix_clk = pix_clk; 1619 1620 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 1621 pix_clk /= 2; 1622 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 1623 switch (timing->display_color_depth) { 1624 case COLOR_DEPTH_888: 1625 normalized_pix_clk = pix_clk; 1626 break; 1627 case COLOR_DEPTH_101010: 1628 normalized_pix_clk = (pix_clk * 30) / 24; 1629 break; 1630 case COLOR_DEPTH_121212: 1631 normalized_pix_clk = (pix_clk * 36) / 24; 1632 break; 1633 case COLOR_DEPTH_161616: 1634 normalized_pix_clk = (pix_clk * 48) / 24; 1635 break; 1636 default: 1637 ASSERT(0); 1638 break; 1639 } 1640 } 1641 return normalized_pix_clk; 1642 } 1643 1644 static void calculate_phy_pix_clks(struct dc_stream_state *stream) 1645 { 1646 /* update actual pixel clock on all streams */ 1647 if (dc_is_hdmi_signal(stream->signal)) 1648 stream->phy_pix_clk = get_norm_pix_clk( 1649 &stream->timing); 1650 else 1651 stream->phy_pix_clk = 1652 stream->timing.pix_clk_khz; 1653 } 1654 1655 enum dc_status resource_map_pool_resources( 1656 const struct dc *dc, 1657 struct dc_state *context, 1658 struct dc_stream_state *stream) 1659 { 1660 const struct resource_pool *pool = dc->res_pool; 1661 int i; 1662 struct dc_context *dc_ctx = dc->ctx; 1663 struct pipe_ctx *pipe_ctx = NULL; 1664 int pipe_idx = -1; 1665 1666 /* TODO Check if this is needed */ 1667 /*if (!resource_is_stream_unchanged(old_context, stream)) { 1668 if (stream != NULL && old_context->streams[i] != NULL) { 1669 stream->bit_depth_params = 1670 old_context->streams[i]->bit_depth_params; 1671 stream->clamping = old_context->streams[i]->clamping; 1672 continue; 1673 } 1674 } 1675 */ 1676 1677 /* acquire new resources */ 1678 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); 1679 1680 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 1681 if (pipe_idx < 0) 1682 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 1683 #endif 1684 1685 if (pipe_idx < 0) 1686 return DC_NO_CONTROLLER_RESOURCE; 1687 1688 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 1689 1690 pipe_ctx->stream_res.stream_enc = 1691 find_first_free_match_stream_enc_for_link( 1692 &context->res_ctx, pool, stream); 1693 1694 if (!pipe_ctx->stream_res.stream_enc) 1695 return DC_NO_STREAM_ENG_RESOURCE; 1696 1697 update_stream_engine_usage( 1698 &context->res_ctx, pool, 1699 pipe_ctx->stream_res.stream_enc, 1700 true); 1701 1702 /* TODO: Add check if ASIC support and EDID audio */ 1703 if (!stream->sink->converter_disable_audio && 1704 dc_is_audio_capable_signal(pipe_ctx->stream->signal) && 1705 stream->audio_info.mode_count) { 1706 pipe_ctx->stream_res.audio = find_first_free_audio( 1707 &context->res_ctx, pool); 1708 1709 /* 1710 * Audio assigned in order first come first get. 1711 * There are asics which has number of audio 1712 * resources less then number of pipes 1713 */ 1714 if (pipe_ctx->stream_res.audio) 1715 update_audio_usage(&context->res_ctx, pool, 1716 pipe_ctx->stream_res.audio, true); 1717 } 1718 1719 for (i = 0; i < context->stream_count; i++) 1720 if (context->streams[i] == stream) { 1721 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; 1722 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id; 1723 return DC_OK; 1724 } 1725 1726 DC_ERROR("Stream %p not found in new ctx!\n", stream); 1727 return DC_ERROR_UNEXPECTED; 1728 } 1729 1730 /* first stream in the context is used to populate the rest */ 1731 void validate_guaranteed_copy_streams( 1732 struct dc_state *context, 1733 int max_streams) 1734 { 1735 int i; 1736 1737 for (i = 1; i < max_streams; i++) { 1738 context->streams[i] = context->streams[0]; 1739 1740 copy_pipe_ctx(&context->res_ctx.pipe_ctx[0], 1741 &context->res_ctx.pipe_ctx[i]); 1742 context->res_ctx.pipe_ctx[i].stream = 1743 context->res_ctx.pipe_ctx[0].stream; 1744 1745 dc_stream_retain(context->streams[i]); 1746 context->stream_count++; 1747 } 1748 } 1749 1750 void dc_resource_state_copy_construct_current( 1751 const struct dc *dc, 1752 struct dc_state *dst_ctx) 1753 { 1754 dc_resource_state_copy_construct(dc->current_state, dst_ctx); 1755 } 1756 1757 1758 void dc_resource_state_construct( 1759 const struct dc *dc, 1760 struct dc_state *dst_ctx) 1761 { 1762 dst_ctx->dis_clk = dc->res_pool->display_clock; 1763 } 1764 1765 enum dc_status dc_validate_global_state( 1766 struct dc *dc, 1767 struct dc_state *new_ctx) 1768 { 1769 enum dc_status result = DC_ERROR_UNEXPECTED; 1770 int i, j; 1771 1772 if (dc->res_pool->funcs->validate_global) { 1773 result = dc->res_pool->funcs->validate_global(dc, new_ctx); 1774 if (result != DC_OK) 1775 return result; 1776 } 1777 1778 for (i = 0; new_ctx && i < new_ctx->stream_count; i++) { 1779 struct dc_stream_state *stream = new_ctx->streams[i]; 1780 1781 for (j = 0; j < dc->res_pool->pipe_count; j++) { 1782 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; 1783 1784 if (pipe_ctx->stream != stream) 1785 continue; 1786 1787 /* Switch to dp clock source only if there is 1788 * no non dp stream that shares the same timing 1789 * with the dp stream. 1790 */ 1791 if (dc_is_dp_signal(pipe_ctx->stream->signal) && 1792 !find_pll_sharable_stream(stream, new_ctx)) { 1793 1794 resource_unreference_clock_source( 1795 &new_ctx->res_ctx, 1796 dc->res_pool, 1797 pipe_ctx->clock_source); 1798 1799 pipe_ctx->clock_source = dc->res_pool->dp_clock_source; 1800 resource_reference_clock_source( 1801 &new_ctx->res_ctx, 1802 dc->res_pool, 1803 pipe_ctx->clock_source); 1804 } 1805 } 1806 } 1807 1808 result = resource_build_scaling_params_for_context(dc, new_ctx); 1809 1810 if (result == DC_OK) 1811 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx)) 1812 result = DC_FAIL_BANDWIDTH_VALIDATE; 1813 1814 return result; 1815 } 1816 1817 static void patch_gamut_packet_checksum( 1818 struct encoder_info_packet *gamut_packet) 1819 { 1820 /* For gamut we recalc checksum */ 1821 if (gamut_packet->valid) { 1822 uint8_t chk_sum = 0; 1823 uint8_t *ptr; 1824 uint8_t i; 1825 1826 /*start of the Gamut data. */ 1827 ptr = &gamut_packet->sb[3]; 1828 1829 for (i = 0; i <= gamut_packet->sb[1]; i++) 1830 chk_sum += ptr[i]; 1831 1832 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); 1833 } 1834 } 1835 1836 static void set_avi_info_frame( 1837 struct encoder_info_packet *info_packet, 1838 struct pipe_ctx *pipe_ctx) 1839 { 1840 struct dc_stream_state *stream = pipe_ctx->stream; 1841 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; 1842 struct info_frame info_frame = { {0} }; 1843 uint32_t pixel_encoding = 0; 1844 enum scanning_type scan_type = SCANNING_TYPE_NODATA; 1845 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA; 1846 bool itc = false; 1847 uint8_t itc_value = 0; 1848 uint8_t cn0_cn1 = 0; 1849 unsigned int cn0_cn1_value = 0; 1850 uint8_t *check_sum = NULL; 1851 uint8_t byte_index = 0; 1852 union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi; 1853 union display_content_support support = {0}; 1854 unsigned int vic = pipe_ctx->stream->timing.vic; 1855 enum dc_timing_3d_format format; 1856 1857 color_space = pipe_ctx->stream->output_color_space; 1858 if (color_space == COLOR_SPACE_UNKNOWN) 1859 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? 1860 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; 1861 1862 /* Initialize header */ 1863 hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI; 1864 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall 1865 * not be used in HDMI 2.0 (Section 10.1) */ 1866 hdmi_info->bits.header.version = 2; 1867 hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE; 1868 1869 /* 1870 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built 1871 * according to HDMI 2.0 spec (Section 10.1) 1872 */ 1873 1874 switch (stream->timing.pixel_encoding) { 1875 case PIXEL_ENCODING_YCBCR422: 1876 pixel_encoding = 1; 1877 break; 1878 1879 case PIXEL_ENCODING_YCBCR444: 1880 pixel_encoding = 2; 1881 break; 1882 case PIXEL_ENCODING_YCBCR420: 1883 pixel_encoding = 3; 1884 break; 1885 1886 case PIXEL_ENCODING_RGB: 1887 default: 1888 pixel_encoding = 0; 1889 } 1890 1891 /* Y0_Y1_Y2 : The pixel encoding */ 1892 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ 1893 hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding; 1894 1895 /* A0 = 1 Active Format Information valid */ 1896 hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID; 1897 1898 /* B0, B1 = 3; Bar info data is valid */ 1899 hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID; 1900 1901 hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM; 1902 1903 /* S0, S1 : Underscan / Overscan */ 1904 /* TODO: un-hardcode scan type */ 1905 scan_type = SCANNING_TYPE_UNDERSCAN; 1906 hdmi_info->bits.S0_S1 = scan_type; 1907 1908 /* C0, C1 : Colorimetry */ 1909 if (color_space == COLOR_SPACE_YCBCR709 || 1910 color_space == COLOR_SPACE_YCBCR709_LIMITED) 1911 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709; 1912 else if (color_space == COLOR_SPACE_YCBCR601 || 1913 color_space == COLOR_SPACE_YCBCR601_LIMITED) 1914 hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601; 1915 else { 1916 hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA; 1917 } 1918 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE || 1919 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE || 1920 color_space == COLOR_SPACE_2020_YCBCR) { 1921 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR; 1922 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED; 1923 } else if (color_space == COLOR_SPACE_ADOBERGB) { 1924 hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB; 1925 hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED; 1926 } 1927 1928 /* TODO: un-hardcode aspect ratio */ 1929 aspect = stream->timing.aspect_ratio; 1930 1931 switch (aspect) { 1932 case ASPECT_RATIO_4_3: 1933 case ASPECT_RATIO_16_9: 1934 hdmi_info->bits.M0_M1 = aspect; 1935 break; 1936 1937 case ASPECT_RATIO_NO_DATA: 1938 case ASPECT_RATIO_64_27: 1939 case ASPECT_RATIO_256_135: 1940 default: 1941 hdmi_info->bits.M0_M1 = 0; 1942 } 1943 1944 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */ 1945 hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE; 1946 1947 /* TODO: un-hardcode cn0_cn1 and itc */ 1948 1949 cn0_cn1 = 0; 1950 cn0_cn1_value = 0; 1951 1952 itc = true; 1953 itc_value = 1; 1954 1955 support = stream->sink->edid_caps.content_support; 1956 1957 if (itc) { 1958 if (!support.bits.valid_content_type) { 1959 cn0_cn1_value = 0; 1960 } else { 1961 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) { 1962 if (support.bits.graphics_content == 1) { 1963 cn0_cn1_value = 0; 1964 } 1965 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) { 1966 if (support.bits.photo_content == 1) { 1967 cn0_cn1_value = 1; 1968 } else { 1969 cn0_cn1_value = 0; 1970 itc_value = 0; 1971 } 1972 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) { 1973 if (support.bits.cinema_content == 1) { 1974 cn0_cn1_value = 2; 1975 } else { 1976 cn0_cn1_value = 0; 1977 itc_value = 0; 1978 } 1979 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) { 1980 if (support.bits.game_content == 1) { 1981 cn0_cn1_value = 3; 1982 } else { 1983 cn0_cn1_value = 0; 1984 itc_value = 0; 1985 } 1986 } 1987 } 1988 hdmi_info->bits.CN0_CN1 = cn0_cn1_value; 1989 hdmi_info->bits.ITC = itc_value; 1990 } 1991 1992 /* TODO : We should handle YCC quantization */ 1993 /* but we do not have matrix calculation */ 1994 if (stream->sink->edid_caps.qs_bit == 1 && 1995 stream->sink->edid_caps.qy_bit == 1) { 1996 if (color_space == COLOR_SPACE_SRGB || 1997 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) { 1998 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; 1999 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE; 2000 } else if (color_space == COLOR_SPACE_SRGB_LIMITED || 2001 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) { 2002 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE; 2003 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2004 } else { 2005 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2006 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2007 } 2008 } else { 2009 hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 2010 hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 2011 } 2012 2013 ///VIC 2014 format = stream->timing.timing_3d_format; 2015 /*todo, add 3DStereo support*/ 2016 if (format != TIMING_3D_FORMAT_NONE) { 2017 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled 2018 switch (pipe_ctx->stream->timing.hdmi_vic) { 2019 case 1: 2020 vic = 95; 2021 break; 2022 case 2: 2023 vic = 94; 2024 break; 2025 case 3: 2026 vic = 93; 2027 break; 2028 case 4: 2029 vic = 98; 2030 break; 2031 default: 2032 break; 2033 } 2034 } 2035 hdmi_info->bits.VIC0_VIC7 = vic; 2036 2037 /* pixel repetition 2038 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel 2039 * repetition start from 1 */ 2040 hdmi_info->bits.PR0_PR3 = 0; 2041 2042 /* Bar Info 2043 * barTop: Line Number of End of Top Bar. 2044 * barBottom: Line Number of Start of Bottom Bar. 2045 * barLeft: Pixel Number of End of Left Bar. 2046 * barRight: Pixel Number of Start of Right Bar. */ 2047 hdmi_info->bits.bar_top = stream->timing.v_border_top; 2048 hdmi_info->bits.bar_bottom = (stream->timing.v_total 2049 - stream->timing.v_border_bottom + 1); 2050 hdmi_info->bits.bar_left = stream->timing.h_border_left; 2051 hdmi_info->bits.bar_right = (stream->timing.h_total 2052 - stream->timing.h_border_right + 1); 2053 2054 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ 2055 check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0]; 2056 2057 *check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2; 2058 2059 for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++) 2060 *check_sum += hdmi_info->packet_raw_data.sb[byte_index]; 2061 2062 /* one byte complement */ 2063 *check_sum = (uint8_t) (0x100 - *check_sum); 2064 2065 /* Store in hw_path_mode */ 2066 info_packet->hb0 = hdmi_info->packet_raw_data.hb0; 2067 info_packet->hb1 = hdmi_info->packet_raw_data.hb1; 2068 info_packet->hb2 = hdmi_info->packet_raw_data.hb2; 2069 2070 for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet. 2071 info_packet_hdmi.packet_raw_data.sb); byte_index++) 2072 info_packet->sb[byte_index] = info_frame.avi_info_packet. 2073 info_packet_hdmi.packet_raw_data.sb[byte_index]; 2074 2075 info_packet->valid = true; 2076 } 2077 2078 static void set_vendor_info_packet( 2079 struct encoder_info_packet *info_packet, 2080 struct dc_stream_state *stream) 2081 { 2082 uint32_t length = 0; 2083 bool hdmi_vic_mode = false; 2084 uint8_t checksum = 0; 2085 uint32_t i = 0; 2086 enum dc_timing_3d_format format; 2087 // Can be different depending on packet content /*todo*/ 2088 // unsigned int length = pPathMode->dolbyVision ? 24 : 5; 2089 2090 info_packet->valid = false; 2091 2092 format = stream->timing.timing_3d_format; 2093 if (stream->view_format == VIEW_3D_FORMAT_NONE) 2094 format = TIMING_3D_FORMAT_NONE; 2095 2096 /* Can be different depending on packet content */ 2097 length = 5; 2098 2099 if (stream->timing.hdmi_vic != 0 2100 && stream->timing.h_total >= 3840 2101 && stream->timing.v_total >= 2160) 2102 hdmi_vic_mode = true; 2103 2104 /* According to HDMI 1.4a CTS, VSIF should be sent 2105 * for both 3D stereo and HDMI VIC modes. 2106 * For all other modes, there is no VSIF sent. */ 2107 2108 if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode) 2109 return; 2110 2111 /* 24bit IEEE Registration identifier (0x000c03). LSB first. */ 2112 info_packet->sb[1] = 0x03; 2113 info_packet->sb[2] = 0x0C; 2114 info_packet->sb[3] = 0x00; 2115 2116 /*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format. 2117 * The value for HDMI_Video_Format are: 2118 * 0x0 (0b000) - No additional HDMI video format is presented in this 2119 * packet 2120 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC 2121 * parameter follows 2122 * 0x2 (0b010) - 3D format indication present. 3D_Structure and 2123 * potentially 3D_Ext_Data follows 2124 * 0x3..0x7 (0b011..0b111) - reserved for future use */ 2125 if (format != TIMING_3D_FORMAT_NONE) 2126 info_packet->sb[4] = (2 << 5); 2127 else if (hdmi_vic_mode) 2128 info_packet->sb[4] = (1 << 5); 2129 2130 /* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2): 2131 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure. 2132 * The value for 3D_Structure are: 2133 * 0x0 - Frame Packing 2134 * 0x1 - Field Alternative 2135 * 0x2 - Line Alternative 2136 * 0x3 - Side-by-Side (full) 2137 * 0x4 - L + depth 2138 * 0x5 - L + depth + graphics + graphics-depth 2139 * 0x6 - Top-and-Bottom 2140 * 0x7 - Reserved for future use 2141 * 0x8 - Side-by-Side (Half) 2142 * 0x9..0xE - Reserved for future use 2143 * 0xF - Not used */ 2144 switch (format) { 2145 case TIMING_3D_FORMAT_HW_FRAME_PACKING: 2146 case TIMING_3D_FORMAT_SW_FRAME_PACKING: 2147 info_packet->sb[5] = (0x0 << 4); 2148 break; 2149 2150 case TIMING_3D_FORMAT_SIDE_BY_SIDE: 2151 case TIMING_3D_FORMAT_SBS_SW_PACKED: 2152 info_packet->sb[5] = (0x8 << 4); 2153 length = 6; 2154 break; 2155 2156 case TIMING_3D_FORMAT_TOP_AND_BOTTOM: 2157 case TIMING_3D_FORMAT_TB_SW_PACKED: 2158 info_packet->sb[5] = (0x6 << 4); 2159 break; 2160 2161 default: 2162 break; 2163 } 2164 2165 /*PB5: If PB4 is set to 0x1 (extended resolution format) 2166 * fill PB5 with the correct HDMI VIC code */ 2167 if (hdmi_vic_mode) 2168 info_packet->sb[5] = stream->timing.hdmi_vic; 2169 2170 /* Header */ 2171 info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */ 2172 info_packet->hb1 = 0x01; /* Version */ 2173 2174 /* 4 lower bits = Length, 4 higher bits = 0 (reserved) */ 2175 info_packet->hb2 = (uint8_t) (length); 2176 2177 /* Calculate checksum */ 2178 checksum = 0; 2179 checksum += info_packet->hb0; 2180 checksum += info_packet->hb1; 2181 checksum += info_packet->hb2; 2182 2183 for (i = 1; i <= length; i++) 2184 checksum += info_packet->sb[i]; 2185 2186 info_packet->sb[0] = (uint8_t) (0x100 - checksum); 2187 2188 info_packet->valid = true; 2189 } 2190 2191 static void set_spd_info_packet( 2192 struct encoder_info_packet *info_packet, 2193 struct dc_stream_state *stream) 2194 { 2195 /* SPD info packet for FreeSync */ 2196 2197 unsigned char checksum = 0; 2198 unsigned int idx, payload_size = 0; 2199 2200 /* Check if Freesync is supported. Return if false. If true, 2201 * set the corresponding bit in the info packet 2202 */ 2203 if (stream->freesync_ctx.supported == false) 2204 return; 2205 2206 if (dc_is_hdmi_signal(stream->signal)) { 2207 2208 /* HEADER */ 2209 2210 /* HB0 = Packet Type = 0x83 (Source Product 2211 * Descriptor InfoFrame) 2212 */ 2213 info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD; 2214 2215 /* HB1 = Version = 0x01 */ 2216 info_packet->hb1 = 0x01; 2217 2218 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */ 2219 info_packet->hb2 = 0x08; 2220 2221 payload_size = 0x08; 2222 2223 } else if (dc_is_dp_signal(stream->signal)) { 2224 2225 /* HEADER */ 2226 2227 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero 2228 * when used to associate audio related info packets 2229 */ 2230 info_packet->hb0 = 0x00; 2231 2232 /* HB1 = Packet Type = 0x83 (Source Product 2233 * Descriptor InfoFrame) 2234 */ 2235 info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD; 2236 2237 /* HB2 = [Bits 7:0 = Least significant eight bits - 2238 * For INFOFRAME, the value must be 1Bh] 2239 */ 2240 info_packet->hb2 = 0x1B; 2241 2242 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1] 2243 * [Bits 1:0 = Most significant two bits = 0x00] 2244 */ 2245 info_packet->hb3 = 0x04; 2246 2247 payload_size = 0x1B; 2248 } 2249 2250 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */ 2251 info_packet->sb[1] = 0x1A; 2252 2253 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */ 2254 info_packet->sb[2] = 0x00; 2255 2256 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */ 2257 info_packet->sb[3] = 0x00; 2258 2259 /* PB4 = Reserved */ 2260 info_packet->sb[4] = 0x00; 2261 2262 /* PB5 = Reserved */ 2263 info_packet->sb[5] = 0x00; 2264 2265 /* PB6 = [Bits 7:3 = Reserved] */ 2266 info_packet->sb[6] = 0x00; 2267 2268 if (stream->freesync_ctx.supported == true) 2269 /* PB6 = [Bit 0 = FreeSync Supported] */ 2270 info_packet->sb[6] |= 0x01; 2271 2272 if (stream->freesync_ctx.enabled == true) 2273 /* PB6 = [Bit 1 = FreeSync Enabled] */ 2274 info_packet->sb[6] |= 0x02; 2275 2276 if (stream->freesync_ctx.active == true) 2277 /* PB6 = [Bit 2 = FreeSync Active] */ 2278 info_packet->sb[6] |= 0x04; 2279 2280 /* PB7 = FreeSync Minimum refresh rate (Hz) */ 2281 info_packet->sb[7] = (unsigned char) (stream->freesync_ctx. 2282 min_refresh_in_micro_hz / 1000000); 2283 2284 /* PB8 = FreeSync Maximum refresh rate (Hz) 2285 * 2286 * Note: We do not use the maximum capable refresh rate 2287 * of the panel, because we should never go above the field 2288 * rate of the mode timing set. 2289 */ 2290 info_packet->sb[8] = (unsigned char) (stream->freesync_ctx. 2291 nominal_refresh_in_micro_hz / 1000000); 2292 2293 /* PB9 - PB27 = Reserved */ 2294 for (idx = 9; idx <= 27; idx++) 2295 info_packet->sb[idx] = 0x00; 2296 2297 /* Calculate checksum */ 2298 checksum += info_packet->hb0; 2299 checksum += info_packet->hb1; 2300 checksum += info_packet->hb2; 2301 checksum += info_packet->hb3; 2302 2303 for (idx = 1; idx <= payload_size; idx++) 2304 checksum += info_packet->sb[idx]; 2305 2306 /* PB0 = Checksum (one byte complement) */ 2307 info_packet->sb[0] = (unsigned char) (0x100 - checksum); 2308 2309 info_packet->valid = true; 2310 } 2311 2312 static void set_hdr_static_info_packet( 2313 struct encoder_info_packet *info_packet, 2314 struct dc_plane_state *plane_state, 2315 struct dc_stream_state *stream) 2316 { 2317 uint16_t i = 0; 2318 enum signal_type signal = stream->signal; 2319 struct dc_hdr_static_metadata hdr_metadata; 2320 uint32_t data; 2321 2322 if (!plane_state) 2323 return; 2324 2325 hdr_metadata = plane_state->hdr_static_ctx; 2326 2327 if (!hdr_metadata.hdr_supported) 2328 return; 2329 2330 if (dc_is_hdmi_signal(signal)) { 2331 info_packet->valid = true; 2332 2333 info_packet->hb0 = 0x87; 2334 info_packet->hb1 = 0x01; 2335 info_packet->hb2 = 0x1A; 2336 i = 1; 2337 } else if (dc_is_dp_signal(signal)) { 2338 info_packet->valid = true; 2339 2340 info_packet->hb0 = 0x00; 2341 info_packet->hb1 = 0x87; 2342 info_packet->hb2 = 0x1D; 2343 info_packet->hb3 = (0x13 << 2); 2344 i = 2; 2345 } 2346 2347 data = hdr_metadata.is_hdr; 2348 info_packet->sb[i++] = data ? 0x02 : 0x00; 2349 info_packet->sb[i++] = 0x00; 2350 2351 data = hdr_metadata.chromaticity_green_x / 2; 2352 info_packet->sb[i++] = data & 0xFF; 2353 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2354 2355 data = hdr_metadata.chromaticity_green_y / 2; 2356 info_packet->sb[i++] = data & 0xFF; 2357 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2358 2359 data = hdr_metadata.chromaticity_blue_x / 2; 2360 info_packet->sb[i++] = data & 0xFF; 2361 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2362 2363 data = hdr_metadata.chromaticity_blue_y / 2; 2364 info_packet->sb[i++] = data & 0xFF; 2365 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2366 2367 data = hdr_metadata.chromaticity_red_x / 2; 2368 info_packet->sb[i++] = data & 0xFF; 2369 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2370 2371 data = hdr_metadata.chromaticity_red_y / 2; 2372 info_packet->sb[i++] = data & 0xFF; 2373 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2374 2375 data = hdr_metadata.chromaticity_white_point_x / 2; 2376 info_packet->sb[i++] = data & 0xFF; 2377 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2378 2379 data = hdr_metadata.chromaticity_white_point_y / 2; 2380 info_packet->sb[i++] = data & 0xFF; 2381 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2382 2383 data = hdr_metadata.max_luminance; 2384 info_packet->sb[i++] = data & 0xFF; 2385 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2386 2387 data = hdr_metadata.min_luminance; 2388 info_packet->sb[i++] = data & 0xFF; 2389 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2390 2391 data = hdr_metadata.maximum_content_light_level; 2392 info_packet->sb[i++] = data & 0xFF; 2393 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2394 2395 data = hdr_metadata.maximum_frame_average_light_level; 2396 info_packet->sb[i++] = data & 0xFF; 2397 info_packet->sb[i++] = (data & 0xFF00) >> 8; 2398 2399 if (dc_is_hdmi_signal(signal)) { 2400 uint32_t checksum = 0; 2401 2402 checksum += info_packet->hb0; 2403 checksum += info_packet->hb1; 2404 checksum += info_packet->hb2; 2405 2406 for (i = 1; i <= info_packet->hb2; i++) 2407 checksum += info_packet->sb[i]; 2408 2409 info_packet->sb[0] = 0x100 - checksum; 2410 } else if (dc_is_dp_signal(signal)) { 2411 info_packet->sb[0] = 0x01; 2412 info_packet->sb[1] = 0x1A; 2413 } 2414 } 2415 2416 static void set_vsc_info_packet( 2417 struct encoder_info_packet *info_packet, 2418 struct dc_stream_state *stream) 2419 { 2420 unsigned int vscPacketRevision = 0; 2421 unsigned int i; 2422 2423 if (stream->sink->link->psr_enabled) { 2424 vscPacketRevision = 2; 2425 } 2426 2427 /* VSC packet not needed based on the features 2428 * supported by this DP display 2429 */ 2430 if (vscPacketRevision == 0) 2431 return; 2432 2433 if (vscPacketRevision == 0x2) { 2434 /* Secondary-data Packet ID = 0*/ 2435 info_packet->hb0 = 0x00; 2436 /* 07h - Packet Type Value indicating Video 2437 * Stream Configuration packet 2438 */ 2439 info_packet->hb1 = 0x07; 2440 /* 02h = VSC SDP supporting 3D stereo and PSR 2441 * (applies to eDP v1.3 or higher). 2442 */ 2443 info_packet->hb2 = 0x02; 2444 /* 08h = VSC packet supporting 3D stereo + PSR 2445 * (HB2 = 02h). 2446 */ 2447 info_packet->hb3 = 0x08; 2448 2449 for (i = 0; i < 28; i++) 2450 info_packet->sb[i] = 0; 2451 2452 info_packet->valid = true; 2453 } 2454 2455 /*TODO: stereo 3D support and extend pixel encoding colorimetry*/ 2456 } 2457 2458 void dc_resource_state_destruct(struct dc_state *context) 2459 { 2460 int i, j; 2461 2462 for (i = 0; i < context->stream_count; i++) { 2463 for (j = 0; j < context->stream_status[i].plane_count; j++) 2464 dc_plane_state_release( 2465 context->stream_status[i].plane_states[j]); 2466 2467 context->stream_status[i].plane_count = 0; 2468 dc_stream_release(context->streams[i]); 2469 context->streams[i] = NULL; 2470 } 2471 } 2472 2473 /* 2474 * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced 2475 * by the src_ctx 2476 */ 2477 void dc_resource_state_copy_construct( 2478 const struct dc_state *src_ctx, 2479 struct dc_state *dst_ctx) 2480 { 2481 int i, j; 2482 struct kref refcount = dst_ctx->refcount; 2483 2484 *dst_ctx = *src_ctx; 2485 2486 for (i = 0; i < MAX_PIPES; i++) { 2487 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; 2488 2489 if (cur_pipe->top_pipe) 2490 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; 2491 2492 if (cur_pipe->bottom_pipe) 2493 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; 2494 2495 } 2496 2497 for (i = 0; i < dst_ctx->stream_count; i++) { 2498 dc_stream_retain(dst_ctx->streams[i]); 2499 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) 2500 dc_plane_state_retain( 2501 dst_ctx->stream_status[i].plane_states[j]); 2502 } 2503 2504 /* context refcount should not be overridden */ 2505 dst_ctx->refcount = refcount; 2506 2507 } 2508 2509 struct clock_source *dc_resource_find_first_free_pll( 2510 struct resource_context *res_ctx, 2511 const struct resource_pool *pool) 2512 { 2513 int i; 2514 2515 for (i = 0; i < pool->clk_src_count; ++i) { 2516 if (res_ctx->clock_source_ref_count[i] == 0) 2517 return pool->clock_sources[i]; 2518 } 2519 2520 return NULL; 2521 } 2522 2523 void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 2524 { 2525 enum signal_type signal = SIGNAL_TYPE_NONE; 2526 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; 2527 2528 /* default all packets to invalid */ 2529 info->avi.valid = false; 2530 info->gamut.valid = false; 2531 info->vendor.valid = false; 2532 info->spd.valid = false; 2533 info->hdrsmd.valid = false; 2534 info->vsc.valid = false; 2535 2536 signal = pipe_ctx->stream->signal; 2537 2538 /* HDMi and DP have different info packets*/ 2539 if (dc_is_hdmi_signal(signal)) { 2540 set_avi_info_frame(&info->avi, pipe_ctx); 2541 2542 set_vendor_info_packet(&info->vendor, pipe_ctx->stream); 2543 2544 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2545 2546 set_hdr_static_info_packet(&info->hdrsmd, 2547 pipe_ctx->plane_state, pipe_ctx->stream); 2548 2549 } else if (dc_is_dp_signal(signal)) { 2550 set_vsc_info_packet(&info->vsc, pipe_ctx->stream); 2551 2552 set_spd_info_packet(&info->spd, pipe_ctx->stream); 2553 2554 set_hdr_static_info_packet(&info->hdrsmd, 2555 pipe_ctx->plane_state, pipe_ctx->stream); 2556 } 2557 2558 patch_gamut_packet_checksum(&info->gamut); 2559 } 2560 2561 enum dc_status resource_map_clock_resources( 2562 const struct dc *dc, 2563 struct dc_state *context, 2564 struct dc_stream_state *stream) 2565 { 2566 /* acquire new resources */ 2567 const struct resource_pool *pool = dc->res_pool; 2568 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 2569 &context->res_ctx, stream); 2570 2571 if (!pipe_ctx) 2572 return DC_ERROR_UNEXPECTED; 2573 2574 if (dc_is_dp_signal(pipe_ctx->stream->signal) 2575 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 2576 pipe_ctx->clock_source = pool->dp_clock_source; 2577 else { 2578 pipe_ctx->clock_source = NULL; 2579 2580 if (!dc->config.disable_disp_pll_sharing) 2581 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing( 2582 &context->res_ctx, 2583 pipe_ctx); 2584 2585 if (pipe_ctx->clock_source == NULL) 2586 pipe_ctx->clock_source = 2587 dc_resource_find_first_free_pll( 2588 &context->res_ctx, 2589 pool); 2590 } 2591 2592 if (pipe_ctx->clock_source == NULL) 2593 return DC_NO_CLOCK_SOURCE_RESOURCE; 2594 2595 resource_reference_clock_source( 2596 &context->res_ctx, pool, 2597 pipe_ctx->clock_source); 2598 2599 return DC_OK; 2600 } 2601 2602 /* 2603 * Note: We need to disable output if clock sources change, 2604 * since bios does optimization and doesn't apply if changing 2605 * PHY when not already disabled. 2606 */ 2607 bool pipe_need_reprogram( 2608 struct pipe_ctx *pipe_ctx_old, 2609 struct pipe_ctx *pipe_ctx) 2610 { 2611 if (!pipe_ctx_old->stream) 2612 return false; 2613 2614 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) 2615 return true; 2616 2617 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) 2618 return true; 2619 2620 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) 2621 return true; 2622 2623 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source 2624 && pipe_ctx_old->stream != pipe_ctx->stream) 2625 return true; 2626 2627 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) 2628 return true; 2629 2630 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) 2631 return true; 2632 2633 2634 return false; 2635 } 2636 2637 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 2638 struct bit_depth_reduction_params *fmt_bit_depth) 2639 { 2640 enum dc_dither_option option = stream->dither_option; 2641 enum dc_pixel_encoding pixel_encoding = 2642 stream->timing.pixel_encoding; 2643 2644 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); 2645 2646 if (option == DITHER_OPTION_DEFAULT) { 2647 switch (stream->timing.display_color_depth) { 2648 case COLOR_DEPTH_666: 2649 option = DITHER_OPTION_SPATIAL6; 2650 break; 2651 case COLOR_DEPTH_888: 2652 option = DITHER_OPTION_SPATIAL8; 2653 break; 2654 case COLOR_DEPTH_101010: 2655 option = DITHER_OPTION_SPATIAL10; 2656 break; 2657 default: 2658 option = DITHER_OPTION_DISABLE; 2659 } 2660 } 2661 2662 if (option == DITHER_OPTION_DISABLE) 2663 return; 2664 2665 if (option == DITHER_OPTION_TRUN6) { 2666 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2667 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; 2668 } else if (option == DITHER_OPTION_TRUN8 || 2669 option == DITHER_OPTION_TRUN8_SPATIAL6 || 2670 option == DITHER_OPTION_TRUN8_FM6) { 2671 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2672 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; 2673 } else if (option == DITHER_OPTION_TRUN10 || 2674 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2675 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2676 option == DITHER_OPTION_TRUN10_FM8 || 2677 option == DITHER_OPTION_TRUN10_FM6 || 2678 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2679 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2680 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2681 } 2682 2683 /* special case - Formatter can only reduce by 4 bits at most. 2684 * When reducing from 12 to 6 bits, 2685 * HW recommends we use trunc with round mode 2686 * (if we did nothing, trunc to 10 bits would be used) 2687 * note that any 12->10 bit reduction is ignored prior to DCE8, 2688 * as the input was 10 bits. 2689 */ 2690 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2691 option == DITHER_OPTION_SPATIAL6 || 2692 option == DITHER_OPTION_FM6) { 2693 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 2694 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 2695 fmt_bit_depth->flags.TRUNCATE_MODE = 1; 2696 } 2697 2698 /* spatial dither 2699 * note that spatial modes 1-3 are never used 2700 */ 2701 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 2702 option == DITHER_OPTION_SPATIAL6 || 2703 option == DITHER_OPTION_TRUN10_SPATIAL6 || 2704 option == DITHER_OPTION_TRUN8_SPATIAL6) { 2705 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2706 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; 2707 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2708 fmt_bit_depth->flags.RGB_RANDOM = 2709 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2710 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || 2711 option == DITHER_OPTION_SPATIAL8 || 2712 option == DITHER_OPTION_SPATIAL8_FM6 || 2713 option == DITHER_OPTION_TRUN10_SPATIAL8 || 2714 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2715 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2716 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; 2717 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2718 fmt_bit_depth->flags.RGB_RANDOM = 2719 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2720 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || 2721 option == DITHER_OPTION_SPATIAL10 || 2722 option == DITHER_OPTION_SPATIAL10_FM8 || 2723 option == DITHER_OPTION_SPATIAL10_FM6) { 2724 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 2725 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; 2726 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 2727 fmt_bit_depth->flags.RGB_RANDOM = 2728 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 2729 } 2730 2731 if (option == DITHER_OPTION_SPATIAL6 || 2732 option == DITHER_OPTION_SPATIAL8 || 2733 option == DITHER_OPTION_SPATIAL10) { 2734 fmt_bit_depth->flags.FRAME_RANDOM = 0; 2735 } else { 2736 fmt_bit_depth->flags.FRAME_RANDOM = 1; 2737 } 2738 2739 ////////////////////// 2740 //// temporal dither 2741 ////////////////////// 2742 if (option == DITHER_OPTION_FM6 || 2743 option == DITHER_OPTION_SPATIAL8_FM6 || 2744 option == DITHER_OPTION_SPATIAL10_FM6 || 2745 option == DITHER_OPTION_TRUN10_FM6 || 2746 option == DITHER_OPTION_TRUN8_FM6 || 2747 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 2748 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2749 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; 2750 } else if (option == DITHER_OPTION_FM8 || 2751 option == DITHER_OPTION_SPATIAL10_FM8 || 2752 option == DITHER_OPTION_TRUN10_FM8) { 2753 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2754 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; 2755 } else if (option == DITHER_OPTION_FM10) { 2756 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 2757 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; 2758 } 2759 2760 fmt_bit_depth->pixel_encoding = pixel_encoding; 2761 } 2762 2763 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) 2764 { 2765 struct dc *core_dc = dc; 2766 struct dc_link *link = stream->sink->link; 2767 struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; 2768 enum dc_status res = DC_OK; 2769 2770 calculate_phy_pix_clks(stream); 2771 2772 if (!tg->funcs->validate_timing(tg, &stream->timing)) 2773 res = DC_FAIL_CONTROLLER_VALIDATE; 2774 2775 if (res == DC_OK) 2776 if (!link->link_enc->funcs->validate_output_with_stream( 2777 link->link_enc, stream)) 2778 res = DC_FAIL_ENC_VALIDATE; 2779 2780 /* TODO: validate audio ASIC caps, encoder */ 2781 2782 if (res == DC_OK) 2783 res = dc_link_validate_mode_timing(stream, 2784 link, 2785 &stream->timing); 2786 2787 return res; 2788 } 2789 2790 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) 2791 { 2792 enum dc_status res = DC_OK; 2793 2794 /* TODO For now validates pixel format only */ 2795 if (dc->res_pool->funcs->validate_plane) 2796 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps); 2797 2798 return res; 2799 } 2800