1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "resource.h" 29 #include "include/irq_service_interface.h" 30 #include "link_encoder.h" 31 #include "stream_encoder.h" 32 #include "opp.h" 33 #include "timing_generator.h" 34 #include "transform.h" 35 #include "dccg.h" 36 #include "dchubbub.h" 37 #include "dpp.h" 38 #include "core_types.h" 39 #include "set_mode_types.h" 40 #include "virtual/virtual_stream_encoder.h" 41 #include "dpcd_defs.h" 42 #include "link_enc_cfg.h" 43 #include "link.h" 44 #include "virtual/virtual_link_hwss.h" 45 #include "link/hwss/link_hwss_dio.h" 46 #include "link/hwss/link_hwss_dpia.h" 47 #include "link/hwss/link_hwss_hpo_dp.h" 48 #include "link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h" 49 #include "link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h" 50 51 #if defined(CONFIG_DRM_AMD_DC_SI) 52 #include "dce60/dce60_resource.h" 53 #endif 54 #include "dce80/dce80_resource.h" 55 #include "dce100/dce100_resource.h" 56 #include "dce110/dce110_resource.h" 57 #include "dce112/dce112_resource.h" 58 #include "dce120/dce120_resource.h" 59 #include "dcn10/dcn10_resource.h" 60 #include "dcn20/dcn20_resource.h" 61 #include "dcn21/dcn21_resource.h" 62 #include "dcn201/dcn201_resource.h" 63 #include "dcn30/dcn30_resource.h" 64 #include "dcn301/dcn301_resource.h" 65 #include "dcn302/dcn302_resource.h" 66 #include "dcn303/dcn303_resource.h" 67 #include "dcn31/dcn31_resource.h" 68 #include "dcn314/dcn314_resource.h" 69 #include "dcn315/dcn315_resource.h" 70 #include "dcn316/dcn316_resource.h" 71 #include "../dcn32/dcn32_resource.h" 72 #include "../dcn321/dcn321_resource.h" 73 74 #define VISUAL_CONFIRM_BASE_DEFAULT 3 75 #define VISUAL_CONFIRM_BASE_MIN 1 76 #define VISUAL_CONFIRM_BASE_MAX 10 77 /* we choose 240 because it is a common denominator of common v addressable 78 * such as 2160, 1440, 1200, 960. So we take 1/240 portion of v addressable as 79 * the visual confirm dpp offset height. So visual confirm height can stay 80 * relatively the same independent from timing used. 81 */ 82 #define VISUAL_CONFIRM_DPP_OFFSET_DENO 240 83 84 #define DC_LOGGER_INIT(logger) 85 86 #define UNABLE_TO_SPLIT -1 87 88 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 89 { 90 enum dce_version dc_version = DCE_VERSION_UNKNOWN; 91 92 switch (asic_id.chip_family) { 93 94 #if defined(CONFIG_DRM_AMD_DC_SI) 95 case FAMILY_SI: 96 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) || 97 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) || 98 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev)) 99 dc_version = DCE_VERSION_6_0; 100 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev)) 101 dc_version = DCE_VERSION_6_4; 102 else 103 dc_version = DCE_VERSION_6_1; 104 break; 105 #endif 106 case FAMILY_CI: 107 dc_version = DCE_VERSION_8_0; 108 break; 109 case FAMILY_KV: 110 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) || 111 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) || 112 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev)) 113 dc_version = DCE_VERSION_8_3; 114 else 115 dc_version = DCE_VERSION_8_1; 116 break; 117 case FAMILY_CZ: 118 dc_version = DCE_VERSION_11_0; 119 break; 120 121 case FAMILY_VI: 122 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) || 123 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) { 124 dc_version = DCE_VERSION_10_0; 125 break; 126 } 127 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || 128 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || 129 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { 130 dc_version = DCE_VERSION_11_2; 131 } 132 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) 133 dc_version = DCE_VERSION_11_22; 134 break; 135 case FAMILY_AI: 136 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev)) 137 dc_version = DCE_VERSION_12_1; 138 else 139 dc_version = DCE_VERSION_12_0; 140 break; 141 case FAMILY_RV: 142 dc_version = DCN_VERSION_1_0; 143 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) 144 dc_version = DCN_VERSION_1_01; 145 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) 146 dc_version = DCN_VERSION_2_1; 147 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) 148 dc_version = DCN_VERSION_2_1; 149 break; 150 151 case FAMILY_NV: 152 dc_version = DCN_VERSION_2_0; 153 if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) { 154 dc_version = DCN_VERSION_2_01; 155 break; 156 } 157 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) 158 dc_version = DCN_VERSION_3_0; 159 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) 160 dc_version = DCN_VERSION_3_02; 161 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) 162 dc_version = DCN_VERSION_3_03; 163 break; 164 165 case FAMILY_VGH: 166 dc_version = DCN_VERSION_3_01; 167 break; 168 169 case FAMILY_YELLOW_CARP: 170 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) 171 dc_version = DCN_VERSION_3_1; 172 break; 173 case AMDGPU_FAMILY_GC_10_3_6: 174 if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev)) 175 dc_version = DCN_VERSION_3_15; 176 break; 177 case AMDGPU_FAMILY_GC_10_3_7: 178 if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev)) 179 dc_version = DCN_VERSION_3_16; 180 break; 181 case AMDGPU_FAMILY_GC_11_0_0: 182 dc_version = DCN_VERSION_3_2; 183 if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev)) 184 dc_version = DCN_VERSION_3_21; 185 break; 186 case AMDGPU_FAMILY_GC_11_0_1: 187 dc_version = DCN_VERSION_3_14; 188 break; 189 default: 190 dc_version = DCE_VERSION_UNKNOWN; 191 break; 192 } 193 return dc_version; 194 } 195 196 struct resource_pool *dc_create_resource_pool(struct dc *dc, 197 const struct dc_init_data *init_data, 198 enum dce_version dc_version) 199 { 200 struct resource_pool *res_pool = NULL; 201 202 switch (dc_version) { 203 #if defined(CONFIG_DRM_AMD_DC_SI) 204 case DCE_VERSION_6_0: 205 res_pool = dce60_create_resource_pool( 206 init_data->num_virtual_links, dc); 207 break; 208 case DCE_VERSION_6_1: 209 res_pool = dce61_create_resource_pool( 210 init_data->num_virtual_links, dc); 211 break; 212 case DCE_VERSION_6_4: 213 res_pool = dce64_create_resource_pool( 214 init_data->num_virtual_links, dc); 215 break; 216 #endif 217 case DCE_VERSION_8_0: 218 res_pool = dce80_create_resource_pool( 219 init_data->num_virtual_links, dc); 220 break; 221 case DCE_VERSION_8_1: 222 res_pool = dce81_create_resource_pool( 223 init_data->num_virtual_links, dc); 224 break; 225 case DCE_VERSION_8_3: 226 res_pool = dce83_create_resource_pool( 227 init_data->num_virtual_links, dc); 228 break; 229 case DCE_VERSION_10_0: 230 res_pool = dce100_create_resource_pool( 231 init_data->num_virtual_links, dc); 232 break; 233 case DCE_VERSION_11_0: 234 res_pool = dce110_create_resource_pool( 235 init_data->num_virtual_links, dc, 236 init_data->asic_id); 237 break; 238 case DCE_VERSION_11_2: 239 case DCE_VERSION_11_22: 240 res_pool = dce112_create_resource_pool( 241 init_data->num_virtual_links, dc); 242 break; 243 case DCE_VERSION_12_0: 244 case DCE_VERSION_12_1: 245 res_pool = dce120_create_resource_pool( 246 init_data->num_virtual_links, dc); 247 break; 248 249 #if defined(CONFIG_DRM_AMD_DC_FP) 250 case DCN_VERSION_1_0: 251 case DCN_VERSION_1_01: 252 res_pool = dcn10_create_resource_pool(init_data, dc); 253 break; 254 case DCN_VERSION_2_0: 255 res_pool = dcn20_create_resource_pool(init_data, dc); 256 break; 257 case DCN_VERSION_2_1: 258 res_pool = dcn21_create_resource_pool(init_data, dc); 259 break; 260 case DCN_VERSION_2_01: 261 res_pool = dcn201_create_resource_pool(init_data, dc); 262 break; 263 case DCN_VERSION_3_0: 264 res_pool = dcn30_create_resource_pool(init_data, dc); 265 break; 266 case DCN_VERSION_3_01: 267 res_pool = dcn301_create_resource_pool(init_data, dc); 268 break; 269 case DCN_VERSION_3_02: 270 res_pool = dcn302_create_resource_pool(init_data, dc); 271 break; 272 case DCN_VERSION_3_03: 273 res_pool = dcn303_create_resource_pool(init_data, dc); 274 break; 275 case DCN_VERSION_3_1: 276 res_pool = dcn31_create_resource_pool(init_data, dc); 277 break; 278 case DCN_VERSION_3_14: 279 res_pool = dcn314_create_resource_pool(init_data, dc); 280 break; 281 case DCN_VERSION_3_15: 282 res_pool = dcn315_create_resource_pool(init_data, dc); 283 break; 284 case DCN_VERSION_3_16: 285 res_pool = dcn316_create_resource_pool(init_data, dc); 286 break; 287 case DCN_VERSION_3_2: 288 res_pool = dcn32_create_resource_pool(init_data, dc); 289 break; 290 case DCN_VERSION_3_21: 291 res_pool = dcn321_create_resource_pool(init_data, dc); 292 break; 293 #endif /* CONFIG_DRM_AMD_DC_FP */ 294 default: 295 break; 296 } 297 298 if (res_pool != NULL) { 299 if (dc->ctx->dc_bios->fw_info_valid) { 300 res_pool->ref_clocks.xtalin_clock_inKhz = 301 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 302 /* initialize with firmware data first, no all 303 * ASIC have DCCG SW component. FPGA or 304 * simulation need initialization of 305 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz 306 * with xtalin_clock_inKhz 307 */ 308 res_pool->ref_clocks.dccg_ref_clock_inKhz = 309 res_pool->ref_clocks.xtalin_clock_inKhz; 310 res_pool->ref_clocks.dchub_ref_clock_inKhz = 311 res_pool->ref_clocks.xtalin_clock_inKhz; 312 } else 313 ASSERT_CRITICAL(false); 314 } 315 316 return res_pool; 317 } 318 319 void dc_destroy_resource_pool(struct dc *dc) 320 { 321 if (dc) { 322 if (dc->res_pool) 323 dc->res_pool->funcs->destroy(&dc->res_pool); 324 325 kfree(dc->hwseq); 326 } 327 } 328 329 static void update_num_audio( 330 const struct resource_straps *straps, 331 unsigned int *num_audio, 332 struct audio_support *aud_support) 333 { 334 aud_support->dp_audio = true; 335 aud_support->hdmi_audio_native = false; 336 aud_support->hdmi_audio_on_dongle = false; 337 338 if (straps->hdmi_disable == 0) { 339 if (straps->dc_pinstraps_audio & 0x2) { 340 aud_support->hdmi_audio_on_dongle = true; 341 aud_support->hdmi_audio_native = true; 342 } 343 } 344 345 switch (straps->audio_stream_number) { 346 case 0: /* multi streams supported */ 347 break; 348 case 1: /* multi streams not supported */ 349 *num_audio = 1; 350 break; 351 default: 352 DC_ERR("DC: unexpected audio fuse!\n"); 353 } 354 } 355 356 bool resource_construct( 357 unsigned int num_virtual_links, 358 struct dc *dc, 359 struct resource_pool *pool, 360 const struct resource_create_funcs *create_funcs) 361 { 362 struct dc_context *ctx = dc->ctx; 363 const struct resource_caps *caps = pool->res_cap; 364 int i; 365 unsigned int num_audio = caps->num_audio; 366 struct resource_straps straps = {0}; 367 368 if (create_funcs->read_dce_straps) 369 create_funcs->read_dce_straps(dc->ctx, &straps); 370 371 pool->audio_count = 0; 372 if (create_funcs->create_audio) { 373 /* find the total number of streams available via the 374 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 375 * registers (one for each pin) starting from pin 1 376 * up to the max number of audio pins. 377 * We stop on the first pin where 378 * PORT_CONNECTIVITY == 1 (as instructed by HW team). 379 */ 380 update_num_audio(&straps, &num_audio, &pool->audio_support); 381 for (i = 0; i < caps->num_audio; i++) { 382 struct audio *aud = create_funcs->create_audio(ctx, i); 383 384 if (aud == NULL) { 385 DC_ERR("DC: failed to create audio!\n"); 386 return false; 387 } 388 if (!aud->funcs->endpoint_valid(aud)) { 389 aud->funcs->destroy(&aud); 390 break; 391 } 392 pool->audios[i] = aud; 393 pool->audio_count++; 394 } 395 } 396 397 pool->stream_enc_count = 0; 398 if (create_funcs->create_stream_encoder) { 399 for (i = 0; i < caps->num_stream_encoder; i++) { 400 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx); 401 if (pool->stream_enc[i] == NULL) 402 DC_ERR("DC: failed to create stream_encoder!\n"); 403 pool->stream_enc_count++; 404 } 405 } 406 407 pool->hpo_dp_stream_enc_count = 0; 408 if (create_funcs->create_hpo_dp_stream_encoder) { 409 for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) { 410 pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx); 411 if (pool->hpo_dp_stream_enc[i] == NULL) 412 DC_ERR("DC: failed to create HPO DP stream encoder!\n"); 413 pool->hpo_dp_stream_enc_count++; 414 415 } 416 } 417 418 pool->hpo_dp_link_enc_count = 0; 419 if (create_funcs->create_hpo_dp_link_encoder) { 420 for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) { 421 pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx); 422 if (pool->hpo_dp_link_enc[i] == NULL) 423 DC_ERR("DC: failed to create HPO DP link encoder!\n"); 424 pool->hpo_dp_link_enc_count++; 425 } 426 } 427 428 for (i = 0; i < caps->num_mpc_3dlut; i++) { 429 pool->mpc_lut[i] = dc_create_3dlut_func(); 430 if (pool->mpc_lut[i] == NULL) 431 DC_ERR("DC: failed to create MPC 3dlut!\n"); 432 pool->mpc_shaper[i] = dc_create_transfer_func(); 433 if (pool->mpc_shaper[i] == NULL) 434 DC_ERR("DC: failed to create MPC shaper!\n"); 435 } 436 437 dc->caps.dynamic_audio = false; 438 if (pool->audio_count < pool->stream_enc_count) { 439 dc->caps.dynamic_audio = true; 440 } 441 for (i = 0; i < num_virtual_links; i++) { 442 pool->stream_enc[pool->stream_enc_count] = 443 virtual_stream_encoder_create( 444 ctx, ctx->dc_bios); 445 if (pool->stream_enc[pool->stream_enc_count] == NULL) { 446 DC_ERR("DC: failed to create stream_encoder!\n"); 447 return false; 448 } 449 pool->stream_enc_count++; 450 } 451 452 dc->hwseq = create_funcs->create_hwseq(ctx); 453 454 return true; 455 } 456 static int find_matching_clock_source( 457 const struct resource_pool *pool, 458 struct clock_source *clock_source) 459 { 460 461 int i; 462 463 for (i = 0; i < pool->clk_src_count; i++) { 464 if (pool->clock_sources[i] == clock_source) 465 return i; 466 } 467 return -1; 468 } 469 470 void resource_unreference_clock_source( 471 struct resource_context *res_ctx, 472 const struct resource_pool *pool, 473 struct clock_source *clock_source) 474 { 475 int i = find_matching_clock_source(pool, clock_source); 476 477 if (i > -1) 478 res_ctx->clock_source_ref_count[i]--; 479 480 if (pool->dp_clock_source == clock_source) 481 res_ctx->dp_clock_source_ref_count--; 482 } 483 484 void resource_reference_clock_source( 485 struct resource_context *res_ctx, 486 const struct resource_pool *pool, 487 struct clock_source *clock_source) 488 { 489 int i = find_matching_clock_source(pool, clock_source); 490 491 if (i > -1) 492 res_ctx->clock_source_ref_count[i]++; 493 494 if (pool->dp_clock_source == clock_source) 495 res_ctx->dp_clock_source_ref_count++; 496 } 497 498 int resource_get_clock_source_reference( 499 struct resource_context *res_ctx, 500 const struct resource_pool *pool, 501 struct clock_source *clock_source) 502 { 503 int i = find_matching_clock_source(pool, clock_source); 504 505 if (i > -1) 506 return res_ctx->clock_source_ref_count[i]; 507 508 if (pool->dp_clock_source == clock_source) 509 return res_ctx->dp_clock_source_ref_count; 510 511 return -1; 512 } 513 514 bool resource_are_vblanks_synchronizable( 515 struct dc_stream_state *stream1, 516 struct dc_stream_state *stream2) 517 { 518 uint32_t base60_refresh_rates[] = {10, 20, 5}; 519 uint8_t i; 520 uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates); 521 uint64_t frame_time_diff; 522 523 if (stream1->ctx->dc->config.vblank_alignment_dto_params && 524 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 && 525 dc_is_dp_signal(stream1->signal) && 526 dc_is_dp_signal(stream2->signal) && 527 false == stream1->has_non_synchronizable_pclk && 528 false == stream2->has_non_synchronizable_pclk && 529 stream1->timing.flags.VBLANK_SYNCHRONIZABLE && 530 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) { 531 /* disable refresh rates higher than 60Hz for now */ 532 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/ 533 stream1->timing.v_total > 60) 534 return false; 535 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/ 536 stream2->timing.v_total > 60) 537 return false; 538 frame_time_diff = (uint64_t)10000 * 539 stream1->timing.h_total * 540 stream1->timing.v_total * 541 stream2->timing.pix_clk_100hz; 542 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz); 543 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total); 544 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total); 545 for (i = 0; i < rr_count; i++) { 546 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000; 547 548 if (diff < 0) 549 diff = -diff; 550 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff) 551 return true; 552 } 553 } 554 return false; 555 } 556 557 bool resource_are_streams_timing_synchronizable( 558 struct dc_stream_state *stream1, 559 struct dc_stream_state *stream2) 560 { 561 if (stream1->timing.h_total != stream2->timing.h_total) 562 return false; 563 564 if (stream1->timing.v_total != stream2->timing.v_total) 565 return false; 566 567 if (stream1->timing.h_addressable 568 != stream2->timing.h_addressable) 569 return false; 570 571 if (stream1->timing.v_addressable 572 != stream2->timing.v_addressable) 573 return false; 574 575 if (stream1->timing.v_front_porch 576 != stream2->timing.v_front_porch) 577 return false; 578 579 if (stream1->timing.pix_clk_100hz 580 != stream2->timing.pix_clk_100hz) 581 return false; 582 583 if (stream1->clamping.c_depth != stream2->clamping.c_depth) 584 return false; 585 586 if (stream1->phy_pix_clk != stream2->phy_pix_clk 587 && (!dc_is_dp_signal(stream1->signal) 588 || !dc_is_dp_signal(stream2->signal))) 589 return false; 590 591 if (stream1->view_format != stream2->view_format) 592 return false; 593 594 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param) 595 return false; 596 597 return true; 598 } 599 static bool is_dp_and_hdmi_sharable( 600 struct dc_stream_state *stream1, 601 struct dc_stream_state *stream2) 602 { 603 if (stream1->ctx->dc->caps.disable_dp_clk_share) 604 return false; 605 606 if (stream1->clamping.c_depth != COLOR_DEPTH_888 || 607 stream2->clamping.c_depth != COLOR_DEPTH_888) 608 return false; 609 610 return true; 611 612 } 613 614 static bool is_sharable_clk_src( 615 const struct pipe_ctx *pipe_with_clk_src, 616 const struct pipe_ctx *pipe) 617 { 618 if (pipe_with_clk_src->clock_source == NULL) 619 return false; 620 621 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) 622 return false; 623 624 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) || 625 (dc_is_dp_signal(pipe->stream->signal) && 626 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream, 627 pipe->stream))) 628 return false; 629 630 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) 631 && dc_is_dual_link_signal(pipe->stream->signal)) 632 return false; 633 634 if (dc_is_hdmi_signal(pipe->stream->signal) 635 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal)) 636 return false; 637 638 if (!resource_are_streams_timing_synchronizable( 639 pipe_with_clk_src->stream, pipe->stream)) 640 return false; 641 642 return true; 643 } 644 645 struct clock_source *resource_find_used_clk_src_for_sharing( 646 struct resource_context *res_ctx, 647 struct pipe_ctx *pipe_ctx) 648 { 649 int i; 650 651 for (i = 0; i < MAX_PIPES; i++) { 652 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx)) 653 return res_ctx->pipe_ctx[i].clock_source; 654 } 655 656 return NULL; 657 } 658 659 static enum pixel_format convert_pixel_format_to_dalsurface( 660 enum surface_pixel_format surface_pixel_format) 661 { 662 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 663 664 switch (surface_pixel_format) { 665 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 666 dal_pixel_format = PIXEL_FORMAT_INDEX8; 667 break; 668 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 669 dal_pixel_format = PIXEL_FORMAT_RGB565; 670 break; 671 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 672 dal_pixel_format = PIXEL_FORMAT_RGB565; 673 break; 674 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 675 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 676 break; 677 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 678 dal_pixel_format = PIXEL_FORMAT_ARGB8888; 679 break; 680 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 681 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 682 break; 683 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 684 dal_pixel_format = PIXEL_FORMAT_ARGB2101010; 685 break; 686 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 687 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS; 688 break; 689 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 690 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 691 dal_pixel_format = PIXEL_FORMAT_FP16; 692 break; 693 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 694 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 695 dal_pixel_format = PIXEL_FORMAT_420BPP8; 696 break; 697 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 698 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 699 dal_pixel_format = PIXEL_FORMAT_420BPP10; 700 break; 701 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 702 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 703 default: 704 dal_pixel_format = PIXEL_FORMAT_UNKNOWN; 705 break; 706 } 707 return dal_pixel_format; 708 } 709 710 static inline void get_vp_scan_direction( 711 enum dc_rotation_angle rotation, 712 bool horizontal_mirror, 713 bool *orthogonal_rotation, 714 bool *flip_vert_scan_dir, 715 bool *flip_horz_scan_dir) 716 { 717 *orthogonal_rotation = false; 718 *flip_vert_scan_dir = false; 719 *flip_horz_scan_dir = false; 720 if (rotation == ROTATION_ANGLE_180) { 721 *flip_vert_scan_dir = true; 722 *flip_horz_scan_dir = true; 723 } else if (rotation == ROTATION_ANGLE_90) { 724 *orthogonal_rotation = true; 725 *flip_horz_scan_dir = true; 726 } else if (rotation == ROTATION_ANGLE_270) { 727 *orthogonal_rotation = true; 728 *flip_vert_scan_dir = true; 729 } 730 731 if (horizontal_mirror) 732 *flip_horz_scan_dir = !*flip_horz_scan_dir; 733 } 734 735 int resource_get_num_mpc_splits(const struct pipe_ctx *pipe) 736 { 737 int mpc_split_count = 0; 738 const struct pipe_ctx *other_pipe = pipe->bottom_pipe; 739 740 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 741 mpc_split_count++; 742 other_pipe = other_pipe->bottom_pipe; 743 } 744 other_pipe = pipe->top_pipe; 745 while (other_pipe && other_pipe->plane_state == pipe->plane_state) { 746 mpc_split_count++; 747 other_pipe = other_pipe->top_pipe; 748 } 749 750 return mpc_split_count; 751 } 752 753 int resource_get_num_odm_splits(const struct pipe_ctx *pipe) 754 { 755 int odm_split_count = 0; 756 757 pipe = resource_get_otg_master(pipe); 758 759 while (pipe->next_odm_pipe) { 760 odm_split_count++; 761 pipe = pipe->next_odm_pipe; 762 } 763 return odm_split_count; 764 } 765 766 static int get_odm_split_index(struct pipe_ctx *pipe_ctx) 767 { 768 int index = 0; 769 770 pipe_ctx = resource_get_opp_head(pipe_ctx); 771 if (!pipe_ctx) 772 return 0; 773 774 while (pipe_ctx->prev_odm_pipe) { 775 index++; 776 pipe_ctx = pipe_ctx->prev_odm_pipe; 777 } 778 779 return index; 780 } 781 782 static int get_mpc_split_index(struct pipe_ctx *pipe_ctx) 783 { 784 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe; 785 int index = 0; 786 787 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) { 788 index++; 789 split_pipe = split_pipe->top_pipe; 790 } 791 792 return index; 793 } 794 795 /* 796 * This is a preliminary vp size calculation to allow us to check taps support. 797 * The result is completely overridden afterwards. 798 */ 799 static void calculate_viewport_size(struct pipe_ctx *pipe_ctx) 800 { 801 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 802 803 data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width)); 804 data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height)); 805 data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width)); 806 data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height)); 807 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 808 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { 809 swap(data->viewport.width, data->viewport.height); 810 swap(data->viewport_c.width, data->viewport_c.height); 811 } 812 } 813 814 static struct rect intersect_rec(const struct rect *r0, const struct rect *r1) 815 { 816 struct rect rec; 817 int r0_x_end = r0->x + r0->width; 818 int r1_x_end = r1->x + r1->width; 819 int r0_y_end = r0->y + r0->height; 820 int r1_y_end = r1->y + r1->height; 821 822 rec.x = r0->x > r1->x ? r0->x : r1->x; 823 rec.width = r0_x_end > r1_x_end ? r1_x_end - rec.x : r0_x_end - rec.x; 824 rec.y = r0->y > r1->y ? r0->y : r1->y; 825 rec.height = r0_y_end > r1_y_end ? r1_y_end - rec.y : r0_y_end - rec.y; 826 827 /* in case that there is no intersection */ 828 if (rec.width < 0 || rec.height < 0) 829 memset(&rec, 0, sizeof(rec)); 830 831 return rec; 832 } 833 834 static struct rect shift_rec(const struct rect *rec_in, int x, int y) 835 { 836 struct rect rec_out = *rec_in; 837 838 rec_out.x += x; 839 rec_out.y += y; 840 841 return rec_out; 842 } 843 844 static struct rect calculate_odm_slice_in_timing_active(struct pipe_ctx *pipe_ctx) 845 { 846 const struct dc_stream_state *stream = pipe_ctx->stream; 847 int odm_slice_count = resource_get_num_odm_splits(pipe_ctx) + 1; 848 int odm_slice_idx = get_odm_split_index(pipe_ctx); 849 bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count; 850 int h_active = stream->timing.h_addressable + 851 stream->timing.h_border_left + 852 stream->timing.h_border_right; 853 int odm_slice_width = h_active / odm_slice_count; 854 struct rect odm_rec; 855 856 odm_rec.x = odm_slice_width * odm_slice_idx; 857 odm_rec.width = is_last_odm_slice ? 858 /* last slice width is the reminder of h_active */ 859 h_active - odm_slice_width * (odm_slice_count - 1) : 860 /* odm slice width is the floor of h_active / count */ 861 odm_slice_width; 862 odm_rec.y = 0; 863 odm_rec.height = stream->timing.v_addressable + 864 stream->timing.v_border_bottom + 865 stream->timing.v_border_top; 866 867 return odm_rec; 868 } 869 870 static struct rect calculate_plane_rec_in_timing_active( 871 struct pipe_ctx *pipe_ctx, 872 const struct rect *rec_in) 873 { 874 /* 875 * The following diagram shows an example where we map a 1920x1200 876 * desktop to a 2560x1440 timing with a plane rect in the middle 877 * of the screen. To map a plane rect from Stream Source to Timing 878 * Active space, we first multiply stream scaling ratios (i.e 2304/1920 879 * horizontal and 1440/1200 vertical) to the plane's x and y, then 880 * we add stream destination offsets (i.e 128 horizontal, 0 vertical). 881 * This will give us a plane rect's position in Timing Active. However 882 * we have to remove the fractional. The rule is that we find left/right 883 * and top/bottom positions and round the value to the adjacent integer. 884 * 885 * Stream Source Space 886 * ------------ 887 * __________________________________________________ 888 * |Stream Source (1920 x 1200) ^ | 889 * | y | 890 * | <------- w --------|> | 891 * | __________________V | 892 * |<-- x -->|Plane//////////////| ^ | 893 * | |(pre scale)////////| | | 894 * | |///////////////////| | | 895 * | |///////////////////| h | 896 * | |///////////////////| | | 897 * | |///////////////////| | | 898 * | |///////////////////| V | 899 * | | 900 * | | 901 * |__________________________________________________| 902 * 903 * 904 * Timing Active Space 905 * --------------------------------- 906 * 907 * Timing Active (2560 x 1440) 908 * __________________________________________________ 909 * |*****| Stteam Destination (2304 x 1440) |*****| 910 * |*****| |*****| 911 * |<128>| |*****| 912 * |*****| __________________ |*****| 913 * |*****| |Plane/////////////| |*****| 914 * |*****| |(post scale)//////| |*****| 915 * |*****| |//////////////////| |*****| 916 * |*****| |//////////////////| |*****| 917 * |*****| |//////////////////| |*****| 918 * |*****| |//////////////////| |*****| 919 * |*****| |*****| 920 * |*****| |*****| 921 * |*****| |*****| 922 * |*****|______________________________________|*****| 923 * 924 * So the resulting formulas are shown below: 925 * 926 * recout_x = 128 + round(plane_x * 2304 / 1920) 927 * recout_w = 128 + round((plane_x + plane_w) * 2304 / 1920) - recout_x 928 * recout_y = 0 + round(plane_y * 1440 / 1280) 929 * recout_h = 0 + round((plane_y + plane_h) * 1440 / 1200) - recout_y 930 * 931 * NOTE: fixed point division is not error free. To reduce errors 932 * introduced by fixed point division, we divide only after 933 * multiplication is complete. 934 */ 935 const struct dc_stream_state *stream = pipe_ctx->stream; 936 struct rect rec_out = {0}; 937 struct fixed31_32 temp; 938 939 temp = dc_fixpt_from_fraction(rec_in->x * stream->dst.width, 940 stream->src.width); 941 rec_out.x = stream->dst.x + dc_fixpt_round(temp); 942 943 temp = dc_fixpt_from_fraction( 944 (rec_in->x + rec_in->width) * stream->dst.width, 945 stream->src.width); 946 rec_out.width = stream->dst.x + dc_fixpt_round(temp) - rec_out.x; 947 948 temp = dc_fixpt_from_fraction(rec_in->y * stream->dst.height, 949 stream->src.height); 950 rec_out.y = stream->dst.y + dc_fixpt_round(temp); 951 952 temp = dc_fixpt_from_fraction( 953 (rec_in->y + rec_in->height) * stream->dst.height, 954 stream->src.height); 955 rec_out.height = stream->dst.y + dc_fixpt_round(temp) - rec_out.y; 956 957 return rec_out; 958 } 959 960 static struct rect calculate_mpc_slice_in_timing_active( 961 struct pipe_ctx *pipe_ctx, 962 struct rect *plane_clip_rec) 963 { 964 const struct dc_stream_state *stream = pipe_ctx->stream; 965 int mpc_slice_count = resource_get_num_mpc_splits(pipe_ctx) + 1; 966 int mpc_slice_idx = get_mpc_split_index(pipe_ctx); 967 int epimo = mpc_slice_count - plane_clip_rec->width % mpc_slice_count - 1; 968 struct rect mpc_rec; 969 970 mpc_rec.width = plane_clip_rec->width / mpc_slice_count; 971 mpc_rec.x = plane_clip_rec->x + mpc_rec.width * mpc_slice_idx; 972 mpc_rec.height = plane_clip_rec->height; 973 mpc_rec.y = plane_clip_rec->y; 974 ASSERT(mpc_slice_count == 1 || 975 stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || 976 mpc_rec.width % 2 == 0); 977 978 /* extra pixels in the division remainder need to go to pipes after 979 * the extra pixel index minus one(epimo) defined here as: 980 */ 981 if (mpc_slice_idx > epimo) { 982 mpc_rec.x += mpc_slice_idx - epimo - 1; 983 mpc_rec.width += 1; 984 } 985 986 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { 987 ASSERT(mpc_rec.height % 2 == 0); 988 mpc_rec.height /= 2; 989 } 990 return mpc_rec; 991 } 992 993 static void adjust_recout_for_visual_confirm(struct rect *recout, 994 struct pipe_ctx *pipe_ctx) 995 { 996 struct dc *dc = pipe_ctx->stream->ctx->dc; 997 int dpp_offset, base_offset; 998 999 if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp) 1000 return; 1001 1002 dpp_offset = pipe_ctx->stream->timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO; 1003 dpp_offset *= pipe_ctx->plane_res.dpp->inst; 1004 1005 if ((dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_BASE_MIN) && 1006 dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_BASE_MAX) 1007 base_offset = dc->debug.visual_confirm_rect_height; 1008 else 1009 base_offset = VISUAL_CONFIRM_BASE_DEFAULT; 1010 1011 recout->height -= base_offset; 1012 recout->height -= dpp_offset; 1013 } 1014 1015 /* 1016 * The function maps a plane clip from Stream Source Space to ODM Slice Space 1017 * and calculates the rec of the overlapping area of MPC slice of the plane 1018 * clip, ODM slice associated with the pipe context and stream destination rec. 1019 */ 1020 static void calculate_recout(struct pipe_ctx *pipe_ctx) 1021 { 1022 /* 1023 * A plane clip represents the desired plane size and position in Stream 1024 * Source Space. Stream Source is the destination where all planes are 1025 * blended (i.e. positioned, scaled and overlaid). It is a canvas where 1026 * all planes associated with the current stream are drawn together. 1027 * After Stream Source is completed, we will further scale and 1028 * reposition the entire canvas of the stream source to Stream 1029 * Destination in Timing Active Space. This could be due to display 1030 * overscan adjustment where we will need to rescale and reposition all 1031 * the planes so they can fit into a TV with overscan or downscale 1032 * upscale features such as GPU scaling or VSR. 1033 * 1034 * This two step blending is a virtual procedure in software. In 1035 * hardware there is no such thing as Stream Source. all planes are 1036 * blended once in Timing Active Space. Software virtualizes a Stream 1037 * Source space to decouple the math complicity so scaling param 1038 * calculation focuses on one step at a time. 1039 * 1040 * In the following two diagrams, user applied 10% overscan adjustment 1041 * so the Stream Source needs to be scaled down a little before mapping 1042 * to Timing Active Space. As a result the Plane Clip is also scaled 1043 * down by the same ratio, Plane Clip position (i.e. x and y) with 1044 * respect to Stream Source is also scaled down. To map it in Timing 1045 * Active Space additional x and y offsets from Stream Destination are 1046 * added to Plane Clip as well. 1047 * 1048 * Stream Source Space 1049 * ------------ 1050 * __________________________________________________ 1051 * |Stream Source (3840 x 2160) ^ | 1052 * | y | 1053 * | | | 1054 * | __________________V | 1055 * |<-- x -->|Plane Clip/////////| | 1056 * | |(pre scale)////////| | 1057 * | |///////////////////| | 1058 * | |///////////////////| | 1059 * | |///////////////////| | 1060 * | |///////////////////| | 1061 * | |///////////////////| | 1062 * | | 1063 * | | 1064 * |__________________________________________________| 1065 * 1066 * 1067 * Timing Active Space (3840 x 2160) 1068 * --------------------------------- 1069 * 1070 * Timing Active 1071 * __________________________________________________ 1072 * | y_____________________________________________ | 1073 * |x |Stream Destination (3456 x 1944) | | 1074 * | | | | 1075 * | | __________________ | | 1076 * | | |Plane Clip////////| | | 1077 * | | |(post scale)//////| | | 1078 * | | |//////////////////| | | 1079 * | | |//////////////////| | | 1080 * | | |//////////////////| | | 1081 * | | |//////////////////| | | 1082 * | | | | 1083 * | | | | 1084 * | |____________________________________________| | 1085 * |__________________________________________________| 1086 * 1087 * 1088 * In Timing Active Space a plane clip could be further sliced into 1089 * pieces called MPC slices. Each Pipe Context is responsible for 1090 * processing only one MPC slice so the plane processing workload can be 1091 * distributed to multiple DPP Pipes. MPC slices could be blended 1092 * together to a single ODM slice. Each ODM slice is responsible for 1093 * processing a portion of Timing Active divided horizontally so the 1094 * output pixel processing workload can be distributed to multiple OPP 1095 * pipes. All ODM slices are mapped together in ODM block so all MPC 1096 * slices belong to different ODM slices could be pieced together to 1097 * form a single image in Timing Active. MPC slices must belong to 1098 * single ODM slice. If an MPC slice goes across ODM slice boundary, it 1099 * needs to be divided into two MPC slices one for each ODM slice. 1100 * 1101 * In the following diagram the output pixel processing workload is 1102 * divided horizontally into two ODM slices one for each OPP blend tree. 1103 * OPP0 blend tree is responsible for processing left half of Timing 1104 * Active, while OPP2 blend tree is responsible for processing right 1105 * half. 1106 * 1107 * The plane has two MPC slices. However since the right MPC slice goes 1108 * across ODM boundary, two DPP pipes are needed one for each OPP blend 1109 * tree. (i.e. DPP1 for OPP0 blend tree and DPP2 for OPP2 blend tree). 1110 * 1111 * Assuming that we have a Pipe Context associated with OPP0 and DPP1 1112 * working on processing the plane in the diagram. We want to know the 1113 * width and height of the shaded rectangle and its relative position 1114 * with respect to the ODM slice0. This is called the recout of the pipe 1115 * context. 1116 * 1117 * Planes can be at arbitrary size and position and there could be an 1118 * arbitrary number of MPC and ODM slices. The algorithm needs to take 1119 * all scenarios into account. 1120 * 1121 * Timing Active Space (3840 x 2160) 1122 * --------------------------------- 1123 * 1124 * Timing Active 1125 * __________________________________________________ 1126 * |OPP0(ODM slice0)^ |OPP2(ODM slice1) | 1127 * | y | | 1128 * | | <- w -> | 1129 * | _____V________|____ | 1130 * | |DPP0 ^ |DPP1 |DPP2| | 1131 * |<------ x |-----|->|/////| | | 1132 * | | | |/////| | | 1133 * | | h |/////| | | 1134 * | | | |/////| | | 1135 * | |_____V__|/////|____| | 1136 * | | | 1137 * | | | 1138 * | | | 1139 * |_________________________|________________________| 1140 * 1141 * 1142 */ 1143 struct rect plane_clip; 1144 struct rect mpc_slice_of_plane_clip; 1145 struct rect odm_slice; 1146 struct rect overlapping_area; 1147 1148 plane_clip = calculate_plane_rec_in_timing_active(pipe_ctx, 1149 &pipe_ctx->plane_state->clip_rect); 1150 /* guard plane clip from drawing beyond stream dst here */ 1151 plane_clip = intersect_rec(&plane_clip, 1152 &pipe_ctx->stream->dst); 1153 mpc_slice_of_plane_clip = calculate_mpc_slice_in_timing_active( 1154 pipe_ctx, &plane_clip); 1155 odm_slice = calculate_odm_slice_in_timing_active(pipe_ctx); 1156 overlapping_area = intersect_rec(&mpc_slice_of_plane_clip, &odm_slice); 1157 if (overlapping_area.height > 0 && 1158 overlapping_area.width > 0) { 1159 /* shift the overlapping area so it is with respect to current 1160 * ODM slice's position 1161 */ 1162 pipe_ctx->plane_res.scl_data.recout = shift_rec( 1163 &overlapping_area, 1164 -odm_slice.x, -odm_slice.y); 1165 adjust_recout_for_visual_confirm( 1166 &pipe_ctx->plane_res.scl_data.recout, 1167 pipe_ctx); 1168 } else { 1169 /* if there is no overlap, zero recout */ 1170 memset(&pipe_ctx->plane_res.scl_data.recout, 0, 1171 sizeof(struct rect)); 1172 } 1173 1174 } 1175 1176 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) 1177 { 1178 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1179 const struct dc_stream_state *stream = pipe_ctx->stream; 1180 struct rect surf_src = plane_state->src_rect; 1181 const int in_w = stream->src.width; 1182 const int in_h = stream->src.height; 1183 const int out_w = stream->dst.width; 1184 const int out_h = stream->dst.height; 1185 1186 /*Swap surf_src height and width since scaling ratios are in recout rotation*/ 1187 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || 1188 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) 1189 swap(surf_src.height, surf_src.width); 1190 1191 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( 1192 surf_src.width, 1193 plane_state->dst_rect.width); 1194 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( 1195 surf_src.height, 1196 plane_state->dst_rect.height); 1197 1198 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 1199 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; 1200 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 1201 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; 1202 1203 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( 1204 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); 1205 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( 1206 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); 1207 1208 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; 1209 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; 1210 1211 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 1212 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { 1213 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; 1214 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; 1215 } 1216 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate( 1217 pipe_ctx->plane_res.scl_data.ratios.horz, 19); 1218 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( 1219 pipe_ctx->plane_res.scl_data.ratios.vert, 19); 1220 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate( 1221 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19); 1222 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate( 1223 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); 1224 } 1225 1226 1227 /* 1228 * We completely calculate vp offset, size and inits here based entirely on scaling 1229 * ratios and recout for pixel perfect pipe combine. 1230 */ 1231 static void calculate_init_and_vp( 1232 bool flip_scan_dir, 1233 int recout_offset_within_recout_full, 1234 int recout_size, 1235 int src_size, 1236 int taps, 1237 struct fixed31_32 ratio, 1238 struct fixed31_32 *init, 1239 int *vp_offset, 1240 int *vp_size) 1241 { 1242 struct fixed31_32 temp; 1243 int int_part; 1244 1245 /* 1246 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout 1247 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on. 1248 * All following calculations are based on this logic. 1249 * 1250 * Init calculated according to formula: 1251 * init = (scaling_ratio + number_of_taps + 1) / 2 1252 * init_bot = init + scaling_ratio 1253 * to get pixel perfect combine add the fraction from calculating vp offset 1254 */ 1255 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full); 1256 *vp_offset = dc_fixpt_floor(temp); 1257 temp.value &= 0xffffffff; 1258 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int( 1259 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19); 1260 /* 1261 * If viewport has non 0 offset and there are more taps than covered by init then 1262 * we should decrease the offset and increase init so we are never sampling 1263 * outside of viewport. 1264 */ 1265 int_part = dc_fixpt_floor(*init); 1266 if (int_part < taps) { 1267 int_part = taps - int_part; 1268 if (int_part > *vp_offset) 1269 int_part = *vp_offset; 1270 *vp_offset -= int_part; 1271 *init = dc_fixpt_add_int(*init, int_part); 1272 } 1273 /* 1274 * If taps are sampling outside of viewport at end of recout and there are more pixels 1275 * available in the surface we should increase the viewport size, regardless set vp to 1276 * only what is used. 1277 */ 1278 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1)); 1279 *vp_size = dc_fixpt_floor(temp); 1280 if (*vp_size + *vp_offset > src_size) 1281 *vp_size = src_size - *vp_offset; 1282 1283 /* We did all the math assuming we are scanning same direction as display does, 1284 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction 1285 * is flipped we simply need to calculate offset from the other side of plane. 1286 * Note that outside of viewport all scaling hardware works in recout space. 1287 */ 1288 if (flip_scan_dir) 1289 *vp_offset = src_size - *vp_offset - *vp_size; 1290 } 1291 1292 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx) 1293 { 1294 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1295 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; 1296 struct rect src = plane_state->src_rect; 1297 struct rect recout_dst_in_active_timing; 1298 struct rect recout_clip_in_active_timing; 1299 struct rect recout_clip_in_recout_dst; 1300 struct rect overlap_in_active_timing; 1301 struct rect odm_slice = calculate_odm_slice_in_timing_active(pipe_ctx); 1302 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 1303 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; 1304 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; 1305 1306 recout_clip_in_active_timing = shift_rec( 1307 &data->recout, odm_slice.x, odm_slice.y); 1308 recout_dst_in_active_timing = calculate_plane_rec_in_timing_active( 1309 pipe_ctx, &plane_state->dst_rect); 1310 overlap_in_active_timing = intersect_rec(&recout_clip_in_active_timing, 1311 &recout_dst_in_active_timing); 1312 if (overlap_in_active_timing.width > 0 && 1313 overlap_in_active_timing.height > 0) 1314 recout_clip_in_recout_dst = shift_rec(&overlap_in_active_timing, 1315 -recout_dst_in_active_timing.x, 1316 -recout_dst_in_active_timing.y); 1317 else 1318 memset(&recout_clip_in_recout_dst, 0, sizeof(struct rect)); 1319 1320 /* 1321 * Work in recout rotation since that requires less transformations 1322 */ 1323 get_vp_scan_direction( 1324 plane_state->rotation, 1325 plane_state->horizontal_mirror, 1326 &orthogonal_rotation, 1327 &flip_vert_scan_dir, 1328 &flip_horz_scan_dir); 1329 1330 if (orthogonal_rotation) { 1331 swap(src.width, src.height); 1332 swap(flip_vert_scan_dir, flip_horz_scan_dir); 1333 } 1334 1335 calculate_init_and_vp( 1336 flip_horz_scan_dir, 1337 recout_clip_in_recout_dst.x, 1338 data->recout.width, 1339 src.width, 1340 data->taps.h_taps, 1341 data->ratios.horz, 1342 &data->inits.h, 1343 &data->viewport.x, 1344 &data->viewport.width); 1345 calculate_init_and_vp( 1346 flip_horz_scan_dir, 1347 recout_clip_in_recout_dst.x, 1348 data->recout.width, 1349 src.width / vpc_div, 1350 data->taps.h_taps_c, 1351 data->ratios.horz_c, 1352 &data->inits.h_c, 1353 &data->viewport_c.x, 1354 &data->viewport_c.width); 1355 calculate_init_and_vp( 1356 flip_vert_scan_dir, 1357 recout_clip_in_recout_dst.y, 1358 data->recout.height, 1359 src.height, 1360 data->taps.v_taps, 1361 data->ratios.vert, 1362 &data->inits.v, 1363 &data->viewport.y, 1364 &data->viewport.height); 1365 calculate_init_and_vp( 1366 flip_vert_scan_dir, 1367 recout_clip_in_recout_dst.y, 1368 data->recout.height, 1369 src.height / vpc_div, 1370 data->taps.v_taps_c, 1371 data->ratios.vert_c, 1372 &data->inits.v_c, 1373 &data->viewport_c.y, 1374 &data->viewport_c.height); 1375 if (orthogonal_rotation) { 1376 swap(data->viewport.x, data->viewport.y); 1377 swap(data->viewport.width, data->viewport.height); 1378 swap(data->viewport_c.x, data->viewport_c.y); 1379 swap(data->viewport_c.width, data->viewport_c.height); 1380 } 1381 data->viewport.x += src.x; 1382 data->viewport.y += src.y; 1383 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); 1384 data->viewport_c.x += src.x / vpc_div; 1385 data->viewport_c.y += src.y / vpc_div; 1386 } 1387 1388 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 1389 { 1390 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1391 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 1392 const struct rect odm_slice_rec = calculate_odm_slice_in_timing_active(pipe_ctx); 1393 bool res = false; 1394 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 1395 1396 /* Invalid input */ 1397 if (!plane_state->dst_rect.width || 1398 !plane_state->dst_rect.height || 1399 !plane_state->src_rect.width || 1400 !plane_state->src_rect.height) { 1401 ASSERT(0); 1402 return false; 1403 } 1404 1405 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( 1406 pipe_ctx->plane_state->format); 1407 1408 /* Timing borders are part of vactive that we are also supposed to skip in addition 1409 * to any stream dst offset. Since dm logic assumes dst is in addressable 1410 * space we need to add the left and top borders to dst offsets temporarily. 1411 * TODO: fix in DM, stream dst is supposed to be in vactive 1412 */ 1413 pipe_ctx->stream->dst.x += timing->h_border_left; 1414 pipe_ctx->stream->dst.y += timing->v_border_top; 1415 1416 /* Calculate H and V active size */ 1417 pipe_ctx->plane_res.scl_data.h_active = odm_slice_rec.width; 1418 pipe_ctx->plane_res.scl_data.v_active = odm_slice_rec.height; 1419 1420 /* depends on h_active */ 1421 calculate_recout(pipe_ctx); 1422 /* depends on pixel format */ 1423 calculate_scaling_ratios(pipe_ctx); 1424 /* depends on scaling ratios and recout, does not calculate offset yet */ 1425 calculate_viewport_size(pipe_ctx); 1426 1427 if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) { 1428 /* Stopgap for validation of ODM + MPO on one side of screen case */ 1429 if (pipe_ctx->plane_res.scl_data.viewport.height < 1 || 1430 pipe_ctx->plane_res.scl_data.viewport.width < 1) 1431 return false; 1432 } 1433 1434 /* 1435 * LB calculations depend on vp size, h/v_active and scaling ratios 1436 * Setting line buffer pixel depth to 24bpp yields banding 1437 * on certain displays, such as the Sharp 4k. 36bpp is needed 1438 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and 1439 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc 1440 * precision on DCN display engines, but apparently not for DCE, as 1441 * far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have 1442 * problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth, 1443 * neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel 1444 * passthrough). Therefore only use 36 bpp on DCN where it is actually needed. 1445 */ 1446 if (plane_state->ctx->dce_version > DCE_VERSION_MAX) 1447 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; 1448 else 1449 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; 1450 1451 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; 1452 1453 if (pipe_ctx->plane_res.xfm != NULL) 1454 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1455 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1456 1457 if (pipe_ctx->plane_res.dpp != NULL) 1458 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1459 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); 1460 1461 1462 if (!res) { 1463 /* Try 24 bpp linebuffer */ 1464 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; 1465 1466 if (pipe_ctx->plane_res.xfm != NULL) 1467 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( 1468 pipe_ctx->plane_res.xfm, 1469 &pipe_ctx->plane_res.scl_data, 1470 &plane_state->scaling_quality); 1471 1472 if (pipe_ctx->plane_res.dpp != NULL) 1473 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( 1474 pipe_ctx->plane_res.dpp, 1475 &pipe_ctx->plane_res.scl_data, 1476 &plane_state->scaling_quality); 1477 } 1478 1479 /* 1480 * Depends on recout, scaling ratios, h_active and taps 1481 * May need to re-check lb size after this in some obscure scenario 1482 */ 1483 if (res) 1484 calculate_inits_and_viewports(pipe_ctx); 1485 1486 /* 1487 * Handle side by side and top bottom 3d recout offsets after vp calculation 1488 * since 3d is special and needs to calculate vp as if there is no recout offset 1489 * This may break with rotation, good thing we aren't mixing hw rotation and 3d 1490 */ 1491 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) { 1492 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 || 1493 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM && 1494 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE)); 1495 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) 1496 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height; 1497 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) 1498 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width; 1499 } 1500 1501 /* Clamp minimum viewport size */ 1502 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE) 1503 pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE; 1504 if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE) 1505 pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE; 1506 1507 1508 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n" 1509 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n", 1510 __func__, 1511 pipe_ctx->pipe_idx, 1512 pipe_ctx->plane_res.scl_data.viewport.height, 1513 pipe_ctx->plane_res.scl_data.viewport.width, 1514 pipe_ctx->plane_res.scl_data.viewport.x, 1515 pipe_ctx->plane_res.scl_data.viewport.y, 1516 pipe_ctx->plane_res.scl_data.recout.height, 1517 pipe_ctx->plane_res.scl_data.recout.width, 1518 pipe_ctx->plane_res.scl_data.recout.x, 1519 pipe_ctx->plane_res.scl_data.recout.y, 1520 pipe_ctx->plane_res.scl_data.h_active, 1521 pipe_ctx->plane_res.scl_data.v_active, 1522 plane_state->src_rect.height, 1523 plane_state->src_rect.width, 1524 plane_state->src_rect.x, 1525 plane_state->src_rect.y, 1526 plane_state->dst_rect.height, 1527 plane_state->dst_rect.width, 1528 plane_state->dst_rect.x, 1529 plane_state->dst_rect.y, 1530 plane_state->clip_rect.height, 1531 plane_state->clip_rect.width, 1532 plane_state->clip_rect.x, 1533 plane_state->clip_rect.y); 1534 1535 pipe_ctx->stream->dst.x -= timing->h_border_left; 1536 pipe_ctx->stream->dst.y -= timing->v_border_top; 1537 1538 return res; 1539 } 1540 1541 1542 enum dc_status resource_build_scaling_params_for_context( 1543 const struct dc *dc, 1544 struct dc_state *context) 1545 { 1546 int i; 1547 1548 for (i = 0; i < MAX_PIPES; i++) { 1549 if (context->res_ctx.pipe_ctx[i].plane_state != NULL && 1550 context->res_ctx.pipe_ctx[i].stream != NULL) 1551 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) 1552 return DC_FAIL_SCALING; 1553 } 1554 1555 return DC_OK; 1556 } 1557 1558 struct pipe_ctx *resource_find_free_secondary_pipe_legacy( 1559 struct resource_context *res_ctx, 1560 const struct resource_pool *pool, 1561 const struct pipe_ctx *primary_pipe) 1562 { 1563 int i; 1564 struct pipe_ctx *secondary_pipe = NULL; 1565 1566 /* 1567 * We add a preferred pipe mapping to avoid the chance that 1568 * MPCCs already in use will need to be reassigned to other trees. 1569 * For example, if we went with the strict, assign backwards logic: 1570 * 1571 * (State 1) 1572 * Display A on, no surface, top pipe = 0 1573 * Display B on, no surface, top pipe = 1 1574 * 1575 * (State 2) 1576 * Display A on, no surface, top pipe = 0 1577 * Display B on, surface enable, top pipe = 1, bottom pipe = 5 1578 * 1579 * (State 3) 1580 * Display A on, surface enable, top pipe = 0, bottom pipe = 5 1581 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1582 * 1583 * The state 2->3 transition requires remapping MPCC 5 from display B 1584 * to display A. 1585 * 1586 * However, with the preferred pipe logic, state 2 would look like: 1587 * 1588 * (State 2) 1589 * Display A on, no surface, top pipe = 0 1590 * Display B on, surface enable, top pipe = 1, bottom pipe = 4 1591 * 1592 * This would then cause 2->3 to not require remapping any MPCCs. 1593 */ 1594 if (primary_pipe) { 1595 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 1596 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1597 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1598 secondary_pipe->pipe_idx = preferred_pipe_idx; 1599 } 1600 } 1601 1602 /* 1603 * search backwards for the second pipe to keep pipe 1604 * assignment more consistent 1605 */ 1606 if (!secondary_pipe) 1607 for (i = pool->pipe_count - 1; i >= 0; i--) { 1608 if (res_ctx->pipe_ctx[i].stream == NULL) { 1609 secondary_pipe = &res_ctx->pipe_ctx[i]; 1610 secondary_pipe->pipe_idx = i; 1611 break; 1612 } 1613 } 1614 1615 return secondary_pipe; 1616 } 1617 1618 int resource_find_free_pipe_used_in_cur_mpc_blending_tree( 1619 const struct resource_context *cur_res_ctx, 1620 struct resource_context *new_res_ctx, 1621 const struct pipe_ctx *cur_opp_head) 1622 { 1623 const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe; 1624 struct pipe_ctx *new_pipe; 1625 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; 1626 1627 while (cur_sec_dpp) { 1628 /* find a free pipe used in current opp blend tree, 1629 * this is to avoid MPO pipe switching to different opp blending 1630 * tree 1631 */ 1632 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx]; 1633 if (resource_is_pipe_type(new_pipe, FREE_PIPE)) { 1634 free_pipe_idx = cur_sec_dpp->pipe_idx; 1635 break; 1636 } 1637 cur_sec_dpp = cur_sec_dpp->bottom_pipe; 1638 } 1639 1640 return free_pipe_idx; 1641 } 1642 1643 int recource_find_free_pipe_not_used_in_cur_res_ctx( 1644 const struct resource_context *cur_res_ctx, 1645 struct resource_context *new_res_ctx, 1646 const struct resource_pool *pool) 1647 { 1648 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; 1649 const struct pipe_ctx *new_pipe, *cur_pipe; 1650 int i; 1651 1652 for (i = 0; i < pool->pipe_count; i++) { 1653 cur_pipe = &cur_res_ctx->pipe_ctx[i]; 1654 new_pipe = &new_res_ctx->pipe_ctx[i]; 1655 1656 if (resource_is_pipe_type(cur_pipe, FREE_PIPE) && 1657 resource_is_pipe_type(new_pipe, FREE_PIPE)) { 1658 free_pipe_idx = i; 1659 break; 1660 } 1661 } 1662 1663 return free_pipe_idx; 1664 } 1665 1666 int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine( 1667 const struct resource_context *cur_res_ctx, 1668 struct resource_context *new_res_ctx, 1669 const struct resource_pool *pool) 1670 { 1671 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; 1672 const struct pipe_ctx *new_pipe, *cur_pipe; 1673 int i; 1674 1675 for (i = 0; i < pool->pipe_count; i++) { 1676 cur_pipe = &cur_res_ctx->pipe_ctx[i]; 1677 new_pipe = &new_res_ctx->pipe_ctx[i]; 1678 1679 if (resource_is_pipe_type(cur_pipe, DPP_PIPE) && 1680 !resource_is_pipe_type(cur_pipe, OPP_HEAD) && 1681 resource_is_for_mpcc_combine(cur_pipe) && 1682 resource_is_pipe_type(new_pipe, FREE_PIPE)) { 1683 free_pipe_idx = i; 1684 break; 1685 } 1686 } 1687 1688 return free_pipe_idx; 1689 } 1690 1691 int resource_find_any_free_pipe(struct resource_context *new_res_ctx, 1692 const struct resource_pool *pool) 1693 { 1694 int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND; 1695 const struct pipe_ctx *new_pipe; 1696 int i; 1697 1698 for (i = 0; i < pool->pipe_count; i++) { 1699 new_pipe = &new_res_ctx->pipe_ctx[i]; 1700 1701 if (resource_is_pipe_type(new_pipe, FREE_PIPE)) { 1702 free_pipe_idx = i; 1703 break; 1704 } 1705 } 1706 1707 return free_pipe_idx; 1708 } 1709 1710 bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type) 1711 { 1712 #ifdef DBG 1713 if (pipe_ctx->stream == NULL) { 1714 /* a free pipe with dangling states */ 1715 ASSERT(!pipe_ctx->plane_state); 1716 ASSERT(!pipe_ctx->prev_odm_pipe); 1717 ASSERT(!pipe_ctx->next_odm_pipe); 1718 ASSERT(!pipe_ctx->top_pipe); 1719 ASSERT(!pipe_ctx->bottom_pipe); 1720 } else if (pipe_ctx->top_pipe) { 1721 /* a secondary DPP pipe must be signed to a plane */ 1722 ASSERT(pipe_ctx->plane_state) 1723 } 1724 /* Add more checks here to prevent corrupted pipe ctx. It is very hard 1725 * to debug this issue afterwards because we can't pinpoint the code 1726 * location causing inconsistent pipe context states. 1727 */ 1728 #endif 1729 switch (type) { 1730 case OTG_MASTER: 1731 return !pipe_ctx->prev_odm_pipe && 1732 !pipe_ctx->top_pipe && 1733 pipe_ctx->stream; 1734 case OPP_HEAD: 1735 return !pipe_ctx->top_pipe && pipe_ctx->stream; 1736 case DPP_PIPE: 1737 return pipe_ctx->plane_state && pipe_ctx->stream; 1738 case FREE_PIPE: 1739 return !pipe_ctx->plane_state && !pipe_ctx->stream; 1740 default: 1741 return false; 1742 } 1743 } 1744 1745 bool resource_is_for_mpcc_combine(const struct pipe_ctx *pipe_ctx) 1746 { 1747 return resource_get_num_mpc_splits(pipe_ctx) > 0; 1748 } 1749 1750 struct pipe_ctx *resource_get_otg_master_for_stream( 1751 struct resource_context *res_ctx, 1752 struct dc_stream_state *stream) 1753 { 1754 int i; 1755 1756 for (i = 0; i < MAX_PIPES; i++) { 1757 if (res_ctx->pipe_ctx[i].stream == stream && 1758 resource_is_pipe_type(&res_ctx->pipe_ctx[i], OTG_MASTER)) 1759 return &res_ctx->pipe_ctx[i]; 1760 } 1761 return NULL; 1762 } 1763 1764 struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx) 1765 { 1766 struct pipe_ctx *otg_master = resource_get_opp_head(pipe_ctx); 1767 1768 while (otg_master->prev_odm_pipe) 1769 otg_master = otg_master->prev_odm_pipe; 1770 return otg_master; 1771 } 1772 1773 struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx) 1774 { 1775 struct pipe_ctx *opp_head = (struct pipe_ctx *) pipe_ctx; 1776 1777 ASSERT(!resource_is_pipe_type(opp_head, FREE_PIPE)); 1778 while (opp_head->top_pipe) 1779 opp_head = opp_head->top_pipe; 1780 return opp_head; 1781 } 1782 1783 static struct pipe_ctx *get_tail_pipe( 1784 struct pipe_ctx *head_pipe) 1785 { 1786 struct pipe_ctx *tail_pipe = head_pipe->bottom_pipe; 1787 1788 while (tail_pipe) { 1789 head_pipe = tail_pipe; 1790 tail_pipe = tail_pipe->bottom_pipe; 1791 } 1792 1793 return head_pipe; 1794 } 1795 1796 static int acquire_first_split_pipe( 1797 struct resource_context *res_ctx, 1798 const struct resource_pool *pool, 1799 struct dc_stream_state *stream) 1800 { 1801 int i; 1802 1803 for (i = 0; i < pool->pipe_count; i++) { 1804 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i]; 1805 1806 if (split_pipe->top_pipe && 1807 split_pipe->top_pipe->plane_state == split_pipe->plane_state) { 1808 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe; 1809 if (split_pipe->bottom_pipe) 1810 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; 1811 1812 if (split_pipe->top_pipe->plane_state) 1813 resource_build_scaling_params(split_pipe->top_pipe); 1814 1815 memset(split_pipe, 0, sizeof(*split_pipe)); 1816 split_pipe->stream_res.tg = pool->timing_generators[i]; 1817 split_pipe->plane_res.hubp = pool->hubps[i]; 1818 split_pipe->plane_res.ipp = pool->ipps[i]; 1819 split_pipe->plane_res.dpp = pool->dpps[i]; 1820 split_pipe->stream_res.opp = pool->opps[i]; 1821 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; 1822 split_pipe->pipe_idx = i; 1823 1824 split_pipe->stream = stream; 1825 return i; 1826 } 1827 } 1828 return UNABLE_TO_SPLIT; 1829 } 1830 1831 static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe, 1832 struct dc_plane_state *plane_state, 1833 struct dc_state *context) 1834 { 1835 struct pipe_ctx *opp_head_pipe = otg_master_pipe; 1836 1837 while (opp_head_pipe) { 1838 if (opp_head_pipe->plane_state) { 1839 ASSERT(0); 1840 return false; 1841 } 1842 opp_head_pipe->plane_state = plane_state; 1843 opp_head_pipe = opp_head_pipe->next_odm_pipe; 1844 } 1845 1846 return true; 1847 } 1848 1849 static void insert_secondary_dpp_pipe_with_plane(struct pipe_ctx *opp_head_pipe, 1850 struct pipe_ctx *sec_pipe, struct dc_plane_state *plane_state) 1851 { 1852 struct pipe_ctx *tail_pipe = get_tail_pipe(opp_head_pipe); 1853 1854 tail_pipe->bottom_pipe = sec_pipe; 1855 sec_pipe->top_pipe = tail_pipe; 1856 if (tail_pipe->prev_odm_pipe) { 1857 ASSERT(tail_pipe->prev_odm_pipe->bottom_pipe); 1858 sec_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe; 1859 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = sec_pipe; 1860 } 1861 sec_pipe->plane_state = plane_state; 1862 } 1863 1864 /* for each opp head pipe of an otg master pipe, acquire a secondary dpp pipe 1865 * and add the plane. So the plane is added to all MPC blend trees associated 1866 * with the otg master pipe. 1867 */ 1868 static bool acquire_secondary_dpp_pipes_and_add_plane( 1869 struct pipe_ctx *otg_master_pipe, 1870 struct dc_plane_state *plane_state, 1871 struct dc_state *new_ctx, 1872 struct dc_state *cur_ctx, 1873 struct resource_pool *pool) 1874 { 1875 struct pipe_ctx *opp_head_pipe, *sec_pipe; 1876 1877 if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) 1878 return false; 1879 1880 opp_head_pipe = otg_master_pipe; 1881 while (opp_head_pipe) { 1882 sec_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe( 1883 cur_ctx, 1884 new_ctx, 1885 pool, 1886 opp_head_pipe); 1887 if (!sec_pipe) { 1888 /* try tearing down MPCC combine */ 1889 int pipe_idx = acquire_first_split_pipe( 1890 &new_ctx->res_ctx, pool, 1891 otg_master_pipe->stream); 1892 1893 if (pipe_idx >= 0) 1894 sec_pipe = &new_ctx->res_ctx.pipe_ctx[pipe_idx]; 1895 } 1896 1897 if (!sec_pipe) 1898 return false; 1899 1900 insert_secondary_dpp_pipe_with_plane(opp_head_pipe, sec_pipe, 1901 plane_state); 1902 opp_head_pipe = opp_head_pipe->next_odm_pipe; 1903 } 1904 return true; 1905 } 1906 1907 bool dc_add_plane_to_context( 1908 const struct dc *dc, 1909 struct dc_stream_state *stream, 1910 struct dc_plane_state *plane_state, 1911 struct dc_state *context) 1912 { 1913 struct resource_pool *pool = dc->res_pool; 1914 struct pipe_ctx *otg_master_pipe; 1915 struct dc_stream_status *stream_status = NULL; 1916 bool added = false; 1917 1918 stream_status = dc_stream_get_status_from_state(context, stream); 1919 if (stream_status == NULL) { 1920 dm_error("Existing stream not found; failed to attach surface!\n"); 1921 goto out; 1922 } else if (stream_status->plane_count == MAX_SURFACE_NUM) { 1923 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", 1924 plane_state, MAX_SURFACE_NUM); 1925 goto out; 1926 } 1927 1928 otg_master_pipe = resource_get_otg_master_for_stream( 1929 &context->res_ctx, stream); 1930 if (otg_master_pipe->plane_state == NULL) 1931 added = add_plane_to_opp_head_pipes(otg_master_pipe, 1932 plane_state, context); 1933 else 1934 added = acquire_secondary_dpp_pipes_and_add_plane( 1935 otg_master_pipe, plane_state, context, 1936 dc->current_state, pool); 1937 if (added) { 1938 stream_status->plane_states[stream_status->plane_count] = 1939 plane_state; 1940 stream_status->plane_count++; 1941 dc_plane_state_retain(plane_state); 1942 } 1943 1944 out: 1945 return added; 1946 } 1947 1948 bool dc_remove_plane_from_context( 1949 const struct dc *dc, 1950 struct dc_stream_state *stream, 1951 struct dc_plane_state *plane_state, 1952 struct dc_state *context) 1953 { 1954 int i; 1955 struct dc_stream_status *stream_status = NULL; 1956 struct resource_pool *pool = dc->res_pool; 1957 1958 if (!plane_state) 1959 return true; 1960 1961 for (i = 0; i < context->stream_count; i++) 1962 if (context->streams[i] == stream) { 1963 stream_status = &context->stream_status[i]; 1964 break; 1965 } 1966 1967 if (stream_status == NULL) { 1968 dm_error("Existing stream not found; failed to remove plane.\n"); 1969 return false; 1970 } 1971 1972 /* release pipe for plane*/ 1973 for (i = pool->pipe_count - 1; i >= 0; i--) { 1974 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1975 1976 if (pipe_ctx->plane_state == plane_state) { 1977 if (pipe_ctx->top_pipe) 1978 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; 1979 1980 /* Second condition is to avoid setting NULL to top pipe 1981 * of tail pipe making it look like head pipe in subsequent 1982 * deletes 1983 */ 1984 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) 1985 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; 1986 1987 /* 1988 * For head pipe detach surfaces from pipe for tail 1989 * pipe just zero it out 1990 */ 1991 if (!pipe_ctx->top_pipe) 1992 pipe_ctx->plane_state = NULL; 1993 else 1994 memset(pipe_ctx, 0, sizeof(*pipe_ctx)); 1995 } 1996 } 1997 1998 1999 for (i = 0; i < stream_status->plane_count; i++) { 2000 if (stream_status->plane_states[i] == plane_state) { 2001 dc_plane_state_release(stream_status->plane_states[i]); 2002 break; 2003 } 2004 } 2005 2006 if (i == stream_status->plane_count) { 2007 dm_error("Existing plane_state not found; failed to detach it!\n"); 2008 return false; 2009 } 2010 2011 stream_status->plane_count--; 2012 2013 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */ 2014 for (; i < stream_status->plane_count; i++) 2015 stream_status->plane_states[i] = stream_status->plane_states[i + 1]; 2016 2017 stream_status->plane_states[stream_status->plane_count] = NULL; 2018 2019 return true; 2020 } 2021 2022 /** 2023 * dc_rem_all_planes_for_stream - Remove planes attached to the target stream. 2024 * 2025 * @dc: Current dc state. 2026 * @stream: Target stream, which we want to remove the attached plans. 2027 * @context: New context. 2028 * 2029 * Return: 2030 * Return true if DC was able to remove all planes from the target 2031 * stream, otherwise, return false. 2032 */ 2033 bool dc_rem_all_planes_for_stream( 2034 const struct dc *dc, 2035 struct dc_stream_state *stream, 2036 struct dc_state *context) 2037 { 2038 int i, old_plane_count; 2039 struct dc_stream_status *stream_status = NULL; 2040 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; 2041 2042 for (i = 0; i < context->stream_count; i++) 2043 if (context->streams[i] == stream) { 2044 stream_status = &context->stream_status[i]; 2045 break; 2046 } 2047 2048 if (stream_status == NULL) { 2049 dm_error("Existing stream %p not found!\n", stream); 2050 return false; 2051 } 2052 2053 old_plane_count = stream_status->plane_count; 2054 2055 for (i = 0; i < old_plane_count; i++) 2056 del_planes[i] = stream_status->plane_states[i]; 2057 2058 for (i = 0; i < old_plane_count; i++) 2059 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) 2060 return false; 2061 2062 return true; 2063 } 2064 2065 static bool add_all_planes_for_stream( 2066 const struct dc *dc, 2067 struct dc_stream_state *stream, 2068 const struct dc_validation_set set[], 2069 int set_count, 2070 struct dc_state *context) 2071 { 2072 int i, j; 2073 2074 for (i = 0; i < set_count; i++) 2075 if (set[i].stream == stream) 2076 break; 2077 2078 if (i == set_count) { 2079 dm_error("Stream %p not found in set!\n", stream); 2080 return false; 2081 } 2082 2083 for (j = 0; j < set[i].plane_count; j++) 2084 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) 2085 return false; 2086 2087 return true; 2088 } 2089 2090 bool dc_add_all_planes_for_stream( 2091 const struct dc *dc, 2092 struct dc_stream_state *stream, 2093 struct dc_plane_state * const *plane_states, 2094 int plane_count, 2095 struct dc_state *context) 2096 { 2097 struct dc_validation_set set; 2098 int i; 2099 2100 set.stream = stream; 2101 set.plane_count = plane_count; 2102 2103 for (i = 0; i < plane_count; i++) 2104 set.plane_states[i] = plane_states[i]; 2105 2106 return add_all_planes_for_stream(dc, stream, &set, 1, context); 2107 } 2108 2109 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2110 struct dc_stream_state *new_stream) 2111 { 2112 if (cur_stream == NULL) 2113 return true; 2114 2115 /* If output color space is changed, need to reprogram info frames */ 2116 if (cur_stream->output_color_space != new_stream->output_color_space) 2117 return true; 2118 2119 return memcmp( 2120 &cur_stream->timing, 2121 &new_stream->timing, 2122 sizeof(struct dc_crtc_timing)) != 0; 2123 } 2124 2125 static bool are_stream_backends_same( 2126 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) 2127 { 2128 if (stream_a == stream_b) 2129 return true; 2130 2131 if (stream_a == NULL || stream_b == NULL) 2132 return false; 2133 2134 if (dc_is_timing_changed(stream_a, stream_b)) 2135 return false; 2136 2137 if (stream_a->signal != stream_b->signal) 2138 return false; 2139 2140 if (stream_a->dpms_off != stream_b->dpms_off) 2141 return false; 2142 2143 return true; 2144 } 2145 2146 /* 2147 * dc_is_stream_unchanged() - Compare two stream states for equivalence. 2148 * 2149 * Checks if there a difference between the two states 2150 * that would require a mode change. 2151 * 2152 * Does not compare cursor position or attributes. 2153 */ 2154 bool dc_is_stream_unchanged( 2155 struct dc_stream_state *old_stream, struct dc_stream_state *stream) 2156 { 2157 2158 if (!are_stream_backends_same(old_stream, stream)) 2159 return false; 2160 2161 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param) 2162 return false; 2163 2164 /*compare audio info*/ 2165 if (memcmp(&old_stream->audio_info, &stream->audio_info, sizeof(stream->audio_info)) != 0) 2166 return false; 2167 2168 return true; 2169 } 2170 2171 /* 2172 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams. 2173 */ 2174 bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream, 2175 struct dc_stream_state *stream) 2176 { 2177 if (old_stream == stream) 2178 return true; 2179 2180 if (old_stream == NULL || stream == NULL) 2181 return false; 2182 2183 if (memcmp(&old_stream->src, 2184 &stream->src, 2185 sizeof(struct rect)) != 0) 2186 return false; 2187 2188 if (memcmp(&old_stream->dst, 2189 &stream->dst, 2190 sizeof(struct rect)) != 0) 2191 return false; 2192 2193 return true; 2194 } 2195 2196 static void update_stream_engine_usage( 2197 struct resource_context *res_ctx, 2198 const struct resource_pool *pool, 2199 struct stream_encoder *stream_enc, 2200 bool acquired) 2201 { 2202 int i; 2203 2204 for (i = 0; i < pool->stream_enc_count; i++) { 2205 if (pool->stream_enc[i] == stream_enc) 2206 res_ctx->is_stream_enc_acquired[i] = acquired; 2207 } 2208 } 2209 2210 static void update_hpo_dp_stream_engine_usage( 2211 struct resource_context *res_ctx, 2212 const struct resource_pool *pool, 2213 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, 2214 bool acquired) 2215 { 2216 int i; 2217 2218 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { 2219 if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc) 2220 res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired; 2221 } 2222 } 2223 2224 static inline int find_acquired_hpo_dp_link_enc_for_link( 2225 const struct resource_context *res_ctx, 2226 const struct dc_link *link) 2227 { 2228 int i; 2229 2230 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++) 2231 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 && 2232 res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index) 2233 return i; 2234 2235 return -1; 2236 } 2237 2238 static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx, 2239 const struct resource_pool *pool) 2240 { 2241 int i; 2242 2243 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++) 2244 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0) 2245 break; 2246 2247 return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) && 2248 i < pool->hpo_dp_link_enc_count) ? i : -1; 2249 } 2250 2251 static inline void acquire_hpo_dp_link_enc( 2252 struct resource_context *res_ctx, 2253 unsigned int link_index, 2254 int enc_index) 2255 { 2256 res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index; 2257 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1; 2258 } 2259 2260 static inline void retain_hpo_dp_link_enc( 2261 struct resource_context *res_ctx, 2262 int enc_index) 2263 { 2264 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++; 2265 } 2266 2267 static inline void release_hpo_dp_link_enc( 2268 struct resource_context *res_ctx, 2269 int enc_index) 2270 { 2271 ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0); 2272 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--; 2273 } 2274 2275 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx, 2276 const struct resource_pool *pool, 2277 struct pipe_ctx *pipe_ctx, 2278 struct dc_stream_state *stream) 2279 { 2280 int enc_index; 2281 2282 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link); 2283 2284 if (enc_index >= 0) { 2285 retain_hpo_dp_link_enc(res_ctx, enc_index); 2286 } else { 2287 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool); 2288 if (enc_index >= 0) 2289 acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index); 2290 } 2291 2292 if (enc_index >= 0) 2293 pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index]; 2294 2295 return pipe_ctx->link_res.hpo_dp_link_enc != NULL; 2296 } 2297 2298 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx, 2299 struct pipe_ctx *pipe_ctx, 2300 struct dc_stream_state *stream) 2301 { 2302 int enc_index; 2303 2304 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link); 2305 2306 if (enc_index >= 0) { 2307 release_hpo_dp_link_enc(res_ctx, enc_index); 2308 pipe_ctx->link_res.hpo_dp_link_enc = NULL; 2309 } 2310 } 2311 2312 /* TODO: release audio object */ 2313 void update_audio_usage( 2314 struct resource_context *res_ctx, 2315 const struct resource_pool *pool, 2316 struct audio *audio, 2317 bool acquired) 2318 { 2319 int i; 2320 for (i = 0; i < pool->audio_count; i++) { 2321 if (pool->audios[i] == audio) 2322 res_ctx->is_audio_acquired[i] = acquired; 2323 } 2324 } 2325 2326 static int acquire_first_free_pipe( 2327 struct resource_context *res_ctx, 2328 const struct resource_pool *pool, 2329 struct dc_stream_state *stream) 2330 { 2331 int i; 2332 2333 for (i = 0; i < pool->pipe_count; i++) { 2334 if (!res_ctx->pipe_ctx[i].stream) { 2335 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 2336 2337 pipe_ctx->stream_res.tg = pool->timing_generators[i]; 2338 pipe_ctx->plane_res.mi = pool->mis[i]; 2339 pipe_ctx->plane_res.hubp = pool->hubps[i]; 2340 pipe_ctx->plane_res.ipp = pool->ipps[i]; 2341 pipe_ctx->plane_res.xfm = pool->transforms[i]; 2342 pipe_ctx->plane_res.dpp = pool->dpps[i]; 2343 pipe_ctx->stream_res.opp = pool->opps[i]; 2344 if (pool->dpps[i]) 2345 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; 2346 pipe_ctx->pipe_idx = i; 2347 2348 if (i >= pool->timing_generator_count) { 2349 int tg_inst = pool->timing_generator_count - 1; 2350 2351 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 2352 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; 2353 } 2354 2355 pipe_ctx->stream = stream; 2356 return i; 2357 } 2358 } 2359 return -1; 2360 } 2361 2362 static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link( 2363 struct resource_context *res_ctx, 2364 const struct resource_pool *pool, 2365 struct dc_stream_state *stream) 2366 { 2367 int i; 2368 2369 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) { 2370 if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] && 2371 pool->hpo_dp_stream_enc[i]) { 2372 2373 return pool->hpo_dp_stream_enc[i]; 2374 } 2375 } 2376 2377 return NULL; 2378 } 2379 2380 static struct audio *find_first_free_audio( 2381 struct resource_context *res_ctx, 2382 const struct resource_pool *pool, 2383 enum engine_id id, 2384 enum dce_version dc_version) 2385 { 2386 int i, available_audio_count; 2387 2388 available_audio_count = pool->audio_count; 2389 2390 for (i = 0; i < available_audio_count; i++) { 2391 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) { 2392 /*we have enough audio endpoint, find the matching inst*/ 2393 if (id != i) 2394 continue; 2395 return pool->audios[i]; 2396 } 2397 } 2398 2399 /* use engine id to find free audio */ 2400 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) { 2401 return pool->audios[id]; 2402 } 2403 /*not found the matching one, first come first serve*/ 2404 for (i = 0; i < available_audio_count; i++) { 2405 if (res_ctx->is_audio_acquired[i] == false) { 2406 return pool->audios[i]; 2407 } 2408 } 2409 return NULL; 2410 } 2411 2412 /* 2413 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state. 2414 */ 2415 enum dc_status dc_add_stream_to_ctx( 2416 struct dc *dc, 2417 struct dc_state *new_ctx, 2418 struct dc_stream_state *stream) 2419 { 2420 enum dc_status res; 2421 DC_LOGGER_INIT(dc->ctx->logger); 2422 2423 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) { 2424 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream); 2425 return DC_ERROR_UNEXPECTED; 2426 } 2427 2428 new_ctx->streams[new_ctx->stream_count] = stream; 2429 dc_stream_retain(stream); 2430 new_ctx->stream_count++; 2431 2432 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); 2433 if (res != DC_OK) 2434 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res); 2435 2436 return res; 2437 } 2438 2439 /* 2440 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state. 2441 */ 2442 enum dc_status dc_remove_stream_from_ctx( 2443 struct dc *dc, 2444 struct dc_state *new_ctx, 2445 struct dc_stream_state *stream) 2446 { 2447 int i; 2448 struct dc_context *dc_ctx = dc->ctx; 2449 struct pipe_ctx *del_pipe = resource_get_otg_master_for_stream(&new_ctx->res_ctx, stream); 2450 struct pipe_ctx *odm_pipe; 2451 2452 if (!del_pipe) { 2453 DC_ERROR("Pipe not found for stream %p !\n", stream); 2454 return DC_ERROR_UNEXPECTED; 2455 } 2456 2457 odm_pipe = del_pipe->next_odm_pipe; 2458 2459 /* Release primary pipe */ 2460 ASSERT(del_pipe->stream_res.stream_enc); 2461 update_stream_engine_usage( 2462 &new_ctx->res_ctx, 2463 dc->res_pool, 2464 del_pipe->stream_res.stream_enc, 2465 false); 2466 2467 if (dc->link_srv->dp_is_128b_132b_signal(del_pipe)) { 2468 update_hpo_dp_stream_engine_usage( 2469 &new_ctx->res_ctx, dc->res_pool, 2470 del_pipe->stream_res.hpo_dp_stream_enc, 2471 false); 2472 remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream); 2473 } 2474 2475 if (del_pipe->stream_res.audio) 2476 update_audio_usage( 2477 &new_ctx->res_ctx, 2478 dc->res_pool, 2479 del_pipe->stream_res.audio, 2480 false); 2481 2482 resource_unreference_clock_source(&new_ctx->res_ctx, 2483 dc->res_pool, 2484 del_pipe->clock_source); 2485 2486 if (dc->res_pool->funcs->remove_stream_from_ctx) 2487 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream); 2488 2489 while (odm_pipe) { 2490 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 2491 2492 memset(odm_pipe, 0, sizeof(*odm_pipe)); 2493 odm_pipe = next_odm_pipe; 2494 } 2495 memset(del_pipe, 0, sizeof(*del_pipe)); 2496 2497 for (i = 0; i < new_ctx->stream_count; i++) 2498 if (new_ctx->streams[i] == stream) 2499 break; 2500 2501 if (new_ctx->streams[i] != stream) { 2502 DC_ERROR("Context doesn't have stream %p !\n", stream); 2503 return DC_ERROR_UNEXPECTED; 2504 } 2505 2506 dc_stream_release(new_ctx->streams[i]); 2507 new_ctx->stream_count--; 2508 2509 /* Trim back arrays */ 2510 for (; i < new_ctx->stream_count; i++) { 2511 new_ctx->streams[i] = new_ctx->streams[i + 1]; 2512 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; 2513 } 2514 2515 new_ctx->streams[new_ctx->stream_count] = NULL; 2516 memset( 2517 &new_ctx->stream_status[new_ctx->stream_count], 2518 0, 2519 sizeof(new_ctx->stream_status[0])); 2520 2521 return DC_OK; 2522 } 2523 2524 static struct dc_stream_state *find_pll_sharable_stream( 2525 struct dc_stream_state *stream_needs_pll, 2526 struct dc_state *context) 2527 { 2528 int i; 2529 2530 for (i = 0; i < context->stream_count; i++) { 2531 struct dc_stream_state *stream_has_pll = context->streams[i]; 2532 2533 /* We are looking for non dp, non virtual stream */ 2534 if (resource_are_streams_timing_synchronizable( 2535 stream_needs_pll, stream_has_pll) 2536 && !dc_is_dp_signal(stream_has_pll->signal) 2537 && stream_has_pll->link->connector_signal 2538 != SIGNAL_TYPE_VIRTUAL) 2539 return stream_has_pll; 2540 2541 } 2542 2543 return NULL; 2544 } 2545 2546 static int get_norm_pix_clk(const struct dc_crtc_timing *timing) 2547 { 2548 uint32_t pix_clk = timing->pix_clk_100hz; 2549 uint32_t normalized_pix_clk = pix_clk; 2550 2551 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 2552 pix_clk /= 2; 2553 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 2554 switch (timing->display_color_depth) { 2555 case COLOR_DEPTH_666: 2556 case COLOR_DEPTH_888: 2557 normalized_pix_clk = pix_clk; 2558 break; 2559 case COLOR_DEPTH_101010: 2560 normalized_pix_clk = (pix_clk * 30) / 24; 2561 break; 2562 case COLOR_DEPTH_121212: 2563 normalized_pix_clk = (pix_clk * 36) / 24; 2564 break; 2565 case COLOR_DEPTH_161616: 2566 normalized_pix_clk = (pix_clk * 48) / 24; 2567 break; 2568 default: 2569 ASSERT(0); 2570 break; 2571 } 2572 } 2573 return normalized_pix_clk; 2574 } 2575 2576 static void calculate_phy_pix_clks(struct dc_stream_state *stream) 2577 { 2578 /* update actual pixel clock on all streams */ 2579 if (dc_is_hdmi_signal(stream->signal)) 2580 stream->phy_pix_clk = get_norm_pix_clk( 2581 &stream->timing) / 10; 2582 else 2583 stream->phy_pix_clk = 2584 stream->timing.pix_clk_100hz / 10; 2585 2586 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 2587 stream->phy_pix_clk *= 2; 2588 } 2589 2590 static int acquire_resource_from_hw_enabled_state( 2591 struct resource_context *res_ctx, 2592 const struct resource_pool *pool, 2593 struct dc_stream_state *stream) 2594 { 2595 struct dc_link *link = stream->link; 2596 unsigned int i, inst, tg_inst = 0; 2597 uint32_t numPipes = 1; 2598 uint32_t id_src[4] = {0}; 2599 2600 /* Check for enabled DIG to identify enabled display */ 2601 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) 2602 return -1; 2603 2604 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); 2605 2606 if (inst == ENGINE_ID_UNKNOWN) 2607 return -1; 2608 2609 for (i = 0; i < pool->stream_enc_count; i++) { 2610 if (pool->stream_enc[i]->id == inst) { 2611 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( 2612 pool->stream_enc[i]); 2613 break; 2614 } 2615 } 2616 2617 // tg_inst not found 2618 if (i == pool->stream_enc_count) 2619 return -1; 2620 2621 if (tg_inst >= pool->timing_generator_count) 2622 return -1; 2623 2624 if (!res_ctx->pipe_ctx[tg_inst].stream) { 2625 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; 2626 2627 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 2628 id_src[0] = tg_inst; 2629 2630 if (pipe_ctx->stream_res.tg->funcs->get_optc_source) 2631 pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg, 2632 &numPipes, &id_src[0], &id_src[1]); 2633 2634 if (id_src[0] == 0xf && id_src[1] == 0xf) { 2635 id_src[0] = tg_inst; 2636 numPipes = 1; 2637 } 2638 2639 for (i = 0; i < numPipes; i++) { 2640 //Check if src id invalid 2641 if (id_src[i] == 0xf) 2642 return -1; 2643 2644 pipe_ctx = &res_ctx->pipe_ctx[id_src[i]]; 2645 2646 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; 2647 pipe_ctx->plane_res.mi = pool->mis[id_src[i]]; 2648 pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]]; 2649 pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]]; 2650 pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]]; 2651 pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]]; 2652 pipe_ctx->stream_res.opp = pool->opps[id_src[i]]; 2653 2654 if (pool->dpps[id_src[i]]) { 2655 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst; 2656 2657 if (pool->mpc->funcs->read_mpcc_state) { 2658 struct mpcc_state s = {0}; 2659 2660 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); 2661 2662 if (s.dpp_id < MAX_MPCC) 2663 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = 2664 s.dpp_id; 2665 2666 if (s.bot_mpcc_id < MAX_MPCC) 2667 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = 2668 &pool->mpc->mpcc_array[s.bot_mpcc_id]; 2669 2670 if (s.opp_id < MAX_OPP) 2671 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id; 2672 } 2673 } 2674 pipe_ctx->pipe_idx = id_src[i]; 2675 2676 if (id_src[i] >= pool->timing_generator_count) { 2677 id_src[i] = pool->timing_generator_count - 1; 2678 2679 pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]]; 2680 pipe_ctx->stream_res.opp = pool->opps[id_src[i]]; 2681 } 2682 2683 pipe_ctx->stream = stream; 2684 } 2685 2686 if (numPipes == 2) { 2687 stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1; 2688 res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]]; 2689 res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL; 2690 res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL; 2691 res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]]; 2692 } else 2693 stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled; 2694 2695 return id_src[0]; 2696 } 2697 2698 return -1; 2699 } 2700 2701 static void mark_seamless_boot_stream( 2702 const struct dc *dc, 2703 struct dc_stream_state *stream) 2704 { 2705 struct dc_bios *dcb = dc->ctx->dc_bios; 2706 2707 if (dc->config.allow_seamless_boot_optimization && 2708 !dcb->funcs->is_accelerated_mode(dcb)) { 2709 if (dc_validate_boot_timing(dc, stream->sink, &stream->timing)) 2710 stream->apply_seamless_boot_optimization = true; 2711 } 2712 } 2713 2714 enum dc_status resource_map_pool_resources( 2715 const struct dc *dc, 2716 struct dc_state *context, 2717 struct dc_stream_state *stream) 2718 { 2719 const struct resource_pool *pool = dc->res_pool; 2720 int i; 2721 struct dc_context *dc_ctx = dc->ctx; 2722 struct pipe_ctx *pipe_ctx = NULL; 2723 int pipe_idx = -1; 2724 2725 calculate_phy_pix_clks(stream); 2726 2727 mark_seamless_boot_stream(dc, stream); 2728 2729 if (stream->apply_seamless_boot_optimization) { 2730 pipe_idx = acquire_resource_from_hw_enabled_state( 2731 &context->res_ctx, 2732 pool, 2733 stream); 2734 if (pipe_idx < 0) 2735 /* hw resource was assigned to other stream */ 2736 stream->apply_seamless_boot_optimization = false; 2737 } 2738 2739 if (pipe_idx < 0) 2740 /* acquire new resources */ 2741 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); 2742 2743 if (pipe_idx < 0) 2744 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); 2745 2746 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL) 2747 return DC_NO_CONTROLLER_RESOURCE; 2748 2749 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2750 2751 pipe_ctx->stream_res.stream_enc = 2752 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link( 2753 &context->res_ctx, pool, stream); 2754 2755 if (!pipe_ctx->stream_res.stream_enc) 2756 return DC_NO_STREAM_ENC_RESOURCE; 2757 2758 update_stream_engine_usage( 2759 &context->res_ctx, pool, 2760 pipe_ctx->stream_res.stream_enc, 2761 true); 2762 2763 /* Allocate DP HPO Stream Encoder based on signal, hw capabilities 2764 * and link settings 2765 */ 2766 if (dc_is_dp_signal(stream->signal)) { 2767 if (!dc->link_srv->dp_decide_link_settings(stream, &pipe_ctx->link_config.dp_link_settings)) 2768 return DC_FAIL_DP_LINK_BANDWIDTH; 2769 if (dc->link_srv->dp_get_encoding_format( 2770 &pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) { 2771 pipe_ctx->stream_res.hpo_dp_stream_enc = 2772 find_first_free_match_hpo_dp_stream_enc_for_link( 2773 &context->res_ctx, pool, stream); 2774 2775 if (!pipe_ctx->stream_res.hpo_dp_stream_enc) 2776 return DC_NO_STREAM_ENC_RESOURCE; 2777 2778 update_hpo_dp_stream_engine_usage( 2779 &context->res_ctx, pool, 2780 pipe_ctx->stream_res.hpo_dp_stream_enc, 2781 true); 2782 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream)) 2783 return DC_NO_LINK_ENC_RESOURCE; 2784 } 2785 } 2786 2787 /* TODO: Add check if ASIC support and EDID audio */ 2788 if (!stream->converter_disable_audio && 2789 dc_is_audio_capable_signal(pipe_ctx->stream->signal) && 2790 stream->audio_info.mode_count && stream->audio_info.flags.all) { 2791 pipe_ctx->stream_res.audio = find_first_free_audio( 2792 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version); 2793 2794 /* 2795 * Audio assigned in order first come first get. 2796 * There are asics which has number of audio 2797 * resources less then number of pipes 2798 */ 2799 if (pipe_ctx->stream_res.audio) 2800 update_audio_usage(&context->res_ctx, pool, 2801 pipe_ctx->stream_res.audio, true); 2802 } 2803 2804 /* Add ABM to the resource if on EDP */ 2805 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) { 2806 if (pool->abm) 2807 pipe_ctx->stream_res.abm = pool->abm; 2808 else 2809 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst]; 2810 } 2811 2812 for (i = 0; i < context->stream_count; i++) 2813 if (context->streams[i] == stream) { 2814 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; 2815 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst; 2816 context->stream_status[i].audio_inst = 2817 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1; 2818 2819 return DC_OK; 2820 } 2821 2822 DC_ERROR("Stream %p not found in new ctx!\n", stream); 2823 return DC_ERROR_UNEXPECTED; 2824 } 2825 2826 /** 2827 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state 2828 * 2829 * @dc: copy out of dc->current_state 2830 * @dst_ctx: copy into this 2831 * 2832 * This function makes a shallow copy of the current DC state and increments 2833 * refcounts on existing streams and planes. 2834 */ 2835 void dc_resource_state_copy_construct_current( 2836 const struct dc *dc, 2837 struct dc_state *dst_ctx) 2838 { 2839 dc_resource_state_copy_construct(dc->current_state, dst_ctx); 2840 } 2841 2842 2843 void dc_resource_state_construct( 2844 const struct dc *dc, 2845 struct dc_state *dst_ctx) 2846 { 2847 dst_ctx->clk_mgr = dc->clk_mgr; 2848 2849 /* Initialise DIG link encoder resource tracking variables. */ 2850 link_enc_cfg_init(dc, dst_ctx); 2851 } 2852 2853 2854 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) 2855 { 2856 if (dc->res_pool == NULL) 2857 return false; 2858 2859 return dc->res_pool->res_cap->num_dsc > 0; 2860 } 2861 2862 static bool planes_changed_for_existing_stream(struct dc_state *context, 2863 struct dc_stream_state *stream, 2864 const struct dc_validation_set set[], 2865 int set_count) 2866 { 2867 int i, j; 2868 struct dc_stream_status *stream_status = NULL; 2869 2870 for (i = 0; i < context->stream_count; i++) { 2871 if (context->streams[i] == stream) { 2872 stream_status = &context->stream_status[i]; 2873 break; 2874 } 2875 } 2876 2877 if (!stream_status) 2878 ASSERT(0); 2879 2880 for (i = 0; i < set_count; i++) 2881 if (set[i].stream == stream) 2882 break; 2883 2884 if (i == set_count) 2885 ASSERT(0); 2886 2887 if (set[i].plane_count != stream_status->plane_count) 2888 return true; 2889 2890 for (j = 0; j < set[i].plane_count; j++) 2891 if (set[i].plane_states[j] != stream_status->plane_states[j]) 2892 return true; 2893 2894 return false; 2895 } 2896 2897 /** 2898 * dc_validate_with_context - Validate and update the potential new stream in the context object 2899 * 2900 * @dc: Used to get the current state status 2901 * @set: An array of dc_validation_set with all the current streams reference 2902 * @set_count: Total of streams 2903 * @context: New context 2904 * @fast_validate: Enable or disable fast validation 2905 * 2906 * This function updates the potential new stream in the context object. It 2907 * creates multiple lists for the add, remove, and unchanged streams. In 2908 * particular, if the unchanged streams have a plane that changed, it is 2909 * necessary to remove all planes from the unchanged streams. In summary, this 2910 * function is responsible for validating the new context. 2911 * 2912 * Return: 2913 * In case of success, return DC_OK (1), otherwise, return a DC error. 2914 */ 2915 enum dc_status dc_validate_with_context(struct dc *dc, 2916 const struct dc_validation_set set[], 2917 int set_count, 2918 struct dc_state *context, 2919 bool fast_validate) 2920 { 2921 struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 }; 2922 struct dc_stream_state *del_streams[MAX_PIPES] = { 0 }; 2923 struct dc_stream_state *add_streams[MAX_PIPES] = { 0 }; 2924 int old_stream_count = context->stream_count; 2925 enum dc_status res = DC_ERROR_UNEXPECTED; 2926 int unchanged_streams_count = 0; 2927 int del_streams_count = 0; 2928 int add_streams_count = 0; 2929 bool found = false; 2930 int i, j, k; 2931 2932 DC_LOGGER_INIT(dc->ctx->logger); 2933 2934 /* First build a list of streams to be remove from current context */ 2935 for (i = 0; i < old_stream_count; i++) { 2936 struct dc_stream_state *stream = context->streams[i]; 2937 2938 for (j = 0; j < set_count; j++) { 2939 if (stream == set[j].stream) { 2940 found = true; 2941 break; 2942 } 2943 } 2944 2945 if (!found) 2946 del_streams[del_streams_count++] = stream; 2947 2948 found = false; 2949 } 2950 2951 /* Second, build a list of new streams */ 2952 for (i = 0; i < set_count; i++) { 2953 struct dc_stream_state *stream = set[i].stream; 2954 2955 for (j = 0; j < old_stream_count; j++) { 2956 if (stream == context->streams[j]) { 2957 found = true; 2958 break; 2959 } 2960 } 2961 2962 if (!found) 2963 add_streams[add_streams_count++] = stream; 2964 2965 found = false; 2966 } 2967 2968 /* Build a list of unchanged streams which is necessary for handling 2969 * planes change such as added, removed, and updated. 2970 */ 2971 for (i = 0; i < set_count; i++) { 2972 /* Check if stream is part of the delete list */ 2973 for (j = 0; j < del_streams_count; j++) { 2974 if (set[i].stream == del_streams[j]) { 2975 found = true; 2976 break; 2977 } 2978 } 2979 2980 if (!found) { 2981 /* Check if stream is part of the add list */ 2982 for (j = 0; j < add_streams_count; j++) { 2983 if (set[i].stream == add_streams[j]) { 2984 found = true; 2985 break; 2986 } 2987 } 2988 } 2989 2990 if (!found) 2991 unchanged_streams[unchanged_streams_count++] = set[i].stream; 2992 2993 found = false; 2994 } 2995 2996 /* Remove all planes for unchanged streams if planes changed */ 2997 for (i = 0; i < unchanged_streams_count; i++) { 2998 if (planes_changed_for_existing_stream(context, 2999 unchanged_streams[i], 3000 set, 3001 set_count)) { 3002 if (!dc_rem_all_planes_for_stream(dc, 3003 unchanged_streams[i], 3004 context)) { 3005 res = DC_FAIL_DETACH_SURFACES; 3006 goto fail; 3007 } 3008 } 3009 } 3010 3011 /* Remove all planes for removed streams and then remove the streams */ 3012 for (i = 0; i < del_streams_count; i++) { 3013 /* Need to cpy the dwb data from the old stream in order to efc to work */ 3014 if (del_streams[i]->num_wb_info > 0) { 3015 for (j = 0; j < add_streams_count; j++) { 3016 if (del_streams[i]->sink == add_streams[j]->sink) { 3017 add_streams[j]->num_wb_info = del_streams[i]->num_wb_info; 3018 for (k = 0; k < del_streams[i]->num_wb_info; k++) 3019 add_streams[j]->writeback_info[k] = del_streams[i]->writeback_info[k]; 3020 } 3021 } 3022 } 3023 3024 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { 3025 res = DC_FAIL_DETACH_SURFACES; 3026 goto fail; 3027 } 3028 3029 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); 3030 if (res != DC_OK) 3031 goto fail; 3032 } 3033 3034 /* Swap seamless boot stream to pipe 0 (if needed) to ensure pipe_ctx 3035 * matches. This may change in the future if seamless_boot_stream can be 3036 * multiple. 3037 */ 3038 for (i = 0; i < add_streams_count; i++) { 3039 mark_seamless_boot_stream(dc, add_streams[i]); 3040 if (add_streams[i]->apply_seamless_boot_optimization && i != 0) { 3041 struct dc_stream_state *temp = add_streams[0]; 3042 3043 add_streams[0] = add_streams[i]; 3044 add_streams[i] = temp; 3045 break; 3046 } 3047 } 3048 3049 /* Add new streams and then add all planes for the new stream */ 3050 for (i = 0; i < add_streams_count; i++) { 3051 calculate_phy_pix_clks(add_streams[i]); 3052 res = dc_add_stream_to_ctx(dc, context, add_streams[i]); 3053 if (res != DC_OK) 3054 goto fail; 3055 3056 if (!add_all_planes_for_stream(dc, add_streams[i], set, set_count, context)) { 3057 res = DC_FAIL_ATTACH_SURFACES; 3058 goto fail; 3059 } 3060 } 3061 3062 /* Add all planes for unchanged streams if planes changed */ 3063 for (i = 0; i < unchanged_streams_count; i++) { 3064 if (planes_changed_for_existing_stream(context, 3065 unchanged_streams[i], 3066 set, 3067 set_count)) { 3068 if (!add_all_planes_for_stream(dc, unchanged_streams[i], set, set_count, context)) { 3069 res = DC_FAIL_ATTACH_SURFACES; 3070 goto fail; 3071 } 3072 } 3073 } 3074 3075 res = dc_validate_global_state(dc, context, fast_validate); 3076 3077 fail: 3078 if (res != DC_OK) 3079 DC_LOG_WARNING("%s:resource validation failed, dc_status:%d\n", 3080 __func__, 3081 res); 3082 3083 return res; 3084 } 3085 3086 /** 3087 * dc_validate_global_state() - Determine if hardware can support a given state 3088 * 3089 * @dc: dc struct for this driver 3090 * @new_ctx: state to be validated 3091 * @fast_validate: set to true if only yes/no to support matters 3092 * 3093 * Checks hardware resource availability and bandwidth requirement. 3094 * 3095 * Return: 3096 * DC_OK if the result can be programmed. Otherwise, an error code. 3097 */ 3098 enum dc_status dc_validate_global_state( 3099 struct dc *dc, 3100 struct dc_state *new_ctx, 3101 bool fast_validate) 3102 { 3103 enum dc_status result = DC_ERROR_UNEXPECTED; 3104 int i, j; 3105 3106 if (!new_ctx) 3107 return DC_ERROR_UNEXPECTED; 3108 3109 if (dc->res_pool->funcs->validate_global) { 3110 result = dc->res_pool->funcs->validate_global(dc, new_ctx); 3111 if (result != DC_OK) 3112 return result; 3113 } 3114 3115 for (i = 0; i < new_ctx->stream_count; i++) { 3116 struct dc_stream_state *stream = new_ctx->streams[i]; 3117 3118 for (j = 0; j < dc->res_pool->pipe_count; j++) { 3119 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; 3120 3121 if (pipe_ctx->stream != stream) 3122 continue; 3123 3124 if (dc->res_pool->funcs->patch_unknown_plane_state && 3125 pipe_ctx->plane_state && 3126 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { 3127 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); 3128 if (result != DC_OK) 3129 return result; 3130 } 3131 3132 /* Switch to dp clock source only if there is 3133 * no non dp stream that shares the same timing 3134 * with the dp stream. 3135 */ 3136 if (dc_is_dp_signal(pipe_ctx->stream->signal) && 3137 !find_pll_sharable_stream(stream, new_ctx)) { 3138 3139 resource_unreference_clock_source( 3140 &new_ctx->res_ctx, 3141 dc->res_pool, 3142 pipe_ctx->clock_source); 3143 3144 pipe_ctx->clock_source = dc->res_pool->dp_clock_source; 3145 resource_reference_clock_source( 3146 &new_ctx->res_ctx, 3147 dc->res_pool, 3148 pipe_ctx->clock_source); 3149 } 3150 } 3151 } 3152 3153 result = resource_build_scaling_params_for_context(dc, new_ctx); 3154 3155 if (result == DC_OK) 3156 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate)) 3157 result = DC_FAIL_BANDWIDTH_VALIDATE; 3158 3159 /* 3160 * Only update link encoder to stream assignment after bandwidth validation passed. 3161 * TODO: Split out assignment and validation. 3162 */ 3163 if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false) 3164 dc->res_pool->funcs->link_encs_assign( 3165 dc, new_ctx, new_ctx->streams, new_ctx->stream_count); 3166 3167 return result; 3168 } 3169 3170 static void patch_gamut_packet_checksum( 3171 struct dc_info_packet *gamut_packet) 3172 { 3173 /* For gamut we recalc checksum */ 3174 if (gamut_packet->valid) { 3175 uint8_t chk_sum = 0; 3176 uint8_t *ptr; 3177 uint8_t i; 3178 3179 /*start of the Gamut data. */ 3180 ptr = &gamut_packet->sb[3]; 3181 3182 for (i = 0; i <= gamut_packet->sb[1]; i++) 3183 chk_sum += ptr[i]; 3184 3185 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum); 3186 } 3187 } 3188 3189 static void set_avi_info_frame( 3190 struct dc_info_packet *info_packet, 3191 struct pipe_ctx *pipe_ctx) 3192 { 3193 struct dc_stream_state *stream = pipe_ctx->stream; 3194 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; 3195 uint32_t pixel_encoding = 0; 3196 enum scanning_type scan_type = SCANNING_TYPE_NODATA; 3197 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA; 3198 bool itc = false; 3199 uint8_t itc_value = 0; 3200 uint8_t cn0_cn1 = 0; 3201 unsigned int cn0_cn1_value = 0; 3202 uint8_t *check_sum = NULL; 3203 uint8_t byte_index = 0; 3204 union hdmi_info_packet hdmi_info; 3205 union display_content_support support = {0}; 3206 unsigned int vic = pipe_ctx->stream->timing.vic; 3207 unsigned int rid = pipe_ctx->stream->timing.rid; 3208 unsigned int fr_ind = pipe_ctx->stream->timing.fr_index; 3209 enum dc_timing_3d_format format; 3210 3211 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet)); 3212 3213 color_space = pipe_ctx->stream->output_color_space; 3214 if (color_space == COLOR_SPACE_UNKNOWN) 3215 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? 3216 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; 3217 3218 /* Initialize header */ 3219 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI; 3220 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall 3221 * not be used in HDMI 2.0 (Section 10.1) */ 3222 hdmi_info.bits.header.version = 2; 3223 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE; 3224 3225 /* 3226 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built 3227 * according to HDMI 2.0 spec (Section 10.1) 3228 */ 3229 3230 switch (stream->timing.pixel_encoding) { 3231 case PIXEL_ENCODING_YCBCR422: 3232 pixel_encoding = 1; 3233 break; 3234 3235 case PIXEL_ENCODING_YCBCR444: 3236 pixel_encoding = 2; 3237 break; 3238 case PIXEL_ENCODING_YCBCR420: 3239 pixel_encoding = 3; 3240 break; 3241 3242 case PIXEL_ENCODING_RGB: 3243 default: 3244 pixel_encoding = 0; 3245 } 3246 3247 /* Y0_Y1_Y2 : The pixel encoding */ 3248 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */ 3249 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding; 3250 3251 /* A0 = 1 Active Format Information valid */ 3252 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID; 3253 3254 /* B0, B1 = 3; Bar info data is valid */ 3255 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID; 3256 3257 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM; 3258 3259 /* S0, S1 : Underscan / Overscan */ 3260 /* TODO: un-hardcode scan type */ 3261 scan_type = SCANNING_TYPE_UNDERSCAN; 3262 hdmi_info.bits.S0_S1 = scan_type; 3263 3264 /* C0, C1 : Colorimetry */ 3265 switch (color_space) { 3266 case COLOR_SPACE_YCBCR709: 3267 case COLOR_SPACE_YCBCR709_LIMITED: 3268 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709; 3269 break; 3270 case COLOR_SPACE_YCBCR601: 3271 case COLOR_SPACE_YCBCR601_LIMITED: 3272 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601; 3273 break; 3274 case COLOR_SPACE_2020_RGB_FULLRANGE: 3275 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 3276 case COLOR_SPACE_2020_YCBCR: 3277 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR; 3278 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 3279 break; 3280 case COLOR_SPACE_ADOBERGB: 3281 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB; 3282 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED; 3283 break; 3284 case COLOR_SPACE_SRGB: 3285 default: 3286 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA; 3287 break; 3288 } 3289 3290 if (pixel_encoding && color_space == COLOR_SPACE_2020_YCBCR && 3291 stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) { 3292 hdmi_info.bits.EC0_EC2 = 0; 3293 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709; 3294 } 3295 3296 /* TODO: un-hardcode aspect ratio */ 3297 aspect = stream->timing.aspect_ratio; 3298 3299 switch (aspect) { 3300 case ASPECT_RATIO_4_3: 3301 case ASPECT_RATIO_16_9: 3302 hdmi_info.bits.M0_M1 = aspect; 3303 break; 3304 3305 case ASPECT_RATIO_NO_DATA: 3306 case ASPECT_RATIO_64_27: 3307 case ASPECT_RATIO_256_135: 3308 default: 3309 hdmi_info.bits.M0_M1 = 0; 3310 } 3311 3312 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */ 3313 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE; 3314 3315 /* TODO: un-hardcode cn0_cn1 and itc */ 3316 3317 cn0_cn1 = 0; 3318 cn0_cn1_value = 0; 3319 3320 itc = true; 3321 itc_value = 1; 3322 3323 support = stream->content_support; 3324 3325 if (itc) { 3326 if (!support.bits.valid_content_type) { 3327 cn0_cn1_value = 0; 3328 } else { 3329 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) { 3330 if (support.bits.graphics_content == 1) { 3331 cn0_cn1_value = 0; 3332 } 3333 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) { 3334 if (support.bits.photo_content == 1) { 3335 cn0_cn1_value = 1; 3336 } else { 3337 cn0_cn1_value = 0; 3338 itc_value = 0; 3339 } 3340 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) { 3341 if (support.bits.cinema_content == 1) { 3342 cn0_cn1_value = 2; 3343 } else { 3344 cn0_cn1_value = 0; 3345 itc_value = 0; 3346 } 3347 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) { 3348 if (support.bits.game_content == 1) { 3349 cn0_cn1_value = 3; 3350 } else { 3351 cn0_cn1_value = 0; 3352 itc_value = 0; 3353 } 3354 } 3355 } 3356 hdmi_info.bits.CN0_CN1 = cn0_cn1_value; 3357 hdmi_info.bits.ITC = itc_value; 3358 } 3359 3360 if (stream->qs_bit == 1) { 3361 if (color_space == COLOR_SPACE_SRGB || 3362 color_space == COLOR_SPACE_2020_RGB_FULLRANGE) 3363 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; 3364 else if (color_space == COLOR_SPACE_SRGB_LIMITED || 3365 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) 3366 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE; 3367 else 3368 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 3369 } else 3370 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE; 3371 3372 /* TODO : We should handle YCC quantization */ 3373 /* but we do not have matrix calculation */ 3374 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE; 3375 3376 ///VIC 3377 if (pipe_ctx->stream->timing.hdmi_vic != 0) 3378 vic = 0; 3379 format = stream->timing.timing_3d_format; 3380 /*todo, add 3DStereo support*/ 3381 if (format != TIMING_3D_FORMAT_NONE) { 3382 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled 3383 switch (pipe_ctx->stream->timing.hdmi_vic) { 3384 case 1: 3385 vic = 95; 3386 break; 3387 case 2: 3388 vic = 94; 3389 break; 3390 case 3: 3391 vic = 93; 3392 break; 3393 case 4: 3394 vic = 98; 3395 break; 3396 default: 3397 break; 3398 } 3399 } 3400 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/ 3401 hdmi_info.bits.VIC0_VIC7 = vic; 3402 if (vic >= 128) 3403 hdmi_info.bits.header.version = 3; 3404 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1), 3405 * the Source shall use 20 AVI InfoFrame Version 4 3406 */ 3407 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED && 3408 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) { 3409 hdmi_info.bits.header.version = 4; 3410 hdmi_info.bits.header.length = 14; 3411 } 3412 3413 if (rid != 0 && fr_ind != 0) { 3414 hdmi_info.bits.header.version = 5; 3415 hdmi_info.bits.header.length = 15; 3416 3417 hdmi_info.bits.FR0_FR3 = fr_ind & 0xF; 3418 hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1; 3419 hdmi_info.bits.RID0_RID5 = rid; 3420 } 3421 3422 /* pixel repetition 3423 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel 3424 * repetition start from 1 */ 3425 hdmi_info.bits.PR0_PR3 = 0; 3426 3427 /* Bar Info 3428 * barTop: Line Number of End of Top Bar. 3429 * barBottom: Line Number of Start of Bottom Bar. 3430 * barLeft: Pixel Number of End of Left Bar. 3431 * barRight: Pixel Number of Start of Right Bar. */ 3432 hdmi_info.bits.bar_top = stream->timing.v_border_top; 3433 hdmi_info.bits.bar_bottom = (stream->timing.v_total 3434 - stream->timing.v_border_bottom + 1); 3435 hdmi_info.bits.bar_left = stream->timing.h_border_left; 3436 hdmi_info.bits.bar_right = (stream->timing.h_total 3437 - stream->timing.h_border_right + 1); 3438 3439 /* Additional Colorimetry Extension 3440 * Used in conduction with C0-C1 and EC0-EC2 3441 * 0 = DCI-P3 RGB (D65) 3442 * 1 = DCI-P3 RGB (theater) 3443 */ 3444 hdmi_info.bits.ACE0_ACE3 = 0; 3445 3446 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ 3447 check_sum = &hdmi_info.packet_raw_data.sb[0]; 3448 3449 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version; 3450 3451 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++) 3452 *check_sum += hdmi_info.packet_raw_data.sb[byte_index]; 3453 3454 /* one byte complement */ 3455 *check_sum = (uint8_t) (0x100 - *check_sum); 3456 3457 /* Store in hw_path_mode */ 3458 info_packet->hb0 = hdmi_info.packet_raw_data.hb0; 3459 info_packet->hb1 = hdmi_info.packet_raw_data.hb1; 3460 info_packet->hb2 = hdmi_info.packet_raw_data.hb2; 3461 3462 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++) 3463 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index]; 3464 3465 info_packet->valid = true; 3466 } 3467 3468 static void set_vendor_info_packet( 3469 struct dc_info_packet *info_packet, 3470 struct dc_stream_state *stream) 3471 { 3472 /* SPD info packet for FreeSync */ 3473 3474 /* Check if Freesync is supported. Return if false. If true, 3475 * set the corresponding bit in the info packet 3476 */ 3477 if (!stream->vsp_infopacket.valid) 3478 return; 3479 3480 *info_packet = stream->vsp_infopacket; 3481 } 3482 3483 static void set_spd_info_packet( 3484 struct dc_info_packet *info_packet, 3485 struct dc_stream_state *stream) 3486 { 3487 /* SPD info packet for FreeSync */ 3488 3489 /* Check if Freesync is supported. Return if false. If true, 3490 * set the corresponding bit in the info packet 3491 */ 3492 if (!stream->vrr_infopacket.valid) 3493 return; 3494 3495 *info_packet = stream->vrr_infopacket; 3496 } 3497 3498 static void set_hdr_static_info_packet( 3499 struct dc_info_packet *info_packet, 3500 struct dc_stream_state *stream) 3501 { 3502 /* HDR Static Metadata info packet for HDR10 */ 3503 3504 if (!stream->hdr_static_metadata.valid || 3505 stream->use_dynamic_meta) 3506 return; 3507 3508 *info_packet = stream->hdr_static_metadata; 3509 } 3510 3511 static void set_vsc_info_packet( 3512 struct dc_info_packet *info_packet, 3513 struct dc_stream_state *stream) 3514 { 3515 if (!stream->vsc_infopacket.valid) 3516 return; 3517 3518 *info_packet = stream->vsc_infopacket; 3519 } 3520 static void set_hfvs_info_packet( 3521 struct dc_info_packet *info_packet, 3522 struct dc_stream_state *stream) 3523 { 3524 if (!stream->hfvsif_infopacket.valid) 3525 return; 3526 3527 *info_packet = stream->hfvsif_infopacket; 3528 } 3529 3530 static void adaptive_sync_override_dp_info_packets_sdp_line_num( 3531 const struct dc_crtc_timing *timing, 3532 struct enc_sdp_line_num *sdp_line_num, 3533 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param) 3534 { 3535 uint32_t asic_blank_start = 0; 3536 uint32_t asic_blank_end = 0; 3537 uint32_t v_update = 0; 3538 3539 const struct dc_crtc_timing *tg = timing; 3540 3541 /* blank_start = frame end - front porch */ 3542 asic_blank_start = tg->v_total - tg->v_front_porch; 3543 3544 /* blank_end = blank_start - active */ 3545 asic_blank_end = (asic_blank_start - tg->v_border_bottom - 3546 tg->v_addressable - tg->v_border_top); 3547 3548 if (pipe_dlg_param->vstartup_start > asic_blank_end) { 3549 v_update = (tg->v_total - (pipe_dlg_param->vstartup_start - asic_blank_end)); 3550 sdp_line_num->adaptive_sync_line_num_valid = true; 3551 sdp_line_num->adaptive_sync_line_num = (tg->v_total - v_update - 1); 3552 } else { 3553 sdp_line_num->adaptive_sync_line_num_valid = false; 3554 sdp_line_num->adaptive_sync_line_num = 0; 3555 } 3556 } 3557 3558 static void set_adaptive_sync_info_packet( 3559 struct dc_info_packet *info_packet, 3560 const struct dc_stream_state *stream, 3561 struct encoder_info_frame *info_frame, 3562 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param) 3563 { 3564 if (!stream->adaptive_sync_infopacket.valid) 3565 return; 3566 3567 adaptive_sync_override_dp_info_packets_sdp_line_num( 3568 &stream->timing, 3569 &info_frame->sdp_line_num, 3570 pipe_dlg_param); 3571 3572 *info_packet = stream->adaptive_sync_infopacket; 3573 } 3574 3575 static void set_vtem_info_packet( 3576 struct dc_info_packet *info_packet, 3577 struct dc_stream_state *stream) 3578 { 3579 if (!stream->vtem_infopacket.valid) 3580 return; 3581 3582 *info_packet = stream->vtem_infopacket; 3583 } 3584 3585 void dc_resource_state_destruct(struct dc_state *context) 3586 { 3587 int i, j; 3588 3589 for (i = 0; i < context->stream_count; i++) { 3590 for (j = 0; j < context->stream_status[i].plane_count; j++) 3591 dc_plane_state_release( 3592 context->stream_status[i].plane_states[j]); 3593 3594 context->stream_status[i].plane_count = 0; 3595 dc_stream_release(context->streams[i]); 3596 context->streams[i] = NULL; 3597 } 3598 context->stream_count = 0; 3599 } 3600 3601 void dc_resource_state_copy_construct( 3602 const struct dc_state *src_ctx, 3603 struct dc_state *dst_ctx) 3604 { 3605 int i, j; 3606 struct kref refcount = dst_ctx->refcount; 3607 3608 *dst_ctx = *src_ctx; 3609 3610 for (i = 0; i < MAX_PIPES; i++) { 3611 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i]; 3612 3613 if (cur_pipe->top_pipe) 3614 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; 3615 3616 if (cur_pipe->bottom_pipe) 3617 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; 3618 3619 if (cur_pipe->next_odm_pipe) 3620 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; 3621 3622 if (cur_pipe->prev_odm_pipe) 3623 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; 3624 } 3625 3626 for (i = 0; i < dst_ctx->stream_count; i++) { 3627 dc_stream_retain(dst_ctx->streams[i]); 3628 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) 3629 dc_plane_state_retain( 3630 dst_ctx->stream_status[i].plane_states[j]); 3631 } 3632 3633 /* context refcount should not be overridden */ 3634 dst_ctx->refcount = refcount; 3635 3636 } 3637 3638 struct clock_source *dc_resource_find_first_free_pll( 3639 struct resource_context *res_ctx, 3640 const struct resource_pool *pool) 3641 { 3642 int i; 3643 3644 for (i = 0; i < pool->clk_src_count; ++i) { 3645 if (res_ctx->clock_source_ref_count[i] == 0) 3646 return pool->clock_sources[i]; 3647 } 3648 3649 return NULL; 3650 } 3651 3652 void resource_build_info_frame(struct pipe_ctx *pipe_ctx) 3653 { 3654 enum signal_type signal = SIGNAL_TYPE_NONE; 3655 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame; 3656 3657 /* default all packets to invalid */ 3658 info->avi.valid = false; 3659 info->gamut.valid = false; 3660 info->vendor.valid = false; 3661 info->spd.valid = false; 3662 info->hdrsmd.valid = false; 3663 info->vsc.valid = false; 3664 info->hfvsif.valid = false; 3665 info->vtem.valid = false; 3666 info->adaptive_sync.valid = false; 3667 signal = pipe_ctx->stream->signal; 3668 3669 /* HDMi and DP have different info packets*/ 3670 if (dc_is_hdmi_signal(signal)) { 3671 set_avi_info_frame(&info->avi, pipe_ctx); 3672 3673 set_vendor_info_packet(&info->vendor, pipe_ctx->stream); 3674 set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream); 3675 set_vtem_info_packet(&info->vtem, pipe_ctx->stream); 3676 3677 set_spd_info_packet(&info->spd, pipe_ctx->stream); 3678 3679 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 3680 3681 } else if (dc_is_dp_signal(signal)) { 3682 set_vsc_info_packet(&info->vsc, pipe_ctx->stream); 3683 3684 set_spd_info_packet(&info->spd, pipe_ctx->stream); 3685 3686 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); 3687 set_adaptive_sync_info_packet(&info->adaptive_sync, 3688 pipe_ctx->stream, 3689 info, 3690 &pipe_ctx->pipe_dlg_param); 3691 } 3692 3693 patch_gamut_packet_checksum(&info->gamut); 3694 } 3695 3696 enum dc_status resource_map_clock_resources( 3697 const struct dc *dc, 3698 struct dc_state *context, 3699 struct dc_stream_state *stream) 3700 { 3701 /* acquire new resources */ 3702 const struct resource_pool *pool = dc->res_pool; 3703 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream( 3704 &context->res_ctx, stream); 3705 3706 if (!pipe_ctx) 3707 return DC_ERROR_UNEXPECTED; 3708 3709 if (dc_is_dp_signal(pipe_ctx->stream->signal) 3710 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) 3711 pipe_ctx->clock_source = pool->dp_clock_source; 3712 else { 3713 pipe_ctx->clock_source = NULL; 3714 3715 if (!dc->config.disable_disp_pll_sharing) 3716 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing( 3717 &context->res_ctx, 3718 pipe_ctx); 3719 3720 if (pipe_ctx->clock_source == NULL) 3721 pipe_ctx->clock_source = 3722 dc_resource_find_first_free_pll( 3723 &context->res_ctx, 3724 pool); 3725 } 3726 3727 if (pipe_ctx->clock_source == NULL) 3728 return DC_NO_CLOCK_SOURCE_RESOURCE; 3729 3730 resource_reference_clock_source( 3731 &context->res_ctx, pool, 3732 pipe_ctx->clock_source); 3733 3734 return DC_OK; 3735 } 3736 3737 /* 3738 * Note: We need to disable output if clock sources change, 3739 * since bios does optimization and doesn't apply if changing 3740 * PHY when not already disabled. 3741 */ 3742 bool pipe_need_reprogram( 3743 struct pipe_ctx *pipe_ctx_old, 3744 struct pipe_ctx *pipe_ctx) 3745 { 3746 if (!pipe_ctx_old->stream) 3747 return false; 3748 3749 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink) 3750 return true; 3751 3752 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal) 3753 return true; 3754 3755 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio) 3756 return true; 3757 3758 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source 3759 && pipe_ctx_old->stream != pipe_ctx->stream) 3760 return true; 3761 3762 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc) 3763 return true; 3764 3765 if (dc_is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream)) 3766 return true; 3767 3768 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off) 3769 return true; 3770 3771 if (false == pipe_ctx_old->stream->link->link_state_valid && 3772 false == pipe_ctx_old->stream->dpms_off) 3773 return true; 3774 3775 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) 3776 return true; 3777 3778 if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) 3779 return true; 3780 if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc) 3781 return true; 3782 3783 /* DIG link encoder resource assignment for stream changed. */ 3784 if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) { 3785 bool need_reprogram = false; 3786 struct dc *dc = pipe_ctx_old->stream->ctx->dc; 3787 struct link_encoder *link_enc_prev = 3788 link_enc_cfg_get_link_enc_used_by_stream_current(dc, pipe_ctx_old->stream); 3789 3790 if (link_enc_prev != pipe_ctx->stream->link_enc) 3791 need_reprogram = true; 3792 3793 return need_reprogram; 3794 } 3795 3796 return false; 3797 } 3798 3799 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, 3800 struct bit_depth_reduction_params *fmt_bit_depth) 3801 { 3802 enum dc_dither_option option = stream->dither_option; 3803 enum dc_pixel_encoding pixel_encoding = 3804 stream->timing.pixel_encoding; 3805 3806 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); 3807 3808 if (option == DITHER_OPTION_DEFAULT) { 3809 switch (stream->timing.display_color_depth) { 3810 case COLOR_DEPTH_666: 3811 option = DITHER_OPTION_SPATIAL6; 3812 break; 3813 case COLOR_DEPTH_888: 3814 option = DITHER_OPTION_SPATIAL8; 3815 break; 3816 case COLOR_DEPTH_101010: 3817 option = DITHER_OPTION_SPATIAL10; 3818 break; 3819 default: 3820 option = DITHER_OPTION_DISABLE; 3821 } 3822 } 3823 3824 if (option == DITHER_OPTION_DISABLE) 3825 return; 3826 3827 if (option == DITHER_OPTION_TRUN6) { 3828 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 3829 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0; 3830 } else if (option == DITHER_OPTION_TRUN8 || 3831 option == DITHER_OPTION_TRUN8_SPATIAL6 || 3832 option == DITHER_OPTION_TRUN8_FM6) { 3833 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 3834 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1; 3835 } else if (option == DITHER_OPTION_TRUN10 || 3836 option == DITHER_OPTION_TRUN10_SPATIAL6 || 3837 option == DITHER_OPTION_TRUN10_SPATIAL8 || 3838 option == DITHER_OPTION_TRUN10_FM8 || 3839 option == DITHER_OPTION_TRUN10_FM6 || 3840 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 3841 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 3842 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 3843 } 3844 3845 /* special case - Formatter can only reduce by 4 bits at most. 3846 * When reducing from 12 to 6 bits, 3847 * HW recommends we use trunc with round mode 3848 * (if we did nothing, trunc to 10 bits would be used) 3849 * note that any 12->10 bit reduction is ignored prior to DCE8, 3850 * as the input was 10 bits. 3851 */ 3852 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 3853 option == DITHER_OPTION_SPATIAL6 || 3854 option == DITHER_OPTION_FM6) { 3855 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1; 3856 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2; 3857 fmt_bit_depth->flags.TRUNCATE_MODE = 1; 3858 } 3859 3860 /* spatial dither 3861 * note that spatial modes 1-3 are never used 3862 */ 3863 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM || 3864 option == DITHER_OPTION_SPATIAL6 || 3865 option == DITHER_OPTION_TRUN10_SPATIAL6 || 3866 option == DITHER_OPTION_TRUN8_SPATIAL6) { 3867 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 3868 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0; 3869 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 3870 fmt_bit_depth->flags.RGB_RANDOM = 3871 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 3872 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM || 3873 option == DITHER_OPTION_SPATIAL8 || 3874 option == DITHER_OPTION_SPATIAL8_FM6 || 3875 option == DITHER_OPTION_TRUN10_SPATIAL8 || 3876 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 3877 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 3878 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1; 3879 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 3880 fmt_bit_depth->flags.RGB_RANDOM = 3881 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 3882 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM || 3883 option == DITHER_OPTION_SPATIAL10 || 3884 option == DITHER_OPTION_SPATIAL10_FM8 || 3885 option == DITHER_OPTION_SPATIAL10_FM6) { 3886 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1; 3887 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2; 3888 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1; 3889 fmt_bit_depth->flags.RGB_RANDOM = 3890 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; 3891 } 3892 3893 if (option == DITHER_OPTION_SPATIAL6 || 3894 option == DITHER_OPTION_SPATIAL8 || 3895 option == DITHER_OPTION_SPATIAL10) { 3896 fmt_bit_depth->flags.FRAME_RANDOM = 0; 3897 } else { 3898 fmt_bit_depth->flags.FRAME_RANDOM = 1; 3899 } 3900 3901 ////////////////////// 3902 //// temporal dither 3903 ////////////////////// 3904 if (option == DITHER_OPTION_FM6 || 3905 option == DITHER_OPTION_SPATIAL8_FM6 || 3906 option == DITHER_OPTION_SPATIAL10_FM6 || 3907 option == DITHER_OPTION_TRUN10_FM6 || 3908 option == DITHER_OPTION_TRUN8_FM6 || 3909 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) { 3910 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 3911 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0; 3912 } else if (option == DITHER_OPTION_FM8 || 3913 option == DITHER_OPTION_SPATIAL10_FM8 || 3914 option == DITHER_OPTION_TRUN10_FM8) { 3915 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 3916 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1; 3917 } else if (option == DITHER_OPTION_FM10) { 3918 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1; 3919 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2; 3920 } 3921 3922 fmt_bit_depth->pixel_encoding = pixel_encoding; 3923 } 3924 3925 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) 3926 { 3927 struct dc_link *link = stream->link; 3928 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 3929 enum dc_status res = DC_OK; 3930 3931 calculate_phy_pix_clks(stream); 3932 3933 if (!tg->funcs->validate_timing(tg, &stream->timing)) 3934 res = DC_FAIL_CONTROLLER_VALIDATE; 3935 3936 if (res == DC_OK) { 3937 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 3938 !link->link_enc->funcs->validate_output_with_stream( 3939 link->link_enc, stream)) 3940 res = DC_FAIL_ENC_VALIDATE; 3941 } 3942 3943 /* TODO: validate audio ASIC caps, encoder */ 3944 3945 if (res == DC_OK) 3946 res = dc->link_srv->validate_mode_timing(stream, 3947 link, 3948 &stream->timing); 3949 3950 return res; 3951 } 3952 3953 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) 3954 { 3955 enum dc_status res = DC_OK; 3956 3957 /* check if surface has invalid dimensions */ 3958 if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 || 3959 plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0) 3960 return DC_FAIL_SURFACE_VALIDATE; 3961 3962 /* TODO For now validates pixel format only */ 3963 if (dc->res_pool->funcs->validate_plane) 3964 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps); 3965 3966 return res; 3967 } 3968 3969 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format) 3970 { 3971 switch (format) { 3972 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 3973 return 8; 3974 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 3975 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 3976 return 12; 3977 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 3978 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 3979 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 3980 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 3981 return 16; 3982 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 3983 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 3984 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 3985 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 3986 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 3987 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 3988 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 3989 return 32; 3990 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 3991 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 3992 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 3993 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 3994 return 64; 3995 default: 3996 ASSERT_CRITICAL(false); 3997 return -1; 3998 } 3999 } 4000 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes) 4001 { 4002 if (modes) { 4003 if (modes->sample_rates.rate.RATE_192) 4004 return 192000; 4005 if (modes->sample_rates.rate.RATE_176_4) 4006 return 176400; 4007 if (modes->sample_rates.rate.RATE_96) 4008 return 96000; 4009 if (modes->sample_rates.rate.RATE_88_2) 4010 return 88200; 4011 if (modes->sample_rates.rate.RATE_48) 4012 return 48000; 4013 if (modes->sample_rates.rate.RATE_44_1) 4014 return 44100; 4015 if (modes->sample_rates.rate.RATE_32) 4016 return 32000; 4017 } 4018 /*original logic when no audio info*/ 4019 return 441000; 4020 } 4021 4022 void get_audio_check(struct audio_info *aud_modes, 4023 struct audio_check *audio_chk) 4024 { 4025 unsigned int i; 4026 unsigned int max_sample_rate = 0; 4027 4028 if (aud_modes) { 4029 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/ 4030 4031 audio_chk->max_audiosample_rate = 0; 4032 for (i = 0; i < aud_modes->mode_count; i++) { 4033 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]); 4034 if (audio_chk->max_audiosample_rate < max_sample_rate) 4035 audio_chk->max_audiosample_rate = max_sample_rate; 4036 /*dts takes the same as type 2: AP = 0.25*/ 4037 } 4038 /*check which one take more bandwidth*/ 4039 if (audio_chk->max_audiosample_rate > 192000) 4040 audio_chk->audio_packet_type = 0x9;/*AP =1*/ 4041 audio_chk->acat = 0;/*not support*/ 4042 } 4043 } 4044 4045 static struct hpo_dp_link_encoder *get_temp_hpo_dp_link_enc( 4046 const struct resource_context *res_ctx, 4047 const struct resource_pool *const pool, 4048 const struct dc_link *link) 4049 { 4050 struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL; 4051 int enc_index; 4052 4053 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link); 4054 4055 if (enc_index < 0) 4056 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool); 4057 4058 if (enc_index >= 0) 4059 hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index]; 4060 4061 return hpo_dp_link_enc; 4062 } 4063 4064 bool get_temp_dp_link_res(struct dc_link *link, 4065 struct link_resource *link_res, 4066 struct dc_link_settings *link_settings) 4067 { 4068 const struct dc *dc = link->dc; 4069 const struct resource_context *res_ctx = &dc->current_state->res_ctx; 4070 4071 memset(link_res, 0, sizeof(*link_res)); 4072 4073 if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 4074 link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx, 4075 dc->res_pool, link); 4076 if (!link_res->hpo_dp_link_enc) 4077 return false; 4078 } 4079 return true; 4080 } 4081 4082 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc, 4083 struct dc_state *context) 4084 { 4085 int i, j; 4086 struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd; 4087 4088 /* If pipe backend is reset, need to reset pipe syncd status */ 4089 for (i = 0; i < dc->res_pool->pipe_count; i++) { 4090 pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i]; 4091 pipe_ctx = &context->res_ctx.pipe_ctx[i]; 4092 4093 if (!resource_is_pipe_type(pipe_ctx_old, OTG_MASTER)) 4094 continue; 4095 4096 if (!pipe_ctx->stream || 4097 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 4098 4099 /* Reset all the syncd pipes from the disabled pipe */ 4100 for (j = 0; j < dc->res_pool->pipe_count; j++) { 4101 pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j]; 4102 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) || 4103 !IS_PIPE_SYNCD_VALID(pipe_ctx_syncd)) 4104 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j); 4105 } 4106 } 4107 } 4108 } 4109 4110 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc, 4111 struct dc_state *context, 4112 uint8_t disabled_master_pipe_idx) 4113 { 4114 int i; 4115 struct pipe_ctx *pipe_ctx, *pipe_ctx_check; 4116 4117 pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx]; 4118 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) || 4119 !IS_PIPE_SYNCD_VALID(pipe_ctx)) 4120 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx); 4121 4122 /* for the pipe disabled, check if any slave pipe exists and assert */ 4123 for (i = 0; i < dc->res_pool->pipe_count; i++) { 4124 pipe_ctx_check = &context->res_ctx.pipe_ctx[i]; 4125 4126 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) && 4127 IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx)) { 4128 struct pipe_ctx *first_pipe = pipe_ctx_check; 4129 4130 while (first_pipe->prev_odm_pipe) 4131 first_pipe = first_pipe->prev_odm_pipe; 4132 /* When ODM combine is enabled, this case is expected. If the disabled pipe 4133 * is part of the ODM tree, then we should not print an error. 4134 * */ 4135 if (first_pipe->pipe_idx == disabled_master_pipe_idx) 4136 continue; 4137 4138 DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n", 4139 i, disabled_master_pipe_idx); 4140 } 4141 } 4142 } 4143 4144 void reset_sync_context_for_pipe(const struct dc *dc, 4145 struct dc_state *context, 4146 uint8_t pipe_idx) 4147 { 4148 int i; 4149 struct pipe_ctx *pipe_ctx_reset; 4150 4151 /* reset the otg sync context for the pipe and its slave pipes if any */ 4152 for (i = 0; i < dc->res_pool->pipe_count; i++) { 4153 pipe_ctx_reset = &context->res_ctx.pipe_ctx[i]; 4154 4155 if (((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_reset) == pipe_idx) && 4156 IS_PIPE_SYNCD_VALID(pipe_ctx_reset)) || (i == pipe_idx)) 4157 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_reset, i); 4158 } 4159 } 4160 4161 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter) 4162 { 4163 /* TODO - get transmitter to phy idx mapping from DMUB */ 4164 uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A; 4165 4166 if (dc->ctx->dce_version == DCN_VERSION_3_1 && 4167 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 4168 switch (transmitter) { 4169 case TRANSMITTER_UNIPHY_A: 4170 phy_idx = 0; 4171 break; 4172 case TRANSMITTER_UNIPHY_B: 4173 phy_idx = 1; 4174 break; 4175 case TRANSMITTER_UNIPHY_C: 4176 phy_idx = 5; 4177 break; 4178 case TRANSMITTER_UNIPHY_D: 4179 phy_idx = 6; 4180 break; 4181 case TRANSMITTER_UNIPHY_E: 4182 phy_idx = 4; 4183 break; 4184 default: 4185 phy_idx = 0; 4186 break; 4187 } 4188 } 4189 4190 return phy_idx; 4191 } 4192 4193 const struct link_hwss *get_link_hwss(const struct dc_link *link, 4194 const struct link_resource *link_res) 4195 { 4196 /* Link_hwss is only accessible by getter function instead of accessing 4197 * by pointers in dc with the intent to protect against breaking polymorphism. 4198 */ 4199 if (can_use_hpo_dp_link_hwss(link, link_res)) 4200 /* TODO: some assumes that if decided link settings is 128b/132b 4201 * channel coding format hpo_dp_link_enc should be used. 4202 * Others believe that if hpo_dp_link_enc is available in link 4203 * resource then hpo_dp_link_enc must be used. This bound between 4204 * hpo_dp_link_enc != NULL and decided link settings is loosely coupled 4205 * with a premise that both hpo_dp_link_enc pointer and decided link 4206 * settings are determined based on single policy function like 4207 * "decide_link_settings" from upper layer. This "convention" 4208 * cannot be maintained and enforced at current level. 4209 * Therefore a refactor is due so we can enforce a strong bound 4210 * between those two parameters at this level. 4211 * 4212 * To put it simple, we want to make enforcement at low level so that 4213 * we will not return link hwss if caller plans to do 8b/10b 4214 * with an hpo encoder. Or we can return a very dummy one that doesn't 4215 * do work for all functions 4216 */ 4217 return (requires_fixed_vs_pe_retimer_hpo_link_hwss(link) ? 4218 get_hpo_fixed_vs_pe_retimer_dp_link_hwss() : get_hpo_dp_link_hwss()); 4219 else if (can_use_dpia_link_hwss(link, link_res)) 4220 return get_dpia_link_hwss(); 4221 else if (can_use_dio_link_hwss(link, link_res)) 4222 return (requires_fixed_vs_pe_retimer_dio_link_hwss(link)) ? 4223 get_dio_fixed_vs_pe_retimer_link_hwss() : get_dio_link_hwss(); 4224 else 4225 return get_virtual_link_hwss(); 4226 } 4227 4228 bool is_h_timing_divisible_by_2(struct dc_stream_state *stream) 4229 { 4230 bool divisible = false; 4231 uint16_t h_blank_start = 0; 4232 uint16_t h_blank_end = 0; 4233 4234 if (stream) { 4235 h_blank_start = stream->timing.h_total - stream->timing.h_front_porch; 4236 h_blank_end = h_blank_start - stream->timing.h_addressable; 4237 4238 /* HTOTAL, Hblank start/end, and Hsync start/end all must be 4239 * divisible by 2 in order for the horizontal timing params 4240 * to be considered divisible by 2. Hsync start is always 0. 4241 */ 4242 divisible = (stream->timing.h_total % 2 == 0) && 4243 (h_blank_start % 2 == 0) && 4244 (h_blank_end % 2 == 0) && 4245 (stream->timing.h_sync_width % 2 == 0); 4246 } 4247 return divisible; 4248 } 4249 4250 bool dc_resource_acquire_secondary_pipe_for_mpc_odm( 4251 const struct dc *dc, 4252 struct dc_state *state, 4253 struct pipe_ctx *pri_pipe, 4254 struct pipe_ctx *sec_pipe, 4255 bool odm) 4256 { 4257 int pipe_idx = sec_pipe->pipe_idx; 4258 struct pipe_ctx *sec_top, *sec_bottom, *sec_next, *sec_prev; 4259 const struct resource_pool *pool = dc->res_pool; 4260 4261 sec_top = sec_pipe->top_pipe; 4262 sec_bottom = sec_pipe->bottom_pipe; 4263 sec_next = sec_pipe->next_odm_pipe; 4264 sec_prev = sec_pipe->prev_odm_pipe; 4265 4266 *sec_pipe = *pri_pipe; 4267 4268 sec_pipe->top_pipe = sec_top; 4269 sec_pipe->bottom_pipe = sec_bottom; 4270 sec_pipe->next_odm_pipe = sec_next; 4271 sec_pipe->prev_odm_pipe = sec_prev; 4272 4273 sec_pipe->pipe_idx = pipe_idx; 4274 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; 4275 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; 4276 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; 4277 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; 4278 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; 4279 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; 4280 sec_pipe->stream_res.dsc = NULL; 4281 if (odm) { 4282 if (!sec_pipe->top_pipe) 4283 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; 4284 else 4285 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; 4286 if (sec_pipe->stream->timing.flags.DSC == 1) { 4287 #if defined(CONFIG_DRM_AMD_DC_FP) 4288 dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); 4289 #endif 4290 ASSERT(sec_pipe->stream_res.dsc); 4291 if (sec_pipe->stream_res.dsc == NULL) 4292 return false; 4293 } 4294 #if defined(CONFIG_DRM_AMD_DC_FP) 4295 dcn20_build_mapped_resource(dc, state, sec_pipe->stream); 4296 #endif 4297 } 4298 4299 return true; 4300 } 4301 4302 enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc, 4303 struct dc_state *context, 4304 struct pipe_ctx *pipe_ctx) 4305 { 4306 if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) { 4307 if (pipe_ctx->stream_res.hpo_dp_stream_enc == NULL) { 4308 pipe_ctx->stream_res.hpo_dp_stream_enc = 4309 find_first_free_match_hpo_dp_stream_enc_for_link( 4310 &context->res_ctx, dc->res_pool, pipe_ctx->stream); 4311 4312 if (!pipe_ctx->stream_res.hpo_dp_stream_enc) 4313 return DC_NO_STREAM_ENC_RESOURCE; 4314 4315 update_hpo_dp_stream_engine_usage( 4316 &context->res_ctx, dc->res_pool, 4317 pipe_ctx->stream_res.hpo_dp_stream_enc, 4318 true); 4319 } 4320 4321 if (pipe_ctx->link_res.hpo_dp_link_enc == NULL) { 4322 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream)) 4323 return DC_NO_LINK_ENC_RESOURCE; 4324 } 4325 } else { 4326 if (pipe_ctx->stream_res.hpo_dp_stream_enc) { 4327 update_hpo_dp_stream_engine_usage( 4328 &context->res_ctx, dc->res_pool, 4329 pipe_ctx->stream_res.hpo_dp_stream_enc, 4330 false); 4331 pipe_ctx->stream_res.hpo_dp_stream_enc = NULL; 4332 } 4333 if (pipe_ctx->link_res.hpo_dp_link_enc) 4334 remove_hpo_dp_link_enc_from_ctx(&context->res_ctx, pipe_ctx, pipe_ctx->stream); 4335 } 4336 4337 return DC_OK; 4338 } 4339 4340