1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 /* 24 * dc_debug.c 25 * 26 * Created on: Nov 3, 2016 27 * Author: yonsun 28 */ 29 30 #include "dm_services.h" 31 32 #include "dc.h" 33 34 #include "core_status.h" 35 #include "core_types.h" 36 #include "hw_sequencer.h" 37 38 #include "resource.h" 39 40 #define SURFACE_TRACE(...) do {\ 41 if (dc->debug.surface_trace) \ 42 dm_logger_write(logger, \ 43 LOG_IF_TRACE, \ 44 ##__VA_ARGS__); \ 45 } while (0) 46 47 #define TIMING_TRACE(...) do {\ 48 if (dc->debug.timing_trace) \ 49 dm_logger_write(logger, \ 50 LOG_SYNC, \ 51 ##__VA_ARGS__); \ 52 } while (0) 53 54 #define CLOCK_TRACE(...) do {\ 55 if (dc->debug.clock_trace) \ 56 dm_logger_write(logger, \ 57 LOG_BANDWIDTH_CALCS, \ 58 ##__VA_ARGS__); \ 59 } while (0) 60 61 void pre_surface_trace( 62 struct dc *dc, 63 const struct dc_plane_state *const *plane_states, 64 int surface_count) 65 { 66 int i; 67 struct dc *core_dc = dc; 68 struct dal_logger *logger = core_dc->ctx->logger; 69 70 for (i = 0; i < surface_count; i++) { 71 const struct dc_plane_state *plane_state = plane_states[i]; 72 73 SURFACE_TRACE("Planes %d:\n", i); 74 75 SURFACE_TRACE( 76 "plane_state->visible = %d;\n" 77 "plane_state->flip_immediate = %d;\n" 78 "plane_state->address.type = %d;\n" 79 "plane_state->address.grph.addr.quad_part = 0x%X;\n" 80 "plane_state->address.grph.meta_addr.quad_part = 0x%X;\n" 81 "plane_state->scaling_quality.h_taps = %d;\n" 82 "plane_state->scaling_quality.v_taps = %d;\n" 83 "plane_state->scaling_quality.h_taps_c = %d;\n" 84 "plane_state->scaling_quality.v_taps_c = %d;\n", 85 plane_state->visible, 86 plane_state->flip_immediate, 87 plane_state->address.type, 88 plane_state->address.grph.addr.quad_part, 89 plane_state->address.grph.meta_addr.quad_part, 90 plane_state->scaling_quality.h_taps, 91 plane_state->scaling_quality.v_taps, 92 plane_state->scaling_quality.h_taps_c, 93 plane_state->scaling_quality.v_taps_c); 94 95 SURFACE_TRACE( 96 "plane_state->src_rect.x = %d;\n" 97 "plane_state->src_rect.y = %d;\n" 98 "plane_state->src_rect.width = %d;\n" 99 "plane_state->src_rect.height = %d;\n" 100 "plane_state->dst_rect.x = %d;\n" 101 "plane_state->dst_rect.y = %d;\n" 102 "plane_state->dst_rect.width = %d;\n" 103 "plane_state->dst_rect.height = %d;\n" 104 "plane_state->clip_rect.x = %d;\n" 105 "plane_state->clip_rect.y = %d;\n" 106 "plane_state->clip_rect.width = %d;\n" 107 "plane_state->clip_rect.height = %d;\n", 108 plane_state->src_rect.x, 109 plane_state->src_rect.y, 110 plane_state->src_rect.width, 111 plane_state->src_rect.height, 112 plane_state->dst_rect.x, 113 plane_state->dst_rect.y, 114 plane_state->dst_rect.width, 115 plane_state->dst_rect.height, 116 plane_state->clip_rect.x, 117 plane_state->clip_rect.y, 118 plane_state->clip_rect.width, 119 plane_state->clip_rect.height); 120 121 SURFACE_TRACE( 122 "plane_state->plane_size.grph.surface_size.x = %d;\n" 123 "plane_state->plane_size.grph.surface_size.y = %d;\n" 124 "plane_state->plane_size.grph.surface_size.width = %d;\n" 125 "plane_state->plane_size.grph.surface_size.height = %d;\n" 126 "plane_state->plane_size.grph.surface_pitch = %d;\n", 127 plane_state->plane_size.grph.surface_size.x, 128 plane_state->plane_size.grph.surface_size.y, 129 plane_state->plane_size.grph.surface_size.width, 130 plane_state->plane_size.grph.surface_size.height, 131 plane_state->plane_size.grph.surface_pitch); 132 133 134 SURFACE_TRACE( 135 "plane_state->tiling_info.gfx8.num_banks = %d;\n" 136 "plane_state->tiling_info.gfx8.bank_width = %d;\n" 137 "plane_state->tiling_info.gfx8.bank_width_c = %d;\n" 138 "plane_state->tiling_info.gfx8.bank_height = %d;\n" 139 "plane_state->tiling_info.gfx8.bank_height_c = %d;\n" 140 "plane_state->tiling_info.gfx8.tile_aspect = %d;\n" 141 "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n" 142 "plane_state->tiling_info.gfx8.tile_split = %d;\n" 143 "plane_state->tiling_info.gfx8.tile_split_c = %d;\n" 144 "plane_state->tiling_info.gfx8.tile_mode = %d;\n" 145 "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n", 146 plane_state->tiling_info.gfx8.num_banks, 147 plane_state->tiling_info.gfx8.bank_width, 148 plane_state->tiling_info.gfx8.bank_width_c, 149 plane_state->tiling_info.gfx8.bank_height, 150 plane_state->tiling_info.gfx8.bank_height_c, 151 plane_state->tiling_info.gfx8.tile_aspect, 152 plane_state->tiling_info.gfx8.tile_aspect_c, 153 plane_state->tiling_info.gfx8.tile_split, 154 plane_state->tiling_info.gfx8.tile_split_c, 155 plane_state->tiling_info.gfx8.tile_mode, 156 plane_state->tiling_info.gfx8.tile_mode_c); 157 158 SURFACE_TRACE( 159 "plane_state->tiling_info.gfx8.pipe_config = %d;\n" 160 "plane_state->tiling_info.gfx8.array_mode = %d;\n" 161 "plane_state->color_space = %d;\n" 162 "plane_state->input_tf = %d;\n" 163 "plane_state->dcc.enable = %d;\n" 164 "plane_state->format = %d;\n" 165 "plane_state->rotation = %d;\n" 166 "plane_state->stereo_format = %d;\n", 167 plane_state->tiling_info.gfx8.pipe_config, 168 plane_state->tiling_info.gfx8.array_mode, 169 plane_state->color_space, 170 plane_state->input_tf, 171 plane_state->dcc.enable, 172 plane_state->format, 173 plane_state->rotation, 174 plane_state->stereo_format); 175 176 SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n", 177 plane_state->tiling_info.gfx9.swizzle); 178 179 SURFACE_TRACE("\n"); 180 } 181 SURFACE_TRACE("\n"); 182 } 183 184 void update_surface_trace( 185 struct dc *dc, 186 const struct dc_surface_update *updates, 187 int surface_count) 188 { 189 int i; 190 struct dc *core_dc = dc; 191 struct dal_logger *logger = core_dc->ctx->logger; 192 193 for (i = 0; i < surface_count; i++) { 194 const struct dc_surface_update *update = &updates[i]; 195 196 SURFACE_TRACE("Update %d\n", i); 197 if (update->flip_addr) { 198 SURFACE_TRACE("flip_addr->address.type = %d;\n" 199 "flip_addr->address.grph.addr.quad_part = 0x%X;\n" 200 "flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n" 201 "flip_addr->flip_immediate = %d;\n", 202 update->flip_addr->address.type, 203 update->flip_addr->address.grph.addr.quad_part, 204 update->flip_addr->address.grph.meta_addr.quad_part, 205 update->flip_addr->flip_immediate); 206 } 207 208 if (update->plane_info) { 209 SURFACE_TRACE( 210 "plane_info->color_space = %d;\n" 211 "plane_info->input_tf = %d;\n" 212 "plane_info->format = %d;\n" 213 "plane_info->plane_size.grph.surface_pitch = %d;\n" 214 "plane_info->plane_size.grph.surface_size.height = %d;\n" 215 "plane_info->plane_size.grph.surface_size.width = %d;\n" 216 "plane_info->plane_size.grph.surface_size.x = %d;\n" 217 "plane_info->plane_size.grph.surface_size.y = %d;\n" 218 "plane_info->rotation = %d;\n", 219 update->plane_info->color_space, 220 update->plane_info->input_tf, 221 update->plane_info->format, 222 update->plane_info->plane_size.grph.surface_pitch, 223 update->plane_info->plane_size.grph.surface_size.height, 224 update->plane_info->plane_size.grph.surface_size.width, 225 update->plane_info->plane_size.grph.surface_size.x, 226 update->plane_info->plane_size.grph.surface_size.y, 227 update->plane_info->rotation, 228 update->plane_info->stereo_format); 229 230 SURFACE_TRACE( 231 "plane_info->tiling_info.gfx8.num_banks = %d;\n" 232 "plane_info->tiling_info.gfx8.bank_width = %d;\n" 233 "plane_info->tiling_info.gfx8.bank_width_c = %d;\n" 234 "plane_info->tiling_info.gfx8.bank_height = %d;\n" 235 "plane_info->tiling_info.gfx8.bank_height_c = %d;\n" 236 "plane_info->tiling_info.gfx8.tile_aspect = %d;\n" 237 "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n" 238 "plane_info->tiling_info.gfx8.tile_split = %d;\n" 239 "plane_info->tiling_info.gfx8.tile_split_c = %d;\n" 240 "plane_info->tiling_info.gfx8.tile_mode = %d;\n" 241 "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n", 242 update->plane_info->tiling_info.gfx8.num_banks, 243 update->plane_info->tiling_info.gfx8.bank_width, 244 update->plane_info->tiling_info.gfx8.bank_width_c, 245 update->plane_info->tiling_info.gfx8.bank_height, 246 update->plane_info->tiling_info.gfx8.bank_height_c, 247 update->plane_info->tiling_info.gfx8.tile_aspect, 248 update->plane_info->tiling_info.gfx8.tile_aspect_c, 249 update->plane_info->tiling_info.gfx8.tile_split, 250 update->plane_info->tiling_info.gfx8.tile_split_c, 251 update->plane_info->tiling_info.gfx8.tile_mode, 252 update->plane_info->tiling_info.gfx8.tile_mode_c); 253 254 SURFACE_TRACE( 255 "plane_info->tiling_info.gfx8.pipe_config = %d;\n" 256 "plane_info->tiling_info.gfx8.array_mode = %d;\n" 257 "plane_info->visible = %d;\n" 258 "plane_info->per_pixel_alpha = %d;\n", 259 update->plane_info->tiling_info.gfx8.pipe_config, 260 update->plane_info->tiling_info.gfx8.array_mode, 261 update->plane_info->visible, 262 update->plane_info->per_pixel_alpha); 263 264 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", 265 update->plane_info->tiling_info.gfx9.swizzle); 266 } 267 268 if (update->scaling_info) { 269 SURFACE_TRACE( 270 "scaling_info->src_rect.x = %d;\n" 271 "scaling_info->src_rect.y = %d;\n" 272 "scaling_info->src_rect.width = %d;\n" 273 "scaling_info->src_rect.height = %d;\n" 274 "scaling_info->dst_rect.x = %d;\n" 275 "scaling_info->dst_rect.y = %d;\n" 276 "scaling_info->dst_rect.width = %d;\n" 277 "scaling_info->dst_rect.height = %d;\n" 278 "scaling_info->clip_rect.x = %d;\n" 279 "scaling_info->clip_rect.y = %d;\n" 280 "scaling_info->clip_rect.width = %d;\n" 281 "scaling_info->clip_rect.height = %d;\n" 282 "scaling_info->scaling_quality.h_taps = %d;\n" 283 "scaling_info->scaling_quality.v_taps = %d;\n" 284 "scaling_info->scaling_quality.h_taps_c = %d;\n" 285 "scaling_info->scaling_quality.v_taps_c = %d;\n", 286 update->scaling_info->src_rect.x, 287 update->scaling_info->src_rect.y, 288 update->scaling_info->src_rect.width, 289 update->scaling_info->src_rect.height, 290 update->scaling_info->dst_rect.x, 291 update->scaling_info->dst_rect.y, 292 update->scaling_info->dst_rect.width, 293 update->scaling_info->dst_rect.height, 294 update->scaling_info->clip_rect.x, 295 update->scaling_info->clip_rect.y, 296 update->scaling_info->clip_rect.width, 297 update->scaling_info->clip_rect.height, 298 update->scaling_info->scaling_quality.h_taps, 299 update->scaling_info->scaling_quality.v_taps, 300 update->scaling_info->scaling_quality.h_taps_c, 301 update->scaling_info->scaling_quality.v_taps_c); 302 } 303 SURFACE_TRACE("\n"); 304 } 305 SURFACE_TRACE("\n"); 306 } 307 308 void post_surface_trace(struct dc *dc) 309 { 310 struct dc *core_dc = dc; 311 struct dal_logger *logger = core_dc->ctx->logger; 312 313 SURFACE_TRACE("post surface process.\n"); 314 315 } 316 317 void context_timing_trace( 318 struct dc *dc, 319 struct resource_context *res_ctx) 320 { 321 int i; 322 struct dc *core_dc = dc; 323 struct dal_logger *logger = core_dc->ctx->logger; 324 int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; 325 struct crtc_position position; 326 unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index; 327 328 329 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { 330 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 331 /* get_position() returns CRTC vertical/horizontal counter 332 * hence not applicable for underlay pipe 333 */ 334 if (pipe_ctx->stream == NULL 335 || pipe_ctx->pipe_idx == underlay_idx) 336 continue; 337 338 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position); 339 h_pos[i] = position.horizontal_count; 340 v_pos[i] = position.vertical_count; 341 } 342 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { 343 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 344 345 if (pipe_ctx->stream == NULL) 346 continue; 347 348 TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n", 349 pipe_ctx->stream_res.tg->inst, 350 pipe_ctx->stream->timing.h_total, 351 pipe_ctx->stream->timing.v_total, 352 h_pos[i], v_pos[i]); 353 } 354 } 355 356 void context_clock_trace( 357 struct dc *dc, 358 struct dc_state *context) 359 { 360 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 361 struct dc *core_dc = dc; 362 struct dal_logger *logger = core_dc->ctx->logger; 363 364 CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" 365 "dcfclk_deep_sleep_khz:%d fclk_khz:%d\n" 366 "dram_ccm_us:%d min_active_dram_ccm_us:%d\n", 367 context->bw.dcn.calc_clk.dispclk_khz, 368 context->bw.dcn.calc_clk.dppclk_div, 369 context->bw.dcn.calc_clk.dcfclk_khz, 370 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz, 371 context->bw.dcn.calc_clk.fclk_khz, 372 context->bw.dcn.calc_clk.dram_ccm_us, 373 context->bw.dcn.calc_clk.min_active_dram_ccm_us); 374 CLOCK_TRACE("Calculated: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" 375 "dcfclk_deep_sleep_khz:%d fclk_khz:%d\n" 376 "dram_ccm_us:%d min_active_dram_ccm_us:%d\n", 377 context->bw.dcn.calc_clk.dispclk_khz, 378 context->bw.dcn.calc_clk.dppclk_div, 379 context->bw.dcn.calc_clk.dcfclk_khz, 380 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz, 381 context->bw.dcn.calc_clk.fclk_khz, 382 context->bw.dcn.calc_clk.dram_ccm_us, 383 context->bw.dcn.calc_clk.min_active_dram_ccm_us); 384 #endif 385 } 386