1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 /* 24 * dc_debug.c 25 * 26 * Created on: Nov 3, 2016 27 * Author: yonsun 28 */ 29 30 #include "dm_services.h" 31 32 #include "dc.h" 33 34 #include "core_status.h" 35 #include "core_types.h" 36 #include "hw_sequencer.h" 37 38 #include "resource.h" 39 #define DC_LOGGER \ 40 logger 41 42 #define SURFACE_TRACE(...) do {\ 43 if (dc->debug.surface_trace) \ 44 DC_LOG_IF_TRACE(__VA_ARGS__); \ 45 } while (0) 46 47 #define TIMING_TRACE(...) do {\ 48 if (dc->debug.timing_trace) \ 49 DC_LOG_SYNC(__VA_ARGS__); \ 50 } while (0) 51 52 #define CLOCK_TRACE(...) do {\ 53 if (dc->debug.clock_trace) \ 54 DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \ 55 } while (0) 56 57 void pre_surface_trace( 58 struct dc *dc, 59 const struct dc_plane_state *const *plane_states, 60 int surface_count) 61 { 62 int i; 63 struct dc *core_dc = dc; 64 struct dal_logger *logger = core_dc->ctx->logger; 65 66 for (i = 0; i < surface_count; i++) { 67 const struct dc_plane_state *plane_state = plane_states[i]; 68 69 SURFACE_TRACE("Planes %d:\n", i); 70 71 SURFACE_TRACE( 72 "plane_state->visible = %d;\n" 73 "plane_state->flip_immediate = %d;\n" 74 "plane_state->address.type = %d;\n" 75 "plane_state->address.grph.addr.quad_part = 0x%llX;\n" 76 "plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n" 77 "plane_state->scaling_quality.h_taps = %d;\n" 78 "plane_state->scaling_quality.v_taps = %d;\n" 79 "plane_state->scaling_quality.h_taps_c = %d;\n" 80 "plane_state->scaling_quality.v_taps_c = %d;\n", 81 plane_state->visible, 82 plane_state->flip_immediate, 83 plane_state->address.type, 84 plane_state->address.grph.addr.quad_part, 85 plane_state->address.grph.meta_addr.quad_part, 86 plane_state->scaling_quality.h_taps, 87 plane_state->scaling_quality.v_taps, 88 plane_state->scaling_quality.h_taps_c, 89 plane_state->scaling_quality.v_taps_c); 90 91 SURFACE_TRACE( 92 "plane_state->src_rect.x = %d;\n" 93 "plane_state->src_rect.y = %d;\n" 94 "plane_state->src_rect.width = %d;\n" 95 "plane_state->src_rect.height = %d;\n" 96 "plane_state->dst_rect.x = %d;\n" 97 "plane_state->dst_rect.y = %d;\n" 98 "plane_state->dst_rect.width = %d;\n" 99 "plane_state->dst_rect.height = %d;\n" 100 "plane_state->clip_rect.x = %d;\n" 101 "plane_state->clip_rect.y = %d;\n" 102 "plane_state->clip_rect.width = %d;\n" 103 "plane_state->clip_rect.height = %d;\n", 104 plane_state->src_rect.x, 105 plane_state->src_rect.y, 106 plane_state->src_rect.width, 107 plane_state->src_rect.height, 108 plane_state->dst_rect.x, 109 plane_state->dst_rect.y, 110 plane_state->dst_rect.width, 111 plane_state->dst_rect.height, 112 plane_state->clip_rect.x, 113 plane_state->clip_rect.y, 114 plane_state->clip_rect.width, 115 plane_state->clip_rect.height); 116 117 SURFACE_TRACE( 118 "plane_state->plane_size.grph.surface_size.x = %d;\n" 119 "plane_state->plane_size.grph.surface_size.y = %d;\n" 120 "plane_state->plane_size.grph.surface_size.width = %d;\n" 121 "plane_state->plane_size.grph.surface_size.height = %d;\n" 122 "plane_state->plane_size.grph.surface_pitch = %d;\n", 123 plane_state->plane_size.grph.surface_size.x, 124 plane_state->plane_size.grph.surface_size.y, 125 plane_state->plane_size.grph.surface_size.width, 126 plane_state->plane_size.grph.surface_size.height, 127 plane_state->plane_size.grph.surface_pitch); 128 129 130 SURFACE_TRACE( 131 "plane_state->tiling_info.gfx8.num_banks = %d;\n" 132 "plane_state->tiling_info.gfx8.bank_width = %d;\n" 133 "plane_state->tiling_info.gfx8.bank_width_c = %d;\n" 134 "plane_state->tiling_info.gfx8.bank_height = %d;\n" 135 "plane_state->tiling_info.gfx8.bank_height_c = %d;\n" 136 "plane_state->tiling_info.gfx8.tile_aspect = %d;\n" 137 "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n" 138 "plane_state->tiling_info.gfx8.tile_split = %d;\n" 139 "plane_state->tiling_info.gfx8.tile_split_c = %d;\n" 140 "plane_state->tiling_info.gfx8.tile_mode = %d;\n" 141 "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n", 142 plane_state->tiling_info.gfx8.num_banks, 143 plane_state->tiling_info.gfx8.bank_width, 144 plane_state->tiling_info.gfx8.bank_width_c, 145 plane_state->tiling_info.gfx8.bank_height, 146 plane_state->tiling_info.gfx8.bank_height_c, 147 plane_state->tiling_info.gfx8.tile_aspect, 148 plane_state->tiling_info.gfx8.tile_aspect_c, 149 plane_state->tiling_info.gfx8.tile_split, 150 plane_state->tiling_info.gfx8.tile_split_c, 151 plane_state->tiling_info.gfx8.tile_mode, 152 plane_state->tiling_info.gfx8.tile_mode_c); 153 154 SURFACE_TRACE( 155 "plane_state->tiling_info.gfx8.pipe_config = %d;\n" 156 "plane_state->tiling_info.gfx8.array_mode = %d;\n" 157 "plane_state->color_space = %d;\n" 158 "plane_state->input_tf = %d;\n" 159 "plane_state->dcc.enable = %d;\n" 160 "plane_state->format = %d;\n" 161 "plane_state->rotation = %d;\n" 162 "plane_state->stereo_format = %d;\n", 163 plane_state->tiling_info.gfx8.pipe_config, 164 plane_state->tiling_info.gfx8.array_mode, 165 plane_state->color_space, 166 plane_state->input_tf, 167 plane_state->dcc.enable, 168 plane_state->format, 169 plane_state->rotation, 170 plane_state->stereo_format); 171 172 SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n", 173 plane_state->tiling_info.gfx9.swizzle); 174 175 SURFACE_TRACE("\n"); 176 } 177 SURFACE_TRACE("\n"); 178 } 179 180 void update_surface_trace( 181 struct dc *dc, 182 const struct dc_surface_update *updates, 183 int surface_count) 184 { 185 int i; 186 struct dc *core_dc = dc; 187 struct dal_logger *logger = core_dc->ctx->logger; 188 189 for (i = 0; i < surface_count; i++) { 190 const struct dc_surface_update *update = &updates[i]; 191 192 SURFACE_TRACE("Update %d\n", i); 193 if (update->flip_addr) { 194 SURFACE_TRACE("flip_addr->address.type = %d;\n" 195 "flip_addr->address.grph.addr.quad_part = 0x%llX;\n" 196 "flip_addr->address.grph.meta_addr.quad_part = 0x%llX;\n" 197 "flip_addr->flip_immediate = %d;\n", 198 update->flip_addr->address.type, 199 update->flip_addr->address.grph.addr.quad_part, 200 update->flip_addr->address.grph.meta_addr.quad_part, 201 update->flip_addr->flip_immediate); 202 } 203 204 if (update->plane_info) { 205 SURFACE_TRACE( 206 "plane_info->color_space = %d;\n" 207 "plane_info->input_tf = %d;\n" 208 "plane_info->format = %d;\n" 209 "plane_info->plane_size.grph.surface_pitch = %d;\n" 210 "plane_info->plane_size.grph.surface_size.height = %d;\n" 211 "plane_info->plane_size.grph.surface_size.width = %d;\n" 212 "plane_info->plane_size.grph.surface_size.x = %d;\n" 213 "plane_info->plane_size.grph.surface_size.y = %d;\n" 214 "plane_info->rotation = %d;\n" 215 "plane_info->stereo_format = %d;\n", 216 update->plane_info->color_space, 217 update->plane_info->input_tf, 218 update->plane_info->format, 219 update->plane_info->plane_size.grph.surface_pitch, 220 update->plane_info->plane_size.grph.surface_size.height, 221 update->plane_info->plane_size.grph.surface_size.width, 222 update->plane_info->plane_size.grph.surface_size.x, 223 update->plane_info->plane_size.grph.surface_size.y, 224 update->plane_info->rotation, 225 update->plane_info->stereo_format); 226 227 SURFACE_TRACE( 228 "plane_info->tiling_info.gfx8.num_banks = %d;\n" 229 "plane_info->tiling_info.gfx8.bank_width = %d;\n" 230 "plane_info->tiling_info.gfx8.bank_width_c = %d;\n" 231 "plane_info->tiling_info.gfx8.bank_height = %d;\n" 232 "plane_info->tiling_info.gfx8.bank_height_c = %d;\n" 233 "plane_info->tiling_info.gfx8.tile_aspect = %d;\n" 234 "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n" 235 "plane_info->tiling_info.gfx8.tile_split = %d;\n" 236 "plane_info->tiling_info.gfx8.tile_split_c = %d;\n" 237 "plane_info->tiling_info.gfx8.tile_mode = %d;\n" 238 "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n", 239 update->plane_info->tiling_info.gfx8.num_banks, 240 update->plane_info->tiling_info.gfx8.bank_width, 241 update->plane_info->tiling_info.gfx8.bank_width_c, 242 update->plane_info->tiling_info.gfx8.bank_height, 243 update->plane_info->tiling_info.gfx8.bank_height_c, 244 update->plane_info->tiling_info.gfx8.tile_aspect, 245 update->plane_info->tiling_info.gfx8.tile_aspect_c, 246 update->plane_info->tiling_info.gfx8.tile_split, 247 update->plane_info->tiling_info.gfx8.tile_split_c, 248 update->plane_info->tiling_info.gfx8.tile_mode, 249 update->plane_info->tiling_info.gfx8.tile_mode_c); 250 251 SURFACE_TRACE( 252 "plane_info->tiling_info.gfx8.pipe_config = %d;\n" 253 "plane_info->tiling_info.gfx8.array_mode = %d;\n" 254 "plane_info->visible = %d;\n" 255 "plane_info->per_pixel_alpha = %d;\n", 256 update->plane_info->tiling_info.gfx8.pipe_config, 257 update->plane_info->tiling_info.gfx8.array_mode, 258 update->plane_info->visible, 259 update->plane_info->per_pixel_alpha); 260 261 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", 262 update->plane_info->tiling_info.gfx9.swizzle); 263 } 264 265 if (update->scaling_info) { 266 SURFACE_TRACE( 267 "scaling_info->src_rect.x = %d;\n" 268 "scaling_info->src_rect.y = %d;\n" 269 "scaling_info->src_rect.width = %d;\n" 270 "scaling_info->src_rect.height = %d;\n" 271 "scaling_info->dst_rect.x = %d;\n" 272 "scaling_info->dst_rect.y = %d;\n" 273 "scaling_info->dst_rect.width = %d;\n" 274 "scaling_info->dst_rect.height = %d;\n" 275 "scaling_info->clip_rect.x = %d;\n" 276 "scaling_info->clip_rect.y = %d;\n" 277 "scaling_info->clip_rect.width = %d;\n" 278 "scaling_info->clip_rect.height = %d;\n" 279 "scaling_info->scaling_quality.h_taps = %d;\n" 280 "scaling_info->scaling_quality.v_taps = %d;\n" 281 "scaling_info->scaling_quality.h_taps_c = %d;\n" 282 "scaling_info->scaling_quality.v_taps_c = %d;\n", 283 update->scaling_info->src_rect.x, 284 update->scaling_info->src_rect.y, 285 update->scaling_info->src_rect.width, 286 update->scaling_info->src_rect.height, 287 update->scaling_info->dst_rect.x, 288 update->scaling_info->dst_rect.y, 289 update->scaling_info->dst_rect.width, 290 update->scaling_info->dst_rect.height, 291 update->scaling_info->clip_rect.x, 292 update->scaling_info->clip_rect.y, 293 update->scaling_info->clip_rect.width, 294 update->scaling_info->clip_rect.height, 295 update->scaling_info->scaling_quality.h_taps, 296 update->scaling_info->scaling_quality.v_taps, 297 update->scaling_info->scaling_quality.h_taps_c, 298 update->scaling_info->scaling_quality.v_taps_c); 299 } 300 SURFACE_TRACE("\n"); 301 } 302 SURFACE_TRACE("\n"); 303 } 304 305 void post_surface_trace(struct dc *dc) 306 { 307 struct dc *core_dc = dc; 308 struct dal_logger *logger = core_dc->ctx->logger; 309 310 SURFACE_TRACE("post surface process.\n"); 311 312 } 313 314 void context_timing_trace( 315 struct dc *dc, 316 struct resource_context *res_ctx) 317 { 318 int i; 319 struct dc *core_dc = dc; 320 struct dal_logger *logger = core_dc->ctx->logger; 321 int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; 322 struct crtc_position position; 323 unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index; 324 325 326 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { 327 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 328 /* get_position() returns CRTC vertical/horizontal counter 329 * hence not applicable for underlay pipe 330 */ 331 if (pipe_ctx->stream == NULL 332 || pipe_ctx->pipe_idx == underlay_idx) 333 continue; 334 335 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position); 336 h_pos[i] = position.horizontal_count; 337 v_pos[i] = position.vertical_count; 338 } 339 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { 340 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 341 342 if (pipe_ctx->stream == NULL) 343 continue; 344 345 TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n", 346 pipe_ctx->stream_res.tg->inst, 347 pipe_ctx->stream->timing.h_total, 348 pipe_ctx->stream->timing.v_total, 349 h_pos[i], v_pos[i]); 350 } 351 } 352 353 void context_clock_trace( 354 struct dc *dc, 355 struct dc_state *context) 356 { 357 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 358 struct dc *core_dc = dc; 359 struct dal_logger *logger = core_dc->ctx->logger; 360 361 CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n" 362 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n", 363 context->bw.dcn.calc_clk.dispclk_khz, 364 context->bw.dcn.calc_clk.dppclk_khz, 365 context->bw.dcn.calc_clk.dcfclk_khz, 366 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz, 367 context->bw.dcn.calc_clk.fclk_khz, 368 context->bw.dcn.calc_clk.socclk_khz); 369 CLOCK_TRACE("Calculated: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n" 370 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n", 371 context->bw.dcn.calc_clk.dispclk_khz, 372 context->bw.dcn.calc_clk.dppclk_khz, 373 context->bw.dcn.calc_clk.dcfclk_khz, 374 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz, 375 context->bw.dcn.calc_clk.fclk_khz, 376 context->bw.dcn.calc_clk.socclk_khz); 377 #endif 378 } 379