1 /* 2 * dc_debug.c 3 * 4 * Created on: Nov 3, 2016 5 * Author: yonsun 6 */ 7 8 #include "dm_services.h" 9 10 #include "dc.h" 11 12 #include "core_status.h" 13 #include "core_types.h" 14 #include "hw_sequencer.h" 15 16 #include "resource.h" 17 18 #define SURFACE_TRACE(...) do {\ 19 if (dc->debug.surface_trace) \ 20 dm_logger_write(logger, \ 21 LOG_IF_TRACE, \ 22 ##__VA_ARGS__); \ 23 } while (0) 24 25 #define TIMING_TRACE(...) do {\ 26 if (dc->debug.timing_trace) \ 27 dm_logger_write(logger, \ 28 LOG_SYNC, \ 29 ##__VA_ARGS__); \ 30 } while (0) 31 32 void pre_surface_trace( 33 const struct dc *dc, 34 const struct dc_surface *const *surfaces, 35 int surface_count) 36 { 37 int i; 38 struct core_dc *core_dc = DC_TO_CORE(dc); 39 struct dal_logger *logger = core_dc->ctx->logger; 40 41 for (i = 0; i < surface_count; i++) { 42 const struct dc_surface *surface = surfaces[i]; 43 44 SURFACE_TRACE("Surface %d:\n", i); 45 46 SURFACE_TRACE( 47 "surface->visible = %d;\n" 48 "surface->flip_immediate = %d;\n" 49 "surface->address.type = %d;\n" 50 "surface->address.grph.addr.quad_part = 0x%X;\n" 51 "surface->address.grph.meta_addr.quad_part = 0x%X;\n" 52 "surface->scaling_quality.h_taps = %d;\n" 53 "surface->scaling_quality.v_taps = %d;\n" 54 "surface->scaling_quality.h_taps_c = %d;\n" 55 "surface->scaling_quality.v_taps_c = %d;\n", 56 surface->visible, 57 surface->flip_immediate, 58 surface->address.type, 59 surface->address.grph.addr.quad_part, 60 surface->address.grph.meta_addr.quad_part, 61 surface->scaling_quality.h_taps, 62 surface->scaling_quality.v_taps, 63 surface->scaling_quality.h_taps_c, 64 surface->scaling_quality.v_taps_c); 65 66 SURFACE_TRACE( 67 "surface->src_rect.x = %d;\n" 68 "surface->src_rect.y = %d;\n" 69 "surface->src_rect.width = %d;\n" 70 "surface->src_rect.height = %d;\n" 71 "surface->dst_rect.x = %d;\n" 72 "surface->dst_rect.y = %d;\n" 73 "surface->dst_rect.width = %d;\n" 74 "surface->dst_rect.height = %d;\n" 75 "surface->clip_rect.x = %d;\n" 76 "surface->clip_rect.y = %d;\n" 77 "surface->clip_rect.width = %d;\n" 78 "surface->clip_rect.height = %d;\n", 79 surface->src_rect.x, 80 surface->src_rect.y, 81 surface->src_rect.width, 82 surface->src_rect.height, 83 surface->dst_rect.x, 84 surface->dst_rect.y, 85 surface->dst_rect.width, 86 surface->dst_rect.height, 87 surface->clip_rect.x, 88 surface->clip_rect.y, 89 surface->clip_rect.width, 90 surface->clip_rect.height); 91 92 SURFACE_TRACE( 93 "surface->plane_size.grph.surface_size.x = %d;\n" 94 "surface->plane_size.grph.surface_size.y = %d;\n" 95 "surface->plane_size.grph.surface_size.width = %d;\n" 96 "surface->plane_size.grph.surface_size.height = %d;\n" 97 "surface->plane_size.grph.surface_pitch = %d;\n", 98 surface->plane_size.grph.surface_size.x, 99 surface->plane_size.grph.surface_size.y, 100 surface->plane_size.grph.surface_size.width, 101 surface->plane_size.grph.surface_size.height, 102 surface->plane_size.grph.surface_pitch); 103 104 105 SURFACE_TRACE( 106 "surface->tiling_info.gfx8.num_banks = %d;\n" 107 "surface->tiling_info.gfx8.bank_width = %d;\n" 108 "surface->tiling_info.gfx8.bank_width_c = %d;\n" 109 "surface->tiling_info.gfx8.bank_height = %d;\n" 110 "surface->tiling_info.gfx8.bank_height_c = %d;\n" 111 "surface->tiling_info.gfx8.tile_aspect = %d;\n" 112 "surface->tiling_info.gfx8.tile_aspect_c = %d;\n" 113 "surface->tiling_info.gfx8.tile_split = %d;\n" 114 "surface->tiling_info.gfx8.tile_split_c = %d;\n" 115 "surface->tiling_info.gfx8.tile_mode = %d;\n" 116 "surface->tiling_info.gfx8.tile_mode_c = %d;\n", 117 surface->tiling_info.gfx8.num_banks, 118 surface->tiling_info.gfx8.bank_width, 119 surface->tiling_info.gfx8.bank_width_c, 120 surface->tiling_info.gfx8.bank_height, 121 surface->tiling_info.gfx8.bank_height_c, 122 surface->tiling_info.gfx8.tile_aspect, 123 surface->tiling_info.gfx8.tile_aspect_c, 124 surface->tiling_info.gfx8.tile_split, 125 surface->tiling_info.gfx8.tile_split_c, 126 surface->tiling_info.gfx8.tile_mode, 127 surface->tiling_info.gfx8.tile_mode_c); 128 129 SURFACE_TRACE( 130 "surface->tiling_info.gfx8.pipe_config = %d;\n" 131 "surface->tiling_info.gfx8.array_mode = %d;\n" 132 "surface->color_space = %d;\n" 133 "surface->dcc.enable = %d;\n" 134 "surface->format = %d;\n" 135 "surface->rotation = %d;\n" 136 "surface->stereo_format = %d;\n", 137 surface->tiling_info.gfx8.pipe_config, 138 surface->tiling_info.gfx8.array_mode, 139 surface->color_space, 140 surface->dcc.enable, 141 surface->format, 142 surface->rotation, 143 surface->stereo_format); 144 145 #if defined (CONFIG_DRM_AMD_DC_DCE12_0) 146 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", 147 surface->tiling_info.gfx9.swizzle); 148 #endif 149 150 SURFACE_TRACE("\n"); 151 } 152 SURFACE_TRACE("\n"); 153 } 154 155 void update_surface_trace( 156 const struct dc *dc, 157 const struct dc_surface_update *updates, 158 int surface_count) 159 { 160 int i; 161 struct core_dc *core_dc = DC_TO_CORE(dc); 162 struct dal_logger *logger = core_dc->ctx->logger; 163 164 for (i = 0; i < surface_count; i++) { 165 const struct dc_surface_update *update = &updates[i]; 166 167 SURFACE_TRACE("Update %d\n", i); 168 if (update->flip_addr) { 169 SURFACE_TRACE("flip_addr->address.type = %d;\n" 170 "flip_addr->address.grph.addr.quad_part = 0x%X;\n" 171 "flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n" 172 "flip_addr->flip_immediate = %d;\n", 173 update->flip_addr->address.type, 174 update->flip_addr->address.grph.addr.quad_part, 175 update->flip_addr->address.grph.meta_addr.quad_part, 176 update->flip_addr->flip_immediate); 177 } 178 179 if (update->plane_info) { 180 SURFACE_TRACE( 181 "plane_info->color_space = %d;\n" 182 "plane_info->format = %d;\n" 183 "plane_info->plane_size.grph.surface_pitch = %d;\n" 184 "plane_info->plane_size.grph.surface_size.height = %d;\n" 185 "plane_info->plane_size.grph.surface_size.width = %d;\n" 186 "plane_info->plane_size.grph.surface_size.x = %d;\n" 187 "plane_info->plane_size.grph.surface_size.y = %d;\n" 188 "plane_info->rotation = %d;\n", 189 update->plane_info->color_space, 190 update->plane_info->format, 191 update->plane_info->plane_size.grph.surface_pitch, 192 update->plane_info->plane_size.grph.surface_size.height, 193 update->plane_info->plane_size.grph.surface_size.width, 194 update->plane_info->plane_size.grph.surface_size.x, 195 update->plane_info->plane_size.grph.surface_size.y, 196 update->plane_info->rotation, 197 update->plane_info->stereo_format); 198 199 SURFACE_TRACE( 200 "plane_info->tiling_info.gfx8.num_banks = %d;\n" 201 "plane_info->tiling_info.gfx8.bank_width = %d;\n" 202 "plane_info->tiling_info.gfx8.bank_width_c = %d;\n" 203 "plane_info->tiling_info.gfx8.bank_height = %d;\n" 204 "plane_info->tiling_info.gfx8.bank_height_c = %d;\n" 205 "plane_info->tiling_info.gfx8.tile_aspect = %d;\n" 206 "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n" 207 "plane_info->tiling_info.gfx8.tile_split = %d;\n" 208 "plane_info->tiling_info.gfx8.tile_split_c = %d;\n" 209 "plane_info->tiling_info.gfx8.tile_mode = %d;\n" 210 "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n", 211 update->plane_info->tiling_info.gfx8.num_banks, 212 update->plane_info->tiling_info.gfx8.bank_width, 213 update->plane_info->tiling_info.gfx8.bank_width_c, 214 update->plane_info->tiling_info.gfx8.bank_height, 215 update->plane_info->tiling_info.gfx8.bank_height_c, 216 update->plane_info->tiling_info.gfx8.tile_aspect, 217 update->plane_info->tiling_info.gfx8.tile_aspect_c, 218 update->plane_info->tiling_info.gfx8.tile_split, 219 update->plane_info->tiling_info.gfx8.tile_split_c, 220 update->plane_info->tiling_info.gfx8.tile_mode, 221 update->plane_info->tiling_info.gfx8.tile_mode_c); 222 223 SURFACE_TRACE( 224 "plane_info->tiling_info.gfx8.pipe_config = %d;\n" 225 "plane_info->tiling_info.gfx8.array_mode = %d;\n" 226 "plane_info->visible = %d;\n", 227 update->plane_info->tiling_info.gfx8.pipe_config, 228 update->plane_info->tiling_info.gfx8.array_mode, 229 update->plane_info->visible); 230 231 #if defined (CONFIG_DRM_AMD_DC_DCE12_0) 232 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", 233 update->plane_info->tiling_info.gfx9.swizzle); 234 #endif 235 } 236 237 if (update->scaling_info) { 238 SURFACE_TRACE( 239 "scaling_info->src_rect.x = %d;\n" 240 "scaling_info->src_rect.y = %d;\n" 241 "scaling_info->src_rect.width = %d;\n" 242 "scaling_info->src_rect.height = %d;\n" 243 "scaling_info->dst_rect.x = %d;\n" 244 "scaling_info->dst_rect.y = %d;\n" 245 "scaling_info->dst_rect.width = %d;\n" 246 "scaling_info->dst_rect.height = %d;\n" 247 "scaling_info->clip_rect.x = %d;\n" 248 "scaling_info->clip_rect.y = %d;\n" 249 "scaling_info->clip_rect.width = %d;\n" 250 "scaling_info->clip_rect.height = %d;\n" 251 "scaling_info->scaling_quality.h_taps = %d;\n" 252 "scaling_info->scaling_quality.v_taps = %d;\n" 253 "scaling_info->scaling_quality.h_taps_c = %d;\n" 254 "scaling_info->scaling_quality.v_taps_c = %d;\n", 255 update->scaling_info->src_rect.x, 256 update->scaling_info->src_rect.y, 257 update->scaling_info->src_rect.width, 258 update->scaling_info->src_rect.height, 259 update->scaling_info->dst_rect.x, 260 update->scaling_info->dst_rect.y, 261 update->scaling_info->dst_rect.width, 262 update->scaling_info->dst_rect.height, 263 update->scaling_info->clip_rect.x, 264 update->scaling_info->clip_rect.y, 265 update->scaling_info->clip_rect.width, 266 update->scaling_info->clip_rect.height, 267 update->scaling_info->scaling_quality.h_taps, 268 update->scaling_info->scaling_quality.v_taps, 269 update->scaling_info->scaling_quality.h_taps_c, 270 update->scaling_info->scaling_quality.v_taps_c); 271 } 272 SURFACE_TRACE("\n"); 273 } 274 SURFACE_TRACE("\n"); 275 } 276 277 void post_surface_trace(const struct dc *dc) 278 { 279 struct core_dc *core_dc = DC_TO_CORE(dc); 280 struct dal_logger *logger = core_dc->ctx->logger; 281 282 SURFACE_TRACE("post surface process.\n"); 283 284 } 285 286 void context_timing_trace( 287 const struct dc *dc, 288 struct resource_context *res_ctx) 289 { 290 int i; 291 struct core_dc *core_dc = DC_TO_CORE(dc); 292 struct dal_logger *logger = core_dc->ctx->logger; 293 int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; 294 295 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { 296 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 297 298 if (pipe_ctx->stream == NULL) 299 continue; 300 301 pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &h_pos[i], &v_pos[i]); 302 } 303 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { 304 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 305 306 if (pipe_ctx->stream == NULL) 307 continue; 308 309 TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n", 310 pipe_ctx->tg->inst, 311 pipe_ctx->stream->public.timing.h_total, 312 pipe_ctx->stream->public.timing.v_total, 313 h_pos[i], v_pos[i]); 314 } 315 } 316