1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v6_1.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu.h" 26 27 #include "rsmu/rsmu_0_0_2_offset.h" 28 #include "rsmu/rsmu_0_0_2_sh_mask.h" 29 #include "umc/umc_6_1_1_offset.h" 30 #include "umc/umc_6_1_1_sh_mask.h" 31 #include "umc/umc_6_1_2_offset.h" 32 33 #define smnMCA_UMC0_MCUMC_ADDRT0 0x50f10 34 35 #define UMC_6_INST_DIST 0x40000 36 37 /* 38 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr 39 * is the index of 8KB block 40 */ 41 #define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) 42 /* channel index is the index of 256B block */ 43 #define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) 44 /* offset in 256B block */ 45 #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) 46 47 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++) 48 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++) 49 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst)) 50 51 const uint32_t 52 umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = { 53 {2, 18, 11, 27}, {4, 20, 13, 29}, 54 {1, 17, 8, 24}, {7, 23, 14, 30}, 55 {10, 26, 3, 19}, {12, 28, 5, 21}, 56 {9, 25, 0, 16}, {15, 31, 6, 22} 57 }; 58 59 static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev) 60 { 61 WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 62 RSMU_UMC_INDEX_MODE_EN, 0); 63 } 64 65 static inline uint32_t get_umc_6_reg_offset(struct amdgpu_device *adev, 66 uint32_t umc_inst, 67 uint32_t ch_inst) 68 { 69 return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst; 70 } 71 72 static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, 73 uint32_t umc_reg_offset, 74 unsigned long *error_count) 75 { 76 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; 77 uint32_t ecc_err_cnt, ecc_err_cnt_addr; 78 uint64_t mc_umc_status; 79 uint32_t mc_umc_status_addr; 80 81 if (adev->asic_type == CHIP_ARCTURUS) { 82 /* UMC 6_1_2 registers */ 83 ecc_err_cnt_sel_addr = 84 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT); 85 ecc_err_cnt_addr = 86 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT); 87 mc_umc_status_addr = 88 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT); 89 } else { 90 /* UMC 6_1_1 registers */ 91 ecc_err_cnt_sel_addr = 92 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); 93 ecc_err_cnt_addr = 94 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); 95 mc_umc_status_addr = 96 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 97 } 98 99 /* select the lower chip and check the error count */ 100 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); 101 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 102 EccErrCntCsSel, 0); 103 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 104 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); 105 *error_count += 106 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - 107 UMC_V6_1_CE_CNT_INIT); 108 /* clear the lower chip err count */ 109 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); 110 111 /* select the higher chip and check the err counter */ 112 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 113 EccErrCntCsSel, 1); 114 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 115 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); 116 *error_count += 117 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - 118 UMC_V6_1_CE_CNT_INIT); 119 /* clear the higher chip err count */ 120 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); 121 122 /* check for SRAM correctable error 123 MCUMC_STATUS is a 64 bit register */ 124 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 125 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && 126 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 127 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) 128 *error_count += 1; 129 } 130 131 static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev, 132 uint32_t umc_reg_offset, 133 unsigned long *error_count) 134 { 135 uint64_t mc_umc_status; 136 uint32_t mc_umc_status_addr; 137 138 if (adev->asic_type == CHIP_ARCTURUS) { 139 /* UMC 6_1_2 registers */ 140 mc_umc_status_addr = 141 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT); 142 } else { 143 /* UMC 6_1_1 registers */ 144 mc_umc_status_addr = 145 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 146 } 147 148 /* check the MCUMC_STATUS */ 149 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 150 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 151 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || 152 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 153 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 154 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 155 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) 156 *error_count += 1; 157 } 158 159 static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev, 160 void *ras_error_status) 161 { 162 struct ras_err_data* err_data = (struct ras_err_data*)ras_error_status; 163 164 uint32_t umc_inst = 0; 165 uint32_t ch_inst = 0; 166 uint32_t umc_reg_offset = 0; 167 168 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 169 umc_reg_offset = get_umc_6_reg_offset(adev, 170 umc_inst, 171 ch_inst); 172 173 umc_v6_1_query_correctable_error_count(adev, 174 umc_reg_offset, 175 &(err_data->ce_count)); 176 umc_v6_1_querry_uncorrectable_error_count(adev, 177 umc_reg_offset, 178 &(err_data->ue_count)); 179 } 180 } 181 182 static void umc_v6_1_query_error_address(struct amdgpu_device *adev, 183 struct ras_err_data *err_data, 184 uint32_t umc_reg_offset, 185 uint32_t ch_inst, 186 uint32_t umc_inst) 187 { 188 uint32_t lsb, mc_umc_status_addr; 189 uint64_t mc_umc_status, err_addr, retired_page; 190 struct eeprom_table_record *err_rec; 191 uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; 192 193 if (adev->asic_type == CHIP_ARCTURUS) { 194 /* UMC 6_1_2 registers */ 195 mc_umc_status_addr = 196 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT); 197 } else { 198 /* UMC 6_1_1 registers */ 199 mc_umc_status_addr = 200 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 201 } 202 203 /* skip error address process if -ENOMEM */ 204 if (!err_data->err_addr) { 205 /* clear umc status */ 206 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 207 return; 208 } 209 210 err_rec = &err_data->err_addr[err_data->err_addr_cnt]; 211 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); 212 213 /* calculate error address if ue/ce error is detected */ 214 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 215 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 216 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) { 217 err_addr = RREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4); 218 219 /* the lowest lsb bits should be ignored */ 220 lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB); 221 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 222 err_addr &= ~((0x1ULL << lsb) - 1); 223 224 /* translate umc channel address to soc pa, 3 parts are included */ 225 retired_page = ADDR_OF_8KB_BLOCK(err_addr) | 226 ADDR_OF_256B_BLOCK(channel_index) | 227 OFFSET_IN_256B_BLOCK(err_addr); 228 229 /* we only save ue error information currently, ce is skipped */ 230 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) 231 == 1) { 232 err_rec->address = err_addr; 233 /* page frame address is saved */ 234 err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT; 235 err_rec->ts = (uint64_t)ktime_get_real_seconds(); 236 err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; 237 err_rec->cu = 0; 238 err_rec->mem_channel = channel_index; 239 err_rec->mcumc_id = umc_inst; 240 241 err_data->err_addr_cnt++; 242 } 243 } 244 245 /* clear umc status */ 246 WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 247 } 248 249 static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, 250 void *ras_error_status) 251 { 252 struct ras_err_data* err_data = (struct ras_err_data*)ras_error_status; 253 254 uint32_t umc_inst = 0; 255 uint32_t ch_inst = 0; 256 uint32_t umc_reg_offset = 0; 257 258 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 259 umc_reg_offset = get_umc_6_reg_offset(adev, 260 umc_inst, 261 ch_inst); 262 263 umc_v6_1_query_error_address(adev, 264 err_data, 265 umc_reg_offset, 266 ch_inst, 267 umc_inst); 268 } 269 270 } 271 272 static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev, 273 uint32_t umc_reg_offset) 274 { 275 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; 276 uint32_t ecc_err_cnt_addr; 277 278 if (adev->asic_type == CHIP_ARCTURUS) { 279 /* UMC 6_1_2 registers */ 280 ecc_err_cnt_sel_addr = 281 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT); 282 ecc_err_cnt_addr = 283 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT); 284 } else { 285 /* UMC 6_1_1 registers */ 286 ecc_err_cnt_sel_addr = 287 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); 288 ecc_err_cnt_addr = 289 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); 290 } 291 292 /* select the lower chip and check the error count */ 293 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); 294 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 295 EccErrCntCsSel, 0); 296 /* set ce error interrupt type to APIC based interrupt */ 297 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 298 EccErrInt, 0x1); 299 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 300 /* set error count to initial value */ 301 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); 302 303 /* select the higher chip and check the err counter */ 304 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 305 EccErrCntCsSel, 1); 306 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); 307 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); 308 } 309 310 static void umc_v6_1_err_cnt_init(struct amdgpu_device *adev) 311 { 312 uint32_t umc_inst = 0; 313 uint32_t ch_inst = 0; 314 uint32_t umc_reg_offset = 0; 315 316 umc_v6_1_disable_umc_index_mode(adev); 317 318 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { 319 umc_reg_offset = get_umc_6_reg_offset(adev, 320 umc_inst, 321 ch_inst); 322 323 umc_v6_1_err_cnt_init_per_channel(adev, umc_reg_offset); 324 } 325 } 326 327 const struct amdgpu_umc_funcs umc_v6_1_funcs = { 328 .err_cnt_init = umc_v6_1_err_cnt_init, 329 .ras_late_init = amdgpu_umc_ras_late_init, 330 .query_ras_error_count = umc_v6_1_query_ras_error_count, 331 .query_ras_error_address = umc_v6_1_query_ras_error_address, 332 }; 333