1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v6_1.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu.h" 26 27 #include "rsmu/rsmu_0_0_2_offset.h" 28 #include "rsmu/rsmu_0_0_2_sh_mask.h" 29 #include "umc/umc_6_1_1_offset.h" 30 #include "umc/umc_6_1_1_sh_mask.h" 31 32 #define smnMCA_UMC0_MCUMC_ADDRT0 0x50f10 33 34 /* 35 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr 36 * is the index of 8KB block 37 */ 38 #define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) 39 /* channel index is the index of 256B block */ 40 #define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) 41 /* offset in 256B block */ 42 #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) 43 44 const uint32_t 45 umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = { 46 {2, 18, 11, 27}, {4, 20, 13, 29}, 47 {1, 17, 8, 24}, {7, 23, 14, 30}, 48 {10, 26, 3, 19}, {12, 28, 5, 21}, 49 {9, 25, 0, 16}, {15, 31, 6, 22} 50 }; 51 52 static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev, 53 uint32_t umc_instance) 54 { 55 uint32_t rsmu_umc_index; 56 57 rsmu_umc_index = RREG32_SOC15(RSMU, 0, 58 mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU); 59 rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index, 60 RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 61 RSMU_UMC_INDEX_MODE_EN, 1); 62 rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index, 63 RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 64 RSMU_UMC_INDEX_INSTANCE, umc_instance); 65 rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index, 66 RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 67 RSMU_UMC_INDEX_WREN, 1 << umc_instance); 68 WREG32_SOC15(RSMU, 0, mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 69 rsmu_umc_index); 70 } 71 72 static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev) 73 { 74 WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 75 RSMU_UMC_INDEX_MODE_EN, 0); 76 } 77 78 static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, 79 uint32_t umc_reg_offset, 80 unsigned long *error_count) 81 { 82 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; 83 uint32_t ecc_err_cnt, ecc_err_cnt_addr; 84 uint64_t mc_umc_status; 85 uint32_t mc_umc_status_addr; 86 87 ecc_err_cnt_sel_addr = 88 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); 89 ecc_err_cnt_addr = 90 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); 91 mc_umc_status_addr = 92 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 93 94 /* select the lower chip and check the error count */ 95 ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset); 96 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 97 EccErrCntCsSel, 0); 98 WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); 99 ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); 100 *error_count += 101 REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt); 102 /* clear the lower chip err count */ 103 WREG32(ecc_err_cnt_addr + umc_reg_offset, 0); 104 105 /* select the higher chip and check the err counter */ 106 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 107 EccErrCntCsSel, 1); 108 WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); 109 ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); 110 *error_count += 111 REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt); 112 /* clear the higher chip err count */ 113 WREG32(ecc_err_cnt_addr + umc_reg_offset, 0); 114 115 /* check for SRAM correctable error 116 MCUMC_STATUS is a 64 bit register */ 117 mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset); 118 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && 119 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 120 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) 121 *error_count += 1; 122 } 123 124 static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev, 125 uint32_t umc_reg_offset, 126 unsigned long *error_count) 127 { 128 uint64_t mc_umc_status; 129 uint32_t mc_umc_status_addr; 130 131 mc_umc_status_addr = 132 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 133 134 /* check the MCUMC_STATUS */ 135 mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset); 136 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 137 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || 138 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 139 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 140 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 141 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) 142 *error_count += 1; 143 } 144 145 static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev, 146 void *ras_error_status) 147 { 148 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 149 uint32_t umc_inst, channel_inst, umc_reg_offset, mc_umc_status_addr; 150 151 mc_umc_status_addr = 152 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 153 154 for (umc_inst = 0; umc_inst < UMC_V6_1_UMC_INSTANCE_NUM; umc_inst++) { 155 /* enable the index mode to query eror count per channel */ 156 umc_v6_1_enable_umc_index_mode(adev, umc_inst); 157 for (channel_inst = 0; channel_inst < UMC_V6_1_CHANNEL_INSTANCE_NUM; channel_inst++) { 158 /* calc the register offset according to channel instance */ 159 umc_reg_offset = UMC_V6_1_PER_CHANNEL_OFFSET * channel_inst; 160 umc_v6_1_query_correctable_error_count(adev, umc_reg_offset, 161 &(err_data->ce_count)); 162 umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset, 163 &(err_data->ue_count)); 164 /* clear umc status */ 165 WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL); 166 } 167 } 168 umc_v6_1_disable_umc_index_mode(adev); 169 } 170 171 static void umc_v6_1_query_error_address(struct amdgpu_device *adev, 172 uint32_t umc_reg_offset, uint32_t channel_index, 173 struct ras_err_data *err_data) 174 { 175 uint32_t lsb; 176 uint64_t mc_umc_status, err_addr; 177 uint32_t mc_umc_status_addr; 178 179 /* skip error address process if -ENOMEM */ 180 if (!err_data->err_addr) 181 return; 182 183 mc_umc_status_addr = 184 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 185 mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset); 186 187 /* calculate error address if ue/ce error is detected */ 188 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 189 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 190 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) { 191 err_addr = RREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4); 192 193 /* the lowest lsb bits should be ignored */ 194 lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB); 195 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 196 err_addr &= ~((0x1ULL << lsb) - 1); 197 198 /* translate umc channel address to soc pa, 3 parts are included */ 199 err_data->err_addr[err_data->err_addr_cnt] = 200 ADDR_OF_8KB_BLOCK(err_addr) 201 | ADDR_OF_256B_BLOCK(channel_index) 202 | OFFSET_IN_256B_BLOCK(err_addr); 203 204 err_data->err_addr_cnt++; 205 } 206 } 207 208 static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, 209 void *ras_error_status) 210 { 211 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 212 uint32_t umc_inst, channel_inst, umc_reg_offset; 213 uint32_t channel_index, mc_umc_status_addr; 214 215 mc_umc_status_addr = 216 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 217 218 for (umc_inst = 0; umc_inst < UMC_V6_1_UMC_INSTANCE_NUM; umc_inst++) { 219 /* enable the index mode to query eror count per channel */ 220 umc_v6_1_enable_umc_index_mode(adev, umc_inst); 221 for (channel_inst = 0; channel_inst < UMC_V6_1_CHANNEL_INSTANCE_NUM; channel_inst++) { 222 /* calc the register offset according to channel instance */ 223 umc_reg_offset = UMC_V6_1_PER_CHANNEL_OFFSET * channel_inst; 224 /* get channel index of interleaved memory */ 225 channel_index = umc_v6_1_channel_idx_tbl[umc_inst][channel_inst]; 226 227 umc_v6_1_query_error_address(adev, umc_reg_offset, 228 channel_index, err_data); 229 230 /* clear umc status */ 231 WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL); 232 } 233 } 234 235 umc_v6_1_disable_umc_index_mode(adev); 236 } 237 238 static void umc_v6_1_ras_init(struct amdgpu_device *adev) 239 { 240 241 } 242 243 const struct amdgpu_umc_funcs umc_v6_1_funcs = { 244 .ras_init = umc_v6_1_ras_init, 245 .query_ras_error_count = umc_v6_1_query_ras_error_count, 246 .query_ras_error_address = umc_v6_1_query_ras_error_address, 247 .enable_umc_index_mode = umc_v6_1_enable_umc_index_mode, 248 .disable_umc_index_mode = umc_v6_1_disable_umc_index_mode, 249 }; 250