1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v6_1.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu.h" 26 27 #include "rsmu/rsmu_0_0_2_offset.h" 28 #include "rsmu/rsmu_0_0_2_sh_mask.h" 29 #include "umc/umc_6_1_1_offset.h" 30 #include "umc/umc_6_1_1_sh_mask.h" 31 32 #define smnMCA_UMC0_MCUMC_ADDRT0 0x50f10 33 34 /* 35 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr 36 * is the index of 8KB block 37 */ 38 #define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) 39 /* channel index is the index of 256B block */ 40 #define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) 41 /* offset in 256B block */ 42 #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) 43 44 const uint32_t 45 umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = { 46 {2, 18, 11, 27}, {4, 20, 13, 29}, 47 {1, 17, 8, 24}, {7, 23, 14, 30}, 48 {10, 26, 3, 19}, {12, 28, 5, 21}, 49 {9, 25, 0, 16}, {15, 31, 6, 22} 50 }; 51 52 static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev, 53 uint32_t umc_instance) 54 { 55 uint32_t rsmu_umc_index; 56 57 rsmu_umc_index = RREG32_SOC15(RSMU, 0, 58 mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU); 59 rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index, 60 RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 61 RSMU_UMC_INDEX_MODE_EN, 1); 62 rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index, 63 RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 64 RSMU_UMC_INDEX_INSTANCE, umc_instance); 65 rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index, 66 RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 67 RSMU_UMC_INDEX_WREN, 1 << umc_instance); 68 WREG32_SOC15(RSMU, 0, mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 69 rsmu_umc_index); 70 } 71 72 static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev) 73 { 74 WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 75 RSMU_UMC_INDEX_MODE_EN, 0); 76 } 77 78 static uint32_t umc_v6_1_get_umc_inst(struct amdgpu_device *adev) 79 { 80 uint32_t rsmu_umc_index; 81 82 rsmu_umc_index = RREG32_SOC15(RSMU, 0, 83 mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU); 84 return REG_GET_FIELD(rsmu_umc_index, 85 RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU, 86 RSMU_UMC_INDEX_INSTANCE); 87 } 88 89 static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, 90 uint32_t umc_reg_offset, 91 unsigned long *error_count) 92 { 93 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; 94 uint32_t ecc_err_cnt, ecc_err_cnt_addr; 95 uint64_t mc_umc_status; 96 uint32_t mc_umc_status_addr; 97 98 ecc_err_cnt_sel_addr = 99 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); 100 ecc_err_cnt_addr = 101 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); 102 mc_umc_status_addr = 103 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 104 105 /* select the lower chip and check the error count */ 106 ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset); 107 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 108 EccErrCntCsSel, 0); 109 WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); 110 ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); 111 *error_count += 112 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - 113 UMC_V6_1_CE_CNT_INIT); 114 /* clear the lower chip err count */ 115 WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); 116 117 /* select the higher chip and check the err counter */ 118 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 119 EccErrCntCsSel, 1); 120 WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); 121 ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); 122 *error_count += 123 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - 124 UMC_V6_1_CE_CNT_INIT); 125 /* clear the higher chip err count */ 126 WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); 127 128 /* check for SRAM correctable error 129 MCUMC_STATUS is a 64 bit register */ 130 mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); 131 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && 132 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 133 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) 134 *error_count += 1; 135 } 136 137 static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev, 138 uint32_t umc_reg_offset, 139 unsigned long *error_count) 140 { 141 uint64_t mc_umc_status; 142 uint32_t mc_umc_status_addr; 143 144 mc_umc_status_addr = 145 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 146 147 /* check the MCUMC_STATUS */ 148 mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); 149 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 150 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || 151 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 152 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 153 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 154 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) 155 *error_count += 1; 156 } 157 158 static void umc_v6_1_query_error_count(struct amdgpu_device *adev, 159 struct ras_err_data *err_data, uint32_t umc_reg_offset, 160 uint32_t channel_index) 161 { 162 umc_v6_1_query_correctable_error_count(adev, umc_reg_offset, 163 &(err_data->ce_count)); 164 umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset, 165 &(err_data->ue_count)); 166 } 167 168 static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev, 169 void *ras_error_status) 170 { 171 amdgpu_umc_for_each_channel(umc_v6_1_query_error_count); 172 } 173 174 static void umc_v6_1_query_error_address(struct amdgpu_device *adev, 175 struct ras_err_data *err_data, 176 uint32_t umc_reg_offset, uint32_t channel_index) 177 { 178 uint32_t lsb, mc_umc_status_addr; 179 uint64_t mc_umc_status, err_addr, retired_page; 180 struct eeprom_table_record *err_rec; 181 182 mc_umc_status_addr = 183 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); 184 185 /* skip error address process if -ENOMEM */ 186 if (!err_data->err_addr) { 187 /* clear umc status */ 188 WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL); 189 return; 190 } 191 192 err_rec = &err_data->err_addr[err_data->err_addr_cnt]; 193 mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset); 194 195 /* calculate error address if ue/ce error is detected */ 196 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 197 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 198 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) { 199 err_addr = RREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4); 200 201 /* the lowest lsb bits should be ignored */ 202 lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB); 203 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 204 err_addr &= ~((0x1ULL << lsb) - 1); 205 206 /* translate umc channel address to soc pa, 3 parts are included */ 207 retired_page = ADDR_OF_8KB_BLOCK(err_addr) | 208 ADDR_OF_256B_BLOCK(channel_index) | 209 OFFSET_IN_256B_BLOCK(err_addr); 210 211 /* we only save ue error information currently, ce is skipped */ 212 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) 213 == 1) { 214 err_rec->address = err_addr; 215 /* page frame address is saved */ 216 err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT; 217 err_rec->ts = (uint64_t)ktime_get_real_seconds(); 218 err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; 219 err_rec->cu = 0; 220 err_rec->mem_channel = channel_index; 221 err_rec->mcumc_id = umc_v6_1_get_umc_inst(adev); 222 223 err_data->err_addr_cnt++; 224 } 225 } 226 227 /* clear umc status */ 228 WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL); 229 } 230 231 static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, 232 void *ras_error_status) 233 { 234 amdgpu_umc_for_each_channel(umc_v6_1_query_error_address); 235 } 236 237 static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev, 238 struct ras_err_data *err_data, 239 uint32_t umc_reg_offset, uint32_t channel_index) 240 { 241 uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr; 242 uint32_t ecc_err_cnt_addr; 243 244 ecc_err_cnt_sel_addr = 245 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); 246 ecc_err_cnt_addr = 247 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); 248 249 /* select the lower chip and check the error count */ 250 ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset); 251 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 252 EccErrCntCsSel, 0); 253 /* set ce error interrupt type to APIC based interrupt */ 254 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 255 EccErrInt, 0x1); 256 WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); 257 /* set error count to initial value */ 258 WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); 259 260 /* select the higher chip and check the err counter */ 261 ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, 262 EccErrCntCsSel, 1); 263 WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); 264 WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); 265 } 266 267 static void umc_v6_1_err_cnt_init(struct amdgpu_device *adev) 268 { 269 void *ras_error_status = NULL; 270 271 amdgpu_umc_for_each_channel(umc_v6_1_err_cnt_init_per_channel); 272 } 273 274 const struct amdgpu_umc_funcs umc_v6_1_funcs = { 275 .err_cnt_init = umc_v6_1_err_cnt_init, 276 .ras_late_init = amdgpu_umc_ras_late_init, 277 .query_ras_error_count = umc_v6_1_query_ras_error_count, 278 .query_ras_error_address = umc_v6_1_query_ras_error_address, 279 .enable_umc_index_mode = umc_v6_1_enable_umc_index_mode, 280 .disable_umc_index_mode = umc_v6_1_disable_umc_index_mode, 281 }; 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