1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __SOC15_COMMON_H__ 25 #define __SOC15_COMMON_H__ 26 27 /* GET_INST returns the physical instance corresponding to a logical instance */ 28 #define GET_INST(ip, inst) (adev->ip_map.logical_to_dev_inst? adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst): inst) 29 30 /* Register Access Macros */ 31 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 32 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ 33 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset)) 34 35 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \ 36 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \ 37 amdgpu_sriov_wreg(adev, reg, value, flag, hwip) : \ 38 WREG32(reg, value)) 39 40 #define __RREG32_SOC15_RLC__(reg, flag, hwip) \ 41 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \ 42 amdgpu_sriov_rreg(adev, reg, flag, hwip) : \ 43 RREG32(reg)) 44 45 #define WREG32_FIELD15(ip, idx, reg, field, val) \ 46 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 47 (__RREG32_SOC15_RLC__( \ 48 adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 49 0, ip##_HWIP) & \ 50 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ 51 0, ip##_HWIP) 52 53 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \ 54 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \ 55 (__RREG32_SOC15_RLC__( \ 56 adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \ 57 0, ip##_HWIP) & \ 58 ~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \ 59 0, ip##_HWIP) 60 61 #define RREG32_SOC15(ip, inst, reg) \ 62 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 63 0, ip##_HWIP) 64 65 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP) 66 67 #define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP) 68 69 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \ 70 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 71 AMDGPU_REGS_NO_KIQ, ip##_HWIP) 72 73 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ 74 __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_HWIP) 75 76 #define WREG32_SOC15(ip, inst, reg, value) \ 77 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \ 78 value, 0, ip##_HWIP) 79 80 #define WREG32_SOC15_IP(ip, reg, value) \ 81 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP) 82 83 #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \ 84 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP) 85 86 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ 87 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 88 value, AMDGPU_REGS_NO_KIQ, ip##_HWIP) 89 90 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ 91 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \ 92 value, 0, ip##_HWIP) 93 94 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ 95 amdgpu_device_wait_on_rreg(adev, inst, \ 96 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)), \ 97 #reg, expected_value, mask) 98 99 #define SOC15_WAIT_ON_RREG_OFFSET(ip, inst, reg, offset, expected_value, mask) \ 100 amdgpu_device_wait_on_rreg(adev, inst, \ 101 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg) + (offset)), \ 102 #reg, expected_value, mask) 103 104 #define WREG32_RLC(reg, value) \ 105 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP) 106 107 #define WREG32_RLC_EX(prefix, reg, value) \ 108 do { \ 109 if (amdgpu_sriov_fullaccess(adev)) { \ 110 uint32_t i = 0; \ 111 uint32_t retries = 50000; \ 112 uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \ 113 uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \ 114 uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \ 115 WREG32(r0, value); \ 116 WREG32(r1, (reg | 0x80000000)); \ 117 WREG32(spare_int, 0x1); \ 118 for (i = 0; i < retries; i++) { \ 119 u32 tmp = RREG32(r1); \ 120 if (!(tmp & 0x80000000)) \ 121 break; \ 122 udelay(10); \ 123 } \ 124 if (i >= retries) \ 125 pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \ 126 } else { \ 127 WREG32(reg, value); \ 128 } \ 129 } while (0) 130 131 /* shadow the registers in the callback function */ 132 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ 133 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP) 134 135 /* for GC only */ 136 #define RREG32_RLC(reg) \ 137 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP) 138 139 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ 140 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip) 141 142 #define RREG32_RLC_NO_KIQ(reg, hwip) \ 143 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip) 144 145 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \ 146 do { \ 147 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ 148 if (amdgpu_sriov_fullaccess(adev)) { \ 149 uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \ 150 uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \ 151 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \ 152 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \ 153 if (target_reg == grbm_cntl) \ 154 WREG32(r2, value); \ 155 else if (target_reg == grbm_idx) \ 156 WREG32(r3, value); \ 157 WREG32(target_reg, value); \ 158 } else { \ 159 WREG32(target_reg, value); \ 160 } \ 161 } while (0) 162 163 #define RREG32_SOC15_RLC(ip, inst, reg) \ 164 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP) 165 166 #define WREG32_SOC15_RLC(ip, inst, reg, value) \ 167 do { \ 168 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ 169 __WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \ 170 } while (0) 171 172 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ 173 do { \ 174 uint32_t target_reg = adev->reg_offset[GC_HWIP][inst][reg##_BASE_IDX] + reg;\ 175 WREG32_RLC_EX(prefix, target_reg, value); \ 176 } while (0) 177 178 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ 179 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ 180 (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 181 AMDGPU_REGS_RLC, ip##_HWIP) & \ 182 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ 183 AMDGPU_REGS_RLC, ip##_HWIP) 184 185 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \ 186 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP) 187 188 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \ 189 __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP) 190 191 /* inst equals to ext for some IPs */ 192 #define RREG32_SOC15_EXT(ip, inst, reg, ext) \ 193 RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \ 194 + adev->asic_funcs->encode_ext_smn_addressing(ext)) \ 195 196 #define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \ 197 WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \ 198 + adev->asic_funcs->encode_ext_smn_addressing(ext), \ 199 value) \ 200 201 #endif 202