18e3153baSKen Wang /* 28e3153baSKen Wang * Copyright 2016 Advanced Micro Devices, Inc. 38e3153baSKen Wang * 48e3153baSKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 58e3153baSKen Wang * copy of this software and associated documentation files (the "Software"), 68e3153baSKen Wang * to deal in the Software without restriction, including without limitation 78e3153baSKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 88e3153baSKen Wang * and/or sell copies of the Software, and to permit persons to whom the 98e3153baSKen Wang * Software is furnished to do so, subject to the following conditions: 108e3153baSKen Wang * 118e3153baSKen Wang * The above copyright notice and this permission notice shall be included in 128e3153baSKen Wang * all copies or substantial portions of the Software. 138e3153baSKen Wang * 148e3153baSKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 158e3153baSKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 168e3153baSKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 178e3153baSKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 188e3153baSKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 198e3153baSKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 208e3153baSKen Wang * OTHER DEALINGS IN THE SOFTWARE. 218e3153baSKen Wang * 228e3153baSKen Wang */ 238e3153baSKen Wang 248e3153baSKen Wang #ifndef __SOC15_COMMON_H__ 258e3153baSKen Wang #define __SOC15_COMMON_H__ 268e3153baSKen Wang 27b1bb8c01STom St Denis /* Register Access Macros */ 28cd29253fSShaoyun Liu #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 298e3153baSKen Wang 30a5504e9aSPeng Ju Zhou #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \ 311a4772d9SRoy Sun ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_wreg) ? \ 321a4772d9SRoy Sun adev->gfx.rlc.funcs->sriov_wreg(adev, reg, value, flag, hwip) : \ 33a5504e9aSPeng Ju Zhou WREG32(reg, value)) 34a5504e9aSPeng Ju Zhou 35a5504e9aSPeng Ju Zhou #define __RREG32_SOC15_RLC__(reg, flag, hwip) \ 361a4772d9SRoy Sun ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_rreg) ? \ 371a4772d9SRoy Sun adev->gfx.rlc.funcs->sriov_rreg(adev, reg, flag, hwip) : \ 38a5504e9aSPeng Ju Zhou RREG32(reg)) 39a5504e9aSPeng Ju Zhou 40b1bb8c01STom St Denis #define WREG32_FIELD15(ip, idx, reg, field, val) \ 41a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 42a5504e9aSPeng Ju Zhou (__RREG32_SOC15_RLC__( \ 43a5504e9aSPeng Ju Zhou adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 44a5504e9aSPeng Ju Zhou 0, ip##_HWIP) & \ 45a5504e9aSPeng Ju Zhou ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ 46a5504e9aSPeng Ju Zhou 0, ip##_HWIP) 47b1bb8c01STom St Denis 48b1bb8c01STom St Denis #define RREG32_SOC15(ip, inst, reg) \ 49a5504e9aSPeng Ju Zhou __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 50a5504e9aSPeng Ju Zhou 0, ip##_HWIP) 51a5504e9aSPeng Ju Zhou 52a5504e9aSPeng Ju Zhou #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP) 53b1bb8c01STom St Denis 54*0da6f6e5SVictor Skvortsov #define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP) 55*0da6f6e5SVictor Skvortsov 56c2ce6aebSMonk Liu #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \ 57a5504e9aSPeng Ju Zhou __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 58a5504e9aSPeng Ju Zhou AMDGPU_REGS_NO_KIQ, ip##_HWIP) 59c2ce6aebSMonk Liu 60496828e7STom St Denis #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ 61a5504e9aSPeng Ju Zhou __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_HWIP) 62496828e7STom St Denis 63b1bb8c01STom St Denis #define WREG32_SOC15(ip, inst, reg, value) \ 64a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \ 65a5504e9aSPeng Ju Zhou value, 0, ip##_HWIP) 66a5504e9aSPeng Ju Zhou 67a5504e9aSPeng Ju Zhou #define WREG32_SOC15_IP(ip, reg, value) \ 68a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP) 69b1bb8c01STom St Denis 70*0da6f6e5SVictor Skvortsov #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \ 71*0da6f6e5SVictor Skvortsov __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP) 72*0da6f6e5SVictor Skvortsov 73c708535eSShaoyun Liu #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ 74a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 75a5504e9aSPeng Ju Zhou value, AMDGPU_REGS_NO_KIQ, ip##_HWIP) 76c708535eSShaoyun Liu 77496828e7STom St Denis #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ 78a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \ 79a5504e9aSPeng Ju Zhou value, 0, ip##_HWIP) 80496828e7STom St Denis 81450da2efSJames Zhu #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ 82450da2efSJames Zhu ({ int ret = 0; \ 83ac06b4cfSRex Zhu do { \ 847ab3f021SJames Zhu uint32_t old_ = 0; \ 85ac06b4cfSRex Zhu uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 86ac06b4cfSRex Zhu uint32_t loop = adev->usec_timeout; \ 87a63141e3SNathan Chancellor ret = 0; \ 88ac06b4cfSRex Zhu while ((tmp_ & (mask)) != (expected_value)) { \ 897ab3f021SJames Zhu if (old_ != tmp_) { \ 907ab3f021SJames Zhu loop = adev->usec_timeout; \ 917ab3f021SJames Zhu old_ = tmp_; \ 927ab3f021SJames Zhu } else \ 937ab3f021SJames Zhu udelay(1); \ 94ac06b4cfSRex Zhu tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 95ac06b4cfSRex Zhu loop--; \ 96ac06b4cfSRex Zhu if (!loop) { \ 977ab3f021SJames Zhu DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \ 9881bb773fSAlex Deucher inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \ 99ac06b4cfSRex Zhu ret = -ETIMEDOUT; \ 100ac06b4cfSRex Zhu break; \ 101ac06b4cfSRex Zhu } \ 102ac06b4cfSRex Zhu } \ 103450da2efSJames Zhu } while (0); \ 104450da2efSJames Zhu ret; \ 105450da2efSJames Zhu }) 106ac06b4cfSRex Zhu 1076b1ff3ddSTrigger Huang #define WREG32_RLC(reg, value) \ 108a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP) 1096b1ff3ddSTrigger Huang 11088f8575bSDennis Li #define WREG32_RLC_EX(prefix, reg, value) \ 11188f8575bSDennis Li do { \ 11288f8575bSDennis Li if (amdgpu_sriov_fullaccess(adev)) { \ 11388f8575bSDennis Li uint32_t i = 0; \ 11488f8575bSDennis Li uint32_t retries = 50000; \ 11588f8575bSDennis Li uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \ 11688f8575bSDennis Li uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \ 11788f8575bSDennis Li uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \ 11888f8575bSDennis Li WREG32(r0, value); \ 11988f8575bSDennis Li WREG32(r1, (reg | 0x80000000)); \ 12088f8575bSDennis Li WREG32(spare_int, 0x1); \ 12188f8575bSDennis Li for (i = 0; i < retries; i++) { \ 12288f8575bSDennis Li u32 tmp = RREG32(r1); \ 12388f8575bSDennis Li if (!(tmp & 0x80000000)) \ 12488f8575bSDennis Li break; \ 12588f8575bSDennis Li udelay(10); \ 12688f8575bSDennis Li } \ 12788f8575bSDennis Li if (i >= retries) \ 12888f8575bSDennis Li pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \ 12988f8575bSDennis Li } else { \ 13088f8575bSDennis Li WREG32(reg, value); \ 13188f8575bSDennis Li } \ 13288f8575bSDennis Li } while (0) 13388f8575bSDennis Li 134a5504e9aSPeng Ju Zhou /* shadow the registers in the callback function */ 1356b1ff3ddSTrigger Huang #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ 136a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP) 1375e025531SPeng Ju Zhou 138a5504e9aSPeng Ju Zhou /* for GC only */ 1395e025531SPeng Ju Zhou #define RREG32_RLC(reg) \ 140a5504e9aSPeng Ju Zhou __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP) 1415e025531SPeng Ju Zhou 142a5504e9aSPeng Ju Zhou #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ 143a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip) 1446b1ff3ddSTrigger Huang 145a5504e9aSPeng Ju Zhou #define RREG32_RLC_NO_KIQ(reg, hwip) \ 146a5504e9aSPeng Ju Zhou __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip) 1475e025531SPeng Ju Zhou 14822616eb5SDennis Li #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \ 14922616eb5SDennis Li do { \ 15022616eb5SDennis Li uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ 15122616eb5SDennis Li if (amdgpu_sriov_fullaccess(adev)) { \ 15222616eb5SDennis Li uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \ 15322616eb5SDennis Li uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \ 15422616eb5SDennis Li uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \ 15522616eb5SDennis Li uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \ 15622616eb5SDennis Li if (target_reg == grbm_cntl) \ 15722616eb5SDennis Li WREG32(r2, value); \ 15822616eb5SDennis Li else if (target_reg == grbm_idx) \ 15922616eb5SDennis Li WREG32(r3, value); \ 16022616eb5SDennis Li WREG32(target_reg, value); \ 16122616eb5SDennis Li } else { \ 16222616eb5SDennis Li WREG32(target_reg, value); \ 16322616eb5SDennis Li } \ 16422616eb5SDennis Li } while (0) 16522616eb5SDennis Li 1665e025531SPeng Ju Zhou #define RREG32_SOC15_RLC(ip, inst, reg) \ 167a5504e9aSPeng Ju Zhou __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP) 1685e025531SPeng Ju Zhou 1696b1ff3ddSTrigger Huang #define WREG32_SOC15_RLC(ip, inst, reg, value) \ 1706b1ff3ddSTrigger Huang do { \ 1715e025531SPeng Ju Zhou uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\ 172a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \ 1736b1ff3ddSTrigger Huang } while (0) 1746b1ff3ddSTrigger Huang 17588f8575bSDennis Li #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ 17688f8575bSDennis Li do { \ 17788f8575bSDennis Li uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ 17888f8575bSDennis Li WREG32_RLC_EX(prefix, target_reg, value); \ 17988f8575bSDennis Li } while (0) 18088f8575bSDennis Li 1816b1ff3ddSTrigger Huang #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ 182a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ 183a5504e9aSPeng Ju Zhou (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 184a5504e9aSPeng Ju Zhou AMDGPU_REGS_RLC, ip##_HWIP) & \ 185a5504e9aSPeng Ju Zhou ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ 186a5504e9aSPeng Ju Zhou AMDGPU_REGS_RLC, ip##_HWIP) 1876b1ff3ddSTrigger Huang 1886b1ff3ddSTrigger Huang #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \ 189a5504e9aSPeng Ju Zhou __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP) 1906b1ff3ddSTrigger Huang 1915e025531SPeng Ju Zhou #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \ 192a5504e9aSPeng Ju Zhou __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP) 1935e025531SPeng Ju Zhou 1948e3153baSKen Wang #endif 195