xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/soc15.h (revision b8d312aa)
1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __SOC15_H__
25 #define __SOC15_H__
26 
27 #include "nbio_v6_1.h"
28 #include "nbio_v7_0.h"
29 #include "nbio_v7_4.h"
30 
31 #define SOC15_FLUSH_GPU_TLB_NUM_WREG		4
32 #define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT	1
33 
34 extern const struct amd_ip_funcs soc15_common_ip_funcs;
35 
36 struct soc15_reg_golden {
37 	u32	hwip;
38 	u32	instance;
39 	u32	segment;
40 	u32	reg;
41 	u32	and_mask;
42 	u32	or_mask;
43 };
44 
45 struct soc15_reg_entry {
46 	uint32_t hwip;
47 	uint32_t inst;
48 	uint32_t seg;
49 	uint32_t reg_offset;
50 	uint32_t reg_value;
51 	uint32_t se_num;
52 	uint32_t instance;
53 };
54 
55 struct soc15_allowed_register_entry {
56 	uint32_t hwip;
57 	uint32_t inst;
58 	uint32_t seg;
59 	uint32_t reg_offset;
60 	bool grbm_indexed;
61 };
62 
63 #define SOC15_REG_ENTRY(ip, inst, reg)	ip##_HWIP, inst, reg##_BASE_IDX, reg
64 
65 #define SOC15_REG_ENTRY_OFFSET(entry)	(adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
66 
67 #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
68 	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
69 
70 void soc15_grbm_select(struct amdgpu_device *adev,
71 		    u32 me, u32 pipe, u32 queue, u32 vmid);
72 int soc15_set_ip_blocks(struct amdgpu_device *adev);
73 
74 void soc15_program_register_sequence(struct amdgpu_device *adev,
75 					     const struct soc15_reg_golden *registers,
76 					     const u32 array_size);
77 
78 int vega10_reg_base_init(struct amdgpu_device *adev);
79 int vega20_reg_base_init(struct amdgpu_device *adev);
80 int arct_reg_base_init(struct amdgpu_device *adev);
81 
82 void vega10_doorbell_index_init(struct amdgpu_device *adev);
83 void vega20_doorbell_index_init(struct amdgpu_device *adev);
84 #endif
85