1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma/sdma_4_4_2_offset.h" 34 #include "sdma/sdma_4_4_2_sh_mask.h" 35 36 #include "soc15_common.h" 37 #include "soc15.h" 38 #include "vega10_sdma_pkt_open.h" 39 40 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 41 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 42 43 #include "amdgpu_ras.h" 44 45 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 46 47 #define WREG32_SDMA(instance, offset, value) \ 48 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 49 #define RREG32_SDMA(instance, offset) \ 50 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 51 52 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 53 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 54 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 55 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 56 57 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 58 u32 instance, u32 offset) 59 { 60 return (adev->reg_offset[SDMA0_HWIP][instance][0] + offset); 61 } 62 63 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 64 { 65 switch (seq_num) { 66 case 0: 67 return SOC15_IH_CLIENTID_SDMA0; 68 case 1: 69 return SOC15_IH_CLIENTID_SDMA1; 70 case 2: 71 return SOC15_IH_CLIENTID_SDMA2; 72 case 3: 73 return SOC15_IH_CLIENTID_SDMA3; 74 default: 75 return -EINVAL; 76 } 77 } 78 79 static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id) 80 { 81 switch (client_id) { 82 case SOC15_IH_CLIENTID_SDMA0: 83 return 0; 84 case SOC15_IH_CLIENTID_SDMA1: 85 return 1; 86 case SOC15_IH_CLIENTID_SDMA2: 87 return 2; 88 case SOC15_IH_CLIENTID_SDMA3: 89 return 3; 90 default: 91 return -EINVAL; 92 } 93 } 94 95 static void sdma_v4_4_2_init_golden_registers(struct amdgpu_device *adev) 96 { 97 switch (adev->ip_versions[SDMA0_HWIP][0]) { 98 case IP_VERSION(4, 4, 2): 99 break; 100 default: 101 break; 102 } 103 } 104 105 /** 106 * sdma_v4_4_2_init_microcode - load ucode images from disk 107 * 108 * @adev: amdgpu_device pointer 109 * 110 * Use the firmware interface to load the ucode images into 111 * the driver (not loaded into hw). 112 * Returns 0 on success, error on failure. 113 */ 114 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 115 { 116 int ret, i; 117 118 for (i = 0; i < adev->sdma.num_instances; i++) { 119 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2)) { 120 ret = amdgpu_sdma_init_microcode(adev, 0, true); 121 break; 122 } else { 123 ret = amdgpu_sdma_init_microcode(adev, i, false); 124 if (ret) 125 return ret; 126 } 127 } 128 129 return ret; 130 } 131 132 /** 133 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 134 * 135 * @ring: amdgpu ring pointer 136 * 137 * Get the current rptr from the hardware. 138 */ 139 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 140 { 141 u64 *rptr; 142 143 /* XXX check if swapping is necessary on BE */ 144 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 145 146 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 147 return ((*rptr) >> 2); 148 } 149 150 /** 151 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 152 * 153 * @ring: amdgpu ring pointer 154 * 155 * Get the current wptr from the hardware. 156 */ 157 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 158 { 159 struct amdgpu_device *adev = ring->adev; 160 u64 wptr; 161 162 if (ring->use_doorbell) { 163 /* XXX check if swapping is necessary on BE */ 164 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 165 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 166 } else { 167 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 168 wptr = wptr << 32; 169 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 170 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 171 ring->me, wptr); 172 } 173 174 return wptr >> 2; 175 } 176 177 /** 178 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 179 * 180 * @ring: amdgpu ring pointer 181 * 182 * Write the wptr back to the hardware. 183 */ 184 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 185 { 186 struct amdgpu_device *adev = ring->adev; 187 188 DRM_DEBUG("Setting write pointer\n"); 189 if (ring->use_doorbell) { 190 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 191 192 DRM_DEBUG("Using doorbell -- " 193 "wptr_offs == 0x%08x " 194 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 195 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 196 ring->wptr_offs, 197 lower_32_bits(ring->wptr << 2), 198 upper_32_bits(ring->wptr << 2)); 199 /* XXX check if swapping is necessary on BE */ 200 WRITE_ONCE(*wb, (ring->wptr << 2)); 201 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 202 ring->doorbell_index, ring->wptr << 2); 203 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 204 } else { 205 DRM_DEBUG("Not using doorbell -- " 206 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 207 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 208 ring->me, 209 lower_32_bits(ring->wptr << 2), 210 ring->me, 211 upper_32_bits(ring->wptr << 2)); 212 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 213 lower_32_bits(ring->wptr << 2)); 214 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 215 upper_32_bits(ring->wptr << 2)); 216 } 217 } 218 219 /** 220 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 221 * 222 * @ring: amdgpu ring pointer 223 * 224 * Get the current wptr from the hardware. 225 */ 226 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 227 { 228 struct amdgpu_device *adev = ring->adev; 229 u64 wptr; 230 231 if (ring->use_doorbell) { 232 /* XXX check if swapping is necessary on BE */ 233 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 234 } else { 235 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 236 wptr = wptr << 32; 237 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 238 } 239 240 return wptr >> 2; 241 } 242 243 /** 244 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 245 * 246 * @ring: amdgpu ring pointer 247 * 248 * Write the wptr back to the hardware. 249 */ 250 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 251 { 252 struct amdgpu_device *adev = ring->adev; 253 254 if (ring->use_doorbell) { 255 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 256 257 /* XXX check if swapping is necessary on BE */ 258 WRITE_ONCE(*wb, (ring->wptr << 2)); 259 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 260 } else { 261 uint64_t wptr = ring->wptr << 2; 262 263 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 264 lower_32_bits(wptr)); 265 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 266 upper_32_bits(wptr)); 267 } 268 } 269 270 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 271 { 272 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 273 int i; 274 275 for (i = 0; i < count; i++) 276 if (sdma && sdma->burst_nop && (i == 0)) 277 amdgpu_ring_write(ring, ring->funcs->nop | 278 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 279 else 280 amdgpu_ring_write(ring, ring->funcs->nop); 281 } 282 283 /** 284 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 285 * 286 * @ring: amdgpu ring pointer 287 * @job: job to retrieve vmid from 288 * @ib: IB object to schedule 289 * @flags: unused 290 * 291 * Schedule an IB in the DMA ring. 292 */ 293 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 294 struct amdgpu_job *job, 295 struct amdgpu_ib *ib, 296 uint32_t flags) 297 { 298 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 299 300 /* IB packet must end on a 8 DW boundary */ 301 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 302 303 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 304 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 305 /* base must be 32 byte aligned */ 306 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 307 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 308 amdgpu_ring_write(ring, ib->length_dw); 309 amdgpu_ring_write(ring, 0); 310 amdgpu_ring_write(ring, 0); 311 312 } 313 314 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 315 int mem_space, int hdp, 316 uint32_t addr0, uint32_t addr1, 317 uint32_t ref, uint32_t mask, 318 uint32_t inv) 319 { 320 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 321 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 322 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 323 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 324 if (mem_space) { 325 /* memory */ 326 amdgpu_ring_write(ring, addr0); 327 amdgpu_ring_write(ring, addr1); 328 } else { 329 /* registers */ 330 amdgpu_ring_write(ring, addr0 << 2); 331 amdgpu_ring_write(ring, addr1 << 2); 332 } 333 amdgpu_ring_write(ring, ref); /* reference */ 334 amdgpu_ring_write(ring, mask); /* mask */ 335 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 336 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 337 } 338 339 /** 340 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 341 * 342 * @ring: amdgpu ring pointer 343 * 344 * Emit an hdp flush packet on the requested DMA ring. 345 */ 346 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 347 { 348 struct amdgpu_device *adev = ring->adev; 349 u32 ref_and_mask = 0; 350 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 351 352 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 353 354 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 355 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 356 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 357 ref_and_mask, ref_and_mask, 10); 358 } 359 360 /** 361 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 362 * 363 * @ring: amdgpu ring pointer 364 * @addr: address 365 * @seq: sequence number 366 * @flags: fence related flags 367 * 368 * Add a DMA fence packet to the ring to write 369 * the fence seq number and DMA trap packet to generate 370 * an interrupt if needed. 371 */ 372 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 373 unsigned flags) 374 { 375 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 376 /* write the fence */ 377 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 378 /* zero in first two bits */ 379 BUG_ON(addr & 0x3); 380 amdgpu_ring_write(ring, lower_32_bits(addr)); 381 amdgpu_ring_write(ring, upper_32_bits(addr)); 382 amdgpu_ring_write(ring, lower_32_bits(seq)); 383 384 /* optionally write high bits as well */ 385 if (write64bit) { 386 addr += 4; 387 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 388 /* zero in first two bits */ 389 BUG_ON(addr & 0x3); 390 amdgpu_ring_write(ring, lower_32_bits(addr)); 391 amdgpu_ring_write(ring, upper_32_bits(addr)); 392 amdgpu_ring_write(ring, upper_32_bits(seq)); 393 } 394 395 /* generate an interrupt */ 396 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 397 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 398 } 399 400 401 /** 402 * sdma_v4_4_2_gfx_stop - stop the gfx async dma engines 403 * 404 * @adev: amdgpu_device pointer 405 * 406 * Stop the gfx async dma ring buffers. 407 */ 408 static void sdma_v4_4_2_gfx_stop(struct amdgpu_device *adev) 409 { 410 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 411 u32 rb_cntl, ib_cntl; 412 int i, unset = 0; 413 414 for (i = 0; i < adev->sdma.num_instances; i++) { 415 sdma[i] = &adev->sdma.instance[i].ring; 416 417 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 418 amdgpu_ttm_set_buffer_funcs_status(adev, false); 419 unset = 1; 420 } 421 422 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 423 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 424 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 425 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 426 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 427 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 428 } 429 } 430 431 /** 432 * sdma_v4_4_2_rlc_stop - stop the compute async dma engines 433 * 434 * @adev: amdgpu_device pointer 435 * 436 * Stop the compute async dma queues. 437 */ 438 static void sdma_v4_4_2_rlc_stop(struct amdgpu_device *adev) 439 { 440 /* XXX todo */ 441 } 442 443 /** 444 * sdma_v4_4_2_page_stop - stop the page async dma engines 445 * 446 * @adev: amdgpu_device pointer 447 * 448 * Stop the page async dma ring buffers. 449 */ 450 static void sdma_v4_4_2_page_stop(struct amdgpu_device *adev) 451 { 452 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 453 u32 rb_cntl, ib_cntl; 454 int i; 455 bool unset = false; 456 457 for (i = 0; i < adev->sdma.num_instances; i++) { 458 sdma[i] = &adev->sdma.instance[i].page; 459 460 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 461 (!unset)) { 462 amdgpu_ttm_set_buffer_funcs_status(adev, false); 463 unset = true; 464 } 465 466 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 467 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 468 RB_ENABLE, 0); 469 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 470 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 471 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 472 IB_ENABLE, 0); 473 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 474 } 475 } 476 477 /** 478 * sdma_v4_4_2_ctx_switch_enable - stop the async dma engines context switch 479 * 480 * @adev: amdgpu_device pointer 481 * @enable: enable/disable the DMA MEs context switch. 482 * 483 * Halt or unhalt the async dma engines context switch. 484 */ 485 static void sdma_v4_4_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 486 { 487 u32 f32_cntl, phase_quantum = 0; 488 int i; 489 490 if (amdgpu_sdma_phase_quantum) { 491 unsigned value = amdgpu_sdma_phase_quantum; 492 unsigned unit = 0; 493 494 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 495 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 496 value = (value + 1) >> 1; 497 unit++; 498 } 499 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 500 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 501 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 502 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 503 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 504 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 505 WARN_ONCE(1, 506 "clamping sdma_phase_quantum to %uK clock cycles\n", 507 value << unit); 508 } 509 phase_quantum = 510 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 511 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 512 } 513 514 for (i = 0; i < adev->sdma.num_instances; i++) { 515 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 516 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 517 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 518 if (enable && amdgpu_sdma_phase_quantum) { 519 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 520 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 521 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 522 } 523 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 524 525 /* Extend page fault timeout to avoid interrupt storm */ 526 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 527 } 528 529 } 530 531 /** 532 * sdma_v4_4_2_enable - stop the async dma engines 533 * 534 * @adev: amdgpu_device pointer 535 * @enable: enable/disable the DMA MEs. 536 * 537 * Halt or unhalt the async dma engines. 538 */ 539 static void sdma_v4_4_2_enable(struct amdgpu_device *adev, bool enable) 540 { 541 u32 f32_cntl; 542 int i; 543 544 if (!enable) { 545 sdma_v4_4_2_gfx_stop(adev); 546 sdma_v4_4_2_rlc_stop(adev); 547 if (adev->sdma.has_page_queue) 548 sdma_v4_4_2_page_stop(adev); 549 } 550 551 for (i = 0; i < adev->sdma.num_instances; i++) { 552 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 553 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 554 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 555 } 556 } 557 558 /* 559 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 560 */ 561 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 562 { 563 /* Set ring buffer size in dwords */ 564 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 565 566 barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */ 567 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 568 #ifdef __BIG_ENDIAN 569 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 570 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 571 RPTR_WRITEBACK_SWAP_ENABLE, 1); 572 #endif 573 return rb_cntl; 574 } 575 576 /** 577 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 578 * 579 * @adev: amdgpu_device pointer 580 * @i: instance to resume 581 * 582 * Set up the gfx DMA ring buffers and enable them. 583 * Returns 0 for success, error for failure. 584 */ 585 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i) 586 { 587 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 588 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 589 u32 wb_offset; 590 u32 doorbell; 591 u32 doorbell_offset; 592 u64 wptr_gpu_addr; 593 594 wb_offset = (ring->rptr_offs * 4); 595 596 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 597 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 598 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 599 600 /* Initialize the ring buffer's read and write pointers */ 601 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 602 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 603 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 604 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 605 606 /* set the wb address whether it's enabled or not */ 607 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 608 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 609 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 610 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 611 612 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 613 RPTR_WRITEBACK_ENABLE, 1); 614 615 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 616 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 617 618 ring->wptr = 0; 619 620 /* before programing wptr to a less value, need set minor_ptr_update first */ 621 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 622 623 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 624 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 625 626 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 627 ring->use_doorbell); 628 doorbell_offset = REG_SET_FIELD(doorbell_offset, 629 SDMA_GFX_DOORBELL_OFFSET, 630 OFFSET, ring->doorbell_index); 631 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 632 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 633 634 sdma_v4_4_2_ring_set_wptr(ring); 635 636 /* set minor_ptr_update to 0 after wptr programed */ 637 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 638 639 /* setup the wptr shadow polling */ 640 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 641 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 642 lower_32_bits(wptr_gpu_addr)); 643 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 644 upper_32_bits(wptr_gpu_addr)); 645 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 646 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 647 SDMA_GFX_RB_WPTR_POLL_CNTL, 648 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 649 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 650 651 /* enable DMA RB */ 652 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 653 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 654 655 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 656 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 657 #ifdef __BIG_ENDIAN 658 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 659 #endif 660 /* enable DMA IBs */ 661 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 662 663 ring->sched.ready = true; 664 } 665 666 /** 667 * sdma_v4_4_2_page_resume - setup and start the async dma engines 668 * 669 * @adev: amdgpu_device pointer 670 * @i: instance to resume 671 * 672 * Set up the page DMA ring buffers and enable them. 673 * Returns 0 for success, error for failure. 674 */ 675 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i) 676 { 677 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 678 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 679 u32 wb_offset; 680 u32 doorbell; 681 u32 doorbell_offset; 682 u64 wptr_gpu_addr; 683 684 wb_offset = (ring->rptr_offs * 4); 685 686 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 687 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 688 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 689 690 /* Initialize the ring buffer's read and write pointers */ 691 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 692 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 693 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 694 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 695 696 /* set the wb address whether it's enabled or not */ 697 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 698 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 699 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 700 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 701 702 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 703 RPTR_WRITEBACK_ENABLE, 1); 704 705 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 706 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 707 708 ring->wptr = 0; 709 710 /* before programing wptr to a less value, need set minor_ptr_update first */ 711 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 712 713 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 714 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 715 716 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 717 ring->use_doorbell); 718 doorbell_offset = REG_SET_FIELD(doorbell_offset, 719 SDMA_PAGE_DOORBELL_OFFSET, 720 OFFSET, ring->doorbell_index); 721 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 722 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 723 724 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 725 sdma_v4_4_2_page_ring_set_wptr(ring); 726 727 /* set minor_ptr_update to 0 after wptr programed */ 728 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 729 730 /* setup the wptr shadow polling */ 731 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 732 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 733 lower_32_bits(wptr_gpu_addr)); 734 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 735 upper_32_bits(wptr_gpu_addr)); 736 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 737 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 738 SDMA_PAGE_RB_WPTR_POLL_CNTL, 739 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 740 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 741 742 /* enable DMA RB */ 743 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 744 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 745 746 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 747 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 748 #ifdef __BIG_ENDIAN 749 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 750 #endif 751 /* enable DMA IBs */ 752 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 753 754 ring->sched.ready = true; 755 } 756 757 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 758 { 759 760 } 761 762 /** 763 * sdma_v4_4_2_rlc_resume - setup and start the async dma engines 764 * 765 * @adev: amdgpu_device pointer 766 * 767 * Set up the compute DMA queues and enable them. 768 * Returns 0 for success, error for failure. 769 */ 770 static int sdma_v4_4_2_rlc_resume(struct amdgpu_device *adev) 771 { 772 sdma_v4_4_2_init_pg(adev); 773 774 return 0; 775 } 776 777 /** 778 * sdma_v4_4_2_load_microcode - load the sDMA ME ucode 779 * 780 * @adev: amdgpu_device pointer 781 * 782 * Loads the sDMA0/1 ucode. 783 * Returns 0 for success, -EINVAL if the ucode is not available. 784 */ 785 static int sdma_v4_4_2_load_microcode(struct amdgpu_device *adev) 786 { 787 const struct sdma_firmware_header_v1_0 *hdr; 788 const __le32 *fw_data; 789 u32 fw_size; 790 int i, j; 791 792 /* halt the MEs */ 793 sdma_v4_4_2_enable(adev, false); 794 795 for (i = 0; i < adev->sdma.num_instances; i++) { 796 if (!adev->sdma.instance[i].fw) 797 return -EINVAL; 798 799 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 800 amdgpu_ucode_print_sdma_hdr(&hdr->header); 801 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 802 803 fw_data = (const __le32 *) 804 (adev->sdma.instance[i].fw->data + 805 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 806 807 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 808 809 for (j = 0; j < fw_size; j++) 810 WREG32_SDMA(i, regSDMA_UCODE_DATA, 811 le32_to_cpup(fw_data++)); 812 813 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 814 adev->sdma.instance[i].fw_version); 815 } 816 817 return 0; 818 } 819 820 /** 821 * sdma_v4_4_2_start - setup and start the async dma engines 822 * 823 * @adev: amdgpu_device pointer 824 * 825 * Set up the DMA engines and enable them. 826 * Returns 0 for success, error for failure. 827 */ 828 static int sdma_v4_4_2_start(struct amdgpu_device *adev) 829 { 830 struct amdgpu_ring *ring; 831 int i, r = 0; 832 833 if (amdgpu_sriov_vf(adev)) { 834 sdma_v4_4_2_ctx_switch_enable(adev, false); 835 sdma_v4_4_2_enable(adev, false); 836 } else { 837 /* bypass sdma microcode loading on Gopher */ 838 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 839 !(adev->pdev->device == 0x49) && !(adev->pdev->device == 0x50)) { 840 r = sdma_v4_4_2_load_microcode(adev); 841 if (r) 842 return r; 843 } 844 845 /* unhalt the MEs */ 846 sdma_v4_4_2_enable(adev, true); 847 /* enable sdma ring preemption */ 848 sdma_v4_4_2_ctx_switch_enable(adev, true); 849 } 850 851 /* start the gfx rings and rlc compute queues */ 852 for (i = 0; i < adev->sdma.num_instances; i++) { 853 uint32_t temp; 854 855 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 856 sdma_v4_4_2_gfx_resume(adev, i); 857 if (adev->sdma.has_page_queue) 858 sdma_v4_4_2_page_resume(adev, i); 859 860 /* set utc l1 enable flag always to 1 */ 861 temp = RREG32_SDMA(i, regSDMA_CNTL); 862 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 863 WREG32_SDMA(i, regSDMA_CNTL, temp); 864 865 if (!amdgpu_sriov_vf(adev)) { 866 ring = &adev->sdma.instance[i].ring; 867 adev->nbio.funcs->sdma_doorbell_range(adev, i, 868 ring->use_doorbell, ring->doorbell_index, 869 adev->doorbell_index.sdma_doorbell_range); 870 871 /* unhalt engine */ 872 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 873 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 874 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 875 } 876 } 877 878 if (amdgpu_sriov_vf(adev)) { 879 sdma_v4_4_2_ctx_switch_enable(adev, true); 880 sdma_v4_4_2_enable(adev, true); 881 } else { 882 r = sdma_v4_4_2_rlc_resume(adev); 883 if (r) 884 return r; 885 } 886 887 for (i = 0; i < adev->sdma.num_instances; i++) { 888 ring = &adev->sdma.instance[i].ring; 889 890 r = amdgpu_ring_test_helper(ring); 891 if (r) 892 return r; 893 894 if (adev->sdma.has_page_queue) { 895 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 896 897 r = amdgpu_ring_test_helper(page); 898 if (r) 899 return r; 900 901 if (adev->mman.buffer_funcs_ring == page) 902 amdgpu_ttm_set_buffer_funcs_status(adev, true); 903 } 904 905 if (adev->mman.buffer_funcs_ring == ring) 906 amdgpu_ttm_set_buffer_funcs_status(adev, true); 907 } 908 909 return r; 910 } 911 912 /** 913 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 914 * 915 * @ring: amdgpu_ring structure holding ring information 916 * 917 * Test the DMA engine by writing using it to write an 918 * value to memory. 919 * Returns 0 for success, error for failure. 920 */ 921 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 922 { 923 struct amdgpu_device *adev = ring->adev; 924 unsigned i; 925 unsigned index; 926 int r; 927 u32 tmp; 928 u64 gpu_addr; 929 930 r = amdgpu_device_wb_get(adev, &index); 931 if (r) 932 return r; 933 934 gpu_addr = adev->wb.gpu_addr + (index * 4); 935 tmp = 0xCAFEDEAD; 936 adev->wb.wb[index] = cpu_to_le32(tmp); 937 938 r = amdgpu_ring_alloc(ring, 5); 939 if (r) 940 goto error_free_wb; 941 942 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 943 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 944 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 945 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 946 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 947 amdgpu_ring_write(ring, 0xDEADBEEF); 948 amdgpu_ring_commit(ring); 949 950 for (i = 0; i < adev->usec_timeout; i++) { 951 tmp = le32_to_cpu(adev->wb.wb[index]); 952 if (tmp == 0xDEADBEEF) 953 break; 954 udelay(1); 955 } 956 957 if (i >= adev->usec_timeout) 958 r = -ETIMEDOUT; 959 960 error_free_wb: 961 amdgpu_device_wb_free(adev, index); 962 return r; 963 } 964 965 /** 966 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 967 * 968 * @ring: amdgpu_ring structure holding ring information 969 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 970 * 971 * Test a simple IB in the DMA ring. 972 * Returns 0 on success, error on failure. 973 */ 974 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 975 { 976 struct amdgpu_device *adev = ring->adev; 977 struct amdgpu_ib ib; 978 struct dma_fence *f = NULL; 979 unsigned index; 980 long r; 981 u32 tmp = 0; 982 u64 gpu_addr; 983 984 r = amdgpu_device_wb_get(adev, &index); 985 if (r) 986 return r; 987 988 gpu_addr = adev->wb.gpu_addr + (index * 4); 989 tmp = 0xCAFEDEAD; 990 adev->wb.wb[index] = cpu_to_le32(tmp); 991 memset(&ib, 0, sizeof(ib)); 992 r = amdgpu_ib_get(adev, NULL, 256, 993 AMDGPU_IB_POOL_DIRECT, &ib); 994 if (r) 995 goto err0; 996 997 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 998 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 999 ib.ptr[1] = lower_32_bits(gpu_addr); 1000 ib.ptr[2] = upper_32_bits(gpu_addr); 1001 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1002 ib.ptr[4] = 0xDEADBEEF; 1003 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1004 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1005 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1006 ib.length_dw = 8; 1007 1008 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1009 if (r) 1010 goto err1; 1011 1012 r = dma_fence_wait_timeout(f, false, timeout); 1013 if (r == 0) { 1014 r = -ETIMEDOUT; 1015 goto err1; 1016 } else if (r < 0) { 1017 goto err1; 1018 } 1019 tmp = le32_to_cpu(adev->wb.wb[index]); 1020 if (tmp == 0xDEADBEEF) 1021 r = 0; 1022 else 1023 r = -EINVAL; 1024 1025 err1: 1026 amdgpu_ib_free(adev, &ib, NULL); 1027 dma_fence_put(f); 1028 err0: 1029 amdgpu_device_wb_free(adev, index); 1030 return r; 1031 } 1032 1033 1034 /** 1035 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1036 * 1037 * @ib: indirect buffer to fill with commands 1038 * @pe: addr of the page entry 1039 * @src: src addr to copy from 1040 * @count: number of page entries to update 1041 * 1042 * Update PTEs by copying them from the GART using sDMA. 1043 */ 1044 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1045 uint64_t pe, uint64_t src, 1046 unsigned count) 1047 { 1048 unsigned bytes = count * 8; 1049 1050 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1051 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1052 ib->ptr[ib->length_dw++] = bytes - 1; 1053 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1054 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1055 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1056 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1057 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1058 1059 } 1060 1061 /** 1062 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1063 * 1064 * @ib: indirect buffer to fill with commands 1065 * @pe: addr of the page entry 1066 * @value: dst addr to write into pe 1067 * @count: number of page entries to update 1068 * @incr: increase next addr by incr bytes 1069 * 1070 * Update PTEs by writing them manually using sDMA. 1071 */ 1072 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1073 uint64_t value, unsigned count, 1074 uint32_t incr) 1075 { 1076 unsigned ndw = count * 2; 1077 1078 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1079 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1080 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1081 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1082 ib->ptr[ib->length_dw++] = ndw - 1; 1083 for (; ndw > 0; ndw -= 2) { 1084 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1085 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1086 value += incr; 1087 } 1088 } 1089 1090 /** 1091 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1092 * 1093 * @ib: indirect buffer to fill with commands 1094 * @pe: addr of the page entry 1095 * @addr: dst addr to write into pe 1096 * @count: number of page entries to update 1097 * @incr: increase next addr by incr bytes 1098 * @flags: access flags 1099 * 1100 * Update the page tables using sDMA. 1101 */ 1102 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1103 uint64_t pe, 1104 uint64_t addr, unsigned count, 1105 uint32_t incr, uint64_t flags) 1106 { 1107 /* for physically contiguous pages (vram) */ 1108 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1109 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1110 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1111 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1112 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1113 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1114 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1115 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1116 ib->ptr[ib->length_dw++] = 0; 1117 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1118 } 1119 1120 /** 1121 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1122 * 1123 * @ring: amdgpu_ring structure holding ring information 1124 * @ib: indirect buffer to fill with padding 1125 */ 1126 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1127 { 1128 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1129 u32 pad_count; 1130 int i; 1131 1132 pad_count = (-ib->length_dw) & 7; 1133 for (i = 0; i < pad_count; i++) 1134 if (sdma && sdma->burst_nop && (i == 0)) 1135 ib->ptr[ib->length_dw++] = 1136 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1137 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1138 else 1139 ib->ptr[ib->length_dw++] = 1140 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1141 } 1142 1143 1144 /** 1145 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1146 * 1147 * @ring: amdgpu_ring pointer 1148 * 1149 * Make sure all previous operations are completed (CIK). 1150 */ 1151 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1152 { 1153 uint32_t seq = ring->fence_drv.sync_seq; 1154 uint64_t addr = ring->fence_drv.gpu_addr; 1155 1156 /* wait for idle */ 1157 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1158 addr & 0xfffffffc, 1159 upper_32_bits(addr) & 0xffffffff, 1160 seq, 0xffffffff, 4); 1161 } 1162 1163 1164 /** 1165 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1166 * 1167 * @ring: amdgpu_ring pointer 1168 * @vmid: vmid number to use 1169 * @pd_addr: address 1170 * 1171 * Update the page table base and flush the VM TLB 1172 * using sDMA. 1173 */ 1174 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1175 unsigned vmid, uint64_t pd_addr) 1176 { 1177 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1178 } 1179 1180 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1181 uint32_t reg, uint32_t val) 1182 { 1183 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1184 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1185 amdgpu_ring_write(ring, reg); 1186 amdgpu_ring_write(ring, val); 1187 } 1188 1189 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1190 uint32_t val, uint32_t mask) 1191 { 1192 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1193 } 1194 1195 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1196 { 1197 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1198 case IP_VERSION(4, 4, 2): 1199 return false; 1200 default: 1201 return false; 1202 } 1203 } 1204 1205 static int sdma_v4_4_2_early_init(void *handle) 1206 { 1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1208 int r; 1209 1210 r = sdma_v4_4_2_init_microcode(adev); 1211 if (r) { 1212 DRM_ERROR("Failed to load sdma firmware!\n"); 1213 return r; 1214 } 1215 1216 /* TODO: Page queue breaks driver reload under SRIOV */ 1217 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1218 adev->sdma.has_page_queue = true; 1219 1220 sdma_v4_4_2_set_ring_funcs(adev); 1221 sdma_v4_4_2_set_buffer_funcs(adev); 1222 sdma_v4_4_2_set_vm_pte_funcs(adev); 1223 sdma_v4_4_2_set_irq_funcs(adev); 1224 1225 return 0; 1226 } 1227 1228 #if 0 1229 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1230 void *err_data, 1231 struct amdgpu_iv_entry *entry); 1232 #endif 1233 1234 static int sdma_v4_4_2_late_init(void *handle) 1235 { 1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1237 #if 0 1238 struct ras_ih_if ih_info = { 1239 .cb = sdma_v4_4_2_process_ras_data_cb, 1240 }; 1241 #endif 1242 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1243 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && 1244 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) 1245 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1246 } 1247 1248 return 0; 1249 } 1250 1251 static int sdma_v4_4_2_sw_init(void *handle) 1252 { 1253 struct amdgpu_ring *ring; 1254 int r, i; 1255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1256 1257 /* SDMA trap event */ 1258 for (i = 0; i < adev->sdma.num_instances; i++) { 1259 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1260 SDMA0_4_0__SRCID__SDMA_TRAP, 1261 &adev->sdma.trap_irq); 1262 if (r) 1263 return r; 1264 } 1265 1266 /* SDMA SRAM ECC event */ 1267 for (i = 0; i < adev->sdma.num_instances; i++) { 1268 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1269 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1270 &adev->sdma.ecc_irq); 1271 if (r) 1272 return r; 1273 } 1274 1275 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1276 for (i = 0; i < adev->sdma.num_instances; i++) { 1277 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1278 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1279 &adev->sdma.vm_hole_irq); 1280 if (r) 1281 return r; 1282 1283 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1284 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1285 &adev->sdma.doorbell_invalid_irq); 1286 if (r) 1287 return r; 1288 1289 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1290 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1291 &adev->sdma.pool_timeout_irq); 1292 if (r) 1293 return r; 1294 1295 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1296 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1297 &adev->sdma.srbm_write_irq); 1298 if (r) 1299 return r; 1300 } 1301 1302 for (i = 0; i < adev->sdma.num_instances; i++) { 1303 ring = &adev->sdma.instance[i].ring; 1304 ring->ring_obj = NULL; 1305 ring->use_doorbell = true; 1306 1307 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1308 ring->use_doorbell?"true":"false"); 1309 1310 /* doorbell size is 2 dwords, get DWORD offset */ 1311 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1312 1313 sprintf(ring->name, "sdma%d", i); 1314 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1315 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1316 AMDGPU_RING_PRIO_DEFAULT, NULL); 1317 if (r) 1318 return r; 1319 1320 if (adev->sdma.has_page_queue) { 1321 ring = &adev->sdma.instance[i].page; 1322 ring->ring_obj = NULL; 1323 ring->use_doorbell = true; 1324 1325 /* paging queue use same doorbell index/routing as gfx queue 1326 * with 0x400 (4096 dwords) offset on second doorbell page 1327 */ 1328 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1329 ring->doorbell_index += 0x400; 1330 1331 sprintf(ring->name, "page%d", i); 1332 r = amdgpu_ring_init(adev, ring, 1024, 1333 &adev->sdma.trap_irq, 1334 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1335 AMDGPU_RING_PRIO_DEFAULT, NULL); 1336 if (r) 1337 return r; 1338 } 1339 } 1340 1341 return r; 1342 } 1343 1344 static int sdma_v4_4_2_sw_fini(void *handle) 1345 { 1346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1347 int i; 1348 1349 for (i = 0; i < adev->sdma.num_instances; i++) { 1350 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1351 if (adev->sdma.has_page_queue) 1352 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1353 } 1354 1355 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2)) 1356 amdgpu_sdma_destroy_inst_ctx(adev, true); 1357 else 1358 amdgpu_sdma_destroy_inst_ctx(adev, false); 1359 1360 return 0; 1361 } 1362 1363 static int sdma_v4_4_2_hw_init(void *handle) 1364 { 1365 int r; 1366 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1367 1368 if (adev->flags & AMD_IS_APU) 1369 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1370 1371 if (!amdgpu_sriov_vf(adev)) 1372 sdma_v4_4_2_init_golden_registers(adev); 1373 1374 r = sdma_v4_4_2_start(adev); 1375 1376 return r; 1377 } 1378 1379 static int sdma_v4_4_2_hw_fini(void *handle) 1380 { 1381 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1382 int i; 1383 1384 if (amdgpu_sriov_vf(adev)) 1385 return 0; 1386 1387 for (i = 0; i < adev->sdma.num_instances; i++) { 1388 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1389 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1390 } 1391 1392 sdma_v4_4_2_ctx_switch_enable(adev, false); 1393 sdma_v4_4_2_enable(adev, false); 1394 1395 return 0; 1396 } 1397 1398 static int sdma_v4_4_2_suspend(void *handle) 1399 { 1400 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1401 1402 return sdma_v4_4_2_hw_fini(adev); 1403 } 1404 1405 static int sdma_v4_4_2_resume(void *handle) 1406 { 1407 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1408 1409 return sdma_v4_4_2_hw_init(adev); 1410 } 1411 1412 static bool sdma_v4_4_2_is_idle(void *handle) 1413 { 1414 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1415 u32 i; 1416 1417 for (i = 0; i < adev->sdma.num_instances; i++) { 1418 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1419 1420 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1421 return false; 1422 } 1423 1424 return true; 1425 } 1426 1427 static int sdma_v4_4_2_wait_for_idle(void *handle) 1428 { 1429 unsigned i, j; 1430 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1431 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1432 1433 for (i = 0; i < adev->usec_timeout; i++) { 1434 for (j = 0; j < adev->sdma.num_instances; j++) { 1435 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1436 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1437 break; 1438 } 1439 if (j == adev->sdma.num_instances) 1440 return 0; 1441 udelay(1); 1442 } 1443 return -ETIMEDOUT; 1444 } 1445 1446 static int sdma_v4_4_2_soft_reset(void *handle) 1447 { 1448 /* todo */ 1449 1450 return 0; 1451 } 1452 1453 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1454 struct amdgpu_irq_src *source, 1455 unsigned type, 1456 enum amdgpu_interrupt_state state) 1457 { 1458 u32 sdma_cntl; 1459 1460 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1461 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1462 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1463 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1464 1465 return 0; 1466 } 1467 1468 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1469 struct amdgpu_irq_src *source, 1470 struct amdgpu_iv_entry *entry) 1471 { 1472 uint32_t instance; 1473 1474 DRM_DEBUG("IH: SDMA trap\n"); 1475 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1476 switch (entry->ring_id) { 1477 case 0: 1478 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 1479 break; 1480 default: 1481 break; 1482 } 1483 return 0; 1484 } 1485 1486 #if 0 1487 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1488 void *err_data, 1489 struct amdgpu_iv_entry *entry) 1490 { 1491 int instance; 1492 1493 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1494 * be disabled and the driver should only look for the aggregated 1495 * interrupt via sync flood 1496 */ 1497 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 1498 goto out; 1499 1500 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1501 if (instance < 0) 1502 goto out; 1503 1504 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1505 1506 out: 1507 return AMDGPU_RAS_SUCCESS; 1508 } 1509 #endif 1510 1511 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1512 struct amdgpu_irq_src *source, 1513 struct amdgpu_iv_entry *entry) 1514 { 1515 int instance; 1516 1517 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1518 1519 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1520 if (instance < 0) 1521 return 0; 1522 1523 switch (entry->ring_id) { 1524 case 0: 1525 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1526 break; 1527 } 1528 return 0; 1529 } 1530 1531 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1532 struct amdgpu_irq_src *source, 1533 unsigned type, 1534 enum amdgpu_interrupt_state state) 1535 { 1536 u32 sdma_edc_config; 1537 1538 sdma_edc_config = RREG32_SDMA(type, regCC_SDMA_EDC_CONFIG); 1539 /* 1540 * FIXME: This was inherited from Aldebaran, but no this field 1541 * definition in the regspec of both Aldebaran and SDMA 4.4.2 1542 */ 1543 sdma_edc_config |= (state == AMDGPU_IRQ_STATE_ENABLE) ? (1 << 2) : 0; 1544 WREG32_SDMA(type, regCC_SDMA_EDC_CONFIG, sdma_edc_config); 1545 1546 return 0; 1547 } 1548 1549 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1550 struct amdgpu_iv_entry *entry) 1551 { 1552 int instance; 1553 struct amdgpu_task_info task_info; 1554 u64 addr; 1555 1556 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1557 if (instance < 0 || instance >= adev->sdma.num_instances) { 1558 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1559 return -EINVAL; 1560 } 1561 1562 addr = (u64)entry->src_data[0] << 12; 1563 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1564 1565 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 1566 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1567 1568 dev_dbg_ratelimited(adev->dev, 1569 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " 1570 "pasid:%u, for process %s pid %d thread %s pid %d\n", 1571 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1572 entry->pasid, task_info.process_name, task_info.tgid, 1573 task_info.task_name, task_info.pid); 1574 return 0; 1575 } 1576 1577 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1578 struct amdgpu_irq_src *source, 1579 struct amdgpu_iv_entry *entry) 1580 { 1581 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1582 sdma_v4_4_2_print_iv_entry(adev, entry); 1583 return 0; 1584 } 1585 1586 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1587 struct amdgpu_irq_src *source, 1588 struct amdgpu_iv_entry *entry) 1589 { 1590 1591 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1592 sdma_v4_4_2_print_iv_entry(adev, entry); 1593 return 0; 1594 } 1595 1596 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1597 struct amdgpu_irq_src *source, 1598 struct amdgpu_iv_entry *entry) 1599 { 1600 dev_dbg_ratelimited(adev->dev, 1601 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1602 sdma_v4_4_2_print_iv_entry(adev, entry); 1603 return 0; 1604 } 1605 1606 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1607 struct amdgpu_irq_src *source, 1608 struct amdgpu_iv_entry *entry) 1609 { 1610 dev_dbg_ratelimited(adev->dev, 1611 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1612 sdma_v4_4_2_print_iv_entry(adev, entry); 1613 return 0; 1614 } 1615 1616 static void sdma_v4_4_2_update_medium_grain_clock_gating( 1617 struct amdgpu_device *adev, 1618 bool enable) 1619 { 1620 uint32_t data, def; 1621 int i; 1622 1623 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1624 for (i = 0; i < adev->sdma.num_instances; i++) { 1625 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1626 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1627 SDMA_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1628 SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1629 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1630 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1631 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1632 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1633 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1634 if (def != data) 1635 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1636 } 1637 } else { 1638 for (i = 0; i < adev->sdma.num_instances; i++) { 1639 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1640 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1641 SDMA_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1642 SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1643 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1644 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1645 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1646 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1647 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1648 if (def != data) 1649 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1650 } 1651 } 1652 } 1653 1654 1655 static void sdma_v4_4_2_update_medium_grain_light_sleep( 1656 struct amdgpu_device *adev, 1657 bool enable) 1658 { 1659 uint32_t data, def; 1660 int i; 1661 1662 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1663 for (i = 0; i < adev->sdma.num_instances; i++) { 1664 /* 1-not override: enable sdma mem light sleep */ 1665 def = data = RREG32_SDMA(0, regSDMA_POWER_CNTL); 1666 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1667 if (def != data) 1668 WREG32_SDMA(0, regSDMA_POWER_CNTL, data); 1669 } 1670 } else { 1671 for (i = 0; i < adev->sdma.num_instances; i++) { 1672 /* 0-override:disable sdma mem light sleep */ 1673 def = data = RREG32_SDMA(0, regSDMA_POWER_CNTL); 1674 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1675 if (def != data) 1676 WREG32_SDMA(0, regSDMA_POWER_CNTL, data); 1677 } 1678 } 1679 } 1680 1681 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1682 enum amd_clockgating_state state) 1683 { 1684 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1685 1686 if (amdgpu_sriov_vf(adev)) 1687 return 0; 1688 1689 sdma_v4_4_2_update_medium_grain_clock_gating(adev, 1690 state == AMD_CG_STATE_GATE); 1691 sdma_v4_4_2_update_medium_grain_light_sleep(adev, 1692 state == AMD_CG_STATE_GATE); 1693 return 0; 1694 } 1695 1696 static int sdma_v4_4_2_set_powergating_state(void *handle, 1697 enum amd_powergating_state state) 1698 { 1699 return 0; 1700 } 1701 1702 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags) 1703 { 1704 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1705 int data; 1706 1707 if (amdgpu_sriov_vf(adev)) 1708 *flags = 0; 1709 1710 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1711 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, regSDMA_CLK_CTRL)); 1712 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1713 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1714 1715 /* AMD_CG_SUPPORT_SDMA_LS */ 1716 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, regSDMA_POWER_CNTL)); 1717 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1718 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1719 } 1720 1721 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 1722 .name = "sdma_v4_4_2", 1723 .early_init = sdma_v4_4_2_early_init, 1724 .late_init = sdma_v4_4_2_late_init, 1725 .sw_init = sdma_v4_4_2_sw_init, 1726 .sw_fini = sdma_v4_4_2_sw_fini, 1727 .hw_init = sdma_v4_4_2_hw_init, 1728 .hw_fini = sdma_v4_4_2_hw_fini, 1729 .suspend = sdma_v4_4_2_suspend, 1730 .resume = sdma_v4_4_2_resume, 1731 .is_idle = sdma_v4_4_2_is_idle, 1732 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 1733 .soft_reset = sdma_v4_4_2_soft_reset, 1734 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 1735 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 1736 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 1737 }; 1738 1739 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 1740 .type = AMDGPU_RING_TYPE_SDMA, 1741 .align_mask = 0xf, 1742 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1743 .support_64bit_ptrs = true, 1744 .vmhub = AMDGPU_MMHUB_0, 1745 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1746 .get_wptr = sdma_v4_4_2_ring_get_wptr, 1747 .set_wptr = sdma_v4_4_2_ring_set_wptr, 1748 .emit_frame_size = 1749 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1750 3 + /* hdp invalidate */ 1751 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1752 /* sdma_v4_4_2_ring_emit_vm_flush */ 1753 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1754 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1755 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1756 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1757 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1758 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1759 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1760 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1761 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1762 .test_ring = sdma_v4_4_2_ring_test_ring, 1763 .test_ib = sdma_v4_4_2_ring_test_ib, 1764 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1765 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1766 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1767 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1768 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1769 }; 1770 1771 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 1772 .type = AMDGPU_RING_TYPE_SDMA, 1773 .align_mask = 0xf, 1774 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1775 .support_64bit_ptrs = true, 1776 .vmhub = AMDGPU_MMHUB_0, 1777 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1778 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 1779 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 1780 .emit_frame_size = 1781 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1782 3 + /* hdp invalidate */ 1783 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1784 /* sdma_v4_4_2_ring_emit_vm_flush */ 1785 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1786 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1787 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1788 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1789 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1790 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1791 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1792 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1793 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1794 .test_ring = sdma_v4_4_2_ring_test_ring, 1795 .test_ib = sdma_v4_4_2_ring_test_ib, 1796 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1797 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1798 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1799 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1800 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1801 }; 1802 1803 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 1804 { 1805 int i; 1806 1807 for (i = 0; i < adev->sdma.num_instances; i++) { 1808 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 1809 adev->sdma.instance[i].ring.me = i; 1810 if (adev->sdma.has_page_queue) { 1811 adev->sdma.instance[i].page.funcs = 1812 &sdma_v4_4_2_page_ring_funcs; 1813 adev->sdma.instance[i].page.me = i; 1814 } 1815 } 1816 } 1817 1818 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 1819 .set = sdma_v4_4_2_set_trap_irq_state, 1820 .process = sdma_v4_4_2_process_trap_irq, 1821 }; 1822 1823 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 1824 .process = sdma_v4_4_2_process_illegal_inst_irq, 1825 }; 1826 1827 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 1828 .set = sdma_v4_4_2_set_ecc_irq_state, 1829 .process = amdgpu_sdma_process_ecc_irq, 1830 }; 1831 1832 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 1833 .process = sdma_v4_4_2_process_vm_hole_irq, 1834 }; 1835 1836 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 1837 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 1838 }; 1839 1840 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 1841 .process = sdma_v4_4_2_process_pool_timeout_irq, 1842 }; 1843 1844 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 1845 .process = sdma_v4_4_2_process_srbm_write_irq, 1846 }; 1847 1848 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 1849 { 1850 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 1851 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 1852 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 1853 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 1854 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 1855 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 1856 1857 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 1858 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 1859 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 1860 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 1861 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 1862 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 1863 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 1864 } 1865 1866 /** 1867 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 1868 * 1869 * @ib: indirect buffer to copy to 1870 * @src_offset: src GPU address 1871 * @dst_offset: dst GPU address 1872 * @byte_count: number of bytes to xfer 1873 * @tmz: if a secure copy should be used 1874 * 1875 * Copy GPU buffers using the DMA engine. 1876 * Used by the amdgpu ttm implementation to move pages if 1877 * registered as the asic copy callback. 1878 */ 1879 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 1880 uint64_t src_offset, 1881 uint64_t dst_offset, 1882 uint32_t byte_count, 1883 bool tmz) 1884 { 1885 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1886 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1887 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1888 ib->ptr[ib->length_dw++] = byte_count - 1; 1889 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1890 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1891 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1892 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1893 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1894 } 1895 1896 /** 1897 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 1898 * 1899 * @ib: indirect buffer to copy to 1900 * @src_data: value to write to buffer 1901 * @dst_offset: dst GPU address 1902 * @byte_count: number of bytes to xfer 1903 * 1904 * Fill GPU buffers using the DMA engine. 1905 */ 1906 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 1907 uint32_t src_data, 1908 uint64_t dst_offset, 1909 uint32_t byte_count) 1910 { 1911 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1912 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1913 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1914 ib->ptr[ib->length_dw++] = src_data; 1915 ib->ptr[ib->length_dw++] = byte_count - 1; 1916 } 1917 1918 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 1919 .copy_max_bytes = 0x400000, 1920 .copy_num_dw = 7, 1921 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 1922 1923 .fill_max_bytes = 0x400000, 1924 .fill_num_dw = 5, 1925 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 1926 }; 1927 1928 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 1929 { 1930 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 1931 if (adev->sdma.has_page_queue) 1932 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 1933 else 1934 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1935 } 1936 1937 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 1938 .copy_pte_num_dw = 7, 1939 .copy_pte = sdma_v4_4_2_vm_copy_pte, 1940 1941 .write_pte = sdma_v4_4_2_vm_write_pte, 1942 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 1943 }; 1944 1945 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1946 { 1947 struct drm_gpu_scheduler *sched; 1948 unsigned i; 1949 1950 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 1951 for (i = 0; i < adev->sdma.num_instances; i++) { 1952 if (adev->sdma.has_page_queue) 1953 sched = &adev->sdma.instance[i].page.sched; 1954 else 1955 sched = &adev->sdma.instance[i].ring.sched; 1956 adev->vm_manager.vm_pte_scheds[i] = sched; 1957 } 1958 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1959 } 1960 1961 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 1962 .type = AMD_IP_BLOCK_TYPE_SDMA, 1963 .major = 4, 1964 .minor = 4, 1965 .rev = 0, 1966 .funcs = &sdma_v4_4_2_ip_funcs, 1967 }; 1968