1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 34 #include "sdma/sdma_4_4_2_offset.h" 35 #include "sdma/sdma_4_4_2_sh_mask.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 #include "amdgpu_ras.h" 45 46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 47 48 #define WREG32_SDMA(instance, offset, value) \ 49 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 50 #define RREG32_SDMA(instance, offset) \ 51 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 52 53 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 54 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 55 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 56 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 57 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 58 59 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 60 u32 instance, u32 offset) 61 { 62 u32 dev_inst = GET_INST(SDMA0, instance); 63 64 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 65 } 66 67 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 68 { 69 switch (seq_num) { 70 case 0: 71 return SOC15_IH_CLIENTID_SDMA0; 72 case 1: 73 return SOC15_IH_CLIENTID_SDMA1; 74 case 2: 75 return SOC15_IH_CLIENTID_SDMA2; 76 case 3: 77 return SOC15_IH_CLIENTID_SDMA3; 78 default: 79 return -EINVAL; 80 } 81 } 82 83 static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id) 84 { 85 switch (client_id) { 86 case SOC15_IH_CLIENTID_SDMA0: 87 return 0; 88 case SOC15_IH_CLIENTID_SDMA1: 89 return 1; 90 case SOC15_IH_CLIENTID_SDMA2: 91 return 2; 92 case SOC15_IH_CLIENTID_SDMA3: 93 return 3; 94 default: 95 return -EINVAL; 96 } 97 } 98 99 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 100 uint32_t inst_mask) 101 { 102 u32 val; 103 int i; 104 105 for (i = 0; i < adev->sdma.num_instances; i++) { 106 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 107 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 108 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 109 PIPE_INTERLEAVE_SIZE, 0); 110 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 111 112 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 113 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 114 4); 115 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 116 PIPE_INTERLEAVE_SIZE, 0); 117 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 118 } 119 } 120 121 /** 122 * sdma_v4_4_2_init_microcode - load ucode images from disk 123 * 124 * @adev: amdgpu_device pointer 125 * 126 * Use the firmware interface to load the ucode images into 127 * the driver (not loaded into hw). 128 * Returns 0 on success, error on failure. 129 */ 130 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 131 { 132 int ret, i; 133 134 for (i = 0; i < adev->sdma.num_instances; i++) { 135 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2)) { 136 ret = amdgpu_sdma_init_microcode(adev, 0, true); 137 break; 138 } else { 139 ret = amdgpu_sdma_init_microcode(adev, i, false); 140 if (ret) 141 return ret; 142 } 143 } 144 145 return ret; 146 } 147 148 /** 149 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 150 * 151 * @ring: amdgpu ring pointer 152 * 153 * Get the current rptr from the hardware. 154 */ 155 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 156 { 157 u64 *rptr; 158 159 /* XXX check if swapping is necessary on BE */ 160 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 161 162 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 163 return ((*rptr) >> 2); 164 } 165 166 /** 167 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 168 * 169 * @ring: amdgpu ring pointer 170 * 171 * Get the current wptr from the hardware. 172 */ 173 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 174 { 175 struct amdgpu_device *adev = ring->adev; 176 u64 wptr; 177 178 if (ring->use_doorbell) { 179 /* XXX check if swapping is necessary on BE */ 180 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 181 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 182 } else { 183 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 184 wptr = wptr << 32; 185 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 186 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 187 ring->me, wptr); 188 } 189 190 return wptr >> 2; 191 } 192 193 /** 194 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 195 * 196 * @ring: amdgpu ring pointer 197 * 198 * Write the wptr back to the hardware. 199 */ 200 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 201 { 202 struct amdgpu_device *adev = ring->adev; 203 204 DRM_DEBUG("Setting write pointer\n"); 205 if (ring->use_doorbell) { 206 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 207 208 DRM_DEBUG("Using doorbell -- " 209 "wptr_offs == 0x%08x " 210 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 211 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 212 ring->wptr_offs, 213 lower_32_bits(ring->wptr << 2), 214 upper_32_bits(ring->wptr << 2)); 215 /* XXX check if swapping is necessary on BE */ 216 WRITE_ONCE(*wb, (ring->wptr << 2)); 217 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 218 ring->doorbell_index, ring->wptr << 2); 219 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 220 } else { 221 DRM_DEBUG("Not using doorbell -- " 222 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 223 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 224 ring->me, 225 lower_32_bits(ring->wptr << 2), 226 ring->me, 227 upper_32_bits(ring->wptr << 2)); 228 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 229 lower_32_bits(ring->wptr << 2)); 230 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 231 upper_32_bits(ring->wptr << 2)); 232 } 233 } 234 235 /** 236 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 237 * 238 * @ring: amdgpu ring pointer 239 * 240 * Get the current wptr from the hardware. 241 */ 242 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 243 { 244 struct amdgpu_device *adev = ring->adev; 245 u64 wptr; 246 247 if (ring->use_doorbell) { 248 /* XXX check if swapping is necessary on BE */ 249 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 250 } else { 251 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 252 wptr = wptr << 32; 253 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 254 } 255 256 return wptr >> 2; 257 } 258 259 /** 260 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 261 * 262 * @ring: amdgpu ring pointer 263 * 264 * Write the wptr back to the hardware. 265 */ 266 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 267 { 268 struct amdgpu_device *adev = ring->adev; 269 270 if (ring->use_doorbell) { 271 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 272 273 /* XXX check if swapping is necessary on BE */ 274 WRITE_ONCE(*wb, (ring->wptr << 2)); 275 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 276 } else { 277 uint64_t wptr = ring->wptr << 2; 278 279 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 280 lower_32_bits(wptr)); 281 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 282 upper_32_bits(wptr)); 283 } 284 } 285 286 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 287 { 288 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 289 int i; 290 291 for (i = 0; i < count; i++) 292 if (sdma && sdma->burst_nop && (i == 0)) 293 amdgpu_ring_write(ring, ring->funcs->nop | 294 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 295 else 296 amdgpu_ring_write(ring, ring->funcs->nop); 297 } 298 299 /** 300 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 301 * 302 * @ring: amdgpu ring pointer 303 * @job: job to retrieve vmid from 304 * @ib: IB object to schedule 305 * @flags: unused 306 * 307 * Schedule an IB in the DMA ring. 308 */ 309 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 310 struct amdgpu_job *job, 311 struct amdgpu_ib *ib, 312 uint32_t flags) 313 { 314 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 315 316 /* IB packet must end on a 8 DW boundary */ 317 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 318 319 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 320 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 321 /* base must be 32 byte aligned */ 322 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 323 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 324 amdgpu_ring_write(ring, ib->length_dw); 325 amdgpu_ring_write(ring, 0); 326 amdgpu_ring_write(ring, 0); 327 328 } 329 330 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 331 int mem_space, int hdp, 332 uint32_t addr0, uint32_t addr1, 333 uint32_t ref, uint32_t mask, 334 uint32_t inv) 335 { 336 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 337 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 338 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 339 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 340 if (mem_space) { 341 /* memory */ 342 amdgpu_ring_write(ring, addr0); 343 amdgpu_ring_write(ring, addr1); 344 } else { 345 /* registers */ 346 amdgpu_ring_write(ring, addr0 << 2); 347 amdgpu_ring_write(ring, addr1 << 2); 348 } 349 amdgpu_ring_write(ring, ref); /* reference */ 350 amdgpu_ring_write(ring, mask); /* mask */ 351 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 352 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 353 } 354 355 /** 356 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 357 * 358 * @ring: amdgpu ring pointer 359 * 360 * Emit an hdp flush packet on the requested DMA ring. 361 */ 362 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 363 { 364 struct amdgpu_device *adev = ring->adev; 365 u32 ref_and_mask = 0; 366 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 367 368 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 369 370 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 371 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 372 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 373 ref_and_mask, ref_and_mask, 10); 374 } 375 376 /** 377 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 378 * 379 * @ring: amdgpu ring pointer 380 * @addr: address 381 * @seq: sequence number 382 * @flags: fence related flags 383 * 384 * Add a DMA fence packet to the ring to write 385 * the fence seq number and DMA trap packet to generate 386 * an interrupt if needed. 387 */ 388 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 389 unsigned flags) 390 { 391 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 392 /* write the fence */ 393 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 394 /* zero in first two bits */ 395 BUG_ON(addr & 0x3); 396 amdgpu_ring_write(ring, lower_32_bits(addr)); 397 amdgpu_ring_write(ring, upper_32_bits(addr)); 398 amdgpu_ring_write(ring, lower_32_bits(seq)); 399 400 /* optionally write high bits as well */ 401 if (write64bit) { 402 addr += 4; 403 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 404 /* zero in first two bits */ 405 BUG_ON(addr & 0x3); 406 amdgpu_ring_write(ring, lower_32_bits(addr)); 407 amdgpu_ring_write(ring, upper_32_bits(addr)); 408 amdgpu_ring_write(ring, upper_32_bits(seq)); 409 } 410 411 /* generate an interrupt */ 412 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 413 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 414 } 415 416 417 /** 418 * sdma_v4_4_2_gfx_stop - stop the gfx async dma engines 419 * 420 * @adev: amdgpu_device pointer 421 * 422 * Stop the gfx async dma ring buffers. 423 */ 424 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 425 uint32_t inst_mask) 426 { 427 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 428 u32 rb_cntl, ib_cntl; 429 int i, unset = 0; 430 431 for_each_inst(i, inst_mask) { 432 sdma[i] = &adev->sdma.instance[i].ring; 433 434 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 435 amdgpu_ttm_set_buffer_funcs_status(adev, false); 436 unset = 1; 437 } 438 439 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 440 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 441 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 442 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 443 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 444 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 445 } 446 } 447 448 /** 449 * sdma_v4_4_2_rlc_stop - stop the compute async dma engines 450 * 451 * @adev: amdgpu_device pointer 452 * 453 * Stop the compute async dma queues. 454 */ 455 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 456 uint32_t inst_mask) 457 { 458 /* XXX todo */ 459 } 460 461 /** 462 * sdma_v4_4_2_page_stop - stop the page async dma engines 463 * 464 * @adev: amdgpu_device pointer 465 * 466 * Stop the page async dma ring buffers. 467 */ 468 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 469 uint32_t inst_mask) 470 { 471 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 472 u32 rb_cntl, ib_cntl; 473 int i; 474 bool unset = false; 475 476 for_each_inst(i, inst_mask) { 477 sdma[i] = &adev->sdma.instance[i].page; 478 479 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 480 (!unset)) { 481 amdgpu_ttm_set_buffer_funcs_status(adev, false); 482 unset = true; 483 } 484 485 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 486 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 487 RB_ENABLE, 0); 488 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 489 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 490 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 491 IB_ENABLE, 0); 492 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 493 } 494 } 495 496 /** 497 * sdma_v4_4_2_ctx_switch_enable - stop the async dma engines context switch 498 * 499 * @adev: amdgpu_device pointer 500 * @enable: enable/disable the DMA MEs context switch. 501 * 502 * Halt or unhalt the async dma engines context switch. 503 */ 504 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 505 bool enable, uint32_t inst_mask) 506 { 507 u32 f32_cntl, phase_quantum = 0; 508 int i; 509 510 if (amdgpu_sdma_phase_quantum) { 511 unsigned value = amdgpu_sdma_phase_quantum; 512 unsigned unit = 0; 513 514 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 515 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 516 value = (value + 1) >> 1; 517 unit++; 518 } 519 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 520 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 521 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 522 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 523 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 524 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 525 WARN_ONCE(1, 526 "clamping sdma_phase_quantum to %uK clock cycles\n", 527 value << unit); 528 } 529 phase_quantum = 530 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 531 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 532 } 533 534 for_each_inst(i, inst_mask) { 535 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 536 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 537 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 538 if (enable && amdgpu_sdma_phase_quantum) { 539 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 540 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 541 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 542 } 543 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 544 545 /* Extend page fault timeout to avoid interrupt storm */ 546 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 547 } 548 } 549 550 /** 551 * sdma_v4_4_2_enable - stop the async dma engines 552 * 553 * @adev: amdgpu_device pointer 554 * @enable: enable/disable the DMA MEs. 555 * @inst_mask: mask of dma engine instances to be enabled 556 * 557 * Halt or unhalt the async dma engines. 558 */ 559 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 560 uint32_t inst_mask) 561 { 562 u32 f32_cntl; 563 int i; 564 565 if (!enable) { 566 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 567 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 568 if (adev->sdma.has_page_queue) 569 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 570 571 /* SDMA FW needs to respond to FREEZE requests during reset. 572 * Keep it running during reset */ 573 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 574 return; 575 } 576 577 for_each_inst(i, inst_mask) { 578 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 579 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 580 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 581 } 582 } 583 584 /* 585 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 586 */ 587 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 588 { 589 /* Set ring buffer size in dwords */ 590 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 591 592 barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */ 593 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 594 #ifdef __BIG_ENDIAN 595 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 596 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 597 RPTR_WRITEBACK_SWAP_ENABLE, 1); 598 #endif 599 return rb_cntl; 600 } 601 602 /** 603 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 604 * 605 * @adev: amdgpu_device pointer 606 * @i: instance to resume 607 * 608 * Set up the gfx DMA ring buffers and enable them. 609 * Returns 0 for success, error for failure. 610 */ 611 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i) 612 { 613 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 614 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 615 u32 wb_offset; 616 u32 doorbell; 617 u32 doorbell_offset; 618 u64 wptr_gpu_addr; 619 620 wb_offset = (ring->rptr_offs * 4); 621 622 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 623 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 624 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 625 626 /* Initialize the ring buffer's read and write pointers */ 627 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 628 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 629 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 630 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 631 632 /* set the wb address whether it's enabled or not */ 633 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 634 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 635 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 636 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 637 638 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 639 RPTR_WRITEBACK_ENABLE, 1); 640 641 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 642 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 643 644 ring->wptr = 0; 645 646 /* before programing wptr to a less value, need set minor_ptr_update first */ 647 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 648 649 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 650 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 651 652 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 653 ring->use_doorbell); 654 doorbell_offset = REG_SET_FIELD(doorbell_offset, 655 SDMA_GFX_DOORBELL_OFFSET, 656 OFFSET, ring->doorbell_index); 657 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 658 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 659 660 sdma_v4_4_2_ring_set_wptr(ring); 661 662 /* set minor_ptr_update to 0 after wptr programed */ 663 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 664 665 /* setup the wptr shadow polling */ 666 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 667 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 668 lower_32_bits(wptr_gpu_addr)); 669 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 670 upper_32_bits(wptr_gpu_addr)); 671 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 672 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 673 SDMA_GFX_RB_WPTR_POLL_CNTL, 674 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 675 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 676 677 /* enable DMA RB */ 678 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 679 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 680 681 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 682 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 683 #ifdef __BIG_ENDIAN 684 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 685 #endif 686 /* enable DMA IBs */ 687 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 688 689 ring->sched.ready = true; 690 } 691 692 /** 693 * sdma_v4_4_2_page_resume - setup and start the async dma engines 694 * 695 * @adev: amdgpu_device pointer 696 * @i: instance to resume 697 * 698 * Set up the page DMA ring buffers and enable them. 699 * Returns 0 for success, error for failure. 700 */ 701 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i) 702 { 703 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 704 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 705 u32 wb_offset; 706 u32 doorbell; 707 u32 doorbell_offset; 708 u64 wptr_gpu_addr; 709 710 wb_offset = (ring->rptr_offs * 4); 711 712 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 713 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 714 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 715 716 /* Initialize the ring buffer's read and write pointers */ 717 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 718 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 719 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 720 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 721 722 /* set the wb address whether it's enabled or not */ 723 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 724 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 725 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 726 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 727 728 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 729 RPTR_WRITEBACK_ENABLE, 1); 730 731 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 732 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 733 734 ring->wptr = 0; 735 736 /* before programing wptr to a less value, need set minor_ptr_update first */ 737 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 738 739 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 740 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 741 742 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 743 ring->use_doorbell); 744 doorbell_offset = REG_SET_FIELD(doorbell_offset, 745 SDMA_PAGE_DOORBELL_OFFSET, 746 OFFSET, ring->doorbell_index); 747 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 748 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 749 750 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 751 sdma_v4_4_2_page_ring_set_wptr(ring); 752 753 /* set minor_ptr_update to 0 after wptr programed */ 754 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 755 756 /* setup the wptr shadow polling */ 757 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 758 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 759 lower_32_bits(wptr_gpu_addr)); 760 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 761 upper_32_bits(wptr_gpu_addr)); 762 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 763 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 764 SDMA_PAGE_RB_WPTR_POLL_CNTL, 765 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 766 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 767 768 /* enable DMA RB */ 769 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 770 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 771 772 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 773 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 774 #ifdef __BIG_ENDIAN 775 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 776 #endif 777 /* enable DMA IBs */ 778 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 779 780 ring->sched.ready = true; 781 } 782 783 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 784 { 785 786 } 787 788 /** 789 * sdma_v4_4_2_rlc_resume - setup and start the async dma engines 790 * 791 * @adev: amdgpu_device pointer 792 * 793 * Set up the compute DMA queues and enable them. 794 * Returns 0 for success, error for failure. 795 */ 796 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 797 uint32_t inst_mask) 798 { 799 sdma_v4_4_2_init_pg(adev); 800 801 return 0; 802 } 803 804 /** 805 * sdma_v4_4_2_load_microcode - load the sDMA ME ucode 806 * 807 * @adev: amdgpu_device pointer 808 * 809 * Loads the sDMA0/1 ucode. 810 * Returns 0 for success, -EINVAL if the ucode is not available. 811 */ 812 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 813 uint32_t inst_mask) 814 { 815 const struct sdma_firmware_header_v1_0 *hdr; 816 const __le32 *fw_data; 817 u32 fw_size; 818 int i, j; 819 820 /* halt the MEs */ 821 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 822 823 for_each_inst(i, inst_mask) { 824 if (!adev->sdma.instance[i].fw) 825 return -EINVAL; 826 827 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 828 amdgpu_ucode_print_sdma_hdr(&hdr->header); 829 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 830 831 fw_data = (const __le32 *) 832 (adev->sdma.instance[i].fw->data + 833 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 834 835 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 836 837 for (j = 0; j < fw_size; j++) 838 WREG32_SDMA(i, regSDMA_UCODE_DATA, 839 le32_to_cpup(fw_data++)); 840 841 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 842 adev->sdma.instance[i].fw_version); 843 } 844 845 return 0; 846 } 847 848 /** 849 * sdma_v4_4_2_inst_start - setup and start the async dma engines 850 * 851 * @adev: amdgpu_device pointer 852 * 853 * Set up the DMA engines and enable them. 854 * Returns 0 for success, error for failure. 855 */ 856 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 857 uint32_t inst_mask) 858 { 859 struct amdgpu_ring *ring; 860 uint32_t tmp_mask; 861 int i, r = 0; 862 863 if (amdgpu_sriov_vf(adev)) { 864 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 865 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 866 } else { 867 /* bypass sdma microcode loading on Gopher */ 868 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 869 adev->sdma.instance[0].fw) { 870 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 871 if (r) 872 return r; 873 } 874 875 /* unhalt the MEs */ 876 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 877 /* enable sdma ring preemption */ 878 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 879 } 880 881 /* start the gfx rings and rlc compute queues */ 882 tmp_mask = inst_mask; 883 for_each_inst(i, tmp_mask) { 884 uint32_t temp; 885 886 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 887 sdma_v4_4_2_gfx_resume(adev, i); 888 if (adev->sdma.has_page_queue) 889 sdma_v4_4_2_page_resume(adev, i); 890 891 /* set utc l1 enable flag always to 1 */ 892 temp = RREG32_SDMA(i, regSDMA_CNTL); 893 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 894 /* enable context empty interrupt during initialization */ 895 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 896 WREG32_SDMA(i, regSDMA_CNTL, temp); 897 898 if (!amdgpu_sriov_vf(adev)) { 899 ring = &adev->sdma.instance[i].ring; 900 adev->nbio.funcs->sdma_doorbell_range(adev, i, 901 ring->use_doorbell, ring->doorbell_index, 902 adev->doorbell_index.sdma_doorbell_range); 903 904 /* unhalt engine */ 905 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 906 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 907 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 908 } 909 } 910 911 if (amdgpu_sriov_vf(adev)) { 912 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 913 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 914 } else { 915 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 916 if (r) 917 return r; 918 } 919 920 tmp_mask = inst_mask; 921 for_each_inst(i, tmp_mask) { 922 ring = &adev->sdma.instance[i].ring; 923 924 r = amdgpu_ring_test_helper(ring); 925 if (r) 926 return r; 927 928 if (adev->sdma.has_page_queue) { 929 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 930 931 r = amdgpu_ring_test_helper(page); 932 if (r) 933 return r; 934 935 if (adev->mman.buffer_funcs_ring == page) 936 amdgpu_ttm_set_buffer_funcs_status(adev, true); 937 } 938 939 if (adev->mman.buffer_funcs_ring == ring) 940 amdgpu_ttm_set_buffer_funcs_status(adev, true); 941 } 942 943 return r; 944 } 945 946 /** 947 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 948 * 949 * @ring: amdgpu_ring structure holding ring information 950 * 951 * Test the DMA engine by writing using it to write an 952 * value to memory. 953 * Returns 0 for success, error for failure. 954 */ 955 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 956 { 957 struct amdgpu_device *adev = ring->adev; 958 unsigned i; 959 unsigned index; 960 int r; 961 u32 tmp; 962 u64 gpu_addr; 963 964 r = amdgpu_device_wb_get(adev, &index); 965 if (r) 966 return r; 967 968 gpu_addr = adev->wb.gpu_addr + (index * 4); 969 tmp = 0xCAFEDEAD; 970 adev->wb.wb[index] = cpu_to_le32(tmp); 971 972 r = amdgpu_ring_alloc(ring, 5); 973 if (r) 974 goto error_free_wb; 975 976 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 977 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 978 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 979 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 980 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 981 amdgpu_ring_write(ring, 0xDEADBEEF); 982 amdgpu_ring_commit(ring); 983 984 for (i = 0; i < adev->usec_timeout; i++) { 985 tmp = le32_to_cpu(adev->wb.wb[index]); 986 if (tmp == 0xDEADBEEF) 987 break; 988 udelay(1); 989 } 990 991 if (i >= adev->usec_timeout) 992 r = -ETIMEDOUT; 993 994 error_free_wb: 995 amdgpu_device_wb_free(adev, index); 996 return r; 997 } 998 999 /** 1000 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1001 * 1002 * @ring: amdgpu_ring structure holding ring information 1003 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1004 * 1005 * Test a simple IB in the DMA ring. 1006 * Returns 0 on success, error on failure. 1007 */ 1008 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1009 { 1010 struct amdgpu_device *adev = ring->adev; 1011 struct amdgpu_ib ib; 1012 struct dma_fence *f = NULL; 1013 unsigned index; 1014 long r; 1015 u32 tmp = 0; 1016 u64 gpu_addr; 1017 1018 r = amdgpu_device_wb_get(adev, &index); 1019 if (r) 1020 return r; 1021 1022 gpu_addr = adev->wb.gpu_addr + (index * 4); 1023 tmp = 0xCAFEDEAD; 1024 adev->wb.wb[index] = cpu_to_le32(tmp); 1025 memset(&ib, 0, sizeof(ib)); 1026 r = amdgpu_ib_get(adev, NULL, 256, 1027 AMDGPU_IB_POOL_DIRECT, &ib); 1028 if (r) 1029 goto err0; 1030 1031 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1032 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1033 ib.ptr[1] = lower_32_bits(gpu_addr); 1034 ib.ptr[2] = upper_32_bits(gpu_addr); 1035 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1036 ib.ptr[4] = 0xDEADBEEF; 1037 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1038 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1039 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1040 ib.length_dw = 8; 1041 1042 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1043 if (r) 1044 goto err1; 1045 1046 r = dma_fence_wait_timeout(f, false, timeout); 1047 if (r == 0) { 1048 r = -ETIMEDOUT; 1049 goto err1; 1050 } else if (r < 0) { 1051 goto err1; 1052 } 1053 tmp = le32_to_cpu(adev->wb.wb[index]); 1054 if (tmp == 0xDEADBEEF) 1055 r = 0; 1056 else 1057 r = -EINVAL; 1058 1059 err1: 1060 amdgpu_ib_free(adev, &ib, NULL); 1061 dma_fence_put(f); 1062 err0: 1063 amdgpu_device_wb_free(adev, index); 1064 return r; 1065 } 1066 1067 1068 /** 1069 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1070 * 1071 * @ib: indirect buffer to fill with commands 1072 * @pe: addr of the page entry 1073 * @src: src addr to copy from 1074 * @count: number of page entries to update 1075 * 1076 * Update PTEs by copying them from the GART using sDMA. 1077 */ 1078 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1079 uint64_t pe, uint64_t src, 1080 unsigned count) 1081 { 1082 unsigned bytes = count * 8; 1083 1084 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1085 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1086 ib->ptr[ib->length_dw++] = bytes - 1; 1087 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1088 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1089 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1090 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1091 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1092 1093 } 1094 1095 /** 1096 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1097 * 1098 * @ib: indirect buffer to fill with commands 1099 * @pe: addr of the page entry 1100 * @value: dst addr to write into pe 1101 * @count: number of page entries to update 1102 * @incr: increase next addr by incr bytes 1103 * 1104 * Update PTEs by writing them manually using sDMA. 1105 */ 1106 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1107 uint64_t value, unsigned count, 1108 uint32_t incr) 1109 { 1110 unsigned ndw = count * 2; 1111 1112 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1113 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1114 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1115 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1116 ib->ptr[ib->length_dw++] = ndw - 1; 1117 for (; ndw > 0; ndw -= 2) { 1118 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1119 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1120 value += incr; 1121 } 1122 } 1123 1124 /** 1125 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1126 * 1127 * @ib: indirect buffer to fill with commands 1128 * @pe: addr of the page entry 1129 * @addr: dst addr to write into pe 1130 * @count: number of page entries to update 1131 * @incr: increase next addr by incr bytes 1132 * @flags: access flags 1133 * 1134 * Update the page tables using sDMA. 1135 */ 1136 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1137 uint64_t pe, 1138 uint64_t addr, unsigned count, 1139 uint32_t incr, uint64_t flags) 1140 { 1141 /* for physically contiguous pages (vram) */ 1142 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1143 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1144 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1145 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1146 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1147 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1148 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1149 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1150 ib->ptr[ib->length_dw++] = 0; 1151 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1152 } 1153 1154 /** 1155 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1156 * 1157 * @ring: amdgpu_ring structure holding ring information 1158 * @ib: indirect buffer to fill with padding 1159 */ 1160 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1161 { 1162 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1163 u32 pad_count; 1164 int i; 1165 1166 pad_count = (-ib->length_dw) & 7; 1167 for (i = 0; i < pad_count; i++) 1168 if (sdma && sdma->burst_nop && (i == 0)) 1169 ib->ptr[ib->length_dw++] = 1170 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1171 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1172 else 1173 ib->ptr[ib->length_dw++] = 1174 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1175 } 1176 1177 1178 /** 1179 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1180 * 1181 * @ring: amdgpu_ring pointer 1182 * 1183 * Make sure all previous operations are completed (CIK). 1184 */ 1185 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1186 { 1187 uint32_t seq = ring->fence_drv.sync_seq; 1188 uint64_t addr = ring->fence_drv.gpu_addr; 1189 1190 /* wait for idle */ 1191 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1192 addr & 0xfffffffc, 1193 upper_32_bits(addr) & 0xffffffff, 1194 seq, 0xffffffff, 4); 1195 } 1196 1197 1198 /** 1199 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1200 * 1201 * @ring: amdgpu_ring pointer 1202 * @vmid: vmid number to use 1203 * @pd_addr: address 1204 * 1205 * Update the page table base and flush the VM TLB 1206 * using sDMA. 1207 */ 1208 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1209 unsigned vmid, uint64_t pd_addr) 1210 { 1211 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1212 } 1213 1214 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1215 uint32_t reg, uint32_t val) 1216 { 1217 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1218 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1219 amdgpu_ring_write(ring, reg); 1220 amdgpu_ring_write(ring, val); 1221 } 1222 1223 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1224 uint32_t val, uint32_t mask) 1225 { 1226 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1227 } 1228 1229 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1230 { 1231 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1232 case IP_VERSION(4, 4, 2): 1233 return false; 1234 default: 1235 return false; 1236 } 1237 } 1238 1239 static int sdma_v4_4_2_early_init(void *handle) 1240 { 1241 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1242 int r; 1243 1244 r = sdma_v4_4_2_init_microcode(adev); 1245 if (r) { 1246 DRM_ERROR("Failed to load sdma firmware!\n"); 1247 return r; 1248 } 1249 1250 /* TODO: Page queue breaks driver reload under SRIOV */ 1251 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1252 adev->sdma.has_page_queue = true; 1253 1254 sdma_v4_4_2_set_ring_funcs(adev); 1255 sdma_v4_4_2_set_buffer_funcs(adev); 1256 sdma_v4_4_2_set_vm_pte_funcs(adev); 1257 sdma_v4_4_2_set_irq_funcs(adev); 1258 sdma_v4_4_2_set_ras_funcs(adev); 1259 1260 return 0; 1261 } 1262 1263 #if 0 1264 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1265 void *err_data, 1266 struct amdgpu_iv_entry *entry); 1267 #endif 1268 1269 static int sdma_v4_4_2_late_init(void *handle) 1270 { 1271 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1272 #if 0 1273 struct ras_ih_if ih_info = { 1274 .cb = sdma_v4_4_2_process_ras_data_cb, 1275 }; 1276 #endif 1277 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1278 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && 1279 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) 1280 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1281 } 1282 1283 return 0; 1284 } 1285 1286 static int sdma_v4_4_2_sw_init(void *handle) 1287 { 1288 struct amdgpu_ring *ring; 1289 int r, i; 1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1291 u32 aid_id; 1292 1293 /* SDMA trap event */ 1294 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1295 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1296 SDMA0_4_0__SRCID__SDMA_TRAP, 1297 &adev->sdma.trap_irq); 1298 if (r) 1299 return r; 1300 } 1301 1302 /* SDMA SRAM ECC event */ 1303 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1304 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1305 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1306 &adev->sdma.ecc_irq); 1307 if (r) 1308 return r; 1309 } 1310 1311 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1312 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1313 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1314 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1315 &adev->sdma.vm_hole_irq); 1316 if (r) 1317 return r; 1318 1319 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1320 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1321 &adev->sdma.doorbell_invalid_irq); 1322 if (r) 1323 return r; 1324 1325 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1326 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1327 &adev->sdma.pool_timeout_irq); 1328 if (r) 1329 return r; 1330 1331 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1332 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1333 &adev->sdma.srbm_write_irq); 1334 if (r) 1335 return r; 1336 } 1337 1338 for (i = 0; i < adev->sdma.num_instances; i++) { 1339 ring = &adev->sdma.instance[i].ring; 1340 ring->ring_obj = NULL; 1341 ring->use_doorbell = true; 1342 aid_id = adev->sdma.instance[i].aid_id; 1343 1344 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1345 ring->use_doorbell?"true":"false"); 1346 1347 /* doorbell size is 2 dwords, get DWORD offset */ 1348 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1349 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1350 1351 sprintf(ring->name, "sdma%d.%d", aid_id, 1352 i % adev->sdma.num_inst_per_aid); 1353 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1354 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1355 AMDGPU_RING_PRIO_DEFAULT, NULL); 1356 if (r) 1357 return r; 1358 1359 if (adev->sdma.has_page_queue) { 1360 ring = &adev->sdma.instance[i].page; 1361 ring->ring_obj = NULL; 1362 ring->use_doorbell = true; 1363 1364 /* doorbell index of page queue is assigned right after 1365 * gfx queue on the same instance 1366 */ 1367 ring->doorbell_index = 1368 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1369 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1370 1371 sprintf(ring->name, "page%d.%d", aid_id, 1372 i % adev->sdma.num_inst_per_aid); 1373 r = amdgpu_ring_init(adev, ring, 1024, 1374 &adev->sdma.trap_irq, 1375 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1376 AMDGPU_RING_PRIO_DEFAULT, NULL); 1377 if (r) 1378 return r; 1379 } 1380 } 1381 1382 if (amdgpu_sdma_ras_sw_init(adev)) { 1383 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1384 return -EINVAL; 1385 } 1386 1387 return r; 1388 } 1389 1390 static int sdma_v4_4_2_sw_fini(void *handle) 1391 { 1392 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1393 int i; 1394 1395 for (i = 0; i < adev->sdma.num_instances; i++) { 1396 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1397 if (adev->sdma.has_page_queue) 1398 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1399 } 1400 1401 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2)) 1402 amdgpu_sdma_destroy_inst_ctx(adev, true); 1403 else 1404 amdgpu_sdma_destroy_inst_ctx(adev, false); 1405 1406 return 0; 1407 } 1408 1409 static int sdma_v4_4_2_hw_init(void *handle) 1410 { 1411 int r; 1412 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1413 uint32_t inst_mask; 1414 1415 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1416 if (!amdgpu_sriov_vf(adev)) 1417 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1418 1419 r = sdma_v4_4_2_inst_start(adev, inst_mask); 1420 1421 return r; 1422 } 1423 1424 static int sdma_v4_4_2_hw_fini(void *handle) 1425 { 1426 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1427 uint32_t inst_mask; 1428 int i; 1429 1430 if (amdgpu_sriov_vf(adev)) 1431 return 0; 1432 1433 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1434 for (i = 0; i < adev->sdma.num_instances; i++) { 1435 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1436 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1437 } 1438 1439 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1440 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1441 1442 return 0; 1443 } 1444 1445 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1446 enum amd_clockgating_state state); 1447 1448 static int sdma_v4_4_2_suspend(void *handle) 1449 { 1450 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1451 1452 if (amdgpu_in_reset(adev)) 1453 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 1454 1455 return sdma_v4_4_2_hw_fini(adev); 1456 } 1457 1458 static int sdma_v4_4_2_resume(void *handle) 1459 { 1460 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1461 1462 return sdma_v4_4_2_hw_init(adev); 1463 } 1464 1465 static bool sdma_v4_4_2_is_idle(void *handle) 1466 { 1467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1468 u32 i; 1469 1470 for (i = 0; i < adev->sdma.num_instances; i++) { 1471 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1472 1473 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1474 return false; 1475 } 1476 1477 return true; 1478 } 1479 1480 static int sdma_v4_4_2_wait_for_idle(void *handle) 1481 { 1482 unsigned i, j; 1483 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1484 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1485 1486 for (i = 0; i < adev->usec_timeout; i++) { 1487 for (j = 0; j < adev->sdma.num_instances; j++) { 1488 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1489 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1490 break; 1491 } 1492 if (j == adev->sdma.num_instances) 1493 return 0; 1494 udelay(1); 1495 } 1496 return -ETIMEDOUT; 1497 } 1498 1499 static int sdma_v4_4_2_soft_reset(void *handle) 1500 { 1501 /* todo */ 1502 1503 return 0; 1504 } 1505 1506 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1507 struct amdgpu_irq_src *source, 1508 unsigned type, 1509 enum amdgpu_interrupt_state state) 1510 { 1511 u32 sdma_cntl; 1512 1513 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1514 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1515 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1516 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1517 1518 return 0; 1519 } 1520 1521 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1522 struct amdgpu_irq_src *source, 1523 struct amdgpu_iv_entry *entry) 1524 { 1525 uint32_t instance, i; 1526 1527 DRM_DEBUG("IH: SDMA trap\n"); 1528 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1529 1530 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1531 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1532 * Match node id with the AID id associated with the SDMA instance. */ 1533 for (i = instance; i < adev->sdma.num_instances; 1534 i += adev->sdma.num_inst_per_aid) { 1535 if (adev->sdma.instance[i].aid_id == 1536 node_id_to_phys_map[entry->node_id]) 1537 break; 1538 } 1539 1540 if (i >= adev->sdma.num_instances) { 1541 dev_WARN_ONCE( 1542 adev->dev, 1, 1543 "Couldn't find the right sdma instance in trap handler"); 1544 return 0; 1545 } 1546 1547 switch (entry->ring_id) { 1548 case 0: 1549 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1550 break; 1551 default: 1552 break; 1553 } 1554 return 0; 1555 } 1556 1557 #if 0 1558 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1559 void *err_data, 1560 struct amdgpu_iv_entry *entry) 1561 { 1562 int instance; 1563 1564 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1565 * be disabled and the driver should only look for the aggregated 1566 * interrupt via sync flood 1567 */ 1568 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1569 goto out; 1570 1571 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1572 if (instance < 0) 1573 goto out; 1574 1575 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1576 1577 out: 1578 return AMDGPU_RAS_SUCCESS; 1579 } 1580 #endif 1581 1582 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1583 struct amdgpu_irq_src *source, 1584 struct amdgpu_iv_entry *entry) 1585 { 1586 int instance; 1587 1588 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1589 1590 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1591 if (instance < 0) 1592 return 0; 1593 1594 switch (entry->ring_id) { 1595 case 0: 1596 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1597 break; 1598 } 1599 return 0; 1600 } 1601 1602 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1603 struct amdgpu_irq_src *source, 1604 unsigned type, 1605 enum amdgpu_interrupt_state state) 1606 { 1607 u32 sdma_cntl; 1608 1609 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1610 switch (state) { 1611 case AMDGPU_IRQ_STATE_DISABLE: 1612 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, 1613 DRAM_ECC_INT_ENABLE, 0); 1614 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1615 break; 1616 /* sdma ecc interrupt is enabled by default 1617 * driver doesn't need to do anything to 1618 * enable the interrupt */ 1619 case AMDGPU_IRQ_STATE_ENABLE: 1620 default: 1621 break; 1622 } 1623 1624 return 0; 1625 } 1626 1627 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1628 struct amdgpu_iv_entry *entry) 1629 { 1630 int instance; 1631 struct amdgpu_task_info task_info; 1632 u64 addr; 1633 1634 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1635 if (instance < 0 || instance >= adev->sdma.num_instances) { 1636 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1637 return -EINVAL; 1638 } 1639 1640 addr = (u64)entry->src_data[0] << 12; 1641 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1642 1643 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 1644 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1645 1646 dev_dbg_ratelimited(adev->dev, 1647 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " 1648 "pasid:%u, for process %s pid %d thread %s pid %d\n", 1649 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1650 entry->pasid, task_info.process_name, task_info.tgid, 1651 task_info.task_name, task_info.pid); 1652 return 0; 1653 } 1654 1655 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1656 struct amdgpu_irq_src *source, 1657 struct amdgpu_iv_entry *entry) 1658 { 1659 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1660 sdma_v4_4_2_print_iv_entry(adev, entry); 1661 return 0; 1662 } 1663 1664 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1665 struct amdgpu_irq_src *source, 1666 struct amdgpu_iv_entry *entry) 1667 { 1668 1669 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1670 sdma_v4_4_2_print_iv_entry(adev, entry); 1671 return 0; 1672 } 1673 1674 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1675 struct amdgpu_irq_src *source, 1676 struct amdgpu_iv_entry *entry) 1677 { 1678 dev_dbg_ratelimited(adev->dev, 1679 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1680 sdma_v4_4_2_print_iv_entry(adev, entry); 1681 return 0; 1682 } 1683 1684 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1685 struct amdgpu_irq_src *source, 1686 struct amdgpu_iv_entry *entry) 1687 { 1688 dev_dbg_ratelimited(adev->dev, 1689 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1690 sdma_v4_4_2_print_iv_entry(adev, entry); 1691 return 0; 1692 } 1693 1694 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1695 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1696 { 1697 uint32_t data, def; 1698 int i; 1699 1700 /* leave as default if it is not driver controlled */ 1701 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1702 return; 1703 1704 if (enable) { 1705 for_each_inst(i, inst_mask) { 1706 /* 1-not override: enable sdma mem light sleep */ 1707 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1708 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1709 if (def != data) 1710 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1711 } 1712 } else { 1713 for_each_inst(i, inst_mask) { 1714 /* 0-override:disable sdma mem light sleep */ 1715 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1716 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1717 if (def != data) 1718 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1719 } 1720 } 1721 } 1722 1723 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1724 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1725 { 1726 uint32_t data, def; 1727 int i; 1728 1729 /* leave as default if it is not driver controlled */ 1730 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1731 return; 1732 1733 if (enable) { 1734 for_each_inst(i, inst_mask) { 1735 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1736 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1737 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1738 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1739 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1740 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1741 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1742 if (def != data) 1743 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1744 } 1745 } else { 1746 for_each_inst(i, inst_mask) { 1747 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1748 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1749 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1750 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1751 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1752 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1753 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1754 if (def != data) 1755 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1756 } 1757 } 1758 } 1759 1760 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1761 enum amd_clockgating_state state) 1762 { 1763 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1764 uint32_t inst_mask; 1765 1766 if (amdgpu_sriov_vf(adev)) 1767 return 0; 1768 1769 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1770 1771 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1772 adev, state == AMD_CG_STATE_GATE, inst_mask); 1773 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1774 adev, state == AMD_CG_STATE_GATE, inst_mask); 1775 return 0; 1776 } 1777 1778 static int sdma_v4_4_2_set_powergating_state(void *handle, 1779 enum amd_powergating_state state) 1780 { 1781 return 0; 1782 } 1783 1784 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags) 1785 { 1786 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1787 int data; 1788 1789 if (amdgpu_sriov_vf(adev)) 1790 *flags = 0; 1791 1792 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1793 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 1794 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 1795 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1796 1797 /* AMD_CG_SUPPORT_SDMA_LS */ 1798 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 1799 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1800 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1801 } 1802 1803 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 1804 .name = "sdma_v4_4_2", 1805 .early_init = sdma_v4_4_2_early_init, 1806 .late_init = sdma_v4_4_2_late_init, 1807 .sw_init = sdma_v4_4_2_sw_init, 1808 .sw_fini = sdma_v4_4_2_sw_fini, 1809 .hw_init = sdma_v4_4_2_hw_init, 1810 .hw_fini = sdma_v4_4_2_hw_fini, 1811 .suspend = sdma_v4_4_2_suspend, 1812 .resume = sdma_v4_4_2_resume, 1813 .is_idle = sdma_v4_4_2_is_idle, 1814 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 1815 .soft_reset = sdma_v4_4_2_soft_reset, 1816 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 1817 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 1818 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 1819 }; 1820 1821 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 1822 .type = AMDGPU_RING_TYPE_SDMA, 1823 .align_mask = 0xf, 1824 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1825 .support_64bit_ptrs = true, 1826 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1827 .get_wptr = sdma_v4_4_2_ring_get_wptr, 1828 .set_wptr = sdma_v4_4_2_ring_set_wptr, 1829 .emit_frame_size = 1830 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1831 3 + /* hdp invalidate */ 1832 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1833 /* sdma_v4_4_2_ring_emit_vm_flush */ 1834 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1835 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1836 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1837 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1838 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1839 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1840 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1841 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1842 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1843 .test_ring = sdma_v4_4_2_ring_test_ring, 1844 .test_ib = sdma_v4_4_2_ring_test_ib, 1845 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1846 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1847 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1848 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1849 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1850 }; 1851 1852 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 1853 .type = AMDGPU_RING_TYPE_SDMA, 1854 .align_mask = 0xf, 1855 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1856 .support_64bit_ptrs = true, 1857 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1858 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 1859 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 1860 .emit_frame_size = 1861 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1862 3 + /* hdp invalidate */ 1863 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1864 /* sdma_v4_4_2_ring_emit_vm_flush */ 1865 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1866 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1867 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1868 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1869 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1870 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1871 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1872 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1873 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1874 .test_ring = sdma_v4_4_2_ring_test_ring, 1875 .test_ib = sdma_v4_4_2_ring_test_ib, 1876 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1877 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1878 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1879 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1880 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1881 }; 1882 1883 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 1884 { 1885 int i, dev_inst; 1886 1887 for (i = 0; i < adev->sdma.num_instances; i++) { 1888 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 1889 adev->sdma.instance[i].ring.me = i; 1890 if (adev->sdma.has_page_queue) { 1891 adev->sdma.instance[i].page.funcs = 1892 &sdma_v4_4_2_page_ring_funcs; 1893 adev->sdma.instance[i].page.me = i; 1894 } 1895 1896 dev_inst = GET_INST(SDMA0, i); 1897 /* AID to which SDMA belongs depends on physical instance */ 1898 adev->sdma.instance[i].aid_id = 1899 dev_inst / adev->sdma.num_inst_per_aid; 1900 } 1901 } 1902 1903 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 1904 .set = sdma_v4_4_2_set_trap_irq_state, 1905 .process = sdma_v4_4_2_process_trap_irq, 1906 }; 1907 1908 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 1909 .process = sdma_v4_4_2_process_illegal_inst_irq, 1910 }; 1911 1912 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 1913 .set = sdma_v4_4_2_set_ecc_irq_state, 1914 .process = amdgpu_sdma_process_ecc_irq, 1915 }; 1916 1917 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 1918 .process = sdma_v4_4_2_process_vm_hole_irq, 1919 }; 1920 1921 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 1922 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 1923 }; 1924 1925 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 1926 .process = sdma_v4_4_2_process_pool_timeout_irq, 1927 }; 1928 1929 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 1930 .process = sdma_v4_4_2_process_srbm_write_irq, 1931 }; 1932 1933 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 1934 { 1935 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 1936 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 1937 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 1938 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 1939 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 1940 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 1941 1942 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 1943 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 1944 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 1945 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 1946 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 1947 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 1948 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 1949 } 1950 1951 /** 1952 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 1953 * 1954 * @ib: indirect buffer to copy to 1955 * @src_offset: src GPU address 1956 * @dst_offset: dst GPU address 1957 * @byte_count: number of bytes to xfer 1958 * @tmz: if a secure copy should be used 1959 * 1960 * Copy GPU buffers using the DMA engine. 1961 * Used by the amdgpu ttm implementation to move pages if 1962 * registered as the asic copy callback. 1963 */ 1964 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 1965 uint64_t src_offset, 1966 uint64_t dst_offset, 1967 uint32_t byte_count, 1968 bool tmz) 1969 { 1970 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1971 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1972 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1973 ib->ptr[ib->length_dw++] = byte_count - 1; 1974 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1975 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1976 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1977 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1978 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1979 } 1980 1981 /** 1982 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 1983 * 1984 * @ib: indirect buffer to copy to 1985 * @src_data: value to write to buffer 1986 * @dst_offset: dst GPU address 1987 * @byte_count: number of bytes to xfer 1988 * 1989 * Fill GPU buffers using the DMA engine. 1990 */ 1991 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 1992 uint32_t src_data, 1993 uint64_t dst_offset, 1994 uint32_t byte_count) 1995 { 1996 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1997 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1998 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1999 ib->ptr[ib->length_dw++] = src_data; 2000 ib->ptr[ib->length_dw++] = byte_count - 1; 2001 } 2002 2003 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2004 .copy_max_bytes = 0x400000, 2005 .copy_num_dw = 7, 2006 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2007 2008 .fill_max_bytes = 0x400000, 2009 .fill_num_dw = 5, 2010 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2011 }; 2012 2013 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2014 { 2015 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 2016 if (adev->sdma.has_page_queue) 2017 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2018 else 2019 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2020 } 2021 2022 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2023 .copy_pte_num_dw = 7, 2024 .copy_pte = sdma_v4_4_2_vm_copy_pte, 2025 2026 .write_pte = sdma_v4_4_2_vm_write_pte, 2027 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2028 }; 2029 2030 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2031 { 2032 struct drm_gpu_scheduler *sched; 2033 unsigned i; 2034 2035 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2036 for (i = 0; i < adev->sdma.num_instances; i++) { 2037 if (adev->sdma.has_page_queue) 2038 sched = &adev->sdma.instance[i].page.sched; 2039 else 2040 sched = &adev->sdma.instance[i].ring.sched; 2041 adev->vm_manager.vm_pte_scheds[i] = sched; 2042 } 2043 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2044 } 2045 2046 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2047 .type = AMD_IP_BLOCK_TYPE_SDMA, 2048 .major = 4, 2049 .minor = 4, 2050 .rev = 0, 2051 .funcs = &sdma_v4_4_2_ip_funcs, 2052 }; 2053 2054 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2055 { 2056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2057 int r; 2058 2059 if (!amdgpu_sriov_vf(adev)) 2060 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2061 2062 r = sdma_v4_4_2_inst_start(adev, inst_mask); 2063 2064 return r; 2065 } 2066 2067 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2068 { 2069 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2070 uint32_t tmp_mask = inst_mask; 2071 int i; 2072 2073 for_each_inst(i, tmp_mask) { 2074 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2075 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2076 } 2077 2078 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2079 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2080 2081 return 0; 2082 } 2083 2084 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2085 .suspend = &sdma_v4_4_2_xcp_suspend, 2086 .resume = &sdma_v4_4_2_xcp_resume 2087 }; 2088 2089 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2090 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2091 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2092 }; 2093 2094 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2095 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2096 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2097 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2098 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2099 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2100 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2101 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2102 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2103 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2104 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2105 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2106 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2107 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2108 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2109 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2110 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2111 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2112 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2113 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2114 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2115 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2116 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2117 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2118 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2119 }; 2120 2121 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2122 uint32_t sdma_inst, 2123 void *ras_err_status) 2124 { 2125 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2126 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2127 2128 /* sdma v4_4_2 doesn't support query ce counts */ 2129 amdgpu_ras_inst_query_ras_error_count(adev, 2130 sdma_v4_2_2_ue_reg_list, 2131 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2132 sdma_v4_4_2_ras_memory_list, 2133 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2134 sdma_dev_inst, 2135 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2136 &err_data->ue_count); 2137 } 2138 2139 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2140 void *ras_err_status) 2141 { 2142 uint32_t inst_mask; 2143 int i = 0; 2144 2145 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2146 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2147 for_each_inst(i, inst_mask) 2148 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2149 } else { 2150 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2151 } 2152 } 2153 2154 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2155 uint32_t sdma_inst) 2156 { 2157 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2158 2159 amdgpu_ras_inst_reset_ras_error_count(adev, 2160 sdma_v4_2_2_ue_reg_list, 2161 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2162 sdma_dev_inst); 2163 } 2164 2165 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2166 { 2167 uint32_t inst_mask; 2168 int i = 0; 2169 2170 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2171 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2172 for_each_inst(i, inst_mask) 2173 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2174 } else { 2175 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2176 } 2177 } 2178 2179 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2180 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2181 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2182 }; 2183 2184 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2185 .ras_block = { 2186 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2187 }, 2188 }; 2189 2190 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2191 { 2192 adev->sdma.ras = &sdma_v4_4_2_ras; 2193 } 2194