1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_xcp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_trace.h"
33 
34 #include "sdma/sdma_4_4_2_offset.h"
35 #include "sdma/sdma_4_4_2_sh_mask.h"
36 
37 #include "soc15_common.h"
38 #include "soc15.h"
39 #include "vega10_sdma_pkt_open.h"
40 
41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
43 
44 #include "amdgpu_ras.h"
45 
46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");
47 
48 #define WREG32_SDMA(instance, offset, value) \
49 	WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
50 #define RREG32_SDMA(instance, offset) \
51 	RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
52 
53 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev);
54 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);
55 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);
56 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
57 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);
58 
59 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
60 		u32 instance, u32 offset)
61 {
62 	u32 dev_inst = GET_INST(SDMA0, instance);
63 
64 	return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
65 }
66 
67 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)
68 {
69 	switch (seq_num) {
70 	case 0:
71 		return SOC15_IH_CLIENTID_SDMA0;
72 	case 1:
73 		return SOC15_IH_CLIENTID_SDMA1;
74 	case 2:
75 		return SOC15_IH_CLIENTID_SDMA2;
76 	case 3:
77 		return SOC15_IH_CLIENTID_SDMA3;
78 	default:
79 		return -EINVAL;
80 	}
81 }
82 
83 static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id)
84 {
85 	switch (client_id) {
86 	case SOC15_IH_CLIENTID_SDMA0:
87 		return 0;
88 	case SOC15_IH_CLIENTID_SDMA1:
89 		return 1;
90 	case SOC15_IH_CLIENTID_SDMA2:
91 		return 2;
92 	case SOC15_IH_CLIENTID_SDMA3:
93 		return 3;
94 	default:
95 		return -EINVAL;
96 	}
97 }
98 
99 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev,
100 						   uint32_t inst_mask)
101 {
102 	u32 val;
103 	int i;
104 
105 	for (i = 0; i < adev->sdma.num_instances; i++) {
106 		val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
107 		val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
108 		val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
109 				    PIPE_INTERLEAVE_SIZE, 0);
110 		WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
111 
112 		val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
113 		val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
114 				    4);
115 		val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
116 				    PIPE_INTERLEAVE_SIZE, 0);
117 		WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
118 	}
119 }
120 
121 /**
122  * sdma_v4_4_2_init_microcode - load ucode images from disk
123  *
124  * @adev: amdgpu_device pointer
125  *
126  * Use the firmware interface to load the ucode images into
127  * the driver (not loaded into hw).
128  * Returns 0 on success, error on failure.
129  */
130 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)
131 {
132 	int ret, i;
133 
134 	for (i = 0; i < adev->sdma.num_instances; i++) {
135 		if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2)) {
136 			ret = amdgpu_sdma_init_microcode(adev, 0, true);
137 			break;
138 		} else {
139 			ret = amdgpu_sdma_init_microcode(adev, i, false);
140 			if (ret)
141 				return ret;
142 		}
143 	}
144 
145 	return ret;
146 }
147 
148 /**
149  * sdma_v4_4_2_ring_get_rptr - get the current read pointer
150  *
151  * @ring: amdgpu ring pointer
152  *
153  * Get the current rptr from the hardware.
154  */
155 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
156 {
157 	u64 *rptr;
158 
159 	/* XXX check if swapping is necessary on BE */
160 	rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
161 
162 	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
163 	return ((*rptr) >> 2);
164 }
165 
166 /**
167  * sdma_v4_4_2_ring_get_wptr - get the current write pointer
168  *
169  * @ring: amdgpu ring pointer
170  *
171  * Get the current wptr from the hardware.
172  */
173 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
174 {
175 	struct amdgpu_device *adev = ring->adev;
176 	u64 wptr;
177 
178 	if (ring->use_doorbell) {
179 		/* XXX check if swapping is necessary on BE */
180 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
181 		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
182 	} else {
183 		wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
184 		wptr = wptr << 32;
185 		wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
186 		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
187 				ring->me, wptr);
188 	}
189 
190 	return wptr >> 2;
191 }
192 
193 /**
194  * sdma_v4_4_2_ring_set_wptr - commit the write pointer
195  *
196  * @ring: amdgpu ring pointer
197  *
198  * Write the wptr back to the hardware.
199  */
200 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
201 {
202 	struct amdgpu_device *adev = ring->adev;
203 
204 	DRM_DEBUG("Setting write pointer\n");
205 	if (ring->use_doorbell) {
206 		u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
207 
208 		DRM_DEBUG("Using doorbell -- "
209 				"wptr_offs == 0x%08x "
210 				"lower_32_bits(ring->wptr) << 2 == 0x%08x "
211 				"upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
212 				ring->wptr_offs,
213 				lower_32_bits(ring->wptr << 2),
214 				upper_32_bits(ring->wptr << 2));
215 		/* XXX check if swapping is necessary on BE */
216 		WRITE_ONCE(*wb, (ring->wptr << 2));
217 		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
218 				ring->doorbell_index, ring->wptr << 2);
219 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
220 	} else {
221 		DRM_DEBUG("Not using doorbell -- "
222 				"regSDMA%i_GFX_RB_WPTR == 0x%08x "
223 				"regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
224 				ring->me,
225 				lower_32_bits(ring->wptr << 2),
226 				ring->me,
227 				upper_32_bits(ring->wptr << 2));
228 		WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR,
229 			    lower_32_bits(ring->wptr << 2));
230 		WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI,
231 			    upper_32_bits(ring->wptr << 2));
232 	}
233 }
234 
235 /**
236  * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer
237  *
238  * @ring: amdgpu ring pointer
239  *
240  * Get the current wptr from the hardware.
241  */
242 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring)
243 {
244 	struct amdgpu_device *adev = ring->adev;
245 	u64 wptr;
246 
247 	if (ring->use_doorbell) {
248 		/* XXX check if swapping is necessary on BE */
249 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
250 	} else {
251 		wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
252 		wptr = wptr << 32;
253 		wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
254 	}
255 
256 	return wptr >> 2;
257 }
258 
259 /**
260  * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer
261  *
262  * @ring: amdgpu ring pointer
263  *
264  * Write the wptr back to the hardware.
265  */
266 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring)
267 {
268 	struct amdgpu_device *adev = ring->adev;
269 
270 	if (ring->use_doorbell) {
271 		u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
272 
273 		/* XXX check if swapping is necessary on BE */
274 		WRITE_ONCE(*wb, (ring->wptr << 2));
275 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
276 	} else {
277 		uint64_t wptr = ring->wptr << 2;
278 
279 		WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR,
280 			    lower_32_bits(wptr));
281 		WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI,
282 			    upper_32_bits(wptr));
283 	}
284 }
285 
286 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
287 {
288 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
289 	int i;
290 
291 	for (i = 0; i < count; i++)
292 		if (sdma && sdma->burst_nop && (i == 0))
293 			amdgpu_ring_write(ring, ring->funcs->nop |
294 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
295 		else
296 			amdgpu_ring_write(ring, ring->funcs->nop);
297 }
298 
299 /**
300  * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine
301  *
302  * @ring: amdgpu ring pointer
303  * @job: job to retrieve vmid from
304  * @ib: IB object to schedule
305  * @flags: unused
306  *
307  * Schedule an IB in the DMA ring.
308  */
309 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring,
310 				   struct amdgpu_job *job,
311 				   struct amdgpu_ib *ib,
312 				   uint32_t flags)
313 {
314 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
315 
316 	/* IB packet must end on a 8 DW boundary */
317 	sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
318 
319 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
320 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
321 	/* base must be 32 byte aligned */
322 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
323 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
324 	amdgpu_ring_write(ring, ib->length_dw);
325 	amdgpu_ring_write(ring, 0);
326 	amdgpu_ring_write(ring, 0);
327 
328 }
329 
330 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring,
331 				   int mem_space, int hdp,
332 				   uint32_t addr0, uint32_t addr1,
333 				   uint32_t ref, uint32_t mask,
334 				   uint32_t inv)
335 {
336 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
337 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
338 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
339 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
340 	if (mem_space) {
341 		/* memory */
342 		amdgpu_ring_write(ring, addr0);
343 		amdgpu_ring_write(ring, addr1);
344 	} else {
345 		/* registers */
346 		amdgpu_ring_write(ring, addr0 << 2);
347 		amdgpu_ring_write(ring, addr1 << 2);
348 	}
349 	amdgpu_ring_write(ring, ref); /* reference */
350 	amdgpu_ring_write(ring, mask); /* mask */
351 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
352 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
353 }
354 
355 /**
356  * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
357  *
358  * @ring: amdgpu ring pointer
359  *
360  * Emit an hdp flush packet on the requested DMA ring.
361  */
362 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
363 {
364 	struct amdgpu_device *adev = ring->adev;
365 	u32 ref_and_mask = 0;
366 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
367 
368 	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0
369 		       << (ring->me % adev->sdma.num_inst_per_aid);
370 
371 	sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
372 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
373 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
374 			       ref_and_mask, ref_and_mask, 10);
375 }
376 
377 /**
378  * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring
379  *
380  * @ring: amdgpu ring pointer
381  * @addr: address
382  * @seq: sequence number
383  * @flags: fence related flags
384  *
385  * Add a DMA fence packet to the ring to write
386  * the fence seq number and DMA trap packet to generate
387  * an interrupt if needed.
388  */
389 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
390 				      unsigned flags)
391 {
392 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
393 	/* write the fence */
394 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
395 	/* zero in first two bits */
396 	BUG_ON(addr & 0x3);
397 	amdgpu_ring_write(ring, lower_32_bits(addr));
398 	amdgpu_ring_write(ring, upper_32_bits(addr));
399 	amdgpu_ring_write(ring, lower_32_bits(seq));
400 
401 	/* optionally write high bits as well */
402 	if (write64bit) {
403 		addr += 4;
404 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
405 		/* zero in first two bits */
406 		BUG_ON(addr & 0x3);
407 		amdgpu_ring_write(ring, lower_32_bits(addr));
408 		amdgpu_ring_write(ring, upper_32_bits(addr));
409 		amdgpu_ring_write(ring, upper_32_bits(seq));
410 	}
411 
412 	/* generate an interrupt */
413 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
414 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
415 }
416 
417 
418 /**
419  * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines
420  *
421  * @adev: amdgpu_device pointer
422  * @inst_mask: mask of dma engine instances to be disabled
423  *
424  * Stop the gfx async dma ring buffers.
425  */
426 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
427 				      uint32_t inst_mask)
428 {
429 	struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
430 	u32 rb_cntl, ib_cntl;
431 	int i, unset = 0;
432 
433 	for_each_inst(i, inst_mask) {
434 		sdma[i] = &adev->sdma.instance[i].ring;
435 
436 		if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
437 			amdgpu_ttm_set_buffer_funcs_status(adev, false);
438 			unset = 1;
439 		}
440 
441 		rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
442 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);
443 		WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
444 		ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
445 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
446 		WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
447 	}
448 }
449 
450 /**
451  * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines
452  *
453  * @adev: amdgpu_device pointer
454  * @inst_mask: mask of dma engine instances to be disabled
455  *
456  * Stop the compute async dma queues.
457  */
458 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
459 				      uint32_t inst_mask)
460 {
461 	/* XXX todo */
462 }
463 
464 /**
465  * sdma_v4_4_2_inst_page_stop - stop the page async dma engines
466  *
467  * @adev: amdgpu_device pointer
468  * @inst_mask: mask of dma engine instances to be disabled
469  *
470  * Stop the page async dma ring buffers.
471  */
472 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
473 				       uint32_t inst_mask)
474 {
475 	struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
476 	u32 rb_cntl, ib_cntl;
477 	int i;
478 	bool unset = false;
479 
480 	for_each_inst(i, inst_mask) {
481 		sdma[i] = &adev->sdma.instance[i].page;
482 
483 		if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
484 			(!unset)) {
485 			amdgpu_ttm_set_buffer_funcs_status(adev, false);
486 			unset = true;
487 		}
488 
489 		rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
490 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
491 					RB_ENABLE, 0);
492 		WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
493 		ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
494 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,
495 					IB_ENABLE, 0);
496 		WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
497 	}
498 }
499 
500 /**
501  * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch
502  *
503  * @adev: amdgpu_device pointer
504  * @enable: enable/disable the DMA MEs context switch.
505  * @inst_mask: mask of dma engine instances to be enabled
506  *
507  * Halt or unhalt the async dma engines context switch.
508  */
509 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev,
510 					       bool enable, uint32_t inst_mask)
511 {
512 	u32 f32_cntl, phase_quantum = 0;
513 	int i;
514 
515 	if (amdgpu_sdma_phase_quantum) {
516 		unsigned value = amdgpu_sdma_phase_quantum;
517 		unsigned unit = 0;
518 
519 		while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
520 				SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) {
521 			value = (value + 1) >> 1;
522 			unit++;
523 		}
524 		if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
525 			    SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) {
526 			value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
527 				 SDMA_PHASE0_QUANTUM__VALUE__SHIFT);
528 			unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
529 				SDMA_PHASE0_QUANTUM__UNIT__SHIFT);
530 			WARN_ONCE(1,
531 			"clamping sdma_phase_quantum to %uK clock cycles\n",
532 				  value << unit);
533 		}
534 		phase_quantum =
535 			value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT |
536 			unit  << SDMA_PHASE0_QUANTUM__UNIT__SHIFT;
537 	}
538 
539 	for_each_inst(i, inst_mask) {
540 		f32_cntl = RREG32_SDMA(i, regSDMA_CNTL);
541 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,
542 				AUTO_CTXSW_ENABLE, enable ? 1 : 0);
543 		if (enable && amdgpu_sdma_phase_quantum) {
544 			WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum);
545 			WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum);
546 			WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum);
547 		}
548 		WREG32_SDMA(i, regSDMA_CNTL, f32_cntl);
549 
550 		/* Extend page fault timeout to avoid interrupt storm */
551 		WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080);
552 	}
553 }
554 
555 /**
556  * sdma_v4_4_2_inst_enable - stop the async dma engines
557  *
558  * @adev: amdgpu_device pointer
559  * @enable: enable/disable the DMA MEs.
560  * @inst_mask: mask of dma engine instances to be enabled
561  *
562  * Halt or unhalt the async dma engines.
563  */
564 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
565 				    uint32_t inst_mask)
566 {
567 	u32 f32_cntl;
568 	int i;
569 
570 	if (!enable) {
571 		sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
572 		sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
573 		if (adev->sdma.has_page_queue)
574 			sdma_v4_4_2_inst_page_stop(adev, inst_mask);
575 
576 		/* SDMA FW needs to respond to FREEZE requests during reset.
577 		 * Keep it running during reset */
578 		if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
579 			return;
580 	}
581 
582 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
583 		return;
584 
585 	for_each_inst(i, inst_mask) {
586 		f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL);
587 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);
588 		WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl);
589 	}
590 }
591 
592 /*
593  * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl
594  */
595 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
596 {
597 	/* Set ring buffer size in dwords */
598 	uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
599 
600 	barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */
601 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
602 #ifdef __BIG_ENDIAN
603 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
604 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
605 				RPTR_WRITEBACK_SWAP_ENABLE, 1);
606 #endif
607 	return rb_cntl;
608 }
609 
610 /**
611  * sdma_v4_4_2_gfx_resume - setup and start the async dma engines
612  *
613  * @adev: amdgpu_device pointer
614  * @i: instance to resume
615  *
616  * Set up the gfx DMA ring buffers and enable them.
617  * Returns 0 for success, error for failure.
618  */
619 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)
620 {
621 	struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
622 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
623 	u32 wb_offset;
624 	u32 doorbell;
625 	u32 doorbell_offset;
626 	u64 wptr_gpu_addr;
627 
628 	wb_offset = (ring->rptr_offs * 4);
629 
630 	rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
631 	rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
632 	WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
633 
634 	/* Initialize the ring buffer's read and write pointers */
635 	WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
636 	WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
637 	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
638 	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
639 
640 	/* set the wb address whether it's enabled or not */
641 	WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI,
642 	       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
643 	WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO,
644 	       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
645 
646 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
647 				RPTR_WRITEBACK_ENABLE, 1);
648 
649 	WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
650 	WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
651 
652 	ring->wptr = 0;
653 
654 	/* before programing wptr to a less value, need set minor_ptr_update first */
655 	WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
656 
657 	doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
658 	doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
659 
660 	doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,
661 				 ring->use_doorbell);
662 	doorbell_offset = REG_SET_FIELD(doorbell_offset,
663 					SDMA_GFX_DOORBELL_OFFSET,
664 					OFFSET, ring->doorbell_index);
665 	WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
666 	WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
667 
668 	sdma_v4_4_2_ring_set_wptr(ring);
669 
670 	/* set minor_ptr_update to 0 after wptr programed */
671 	WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0);
672 
673 	/* setup the wptr shadow polling */
674 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
675 	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO,
676 		    lower_32_bits(wptr_gpu_addr));
677 	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI,
678 		    upper_32_bits(wptr_gpu_addr));
679 	wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL);
680 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
681 				       SDMA_GFX_RB_WPTR_POLL_CNTL,
682 				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
683 	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
684 
685 	/* enable DMA RB */
686 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);
687 	WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
688 
689 	ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
690 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);
691 #ifdef __BIG_ENDIAN
692 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
693 #endif
694 	/* enable DMA IBs */
695 	WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
696 }
697 
698 /**
699  * sdma_v4_4_2_page_resume - setup and start the async dma engines
700  *
701  * @adev: amdgpu_device pointer
702  * @i: instance to resume
703  *
704  * Set up the page DMA ring buffers and enable them.
705  * Returns 0 for success, error for failure.
706  */
707 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)
708 {
709 	struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
710 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
711 	u32 wb_offset;
712 	u32 doorbell;
713 	u32 doorbell_offset;
714 	u64 wptr_gpu_addr;
715 
716 	wb_offset = (ring->rptr_offs * 4);
717 
718 	rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
719 	rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
720 	WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
721 
722 	/* Initialize the ring buffer's read and write pointers */
723 	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
724 	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
725 	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
726 	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
727 
728 	/* set the wb address whether it's enabled or not */
729 	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
730 	       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
731 	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO,
732 	       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
733 
734 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
735 				RPTR_WRITEBACK_ENABLE, 1);
736 
737 	WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
738 	WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
739 
740 	ring->wptr = 0;
741 
742 	/* before programing wptr to a less value, need set minor_ptr_update first */
743 	WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
744 
745 	doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL);
746 	doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET);
747 
748 	doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,
749 				 ring->use_doorbell);
750 	doorbell_offset = REG_SET_FIELD(doorbell_offset,
751 					SDMA_PAGE_DOORBELL_OFFSET,
752 					OFFSET, ring->doorbell_index);
753 	WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell);
754 	WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset);
755 
756 	/* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */
757 	sdma_v4_4_2_page_ring_set_wptr(ring);
758 
759 	/* set minor_ptr_update to 0 after wptr programed */
760 	WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0);
761 
762 	/* setup the wptr shadow polling */
763 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
764 	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO,
765 		    lower_32_bits(wptr_gpu_addr));
766 	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI,
767 		    upper_32_bits(wptr_gpu_addr));
768 	wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL);
769 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
770 				       SDMA_PAGE_RB_WPTR_POLL_CNTL,
771 				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
772 	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
773 
774 	/* enable DMA RB */
775 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);
776 	WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
777 
778 	ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
779 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);
780 #ifdef __BIG_ENDIAN
781 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
782 #endif
783 	/* enable DMA IBs */
784 	WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
785 }
786 
787 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
788 {
789 
790 }
791 
792 /**
793  * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines
794  *
795  * @adev: amdgpu_device pointer
796  * @inst_mask: mask of dma engine instances to be enabled
797  *
798  * Set up the compute DMA queues and enable them.
799  * Returns 0 for success, error for failure.
800  */
801 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
802 				       uint32_t inst_mask)
803 {
804 	sdma_v4_4_2_init_pg(adev);
805 
806 	return 0;
807 }
808 
809 /**
810  * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
811  *
812  * @adev: amdgpu_device pointer
813  * @inst_mask: mask of dma engine instances to be enabled
814  *
815  * Loads the sDMA0/1 ucode.
816  * Returns 0 for success, -EINVAL if the ucode is not available.
817  */
818 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,
819 					   uint32_t inst_mask)
820 {
821 	const struct sdma_firmware_header_v1_0 *hdr;
822 	const __le32 *fw_data;
823 	u32 fw_size;
824 	int i, j;
825 
826 	/* halt the MEs */
827 	sdma_v4_4_2_inst_enable(adev, false, inst_mask);
828 
829 	for_each_inst(i, inst_mask) {
830 		if (!adev->sdma.instance[i].fw)
831 			return -EINVAL;
832 
833 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
834 		amdgpu_ucode_print_sdma_hdr(&hdr->header);
835 		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
836 
837 		fw_data = (const __le32 *)
838 			(adev->sdma.instance[i].fw->data +
839 				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
840 
841 		WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0);
842 
843 		for (j = 0; j < fw_size; j++)
844 			WREG32_SDMA(i, regSDMA_UCODE_DATA,
845 				    le32_to_cpup(fw_data++));
846 
847 		WREG32_SDMA(i, regSDMA_UCODE_ADDR,
848 			    adev->sdma.instance[i].fw_version);
849 	}
850 
851 	return 0;
852 }
853 
854 /**
855  * sdma_v4_4_2_inst_start - setup and start the async dma engines
856  *
857  * @adev: amdgpu_device pointer
858  * @inst_mask: mask of dma engine instances to be enabled
859  *
860  * Set up the DMA engines and enable them.
861  * Returns 0 for success, error for failure.
862  */
863 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
864 				  uint32_t inst_mask)
865 {
866 	struct amdgpu_ring *ring;
867 	uint32_t tmp_mask;
868 	int i, r = 0;
869 
870 	if (amdgpu_sriov_vf(adev)) {
871 		sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
872 		sdma_v4_4_2_inst_enable(adev, false, inst_mask);
873 	} else {
874 		/* bypass sdma microcode loading on Gopher */
875 		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP &&
876 		    adev->sdma.instance[0].fw) {
877 			r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);
878 			if (r)
879 				return r;
880 		}
881 
882 		/* unhalt the MEs */
883 		sdma_v4_4_2_inst_enable(adev, true, inst_mask);
884 		/* enable sdma ring preemption */
885 		sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
886 	}
887 
888 	/* start the gfx rings and rlc compute queues */
889 	tmp_mask = inst_mask;
890 	for_each_inst(i, tmp_mask) {
891 		uint32_t temp;
892 
893 		WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
894 		sdma_v4_4_2_gfx_resume(adev, i);
895 		if (adev->sdma.has_page_queue)
896 			sdma_v4_4_2_page_resume(adev, i);
897 
898 		/* set utc l1 enable flag always to 1 */
899 		temp = RREG32_SDMA(i, regSDMA_CNTL);
900 		temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
901 		/* enable context empty interrupt during initialization */
902 		temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);
903 		WREG32_SDMA(i, regSDMA_CNTL, temp);
904 
905 		if (!amdgpu_sriov_vf(adev)) {
906 			if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
907 				/* unhalt engine */
908 				temp = RREG32_SDMA(i, regSDMA_F32_CNTL);
909 				temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);
910 				WREG32_SDMA(i, regSDMA_F32_CNTL, temp);
911 			}
912 		}
913 	}
914 
915 	if (amdgpu_sriov_vf(adev)) {
916 		sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
917 		sdma_v4_4_2_inst_enable(adev, true, inst_mask);
918 	} else {
919 		r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
920 		if (r)
921 			return r;
922 	}
923 
924 	tmp_mask = inst_mask;
925 	for_each_inst(i, tmp_mask) {
926 		ring = &adev->sdma.instance[i].ring;
927 
928 		r = amdgpu_ring_test_helper(ring);
929 		if (r)
930 			return r;
931 
932 		if (adev->sdma.has_page_queue) {
933 			struct amdgpu_ring *page = &adev->sdma.instance[i].page;
934 
935 			r = amdgpu_ring_test_helper(page);
936 			if (r)
937 				return r;
938 
939 			if (adev->mman.buffer_funcs_ring == page)
940 				amdgpu_ttm_set_buffer_funcs_status(adev, true);
941 		}
942 
943 		if (adev->mman.buffer_funcs_ring == ring)
944 			amdgpu_ttm_set_buffer_funcs_status(adev, true);
945 	}
946 
947 	return r;
948 }
949 
950 /**
951  * sdma_v4_4_2_ring_test_ring - simple async dma engine test
952  *
953  * @ring: amdgpu_ring structure holding ring information
954  *
955  * Test the DMA engine by writing using it to write an
956  * value to memory.
957  * Returns 0 for success, error for failure.
958  */
959 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
960 {
961 	struct amdgpu_device *adev = ring->adev;
962 	unsigned i;
963 	unsigned index;
964 	int r;
965 	u32 tmp;
966 	u64 gpu_addr;
967 
968 	r = amdgpu_device_wb_get(adev, &index);
969 	if (r)
970 		return r;
971 
972 	gpu_addr = adev->wb.gpu_addr + (index * 4);
973 	tmp = 0xCAFEDEAD;
974 	adev->wb.wb[index] = cpu_to_le32(tmp);
975 
976 	r = amdgpu_ring_alloc(ring, 5);
977 	if (r)
978 		goto error_free_wb;
979 
980 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
981 			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
982 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
983 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
984 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
985 	amdgpu_ring_write(ring, 0xDEADBEEF);
986 	amdgpu_ring_commit(ring);
987 
988 	for (i = 0; i < adev->usec_timeout; i++) {
989 		tmp = le32_to_cpu(adev->wb.wb[index]);
990 		if (tmp == 0xDEADBEEF)
991 			break;
992 		udelay(1);
993 	}
994 
995 	if (i >= adev->usec_timeout)
996 		r = -ETIMEDOUT;
997 
998 error_free_wb:
999 	amdgpu_device_wb_free(adev, index);
1000 	return r;
1001 }
1002 
1003 /**
1004  * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine
1005  *
1006  * @ring: amdgpu_ring structure holding ring information
1007  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1008  *
1009  * Test a simple IB in the DMA ring.
1010  * Returns 0 on success, error on failure.
1011  */
1012 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1013 {
1014 	struct amdgpu_device *adev = ring->adev;
1015 	struct amdgpu_ib ib;
1016 	struct dma_fence *f = NULL;
1017 	unsigned index;
1018 	long r;
1019 	u32 tmp = 0;
1020 	u64 gpu_addr;
1021 
1022 	r = amdgpu_device_wb_get(adev, &index);
1023 	if (r)
1024 		return r;
1025 
1026 	gpu_addr = adev->wb.gpu_addr + (index * 4);
1027 	tmp = 0xCAFEDEAD;
1028 	adev->wb.wb[index] = cpu_to_le32(tmp);
1029 	memset(&ib, 0, sizeof(ib));
1030 	r = amdgpu_ib_get(adev, NULL, 256,
1031 					AMDGPU_IB_POOL_DIRECT, &ib);
1032 	if (r)
1033 		goto err0;
1034 
1035 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1036 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1037 	ib.ptr[1] = lower_32_bits(gpu_addr);
1038 	ib.ptr[2] = upper_32_bits(gpu_addr);
1039 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1040 	ib.ptr[4] = 0xDEADBEEF;
1041 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1042 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1043 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1044 	ib.length_dw = 8;
1045 
1046 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1047 	if (r)
1048 		goto err1;
1049 
1050 	r = dma_fence_wait_timeout(f, false, timeout);
1051 	if (r == 0) {
1052 		r = -ETIMEDOUT;
1053 		goto err1;
1054 	} else if (r < 0) {
1055 		goto err1;
1056 	}
1057 	tmp = le32_to_cpu(adev->wb.wb[index]);
1058 	if (tmp == 0xDEADBEEF)
1059 		r = 0;
1060 	else
1061 		r = -EINVAL;
1062 
1063 err1:
1064 	amdgpu_ib_free(adev, &ib, NULL);
1065 	dma_fence_put(f);
1066 err0:
1067 	amdgpu_device_wb_free(adev, index);
1068 	return r;
1069 }
1070 
1071 
1072 /**
1073  * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART
1074  *
1075  * @ib: indirect buffer to fill with commands
1076  * @pe: addr of the page entry
1077  * @src: src addr to copy from
1078  * @count: number of page entries to update
1079  *
1080  * Update PTEs by copying them from the GART using sDMA.
1081  */
1082 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1083 				  uint64_t pe, uint64_t src,
1084 				  unsigned count)
1085 {
1086 	unsigned bytes = count * 8;
1087 
1088 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1089 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1090 	ib->ptr[ib->length_dw++] = bytes - 1;
1091 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1092 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
1093 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
1094 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1095 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1096 
1097 }
1098 
1099 /**
1100  * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually
1101  *
1102  * @ib: indirect buffer to fill with commands
1103  * @pe: addr of the page entry
1104  * @value: dst addr to write into pe
1105  * @count: number of page entries to update
1106  * @incr: increase next addr by incr bytes
1107  *
1108  * Update PTEs by writing them manually using sDMA.
1109  */
1110 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1111 				   uint64_t value, unsigned count,
1112 				   uint32_t incr)
1113 {
1114 	unsigned ndw = count * 2;
1115 
1116 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1117 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1118 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1119 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1120 	ib->ptr[ib->length_dw++] = ndw - 1;
1121 	for (; ndw > 0; ndw -= 2) {
1122 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1123 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1124 		value += incr;
1125 	}
1126 }
1127 
1128 /**
1129  * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1130  *
1131  * @ib: indirect buffer to fill with commands
1132  * @pe: addr of the page entry
1133  * @addr: dst addr to write into pe
1134  * @count: number of page entries to update
1135  * @incr: increase next addr by incr bytes
1136  * @flags: access flags
1137  *
1138  * Update the page tables using sDMA.
1139  */
1140 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1141 				     uint64_t pe,
1142 				     uint64_t addr, unsigned count,
1143 				     uint32_t incr, uint64_t flags)
1144 {
1145 	/* for physically contiguous pages (vram) */
1146 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1147 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1148 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1149 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1150 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1151 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1152 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1153 	ib->ptr[ib->length_dw++] = incr; /* increment size */
1154 	ib->ptr[ib->length_dw++] = 0;
1155 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1156 }
1157 
1158 /**
1159  * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw
1160  *
1161  * @ring: amdgpu_ring structure holding ring information
1162  * @ib: indirect buffer to fill with padding
1163  */
1164 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1165 {
1166 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1167 	u32 pad_count;
1168 	int i;
1169 
1170 	pad_count = (-ib->length_dw) & 7;
1171 	for (i = 0; i < pad_count; i++)
1172 		if (sdma && sdma->burst_nop && (i == 0))
1173 			ib->ptr[ib->length_dw++] =
1174 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1175 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1176 		else
1177 			ib->ptr[ib->length_dw++] =
1178 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1179 }
1180 
1181 
1182 /**
1183  * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline
1184  *
1185  * @ring: amdgpu_ring pointer
1186  *
1187  * Make sure all previous operations are completed (CIK).
1188  */
1189 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1190 {
1191 	uint32_t seq = ring->fence_drv.sync_seq;
1192 	uint64_t addr = ring->fence_drv.gpu_addr;
1193 
1194 	/* wait for idle */
1195 	sdma_v4_4_2_wait_reg_mem(ring, 1, 0,
1196 			       addr & 0xfffffffc,
1197 			       upper_32_bits(addr) & 0xffffffff,
1198 			       seq, 0xffffffff, 4);
1199 }
1200 
1201 
1202 /**
1203  * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1204  *
1205  * @ring: amdgpu_ring pointer
1206  * @vmid: vmid number to use
1207  * @pd_addr: address
1208  *
1209  * Update the page table base and flush the VM TLB
1210  * using sDMA.
1211  */
1212 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1213 					 unsigned vmid, uint64_t pd_addr)
1214 {
1215 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1216 }
1217 
1218 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
1219 				     uint32_t reg, uint32_t val)
1220 {
1221 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1222 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1223 	amdgpu_ring_write(ring, reg);
1224 	amdgpu_ring_write(ring, val);
1225 }
1226 
1227 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1228 					 uint32_t val, uint32_t mask)
1229 {
1230 	sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1231 }
1232 
1233 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
1234 {
1235 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
1236 	case IP_VERSION(4, 4, 2):
1237 		return false;
1238 	default:
1239 		return false;
1240 	}
1241 }
1242 
1243 static int sdma_v4_4_2_early_init(void *handle)
1244 {
1245 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1246 	int r;
1247 
1248 	r = sdma_v4_4_2_init_microcode(adev);
1249 	if (r) {
1250 		DRM_ERROR("Failed to load sdma firmware!\n");
1251 		return r;
1252 	}
1253 
1254 	/* TODO: Page queue breaks driver reload under SRIOV */
1255 	if (sdma_v4_4_2_fw_support_paging_queue(adev))
1256 		adev->sdma.has_page_queue = true;
1257 
1258 	sdma_v4_4_2_set_ring_funcs(adev);
1259 	sdma_v4_4_2_set_buffer_funcs(adev);
1260 	sdma_v4_4_2_set_vm_pte_funcs(adev);
1261 	sdma_v4_4_2_set_irq_funcs(adev);
1262 	sdma_v4_4_2_set_ras_funcs(adev);
1263 
1264 	return 0;
1265 }
1266 
1267 #if 0
1268 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1269 		void *err_data,
1270 		struct amdgpu_iv_entry *entry);
1271 #endif
1272 
1273 static int sdma_v4_4_2_late_init(void *handle)
1274 {
1275 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1276 #if 0
1277 	struct ras_ih_if ih_info = {
1278 		.cb = sdma_v4_4_2_process_ras_data_cb,
1279 	};
1280 #endif
1281 	if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1282 		if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
1283 		    adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count)
1284 			adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1285 	}
1286 
1287 	return 0;
1288 }
1289 
1290 static int sdma_v4_4_2_sw_init(void *handle)
1291 {
1292 	struct amdgpu_ring *ring;
1293 	int r, i;
1294 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295 	u32 aid_id;
1296 
1297 	/* SDMA trap event */
1298 	for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1299 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1300 				      SDMA0_4_0__SRCID__SDMA_TRAP,
1301 				      &adev->sdma.trap_irq);
1302 		if (r)
1303 			return r;
1304 	}
1305 
1306 	/* SDMA SRAM ECC event */
1307 	for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1308 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1309 				      SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1310 				      &adev->sdma.ecc_irq);
1311 		if (r)
1312 			return r;
1313 	}
1314 
1315 	/* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1316 	for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1317 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1318 				      SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1319 				      &adev->sdma.vm_hole_irq);
1320 		if (r)
1321 			return r;
1322 
1323 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1324 				      SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1325 				      &adev->sdma.doorbell_invalid_irq);
1326 		if (r)
1327 			return r;
1328 
1329 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1330 				      SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1331 				      &adev->sdma.pool_timeout_irq);
1332 		if (r)
1333 			return r;
1334 
1335 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1336 				      SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1337 				      &adev->sdma.srbm_write_irq);
1338 		if (r)
1339 			return r;
1340 	}
1341 
1342 	for (i = 0; i < adev->sdma.num_instances; i++) {
1343 		ring = &adev->sdma.instance[i].ring;
1344 		ring->ring_obj = NULL;
1345 		ring->use_doorbell = true;
1346 		aid_id = adev->sdma.instance[i].aid_id;
1347 
1348 		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1349 				ring->use_doorbell?"true":"false");
1350 
1351 		/* doorbell size is 2 dwords, get DWORD offset */
1352 		ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1353 		ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1354 
1355 		sprintf(ring->name, "sdma%d.%d", aid_id,
1356 				i % adev->sdma.num_inst_per_aid);
1357 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1358 				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1359 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
1360 		if (r)
1361 			return r;
1362 
1363 		if (adev->sdma.has_page_queue) {
1364 			ring = &adev->sdma.instance[i].page;
1365 			ring->ring_obj = NULL;
1366 			ring->use_doorbell = true;
1367 
1368 			/* doorbell index of page queue is assigned right after
1369 			 * gfx queue on the same instance
1370 			 */
1371 			ring->doorbell_index =
1372 				(adev->doorbell_index.sdma_engine[i] + 1) << 1;
1373 			ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1374 
1375 			sprintf(ring->name, "page%d.%d", aid_id,
1376 					i % adev->sdma.num_inst_per_aid);
1377 			r = amdgpu_ring_init(adev, ring, 1024,
1378 					     &adev->sdma.trap_irq,
1379 					     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1380 					     AMDGPU_RING_PRIO_DEFAULT, NULL);
1381 			if (r)
1382 				return r;
1383 		}
1384 	}
1385 
1386 	if (amdgpu_sdma_ras_sw_init(adev)) {
1387 		dev_err(adev->dev, "fail to initialize sdma ras block\n");
1388 		return -EINVAL;
1389 	}
1390 
1391 	return r;
1392 }
1393 
1394 static int sdma_v4_4_2_sw_fini(void *handle)
1395 {
1396 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1397 	int i;
1398 
1399 	for (i = 0; i < adev->sdma.num_instances; i++) {
1400 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1401 		if (adev->sdma.has_page_queue)
1402 			amdgpu_ring_fini(&adev->sdma.instance[i].page);
1403 	}
1404 
1405 	if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2))
1406 		amdgpu_sdma_destroy_inst_ctx(adev, true);
1407 	else
1408 		amdgpu_sdma_destroy_inst_ctx(adev, false);
1409 
1410 	return 0;
1411 }
1412 
1413 static int sdma_v4_4_2_hw_init(void *handle)
1414 {
1415 	int r;
1416 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1417 	uint32_t inst_mask;
1418 
1419 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1420 	if (!amdgpu_sriov_vf(adev))
1421 		sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
1422 
1423 	r = sdma_v4_4_2_inst_start(adev, inst_mask);
1424 
1425 	return r;
1426 }
1427 
1428 static int sdma_v4_4_2_hw_fini(void *handle)
1429 {
1430 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1431 	uint32_t inst_mask;
1432 	int i;
1433 
1434 	if (amdgpu_sriov_vf(adev))
1435 		return 0;
1436 
1437 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1438 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1439 		for (i = 0; i < adev->sdma.num_instances; i++) {
1440 			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1441 				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1442 		}
1443 	}
1444 
1445 	sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
1446 	sdma_v4_4_2_inst_enable(adev, false, inst_mask);
1447 
1448 	return 0;
1449 }
1450 
1451 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1452 					     enum amd_clockgating_state state);
1453 
1454 static int sdma_v4_4_2_suspend(void *handle)
1455 {
1456 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1457 
1458 	if (amdgpu_in_reset(adev))
1459 		sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
1460 
1461 	return sdma_v4_4_2_hw_fini(adev);
1462 }
1463 
1464 static int sdma_v4_4_2_resume(void *handle)
1465 {
1466 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1467 
1468 	return sdma_v4_4_2_hw_init(adev);
1469 }
1470 
1471 static bool sdma_v4_4_2_is_idle(void *handle)
1472 {
1473 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1474 	u32 i;
1475 
1476 	for (i = 0; i < adev->sdma.num_instances; i++) {
1477 		u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
1478 
1479 		if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
1480 			return false;
1481 	}
1482 
1483 	return true;
1484 }
1485 
1486 static int sdma_v4_4_2_wait_for_idle(void *handle)
1487 {
1488 	unsigned i, j;
1489 	u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1490 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1491 
1492 	for (i = 0; i < adev->usec_timeout; i++) {
1493 		for (j = 0; j < adev->sdma.num_instances; j++) {
1494 			sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG);
1495 			if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK))
1496 				break;
1497 		}
1498 		if (j == adev->sdma.num_instances)
1499 			return 0;
1500 		udelay(1);
1501 	}
1502 	return -ETIMEDOUT;
1503 }
1504 
1505 static int sdma_v4_4_2_soft_reset(void *handle)
1506 {
1507 	/* todo */
1508 
1509 	return 0;
1510 }
1511 
1512 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,
1513 					struct amdgpu_irq_src *source,
1514 					unsigned type,
1515 					enum amdgpu_interrupt_state state)
1516 {
1517 	u32 sdma_cntl;
1518 
1519 	sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1520 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,
1521 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1522 	WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1523 
1524 	return 0;
1525 }
1526 
1527 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
1528 				      struct amdgpu_irq_src *source,
1529 				      struct amdgpu_iv_entry *entry)
1530 {
1531 	uint32_t instance, i;
1532 
1533 	DRM_DEBUG("IH: SDMA trap\n");
1534 	instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1535 
1536 	/* Client id gives the SDMA instance in AID. To know the exact SDMA
1537 	 * instance, interrupt entry gives the node id which corresponds to the AID instance.
1538 	 * Match node id with the AID id associated with the SDMA instance. */
1539 	for (i = instance; i < adev->sdma.num_instances;
1540 	     i += adev->sdma.num_inst_per_aid) {
1541 		if (adev->sdma.instance[i].aid_id ==
1542 		    node_id_to_phys_map[entry->node_id])
1543 			break;
1544 	}
1545 
1546 	if (i >= adev->sdma.num_instances) {
1547 		dev_WARN_ONCE(
1548 			adev->dev, 1,
1549 			"Couldn't find the right sdma instance in trap handler");
1550 		return 0;
1551 	}
1552 
1553 	switch (entry->ring_id) {
1554 	case 0:
1555 		amdgpu_fence_process(&adev->sdma.instance[i].ring);
1556 		break;
1557 	default:
1558 		break;
1559 	}
1560 	return 0;
1561 }
1562 
1563 #if 0
1564 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1565 		void *err_data,
1566 		struct amdgpu_iv_entry *entry)
1567 {
1568 	int instance;
1569 
1570 	/* When “Full RAS” is enabled, the per-IP interrupt sources should
1571 	 * be disabled and the driver should only look for the aggregated
1572 	 * interrupt via sync flood
1573 	 */
1574 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))
1575 		goto out;
1576 
1577 	instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1578 	if (instance < 0)
1579 		goto out;
1580 
1581 	amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
1582 
1583 out:
1584 	return AMDGPU_RAS_SUCCESS;
1585 }
1586 #endif
1587 
1588 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1589 					      struct amdgpu_irq_src *source,
1590 					      struct amdgpu_iv_entry *entry)
1591 {
1592 	int instance;
1593 
1594 	DRM_ERROR("Illegal instruction in SDMA command stream\n");
1595 
1596 	instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1597 	if (instance < 0)
1598 		return 0;
1599 
1600 	switch (entry->ring_id) {
1601 	case 0:
1602 		drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1603 		break;
1604 	}
1605 	return 0;
1606 }
1607 
1608 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
1609 					struct amdgpu_irq_src *source,
1610 					unsigned type,
1611 					enum amdgpu_interrupt_state state)
1612 {
1613 	u32 sdma_cntl;
1614 
1615 	sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1616 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
1617 					state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1618 	WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1619 
1620 	return 0;
1621 }
1622 
1623 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,
1624 					      struct amdgpu_iv_entry *entry)
1625 {
1626 	int instance;
1627 	struct amdgpu_task_info task_info;
1628 	u64 addr;
1629 
1630 	instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1631 	if (instance < 0 || instance >= adev->sdma.num_instances) {
1632 		dev_err(adev->dev, "sdma instance invalid %d\n", instance);
1633 		return -EINVAL;
1634 	}
1635 
1636 	addr = (u64)entry->src_data[0] << 12;
1637 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
1638 
1639 	memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1640 	amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1641 
1642 	dev_dbg_ratelimited(adev->dev,
1643 		   "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
1644 		   "pasid:%u, for process %s pid %d thread %s pid %d\n",
1645 		   instance, addr, entry->src_id, entry->ring_id, entry->vmid,
1646 		   entry->pasid, task_info.process_name, task_info.tgid,
1647 		   task_info.task_name, task_info.pid);
1648 	return 0;
1649 }
1650 
1651 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev,
1652 					      struct amdgpu_irq_src *source,
1653 					      struct amdgpu_iv_entry *entry)
1654 {
1655 	dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
1656 	sdma_v4_4_2_print_iv_entry(adev, entry);
1657 	return 0;
1658 }
1659 
1660 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev,
1661 					      struct amdgpu_irq_src *source,
1662 					      struct amdgpu_iv_entry *entry)
1663 {
1664 
1665 	dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
1666 	sdma_v4_4_2_print_iv_entry(adev, entry);
1667 	return 0;
1668 }
1669 
1670 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev,
1671 					      struct amdgpu_irq_src *source,
1672 					      struct amdgpu_iv_entry *entry)
1673 {
1674 	dev_dbg_ratelimited(adev->dev,
1675 		"Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
1676 	sdma_v4_4_2_print_iv_entry(adev, entry);
1677 	return 0;
1678 }
1679 
1680 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,
1681 					      struct amdgpu_irq_src *source,
1682 					      struct amdgpu_iv_entry *entry)
1683 {
1684 	dev_dbg_ratelimited(adev->dev,
1685 		"SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
1686 	sdma_v4_4_2_print_iv_entry(adev, entry);
1687 	return 0;
1688 }
1689 
1690 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1691 	struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1692 {
1693 	uint32_t data, def;
1694 	int i;
1695 
1696 	/* leave as default if it is not driver controlled */
1697 	if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS))
1698 		return;
1699 
1700 	if (enable) {
1701 		for_each_inst(i, inst_mask) {
1702 			/* 1-not override: enable sdma mem light sleep */
1703 			def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1704 			data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1705 			if (def != data)
1706 				WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1707 		}
1708 	} else {
1709 		for_each_inst(i, inst_mask) {
1710 			/* 0-override:disable sdma mem light sleep */
1711 			def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1712 			data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1713 			if (def != data)
1714 				WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1715 		}
1716 	}
1717 }
1718 
1719 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1720 	struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1721 {
1722 	uint32_t data, def;
1723 	int i;
1724 
1725 	/* leave as default if it is not driver controlled */
1726 	if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG))
1727 		return;
1728 
1729 	if (enable) {
1730 		for_each_inst(i, inst_mask) {
1731 			def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1732 			data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1733 				  SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1734 				  SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1735 				  SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1736 				  SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1737 				  SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1738 			if (def != data)
1739 				WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1740 		}
1741 	} else {
1742 		for_each_inst(i, inst_mask) {
1743 			def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1744 			data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1745 				 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1746 				 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1747 				 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1748 				 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1749 				 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1750 			if (def != data)
1751 				WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1752 		}
1753 	}
1754 }
1755 
1756 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1757 					  enum amd_clockgating_state state)
1758 {
1759 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1760 	uint32_t inst_mask;
1761 
1762 	if (amdgpu_sriov_vf(adev))
1763 		return 0;
1764 
1765 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1766 
1767 	sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1768 		adev, state == AMD_CG_STATE_GATE, inst_mask);
1769 	sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1770 		adev, state == AMD_CG_STATE_GATE, inst_mask);
1771 	return 0;
1772 }
1773 
1774 static int sdma_v4_4_2_set_powergating_state(void *handle,
1775 					  enum amd_powergating_state state)
1776 {
1777 	return 0;
1778 }
1779 
1780 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags)
1781 {
1782 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1783 	int data;
1784 
1785 	if (amdgpu_sriov_vf(adev))
1786 		*flags = 0;
1787 
1788 	/* AMD_CG_SUPPORT_SDMA_MGCG */
1789 	data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
1790 	if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK))
1791 		*flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1792 
1793 	/* AMD_CG_SUPPORT_SDMA_LS */
1794 	data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
1795 	if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1796 		*flags |= AMD_CG_SUPPORT_SDMA_LS;
1797 }
1798 
1799 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
1800 	.name = "sdma_v4_4_2",
1801 	.early_init = sdma_v4_4_2_early_init,
1802 	.late_init = sdma_v4_4_2_late_init,
1803 	.sw_init = sdma_v4_4_2_sw_init,
1804 	.sw_fini = sdma_v4_4_2_sw_fini,
1805 	.hw_init = sdma_v4_4_2_hw_init,
1806 	.hw_fini = sdma_v4_4_2_hw_fini,
1807 	.suspend = sdma_v4_4_2_suspend,
1808 	.resume = sdma_v4_4_2_resume,
1809 	.is_idle = sdma_v4_4_2_is_idle,
1810 	.wait_for_idle = sdma_v4_4_2_wait_for_idle,
1811 	.soft_reset = sdma_v4_4_2_soft_reset,
1812 	.set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
1813 	.set_powergating_state = sdma_v4_4_2_set_powergating_state,
1814 	.get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
1815 };
1816 
1817 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
1818 	.type = AMDGPU_RING_TYPE_SDMA,
1819 	.align_mask = 0xff,
1820 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1821 	.support_64bit_ptrs = true,
1822 	.get_rptr = sdma_v4_4_2_ring_get_rptr,
1823 	.get_wptr = sdma_v4_4_2_ring_get_wptr,
1824 	.set_wptr = sdma_v4_4_2_ring_set_wptr,
1825 	.emit_frame_size =
1826 		6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1827 		3 + /* hdp invalidate */
1828 		6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1829 		/* sdma_v4_4_2_ring_emit_vm_flush */
1830 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1831 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1832 		10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1833 	.emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1834 	.emit_ib = sdma_v4_4_2_ring_emit_ib,
1835 	.emit_fence = sdma_v4_4_2_ring_emit_fence,
1836 	.emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1837 	.emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1838 	.emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1839 	.test_ring = sdma_v4_4_2_ring_test_ring,
1840 	.test_ib = sdma_v4_4_2_ring_test_ib,
1841 	.insert_nop = sdma_v4_4_2_ring_insert_nop,
1842 	.pad_ib = sdma_v4_4_2_ring_pad_ib,
1843 	.emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1844 	.emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1845 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1846 };
1847 
1848 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
1849 	.type = AMDGPU_RING_TYPE_SDMA,
1850 	.align_mask = 0xff,
1851 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1852 	.support_64bit_ptrs = true,
1853 	.get_rptr = sdma_v4_4_2_ring_get_rptr,
1854 	.get_wptr = sdma_v4_4_2_page_ring_get_wptr,
1855 	.set_wptr = sdma_v4_4_2_page_ring_set_wptr,
1856 	.emit_frame_size =
1857 		6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1858 		3 + /* hdp invalidate */
1859 		6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1860 		/* sdma_v4_4_2_ring_emit_vm_flush */
1861 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1862 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1863 		10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1864 	.emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1865 	.emit_ib = sdma_v4_4_2_ring_emit_ib,
1866 	.emit_fence = sdma_v4_4_2_ring_emit_fence,
1867 	.emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1868 	.emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1869 	.emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1870 	.test_ring = sdma_v4_4_2_ring_test_ring,
1871 	.test_ib = sdma_v4_4_2_ring_test_ib,
1872 	.insert_nop = sdma_v4_4_2_ring_insert_nop,
1873 	.pad_ib = sdma_v4_4_2_ring_pad_ib,
1874 	.emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1875 	.emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1876 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1877 };
1878 
1879 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
1880 {
1881 	int i, dev_inst;
1882 
1883 	for (i = 0; i < adev->sdma.num_instances; i++) {
1884 		adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;
1885 		adev->sdma.instance[i].ring.me = i;
1886 		if (adev->sdma.has_page_queue) {
1887 			adev->sdma.instance[i].page.funcs =
1888 				&sdma_v4_4_2_page_ring_funcs;
1889 			adev->sdma.instance[i].page.me = i;
1890 		}
1891 
1892 		dev_inst = GET_INST(SDMA0, i);
1893 		/* AID to which SDMA belongs depends on physical instance */
1894 		adev->sdma.instance[i].aid_id =
1895 			dev_inst / adev->sdma.num_inst_per_aid;
1896 	}
1897 }
1898 
1899 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = {
1900 	.set = sdma_v4_4_2_set_trap_irq_state,
1901 	.process = sdma_v4_4_2_process_trap_irq,
1902 };
1903 
1904 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = {
1905 	.process = sdma_v4_4_2_process_illegal_inst_irq,
1906 };
1907 
1908 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = {
1909 	.set = sdma_v4_4_2_set_ecc_irq_state,
1910 	.process = amdgpu_sdma_process_ecc_irq,
1911 };
1912 
1913 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = {
1914 	.process = sdma_v4_4_2_process_vm_hole_irq,
1915 };
1916 
1917 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = {
1918 	.process = sdma_v4_4_2_process_doorbell_invalid_irq,
1919 };
1920 
1921 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = {
1922 	.process = sdma_v4_4_2_process_pool_timeout_irq,
1923 };
1924 
1925 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {
1926 	.process = sdma_v4_4_2_process_srbm_write_irq,
1927 };
1928 
1929 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)
1930 {
1931 	adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
1932 	adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
1933 	adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
1934 	adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
1935 	adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
1936 	adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
1937 
1938 	adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;
1939 	adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;
1940 	adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;
1941 	adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;
1942 	adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;
1943 	adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;
1944 	adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;
1945 }
1946 
1947 /**
1948  * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
1949  *
1950  * @ib: indirect buffer to copy to
1951  * @src_offset: src GPU address
1952  * @dst_offset: dst GPU address
1953  * @byte_count: number of bytes to xfer
1954  * @tmz: if a secure copy should be used
1955  *
1956  * Copy GPU buffers using the DMA engine.
1957  * Used by the amdgpu ttm implementation to move pages if
1958  * registered as the asic copy callback.
1959  */
1960 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
1961 				       uint64_t src_offset,
1962 				       uint64_t dst_offset,
1963 				       uint32_t byte_count,
1964 				       bool tmz)
1965 {
1966 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1967 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1968 		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1969 	ib->ptr[ib->length_dw++] = byte_count - 1;
1970 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1971 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1972 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1973 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1974 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1975 }
1976 
1977 /**
1978  * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
1979  *
1980  * @ib: indirect buffer to copy to
1981  * @src_data: value to write to buffer
1982  * @dst_offset: dst GPU address
1983  * @byte_count: number of bytes to xfer
1984  *
1985  * Fill GPU buffers using the DMA engine.
1986  */
1987 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
1988 				       uint32_t src_data,
1989 				       uint64_t dst_offset,
1990 				       uint32_t byte_count)
1991 {
1992 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1993 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1994 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1995 	ib->ptr[ib->length_dw++] = src_data;
1996 	ib->ptr[ib->length_dw++] = byte_count - 1;
1997 }
1998 
1999 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
2000 	.copy_max_bytes = 0x400000,
2001 	.copy_num_dw = 7,
2002 	.emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
2003 
2004 	.fill_max_bytes = 0x400000,
2005 	.fill_num_dw = 5,
2006 	.emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
2007 };
2008 
2009 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
2010 {
2011 	adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
2012 	if (adev->sdma.has_page_queue)
2013 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2014 	else
2015 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2016 }
2017 
2018 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
2019 	.copy_pte_num_dw = 7,
2020 	.copy_pte = sdma_v4_4_2_vm_copy_pte,
2021 
2022 	.write_pte = sdma_v4_4_2_vm_write_pte,
2023 	.set_pte_pde = sdma_v4_4_2_vm_set_pte_pde,
2024 };
2025 
2026 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
2027 {
2028 	struct drm_gpu_scheduler *sched;
2029 	unsigned i;
2030 
2031 	adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
2032 	for (i = 0; i < adev->sdma.num_instances; i++) {
2033 		if (adev->sdma.has_page_queue)
2034 			sched = &adev->sdma.instance[i].page.sched;
2035 		else
2036 			sched = &adev->sdma.instance[i].ring.sched;
2037 		adev->vm_manager.vm_pte_scheds[i] = sched;
2038 	}
2039 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2040 }
2041 
2042 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {
2043 	.type = AMD_IP_BLOCK_TYPE_SDMA,
2044 	.major = 4,
2045 	.minor = 4,
2046 	.rev = 0,
2047 	.funcs = &sdma_v4_4_2_ip_funcs,
2048 };
2049 
2050 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)
2051 {
2052 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2053 	int r;
2054 
2055 	if (!amdgpu_sriov_vf(adev))
2056 		sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
2057 
2058 	r = sdma_v4_4_2_inst_start(adev, inst_mask);
2059 
2060 	return r;
2061 }
2062 
2063 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
2064 {
2065 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2066 	uint32_t tmp_mask = inst_mask;
2067 	int i;
2068 
2069 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2070 		for_each_inst(i, tmp_mask) {
2071 			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2072 				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2073 		}
2074 	}
2075 
2076 	sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
2077 	sdma_v4_4_2_inst_enable(adev, false, inst_mask);
2078 
2079 	return 0;
2080 }
2081 
2082 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
2083 	.suspend = &sdma_v4_4_2_xcp_suspend,
2084 	.resume = &sdma_v4_4_2_xcp_resume
2085 };
2086 
2087 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = {
2088 	{AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI),
2089 	1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
2090 };
2091 
2092 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = {
2093 	{AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"},
2094 	{AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"},
2095 	{AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"},
2096 	{AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"},
2097 	{AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"},
2098 	{AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"},
2099 	{AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"},
2100 	{AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"},
2101 	{AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"},
2102 	{AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"},
2103 	{AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"},
2104 	{AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"},
2105 	{AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"},
2106 	{AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"},
2107 	{AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"},
2108 	{AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"},
2109 	{AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"},
2110 	{AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"},
2111 	{AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"},
2112 	{AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"},
2113 	{AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"},
2114 	{AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"},
2115 	{AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"},
2116 	{AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"},
2117 };
2118 
2119 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,
2120 						   uint32_t sdma_inst,
2121 						   void *ras_err_status)
2122 {
2123 	struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
2124 	uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2125 
2126 	/* sdma v4_4_2 doesn't support query ce counts */
2127 	amdgpu_ras_inst_query_ras_error_count(adev,
2128 					sdma_v4_2_2_ue_reg_list,
2129 					ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2130 					sdma_v4_4_2_ras_memory_list,
2131 					ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),
2132 					sdma_dev_inst,
2133 					AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
2134 					&err_data->ue_count);
2135 }
2136 
2137 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,
2138 					      void *ras_err_status)
2139 {
2140 	uint32_t inst_mask;
2141 	int i = 0;
2142 
2143 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2144 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2145 		for_each_inst(i, inst_mask)
2146 			sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status);
2147 	} else {
2148 		dev_warn(adev->dev, "SDMA RAS is not supported\n");
2149 	}
2150 }
2151 
2152 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev,
2153 						   uint32_t sdma_inst)
2154 {
2155 	uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2156 
2157 	amdgpu_ras_inst_reset_ras_error_count(adev,
2158 					sdma_v4_2_2_ue_reg_list,
2159 					ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2160 					sdma_dev_inst);
2161 }
2162 
2163 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev)
2164 {
2165 	uint32_t inst_mask;
2166 	int i = 0;
2167 
2168 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2169 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2170 		for_each_inst(i, inst_mask)
2171 			sdma_v4_4_2_inst_reset_ras_error_count(adev, i);
2172 	} else {
2173 		dev_warn(adev->dev, "SDMA RAS is not supported\n");
2174 	}
2175 }
2176 
2177 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {
2178 	.query_ras_error_count = sdma_v4_4_2_query_ras_error_count,
2179 	.reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
2180 };
2181 
2182 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = {
2183 	.ras_block = {
2184 		.hw_ops = &sdma_v4_4_2_ras_hw_ops,
2185 	},
2186 };
2187 
2188 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev)
2189 {
2190 	adev->sdma.ras = &sdma_v4_4_2_ras;
2191 }
2192