1*2605e60cSXiaojian Du /* 2*2605e60cSXiaojian Du * Copyright 2020 Advanced Micro Devices, Inc. 3*2605e60cSXiaojian Du * 4*2605e60cSXiaojian Du * Permission is hereby granted, free of charge, to any person obtaining a 5*2605e60cSXiaojian Du * copy of this software and associated documentation files (the "Software"), 6*2605e60cSXiaojian Du * to deal in the Software without restriction, including without limitation 7*2605e60cSXiaojian Du * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*2605e60cSXiaojian Du * and/or sell copies of the Software, and to permit persons to whom the 9*2605e60cSXiaojian Du * Software is furnished to do so, subject to the following conditions: 10*2605e60cSXiaojian Du * 11*2605e60cSXiaojian Du * The above copyright notice and this permission notice shall be included in 12*2605e60cSXiaojian Du * all copies or substantial portions of the Software. 13*2605e60cSXiaojian Du * 14*2605e60cSXiaojian Du * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*2605e60cSXiaojian Du * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*2605e60cSXiaojian Du * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*2605e60cSXiaojian Du * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*2605e60cSXiaojian Du * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*2605e60cSXiaojian Du * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*2605e60cSXiaojian Du * OTHER DEALINGS IN THE SOFTWARE. 21*2605e60cSXiaojian Du * 22*2605e60cSXiaojian Du */ 23*2605e60cSXiaojian Du #include "amdgpu.h" 24*2605e60cSXiaojian Du #include "amdgpu_psp.h" 25*2605e60cSXiaojian Du #include "amdgpu_ucode.h" 26*2605e60cSXiaojian Du #include "soc15_common.h" 27*2605e60cSXiaojian Du #include "psp_v13_0_4.h" 28*2605e60cSXiaojian Du 29*2605e60cSXiaojian Du #include "mp/mp_13_0_4_offset.h" 30*2605e60cSXiaojian Du #include "mp/mp_13_0_4_sh_mask.h" 31*2605e60cSXiaojian Du 32*2605e60cSXiaojian Du MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin"); 33*2605e60cSXiaojian Du MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin"); 34*2605e60cSXiaojian Du 35*2605e60cSXiaojian Du static int psp_v13_0_4_init_microcode(struct psp_context *psp) 36*2605e60cSXiaojian Du { 37*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 38*2605e60cSXiaojian Du const char *chip_name; 39*2605e60cSXiaojian Du char ucode_prefix[30]; 40*2605e60cSXiaojian Du int err = 0; 41*2605e60cSXiaojian Du 42*2605e60cSXiaojian Du switch (adev->ip_versions[MP0_HWIP][0]) { 43*2605e60cSXiaojian Du case IP_VERSION(13, 0, 4): 44*2605e60cSXiaojian Du amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 45*2605e60cSXiaojian Du chip_name = ucode_prefix; 46*2605e60cSXiaojian Du break; 47*2605e60cSXiaojian Du default: 48*2605e60cSXiaojian Du BUG(); 49*2605e60cSXiaojian Du } 50*2605e60cSXiaojian Du 51*2605e60cSXiaojian Du switch (adev->ip_versions[MP0_HWIP][0]) { 52*2605e60cSXiaojian Du case IP_VERSION(13, 0, 4): 53*2605e60cSXiaojian Du err = psp_init_toc_microcode(psp, chip_name); 54*2605e60cSXiaojian Du if (err) 55*2605e60cSXiaojian Du return err; 56*2605e60cSXiaojian Du err = psp_init_ta_microcode(psp, chip_name); 57*2605e60cSXiaojian Du if (err) 58*2605e60cSXiaojian Du return err; 59*2605e60cSXiaojian Du break; 60*2605e60cSXiaojian Du default: 61*2605e60cSXiaojian Du BUG(); 62*2605e60cSXiaojian Du } 63*2605e60cSXiaojian Du 64*2605e60cSXiaojian Du return 0; 65*2605e60cSXiaojian Du } 66*2605e60cSXiaojian Du 67*2605e60cSXiaojian Du static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp) 68*2605e60cSXiaojian Du { 69*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 70*2605e60cSXiaojian Du uint32_t sol_reg; 71*2605e60cSXiaojian Du 72*2605e60cSXiaojian Du sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 73*2605e60cSXiaojian Du 74*2605e60cSXiaojian Du return sol_reg != 0x0; 75*2605e60cSXiaojian Du } 76*2605e60cSXiaojian Du 77*2605e60cSXiaojian Du static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp) 78*2605e60cSXiaojian Du { 79*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 80*2605e60cSXiaojian Du 81*2605e60cSXiaojian Du int ret; 82*2605e60cSXiaojian Du int retry_loop; 83*2605e60cSXiaojian Du 84*2605e60cSXiaojian Du for (retry_loop = 0; retry_loop < 10; retry_loop++) { 85*2605e60cSXiaojian Du /* Wait for bootloader to signify that is 86*2605e60cSXiaojian Du ready having bit 31 of C2PMSG_35 set to 1 */ 87*2605e60cSXiaojian Du ret = psp_wait_for(psp, 88*2605e60cSXiaojian Du SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 89*2605e60cSXiaojian Du 0x80000000, 90*2605e60cSXiaojian Du 0x80000000, 91*2605e60cSXiaojian Du false); 92*2605e60cSXiaojian Du 93*2605e60cSXiaojian Du if (ret == 0) 94*2605e60cSXiaojian Du return 0; 95*2605e60cSXiaojian Du } 96*2605e60cSXiaojian Du 97*2605e60cSXiaojian Du return ret; 98*2605e60cSXiaojian Du } 99*2605e60cSXiaojian Du 100*2605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_component(struct psp_context *psp, 101*2605e60cSXiaojian Du struct psp_bin_desc *bin_desc, 102*2605e60cSXiaojian Du enum psp_bootloader_cmd bl_cmd) 103*2605e60cSXiaojian Du { 104*2605e60cSXiaojian Du int ret; 105*2605e60cSXiaojian Du uint32_t psp_gfxdrv_command_reg = 0; 106*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 107*2605e60cSXiaojian Du 108*2605e60cSXiaojian Du /* Check tOS sign of life register to confirm sys driver and sOS 109*2605e60cSXiaojian Du * are already been loaded. 110*2605e60cSXiaojian Du */ 111*2605e60cSXiaojian Du if (psp_v13_0_4_is_sos_alive(psp)) 112*2605e60cSXiaojian Du return 0; 113*2605e60cSXiaojian Du 114*2605e60cSXiaojian Du ret = psp_v13_0_4_wait_for_bootloader(psp); 115*2605e60cSXiaojian Du if (ret) 116*2605e60cSXiaojian Du return ret; 117*2605e60cSXiaojian Du 118*2605e60cSXiaojian Du memset(psp->fw_pri_buf, 0, PSP_1_MEG); 119*2605e60cSXiaojian Du 120*2605e60cSXiaojian Du /* Copy PSP KDB binary to memory */ 121*2605e60cSXiaojian Du memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 122*2605e60cSXiaojian Du 123*2605e60cSXiaojian Du /* Provide the PSP KDB to bootloader */ 124*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 125*2605e60cSXiaojian Du (uint32_t)(psp->fw_pri_mc_addr >> 20)); 126*2605e60cSXiaojian Du psp_gfxdrv_command_reg = bl_cmd; 127*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 128*2605e60cSXiaojian Du psp_gfxdrv_command_reg); 129*2605e60cSXiaojian Du 130*2605e60cSXiaojian Du ret = psp_v13_0_4_wait_for_bootloader(psp); 131*2605e60cSXiaojian Du 132*2605e60cSXiaojian Du return ret; 133*2605e60cSXiaojian Du } 134*2605e60cSXiaojian Du 135*2605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp) 136*2605e60cSXiaojian Du { 137*2605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 138*2605e60cSXiaojian Du } 139*2605e60cSXiaojian Du 140*2605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp) 141*2605e60cSXiaojian Du { 142*2605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 143*2605e60cSXiaojian Du } 144*2605e60cSXiaojian Du 145*2605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp) 146*2605e60cSXiaojian Du { 147*2605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 148*2605e60cSXiaojian Du } 149*2605e60cSXiaojian Du 150*2605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp) 151*2605e60cSXiaojian Du { 152*2605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 153*2605e60cSXiaojian Du } 154*2605e60cSXiaojian Du 155*2605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp) 156*2605e60cSXiaojian Du { 157*2605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 158*2605e60cSXiaojian Du } 159*2605e60cSXiaojian Du 160*2605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp) 161*2605e60cSXiaojian Du { 162*2605e60cSXiaojian Du return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 163*2605e60cSXiaojian Du } 164*2605e60cSXiaojian Du 165*2605e60cSXiaojian Du static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp) 166*2605e60cSXiaojian Du { 167*2605e60cSXiaojian Du int ret; 168*2605e60cSXiaojian Du unsigned int psp_gfxdrv_command_reg = 0; 169*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 170*2605e60cSXiaojian Du 171*2605e60cSXiaojian Du /* Check sOS sign of life register to confirm sys driver and sOS 172*2605e60cSXiaojian Du * are already been loaded. 173*2605e60cSXiaojian Du */ 174*2605e60cSXiaojian Du if (psp_v13_0_4_is_sos_alive(psp)) 175*2605e60cSXiaojian Du return 0; 176*2605e60cSXiaojian Du 177*2605e60cSXiaojian Du ret = psp_v13_0_4_wait_for_bootloader(psp); 178*2605e60cSXiaojian Du if (ret) 179*2605e60cSXiaojian Du return ret; 180*2605e60cSXiaojian Du 181*2605e60cSXiaojian Du memset(psp->fw_pri_buf, 0, PSP_1_MEG); 182*2605e60cSXiaojian Du 183*2605e60cSXiaojian Du /* Copy Secure OS binary to PSP memory */ 184*2605e60cSXiaojian Du memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 185*2605e60cSXiaojian Du 186*2605e60cSXiaojian Du /* Provide the PSP secure OS to bootloader */ 187*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 188*2605e60cSXiaojian Du (uint32_t)(psp->fw_pri_mc_addr >> 20)); 189*2605e60cSXiaojian Du psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 190*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 191*2605e60cSXiaojian Du psp_gfxdrv_command_reg); 192*2605e60cSXiaojian Du 193*2605e60cSXiaojian Du /* there might be handshake issue with hardware which needs delay */ 194*2605e60cSXiaojian Du mdelay(20); 195*2605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 196*2605e60cSXiaojian Du RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 197*2605e60cSXiaojian Du 0, true); 198*2605e60cSXiaojian Du 199*2605e60cSXiaojian Du return ret; 200*2605e60cSXiaojian Du } 201*2605e60cSXiaojian Du 202*2605e60cSXiaojian Du static int psp_v13_0_4_ring_init(struct psp_context *psp, 203*2605e60cSXiaojian Du enum psp_ring_type ring_type) 204*2605e60cSXiaojian Du { 205*2605e60cSXiaojian Du int ret = 0; 206*2605e60cSXiaojian Du struct psp_ring *ring; 207*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 208*2605e60cSXiaojian Du 209*2605e60cSXiaojian Du ring = &psp->km_ring; 210*2605e60cSXiaojian Du 211*2605e60cSXiaojian Du ring->ring_type = ring_type; 212*2605e60cSXiaojian Du 213*2605e60cSXiaojian Du /* allocate 4k Page of Local Frame Buffer memory for ring */ 214*2605e60cSXiaojian Du ring->ring_size = 0x1000; 215*2605e60cSXiaojian Du ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 216*2605e60cSXiaojian Du AMDGPU_GEM_DOMAIN_VRAM, 217*2605e60cSXiaojian Du &adev->firmware.rbuf, 218*2605e60cSXiaojian Du &ring->ring_mem_mc_addr, 219*2605e60cSXiaojian Du (void **)&ring->ring_mem); 220*2605e60cSXiaojian Du if (ret) { 221*2605e60cSXiaojian Du ring->ring_size = 0; 222*2605e60cSXiaojian Du return ret; 223*2605e60cSXiaojian Du } 224*2605e60cSXiaojian Du 225*2605e60cSXiaojian Du return 0; 226*2605e60cSXiaojian Du } 227*2605e60cSXiaojian Du 228*2605e60cSXiaojian Du static int psp_v13_0_4_ring_stop(struct psp_context *psp, 229*2605e60cSXiaojian Du enum psp_ring_type ring_type) 230*2605e60cSXiaojian Du { 231*2605e60cSXiaojian Du int ret = 0; 232*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 233*2605e60cSXiaojian Du 234*2605e60cSXiaojian Du if (amdgpu_sriov_vf(adev)) { 235*2605e60cSXiaojian Du /* Write the ring destroy command*/ 236*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 237*2605e60cSXiaojian Du GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 238*2605e60cSXiaojian Du /* there might be handshake issue with hardware which needs delay */ 239*2605e60cSXiaojian Du mdelay(20); 240*2605e60cSXiaojian Du /* Wait for response flag (bit 31) */ 241*2605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 242*2605e60cSXiaojian Du 0x80000000, 0x80000000, false); 243*2605e60cSXiaojian Du } else { 244*2605e60cSXiaojian Du /* Write the ring destroy command*/ 245*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 246*2605e60cSXiaojian Du GFX_CTRL_CMD_ID_DESTROY_RINGS); 247*2605e60cSXiaojian Du /* there might be handshake issue with hardware which needs delay */ 248*2605e60cSXiaojian Du mdelay(20); 249*2605e60cSXiaojian Du /* Wait for response flag (bit 31) */ 250*2605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 251*2605e60cSXiaojian Du 0x80000000, 0x80000000, false); 252*2605e60cSXiaojian Du } 253*2605e60cSXiaojian Du 254*2605e60cSXiaojian Du return ret; 255*2605e60cSXiaojian Du } 256*2605e60cSXiaojian Du 257*2605e60cSXiaojian Du static int psp_v13_0_4_ring_create(struct psp_context *psp, 258*2605e60cSXiaojian Du enum psp_ring_type ring_type) 259*2605e60cSXiaojian Du { 260*2605e60cSXiaojian Du int ret = 0; 261*2605e60cSXiaojian Du unsigned int psp_ring_reg = 0; 262*2605e60cSXiaojian Du struct psp_ring *ring = &psp->km_ring; 263*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 264*2605e60cSXiaojian Du 265*2605e60cSXiaojian Du if (amdgpu_sriov_vf(adev)) { 266*2605e60cSXiaojian Du ret = psp_v13_0_4_ring_stop(psp, ring_type); 267*2605e60cSXiaojian Du if (ret) { 268*2605e60cSXiaojian Du DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 269*2605e60cSXiaojian Du return ret; 270*2605e60cSXiaojian Du } 271*2605e60cSXiaojian Du 272*2605e60cSXiaojian Du /* Write low address of the ring to C2PMSG_102 */ 273*2605e60cSXiaojian Du psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 274*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 275*2605e60cSXiaojian Du /* Write high address of the ring to C2PMSG_103 */ 276*2605e60cSXiaojian Du psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 277*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 278*2605e60cSXiaojian Du 279*2605e60cSXiaojian Du /* Write the ring initialization command to C2PMSG_101 */ 280*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 281*2605e60cSXiaojian Du GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 282*2605e60cSXiaojian Du 283*2605e60cSXiaojian Du /* there might be handshake issue with hardware which needs delay */ 284*2605e60cSXiaojian Du mdelay(20); 285*2605e60cSXiaojian Du 286*2605e60cSXiaojian Du /* Wait for response flag (bit 31) in C2PMSG_101 */ 287*2605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 288*2605e60cSXiaojian Du 0x80000000, 0x8000FFFF, false); 289*2605e60cSXiaojian Du 290*2605e60cSXiaojian Du } else { 291*2605e60cSXiaojian Du /* Wait for sOS ready for ring creation */ 292*2605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 293*2605e60cSXiaojian Du 0x80000000, 0x80000000, false); 294*2605e60cSXiaojian Du if (ret) { 295*2605e60cSXiaojian Du DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 296*2605e60cSXiaojian Du return ret; 297*2605e60cSXiaojian Du } 298*2605e60cSXiaojian Du 299*2605e60cSXiaojian Du /* Write low address of the ring to C2PMSG_69 */ 300*2605e60cSXiaojian Du psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 301*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 302*2605e60cSXiaojian Du /* Write high address of the ring to C2PMSG_70 */ 303*2605e60cSXiaojian Du psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 304*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 305*2605e60cSXiaojian Du /* Write size of ring to C2PMSG_71 */ 306*2605e60cSXiaojian Du psp_ring_reg = ring->ring_size; 307*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 308*2605e60cSXiaojian Du /* Write the ring initialization command to C2PMSG_64 */ 309*2605e60cSXiaojian Du psp_ring_reg = ring_type; 310*2605e60cSXiaojian Du psp_ring_reg = psp_ring_reg << 16; 311*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 312*2605e60cSXiaojian Du 313*2605e60cSXiaojian Du /* there might be handshake issue with hardware which needs delay */ 314*2605e60cSXiaojian Du mdelay(20); 315*2605e60cSXiaojian Du 316*2605e60cSXiaojian Du /* Wait for response flag (bit 31) in C2PMSG_64 */ 317*2605e60cSXiaojian Du ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 318*2605e60cSXiaojian Du 0x80000000, 0x8000FFFF, false); 319*2605e60cSXiaojian Du } 320*2605e60cSXiaojian Du 321*2605e60cSXiaojian Du return ret; 322*2605e60cSXiaojian Du } 323*2605e60cSXiaojian Du 324*2605e60cSXiaojian Du static int psp_v13_0_4_ring_destroy(struct psp_context *psp, 325*2605e60cSXiaojian Du enum psp_ring_type ring_type) 326*2605e60cSXiaojian Du { 327*2605e60cSXiaojian Du int ret = 0; 328*2605e60cSXiaojian Du struct psp_ring *ring = &psp->km_ring; 329*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 330*2605e60cSXiaojian Du 331*2605e60cSXiaojian Du ret = psp_v13_0_4_ring_stop(psp, ring_type); 332*2605e60cSXiaojian Du if (ret) 333*2605e60cSXiaojian Du DRM_ERROR("Fail to stop psp ring\n"); 334*2605e60cSXiaojian Du 335*2605e60cSXiaojian Du amdgpu_bo_free_kernel(&adev->firmware.rbuf, 336*2605e60cSXiaojian Du &ring->ring_mem_mc_addr, 337*2605e60cSXiaojian Du (void **)&ring->ring_mem); 338*2605e60cSXiaojian Du 339*2605e60cSXiaojian Du return ret; 340*2605e60cSXiaojian Du } 341*2605e60cSXiaojian Du 342*2605e60cSXiaojian Du static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp) 343*2605e60cSXiaojian Du { 344*2605e60cSXiaojian Du uint32_t data; 345*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 346*2605e60cSXiaojian Du 347*2605e60cSXiaojian Du if (amdgpu_sriov_vf(adev)) 348*2605e60cSXiaojian Du data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 349*2605e60cSXiaojian Du else 350*2605e60cSXiaojian Du data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 351*2605e60cSXiaojian Du 352*2605e60cSXiaojian Du return data; 353*2605e60cSXiaojian Du } 354*2605e60cSXiaojian Du 355*2605e60cSXiaojian Du static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value) 356*2605e60cSXiaojian Du { 357*2605e60cSXiaojian Du struct amdgpu_device *adev = psp->adev; 358*2605e60cSXiaojian Du 359*2605e60cSXiaojian Du if (amdgpu_sriov_vf(adev)) { 360*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 361*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 362*2605e60cSXiaojian Du GFX_CTRL_CMD_ID_CONSUME_CMD); 363*2605e60cSXiaojian Du } else 364*2605e60cSXiaojian Du WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 365*2605e60cSXiaojian Du } 366*2605e60cSXiaojian Du 367*2605e60cSXiaojian Du static const struct psp_funcs psp_v13_0_4_funcs = { 368*2605e60cSXiaojian Du .init_microcode = psp_v13_0_4_init_microcode, 369*2605e60cSXiaojian Du .bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb, 370*2605e60cSXiaojian Du .bootloader_load_spl = psp_v13_0_4_bootloader_load_spl, 371*2605e60cSXiaojian Du .bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv, 372*2605e60cSXiaojian Du .bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv, 373*2605e60cSXiaojian Du .bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv, 374*2605e60cSXiaojian Du .bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv, 375*2605e60cSXiaojian Du .bootloader_load_sos = psp_v13_0_4_bootloader_load_sos, 376*2605e60cSXiaojian Du .ring_init = psp_v13_0_4_ring_init, 377*2605e60cSXiaojian Du .ring_create = psp_v13_0_4_ring_create, 378*2605e60cSXiaojian Du .ring_stop = psp_v13_0_4_ring_stop, 379*2605e60cSXiaojian Du .ring_destroy = psp_v13_0_4_ring_destroy, 380*2605e60cSXiaojian Du .ring_get_wptr = psp_v13_0_4_ring_get_wptr, 381*2605e60cSXiaojian Du .ring_set_wptr = psp_v13_0_4_ring_set_wptr, 382*2605e60cSXiaojian Du }; 383*2605e60cSXiaojian Du 384*2605e60cSXiaojian Du void psp_v13_0_4_set_psp_funcs(struct psp_context *psp) 385*2605e60cSXiaojian Du { 386*2605e60cSXiaojian Du psp->funcs = &psp_v13_0_4_funcs; 387*2605e60cSXiaojian Du } 388