1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "gfxhub_v2_1.h" 26 27 #include "gc/gc_10_3_0_offset.h" 28 #include "gc/gc_10_3_0_sh_mask.h" 29 #include "gc/gc_10_3_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 static const char *gfxhub_client_ids[] = { 35 "CB/DB", 36 "Reserved", 37 "GE1", 38 "GE2", 39 "CPF", 40 "CPC", 41 "CPG", 42 "RLC", 43 "TCP", 44 "SQC (inst)", 45 "SQC (data)", 46 "SQG", 47 "Reserved", 48 "SDMA0", 49 "SDMA1", 50 "GCR", 51 "SDMA2", 52 "SDMA3", 53 }; 54 55 static uint32_t gfxhub_v2_1_get_invalidate_req(unsigned int vmid, 56 uint32_t flush_type) 57 { 58 u32 req = 0; 59 60 /* invalidate using legacy mode on vmid*/ 61 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 62 PER_VMID_INVALIDATE_REQ, 1 << vmid); 63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 70 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 71 72 return req; 73 } 74 75 static void 76 gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev, 77 uint32_t status) 78 { 79 u32 cid = REG_GET_FIELD(status, 80 GCVM_L2_PROTECTION_FAULT_STATUS, CID); 81 82 dev_err(adev->dev, 83 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 84 status); 85 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 86 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid], 87 cid); 88 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 89 REG_GET_FIELD(status, 90 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 91 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 92 REG_GET_FIELD(status, 93 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 94 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 95 REG_GET_FIELD(status, 96 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 97 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 98 REG_GET_FIELD(status, 99 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 100 dev_err(adev->dev, "\t RW: 0x%lx\n", 101 REG_GET_FIELD(status, 102 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 103 } 104 105 static u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev) 106 { 107 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 108 109 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 110 base <<= 24; 111 112 return base; 113 } 114 115 static u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev) 116 { 117 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 118 } 119 120 static void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 121 uint64_t page_table_base) 122 { 123 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 124 125 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 126 hub->ctx_addr_distance * vmid, 127 lower_32_bits(page_table_base)); 128 129 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 130 hub->ctx_addr_distance * vmid, 131 upper_32_bits(page_table_base)); 132 } 133 134 static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev) 135 { 136 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 137 138 gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base); 139 140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 141 (u32)(adev->gmc.gart_start >> 12)); 142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 143 (u32)(adev->gmc.gart_start >> 44)); 144 145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 146 (u32)(adev->gmc.gart_end >> 12)); 147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 148 (u32)(adev->gmc.gart_end >> 44)); 149 } 150 151 static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev) 152 { 153 uint64_t value; 154 155 /* Program the AGP BAR */ 156 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 159 160 /* Program the system aperture low logical page number. */ 161 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 163 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 165 166 /* Set default page address. */ 167 value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 168 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 169 (u32)(value >> 12)); 170 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 171 (u32)(value >> 44)); 172 173 /* Program "protection fault". */ 174 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 175 (u32)(adev->dummy_page_addr >> 12)); 176 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 177 (u32)((u64)adev->dummy_page_addr >> 44)); 178 179 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 180 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 181 } 182 183 184 static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev) 185 { 186 uint32_t tmp; 187 188 /* Setup TLB control */ 189 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 190 191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 194 ENABLE_ADVANCED_DRIVER_MODEL, 1); 195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 196 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 199 MTYPE, MTYPE_UC); /* UC, uncached */ 200 201 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 202 } 203 204 static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev) 205 { 206 uint32_t tmp; 207 208 /* These registers are not accessible to VF-SRIOV. 209 * The PF will program them instead. 210 */ 211 if (amdgpu_sriov_vf(adev)) 212 return; 213 214 /* Setup L2 cache */ 215 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 216 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 217 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 219 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 220 /* XXX for emulation, Refer to closed source code.*/ 221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 222 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 225 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 226 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 227 228 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 231 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 232 233 tmp = mmGCVM_L2_CNTL3_DEFAULT; 234 if (adev->gmc.translate_further) { 235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 236 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 237 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 238 } else { 239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 240 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 241 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 242 } 243 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 244 245 tmp = mmGCVM_L2_CNTL4_DEFAULT; 246 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 247 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 248 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 249 250 tmp = mmGCVM_L2_CNTL5_DEFAULT; 251 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 252 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); 253 } 254 255 static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev) 256 { 257 uint32_t tmp; 258 259 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 260 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 261 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 262 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 263 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 264 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 265 } 266 267 static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev) 268 { 269 /* These registers are not accessible to VF-SRIOV. 270 * The PF will program them instead. 271 */ 272 if (amdgpu_sriov_vf(adev)) 273 return; 274 275 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 276 0xFFFFFFFF); 277 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 278 0x0000000F); 279 280 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 281 0); 282 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 283 0); 284 285 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 286 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 287 288 } 289 290 static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev) 291 { 292 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 293 int i; 294 uint32_t tmp; 295 296 for (i = 0; i <= 14; i++) { 297 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 298 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 299 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 300 adev->vm_manager.num_level); 301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 302 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 304 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 305 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 306 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 307 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 308 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 309 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 310 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 311 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 312 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 313 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 314 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 315 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 316 PAGE_TABLE_BLOCK_SIZE, 317 adev->vm_manager.block_size - 9); 318 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 319 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 320 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 321 !adev->gmc.noretry); 322 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 323 i * hub->ctx_distance, tmp); 324 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 325 i * hub->ctx_addr_distance, 0); 326 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 327 i * hub->ctx_addr_distance, 0); 328 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 329 i * hub->ctx_addr_distance, 330 lower_32_bits(adev->vm_manager.max_pfn - 1)); 331 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 332 i * hub->ctx_addr_distance, 333 upper_32_bits(adev->vm_manager.max_pfn - 1)); 334 } 335 } 336 337 static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev) 338 { 339 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 340 unsigned i; 341 342 for (i = 0 ; i < 18; ++i) { 343 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 344 i * hub->eng_addr_distance, 0xffffffff); 345 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 346 i * hub->eng_addr_distance, 0x1f); 347 } 348 } 349 350 static int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev) 351 { 352 if (amdgpu_sriov_vf(adev)) { 353 /* 354 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 355 * VF copy registers so vbios post doesn't program them, for 356 * SRIOV driver need to program them 357 */ 358 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, 359 adev->gmc.vram_start >> 24); 360 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, 361 adev->gmc.vram_end >> 24); 362 } 363 364 /* GART Enable. */ 365 gfxhub_v2_1_init_gart_aperture_regs(adev); 366 gfxhub_v2_1_init_system_aperture_regs(adev); 367 gfxhub_v2_1_init_tlb_regs(adev); 368 gfxhub_v2_1_init_cache_regs(adev); 369 370 gfxhub_v2_1_enable_system_domain(adev); 371 gfxhub_v2_1_disable_identity_aperture(adev); 372 gfxhub_v2_1_setup_vmid_config(adev); 373 gfxhub_v2_1_program_invalidation(adev); 374 375 return 0; 376 } 377 378 static void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev) 379 { 380 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 381 u32 tmp; 382 u32 i; 383 384 /* Disable all tables */ 385 for (i = 0; i < 16; i++) 386 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 387 i * hub->ctx_distance, 0); 388 389 /* Setup TLB control */ 390 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 391 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 392 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 393 ENABLE_ADVANCED_DRIVER_MODEL, 0); 394 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 395 396 /* Setup L2 cache */ 397 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 398 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 399 } 400 401 /** 402 * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling 403 * 404 * @adev: amdgpu_device pointer 405 * @value: true redirects VM faults to the default page 406 */ 407 static void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev, 408 bool value) 409 { 410 u32 tmp; 411 412 /* These registers are not accessible to VF-SRIOV. 413 * The PF will program them instead. 414 */ 415 if (amdgpu_sriov_vf(adev)) 416 return; 417 418 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 419 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 420 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 421 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 422 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 423 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 424 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 425 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 426 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 427 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 428 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 429 value); 430 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 431 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 432 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 433 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 434 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 435 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 436 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 437 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 438 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 439 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 440 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 441 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 442 if (!value) { 443 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 444 CRASH_ON_NO_RETRY_FAULT, 1); 445 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 446 CRASH_ON_RETRY_FAULT, 1); 447 } 448 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 449 } 450 451 static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = { 452 .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status, 453 .get_invalidate_req = gfxhub_v2_1_get_invalidate_req, 454 }; 455 456 static void gfxhub_v2_1_init(struct amdgpu_device *adev) 457 { 458 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 459 460 hub->ctx0_ptb_addr_lo32 = 461 SOC15_REG_OFFSET(GC, 0, 462 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 463 hub->ctx0_ptb_addr_hi32 = 464 SOC15_REG_OFFSET(GC, 0, 465 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 466 hub->vm_inv_eng0_sem = 467 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 468 hub->vm_inv_eng0_req = 469 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 470 hub->vm_inv_eng0_ack = 471 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 472 hub->vm_context0_cntl = 473 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 474 hub->vm_l2_pro_fault_status = 475 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 476 hub->vm_l2_pro_fault_cntl = 477 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 478 479 hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL; 480 hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 481 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 482 hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ - 483 mmGCVM_INVALIDATE_ENG0_REQ; 484 hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 485 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 486 487 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 488 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 489 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 490 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 491 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 492 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 493 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 494 495 hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs; 496 } 497 498 static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev) 499 { 500 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL); 501 u32 max_region = 502 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); 503 u32 max_num_physical_nodes = 0; 504 u32 max_physical_node_id = 0; 505 506 switch (adev->asic_type) { 507 case CHIP_SIENNA_CICHLID: 508 max_num_physical_nodes = 4; 509 max_physical_node_id = 3; 510 break; 511 default: 512 return -EINVAL; 513 } 514 515 /* PF_MAX_REGION=0 means xgmi is disabled */ 516 if (max_region) { 517 adev->gmc.xgmi.num_physical_nodes = max_region + 1; 518 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) 519 return -EINVAL; 520 521 adev->gmc.xgmi.physical_node_id = 522 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); 523 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) 524 return -EINVAL; 525 526 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( 527 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), 528 GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; 529 } 530 531 return 0; 532 } 533 534 const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { 535 .get_fb_location = gfxhub_v2_1_get_fb_location, 536 .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset, 537 .setup_vm_pt_regs = gfxhub_v2_1_setup_vm_pt_regs, 538 .gart_enable = gfxhub_v2_1_gart_enable, 539 .gart_disable = gfxhub_v2_1_gart_disable, 540 .set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default, 541 .init = gfxhub_v2_1_init, 542 .get_xgmi_info = gfxhub_v2_1_get_xgmi_info, 543 }; 544