1af01d47dSLikun Gao /* 2af01d47dSLikun Gao * Copyright 2019 Advanced Micro Devices, Inc. 3af01d47dSLikun Gao * 4af01d47dSLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a 5af01d47dSLikun Gao * copy of this software and associated documentation files (the "Software"), 6af01d47dSLikun Gao * to deal in the Software without restriction, including without limitation 7af01d47dSLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8af01d47dSLikun Gao * and/or sell copies of the Software, and to permit persons to whom the 9af01d47dSLikun Gao * Software is furnished to do so, subject to the following conditions: 10af01d47dSLikun Gao * 11af01d47dSLikun Gao * The above copyright notice and this permission notice shall be included in 12af01d47dSLikun Gao * all copies or substantial portions of the Software. 13af01d47dSLikun Gao * 14af01d47dSLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15af01d47dSLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16af01d47dSLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17af01d47dSLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18af01d47dSLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19af01d47dSLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20af01d47dSLikun Gao * OTHER DEALINGS IN THE SOFTWARE. 21af01d47dSLikun Gao * 22af01d47dSLikun Gao */ 23af01d47dSLikun Gao 24af01d47dSLikun Gao #include "amdgpu.h" 25af01d47dSLikun Gao #include "gfxhub_v2_1.h" 26af01d47dSLikun Gao 27af01d47dSLikun Gao #include "gc/gc_10_3_0_offset.h" 28af01d47dSLikun Gao #include "gc/gc_10_3_0_sh_mask.h" 29af01d47dSLikun Gao #include "gc/gc_10_3_0_default.h" 30af01d47dSLikun Gao #include "navi10_enum.h" 31af01d47dSLikun Gao 32af01d47dSLikun Gao #include "soc15_common.h" 33af01d47dSLikun Gao 34*b3accd6fSXiaomeng Hou #define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP 0x16f8 35*b3accd6fSXiaomeng Hou #define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP_BASE_IDX 0 36*b3accd6fSXiaomeng Hou 3793fabd84SAlex Deucher static const char *gfxhub_client_ids[] = { 3893fabd84SAlex Deucher "CB/DB", 3993fabd84SAlex Deucher "Reserved", 4093fabd84SAlex Deucher "GE1", 4193fabd84SAlex Deucher "GE2", 4293fabd84SAlex Deucher "CPF", 4393fabd84SAlex Deucher "CPC", 4493fabd84SAlex Deucher "CPG", 4593fabd84SAlex Deucher "RLC", 4693fabd84SAlex Deucher "TCP", 4793fabd84SAlex Deucher "SQC (inst)", 4893fabd84SAlex Deucher "SQC (data)", 4993fabd84SAlex Deucher "SQG", 5093fabd84SAlex Deucher "Reserved", 5193fabd84SAlex Deucher "SDMA0", 5293fabd84SAlex Deucher "SDMA1", 5393fabd84SAlex Deucher "GCR", 5493fabd84SAlex Deucher "SDMA2", 5593fabd84SAlex Deucher "SDMA3", 5693fabd84SAlex Deucher }; 5793fabd84SAlex Deucher 58caa9f483SHuang Rui static uint32_t gfxhub_v2_1_get_invalidate_req(unsigned int vmid, 59caa9f483SHuang Rui uint32_t flush_type) 60caa9f483SHuang Rui { 61caa9f483SHuang Rui u32 req = 0; 62caa9f483SHuang Rui 63caa9f483SHuang Rui /* invalidate using legacy mode on vmid*/ 64caa9f483SHuang Rui req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 65caa9f483SHuang Rui PER_VMID_INVALIDATE_REQ, 1 << vmid); 66caa9f483SHuang Rui req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 67caa9f483SHuang Rui req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 68caa9f483SHuang Rui req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 69caa9f483SHuang Rui req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 70caa9f483SHuang Rui req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 71caa9f483SHuang Rui req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 72caa9f483SHuang Rui req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 73caa9f483SHuang Rui CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 74caa9f483SHuang Rui 75caa9f483SHuang Rui return req; 76caa9f483SHuang Rui } 77caa9f483SHuang Rui 782577db91SHuang Rui static void 792577db91SHuang Rui gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev, 802577db91SHuang Rui uint32_t status) 812577db91SHuang Rui { 8293fabd84SAlex Deucher u32 cid = REG_GET_FIELD(status, 8393fabd84SAlex Deucher GCVM_L2_PROTECTION_FAULT_STATUS, CID); 8493fabd84SAlex Deucher 852577db91SHuang Rui dev_err(adev->dev, 862577db91SHuang Rui "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 872577db91SHuang Rui status); 8893fabd84SAlex Deucher dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 8993fabd84SAlex Deucher cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid], 9093fabd84SAlex Deucher cid); 912577db91SHuang Rui dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 922577db91SHuang Rui REG_GET_FIELD(status, 932577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 942577db91SHuang Rui dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 952577db91SHuang Rui REG_GET_FIELD(status, 962577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 972577db91SHuang Rui dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 982577db91SHuang Rui REG_GET_FIELD(status, 992577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 1002577db91SHuang Rui dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 1012577db91SHuang Rui REG_GET_FIELD(status, 1022577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 1032577db91SHuang Rui dev_err(adev->dev, "\t RW: 0x%lx\n", 1042577db91SHuang Rui REG_GET_FIELD(status, 1052577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 1062577db91SHuang Rui } 1072577db91SHuang Rui 1088ffff9b4SOak Zeng static u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev) 109af01d47dSLikun Gao { 110af01d47dSLikun Gao u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 111af01d47dSLikun Gao 112af01d47dSLikun Gao base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 113af01d47dSLikun Gao base <<= 24; 114af01d47dSLikun Gao 115af01d47dSLikun Gao return base; 116af01d47dSLikun Gao } 117af01d47dSLikun Gao 1188ffff9b4SOak Zeng static u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev) 119af01d47dSLikun Gao { 120af01d47dSLikun Gao return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 121af01d47dSLikun Gao } 122af01d47dSLikun Gao 1238ffff9b4SOak Zeng static void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 124af01d47dSLikun Gao uint64_t page_table_base) 125af01d47dSLikun Gao { 12613ae12d9SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 127af01d47dSLikun Gao 128af01d47dSLikun Gao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 12913ae12d9SHuang Rui hub->ctx_addr_distance * vmid, 13013ae12d9SHuang Rui lower_32_bits(page_table_base)); 131af01d47dSLikun Gao 132af01d47dSLikun Gao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 13313ae12d9SHuang Rui hub->ctx_addr_distance * vmid, 13413ae12d9SHuang Rui upper_32_bits(page_table_base)); 135af01d47dSLikun Gao } 136af01d47dSLikun Gao 137af01d47dSLikun Gao static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev) 138af01d47dSLikun Gao { 139af01d47dSLikun Gao uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 140af01d47dSLikun Gao 141af01d47dSLikun Gao gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base); 142af01d47dSLikun Gao 143af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 144af01d47dSLikun Gao (u32)(adev->gmc.gart_start >> 12)); 145af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 146af01d47dSLikun Gao (u32)(adev->gmc.gart_start >> 44)); 147af01d47dSLikun Gao 148af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 149af01d47dSLikun Gao (u32)(adev->gmc.gart_end >> 12)); 150af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 151af01d47dSLikun Gao (u32)(adev->gmc.gart_end >> 44)); 152af01d47dSLikun Gao } 153af01d47dSLikun Gao 154af01d47dSLikun Gao static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev) 155af01d47dSLikun Gao { 156af01d47dSLikun Gao uint64_t value; 157af01d47dSLikun Gao 15899698b51SAlex Deucher /* Program the AGP BAR */ 159af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 16099698b51SAlex Deucher WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 16199698b51SAlex Deucher WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 162af01d47dSLikun Gao 163af01d47dSLikun Gao /* Program the system aperture low logical page number. */ 164af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 16599698b51SAlex Deucher min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 166af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 16799698b51SAlex Deucher max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 168af01d47dSLikun Gao 169af01d47dSLikun Gao /* Set default page address. */ 1700ca565abSOak Zeng value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 171af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 172af01d47dSLikun Gao (u32)(value >> 12)); 173af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 174af01d47dSLikun Gao (u32)(value >> 44)); 175af01d47dSLikun Gao 176af01d47dSLikun Gao /* Program "protection fault". */ 177af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 178af01d47dSLikun Gao (u32)(adev->dummy_page_addr >> 12)); 179af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 180af01d47dSLikun Gao (u32)((u64)adev->dummy_page_addr >> 44)); 181af01d47dSLikun Gao 182af01d47dSLikun Gao WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 183af01d47dSLikun Gao ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 184af01d47dSLikun Gao } 185af01d47dSLikun Gao 186af01d47dSLikun Gao 187af01d47dSLikun Gao static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev) 188af01d47dSLikun Gao { 189af01d47dSLikun Gao uint32_t tmp; 190af01d47dSLikun Gao 191af01d47dSLikun Gao /* Setup TLB control */ 192af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 193af01d47dSLikun Gao 194af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 195af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 196af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 197af01d47dSLikun Gao ENABLE_ADVANCED_DRIVER_MODEL, 1); 198af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 199af01d47dSLikun Gao SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 200af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 201af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 202af01d47dSLikun Gao MTYPE, MTYPE_UC); /* UC, uncached */ 203af01d47dSLikun Gao 204af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 205af01d47dSLikun Gao } 206af01d47dSLikun Gao 207af01d47dSLikun Gao static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev) 208af01d47dSLikun Gao { 209af01d47dSLikun Gao uint32_t tmp; 210af01d47dSLikun Gao 2111d447326SLiu ChengZhe /* These registers are not accessible to VF-SRIOV. 2121d447326SLiu ChengZhe * The PF will program them instead. 2131d447326SLiu ChengZhe */ 2141d447326SLiu ChengZhe if (amdgpu_sriov_vf(adev)) 2151d447326SLiu ChengZhe return; 2161d447326SLiu ChengZhe 217af01d47dSLikun Gao /* Setup L2 cache */ 218af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 219af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 220af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 221af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 222af01d47dSLikun Gao ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 223af01d47dSLikun Gao /* XXX for emulation, Refer to closed source code.*/ 224af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 225af01d47dSLikun Gao L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 226af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 227af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 228af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 229af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 230af01d47dSLikun Gao 231af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 232af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 233af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 234af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 235af01d47dSLikun Gao 236af01d47dSLikun Gao tmp = mmGCVM_L2_CNTL3_DEFAULT; 237af01d47dSLikun Gao if (adev->gmc.translate_further) { 238af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 239af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 240af01d47dSLikun Gao L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 241af01d47dSLikun Gao } else { 242af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 243af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 244af01d47dSLikun Gao L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 245af01d47dSLikun Gao } 246af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 247af01d47dSLikun Gao 248af01d47dSLikun Gao tmp = mmGCVM_L2_CNTL4_DEFAULT; 249af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 250af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 251af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 252af01d47dSLikun Gao 253af01d47dSLikun Gao tmp = mmGCVM_L2_CNTL5_DEFAULT; 254af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 255af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); 256af01d47dSLikun Gao } 257af01d47dSLikun Gao 258af01d47dSLikun Gao static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev) 259af01d47dSLikun Gao { 260af01d47dSLikun Gao uint32_t tmp; 261af01d47dSLikun Gao 262af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 263af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 264af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 265af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 266af01d47dSLikun Gao RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 267af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 268af01d47dSLikun Gao } 269af01d47dSLikun Gao 270af01d47dSLikun Gao static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev) 271af01d47dSLikun Gao { 2721d447326SLiu ChengZhe /* These registers are not accessible to VF-SRIOV. 2731d447326SLiu ChengZhe * The PF will program them instead. 2741d447326SLiu ChengZhe */ 2751d447326SLiu ChengZhe if (amdgpu_sriov_vf(adev)) 2761d447326SLiu ChengZhe return; 2771d447326SLiu ChengZhe 278af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 279af01d47dSLikun Gao 0xFFFFFFFF); 280af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 281af01d47dSLikun Gao 0x0000000F); 282af01d47dSLikun Gao 283af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 284af01d47dSLikun Gao 0); 285af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 286af01d47dSLikun Gao 0); 287af01d47dSLikun Gao 288af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 289af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 290af01d47dSLikun Gao 291af01d47dSLikun Gao } 292af01d47dSLikun Gao 293af01d47dSLikun Gao static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev) 294af01d47dSLikun Gao { 29513ae12d9SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 296af01d47dSLikun Gao int i; 297af01d47dSLikun Gao uint32_t tmp; 298af01d47dSLikun Gao 299af01d47dSLikun Gao for (i = 0; i <= 14; i++) { 300af01d47dSLikun Gao tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 301af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 302af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 303af01d47dSLikun Gao adev->vm_manager.num_level); 304af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 305af01d47dSLikun Gao RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 306af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 307af01d47dSLikun Gao DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 308af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 309af01d47dSLikun Gao PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 310af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 311af01d47dSLikun Gao VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 312af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 313af01d47dSLikun Gao READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 314af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 315af01d47dSLikun Gao WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 316af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 317af01d47dSLikun Gao EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 318af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 319af01d47dSLikun Gao PAGE_TABLE_BLOCK_SIZE, 320af01d47dSLikun Gao adev->vm_manager.block_size - 9); 321af01d47dSLikun Gao /* Send no-retry XNACK on fault to suppress VM fault storm. */ 322af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 323af01d47dSLikun Gao RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 3249b498efaSAlex Deucher !adev->gmc.noretry); 32513ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 32613ae12d9SHuang Rui i * hub->ctx_distance, tmp); 32713ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 32813ae12d9SHuang Rui i * hub->ctx_addr_distance, 0); 32913ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 33013ae12d9SHuang Rui i * hub->ctx_addr_distance, 0); 33113ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 33213ae12d9SHuang Rui i * hub->ctx_addr_distance, 333af01d47dSLikun Gao lower_32_bits(adev->vm_manager.max_pfn - 1)); 33413ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 33513ae12d9SHuang Rui i * hub->ctx_addr_distance, 336af01d47dSLikun Gao upper_32_bits(adev->vm_manager.max_pfn - 1)); 337af01d47dSLikun Gao } 338af01d47dSLikun Gao } 339af01d47dSLikun Gao 340af01d47dSLikun Gao static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev) 341af01d47dSLikun Gao { 34213ae12d9SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 343af01d47dSLikun Gao unsigned i; 344af01d47dSLikun Gao 345af01d47dSLikun Gao for (i = 0 ; i < 18; ++i) { 346af01d47dSLikun Gao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 34713ae12d9SHuang Rui i * hub->eng_addr_distance, 0xffffffff); 348af01d47dSLikun Gao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 34913ae12d9SHuang Rui i * hub->eng_addr_distance, 0x1f); 350af01d47dSLikun Gao } 351af01d47dSLikun Gao } 352af01d47dSLikun Gao 3538ffff9b4SOak Zeng static int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev) 354af01d47dSLikun Gao { 355af01d47dSLikun Gao if (amdgpu_sriov_vf(adev)) { 356af01d47dSLikun Gao /* 357af01d47dSLikun Gao * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 358af01d47dSLikun Gao * VF copy registers so vbios post doesn't program them, for 359af01d47dSLikun Gao * SRIOV driver need to program them 360af01d47dSLikun Gao */ 361af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, 362af01d47dSLikun Gao adev->gmc.vram_start >> 24); 363af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, 364af01d47dSLikun Gao adev->gmc.vram_end >> 24); 365af01d47dSLikun Gao } 366af01d47dSLikun Gao 367af01d47dSLikun Gao /* GART Enable. */ 368af01d47dSLikun Gao gfxhub_v2_1_init_gart_aperture_regs(adev); 369af01d47dSLikun Gao gfxhub_v2_1_init_system_aperture_regs(adev); 370af01d47dSLikun Gao gfxhub_v2_1_init_tlb_regs(adev); 371af01d47dSLikun Gao gfxhub_v2_1_init_cache_regs(adev); 372af01d47dSLikun Gao 373af01d47dSLikun Gao gfxhub_v2_1_enable_system_domain(adev); 374af01d47dSLikun Gao gfxhub_v2_1_disable_identity_aperture(adev); 375af01d47dSLikun Gao gfxhub_v2_1_setup_vmid_config(adev); 376af01d47dSLikun Gao gfxhub_v2_1_program_invalidation(adev); 377af01d47dSLikun Gao 378af01d47dSLikun Gao return 0; 379af01d47dSLikun Gao } 380af01d47dSLikun Gao 3818ffff9b4SOak Zeng static void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev) 382af01d47dSLikun Gao { 38313ae12d9SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 384af01d47dSLikun Gao u32 tmp; 385af01d47dSLikun Gao u32 i; 386af01d47dSLikun Gao 387af01d47dSLikun Gao /* Disable all tables */ 388af01d47dSLikun Gao for (i = 0; i < 16; i++) 38913ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 39013ae12d9SHuang Rui i * hub->ctx_distance, 0); 391af01d47dSLikun Gao 392af01d47dSLikun Gao /* Setup TLB control */ 393af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 394af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 395af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 396af01d47dSLikun Gao ENABLE_ADVANCED_DRIVER_MODEL, 0); 397af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 398af01d47dSLikun Gao 399af01d47dSLikun Gao /* Setup L2 cache */ 400af01d47dSLikun Gao WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 401af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 402af01d47dSLikun Gao } 403af01d47dSLikun Gao 404af01d47dSLikun Gao /** 405af01d47dSLikun Gao * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling 406af01d47dSLikun Gao * 407af01d47dSLikun Gao * @adev: amdgpu_device pointer 408af01d47dSLikun Gao * @value: true redirects VM faults to the default page 409af01d47dSLikun Gao */ 4108ffff9b4SOak Zeng static void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev, 411af01d47dSLikun Gao bool value) 412af01d47dSLikun Gao { 413af01d47dSLikun Gao u32 tmp; 4141d447326SLiu ChengZhe 4151d447326SLiu ChengZhe /* These registers are not accessible to VF-SRIOV. 4161d447326SLiu ChengZhe * The PF will program them instead. 4171d447326SLiu ChengZhe */ 4181d447326SLiu ChengZhe if (amdgpu_sriov_vf(adev)) 4191d447326SLiu ChengZhe return; 4201d447326SLiu ChengZhe 421af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 422af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 423af01d47dSLikun Gao RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 424af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 425af01d47dSLikun Gao PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 426af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 427af01d47dSLikun Gao PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 428af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 429af01d47dSLikun Gao PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 430af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 431af01d47dSLikun Gao TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 432af01d47dSLikun Gao value); 433af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 434af01d47dSLikun Gao NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 435af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 436af01d47dSLikun Gao DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 437af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 438af01d47dSLikun Gao VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 439af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 440af01d47dSLikun Gao READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 441af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 442af01d47dSLikun Gao WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 443af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 444af01d47dSLikun Gao EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 445af01d47dSLikun Gao if (!value) { 446af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 447af01d47dSLikun Gao CRASH_ON_NO_RETRY_FAULT, 1); 448af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 449af01d47dSLikun Gao CRASH_ON_RETRY_FAULT, 1); 450af01d47dSLikun Gao } 451af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 452af01d47dSLikun Gao } 453af01d47dSLikun Gao 4542577db91SHuang Rui static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = { 4552577db91SHuang Rui .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status, 456caa9f483SHuang Rui .get_invalidate_req = gfxhub_v2_1_get_invalidate_req, 4572577db91SHuang Rui }; 4582577db91SHuang Rui 4598ffff9b4SOak Zeng static void gfxhub_v2_1_init(struct amdgpu_device *adev) 460af01d47dSLikun Gao { 461af01d47dSLikun Gao struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 462af01d47dSLikun Gao 463af01d47dSLikun Gao hub->ctx0_ptb_addr_lo32 = 464af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, 465af01d47dSLikun Gao mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 466af01d47dSLikun Gao hub->ctx0_ptb_addr_hi32 = 467af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, 468af01d47dSLikun Gao mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 469af01d47dSLikun Gao hub->vm_inv_eng0_sem = 470af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 471af01d47dSLikun Gao hub->vm_inv_eng0_req = 472af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 473af01d47dSLikun Gao hub->vm_inv_eng0_ack = 474af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 475af01d47dSLikun Gao hub->vm_context0_cntl = 476af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 477af01d47dSLikun Gao hub->vm_l2_pro_fault_status = 478af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 479af01d47dSLikun Gao hub->vm_l2_pro_fault_cntl = 480af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 4811f9d56c3SHuang Rui 4821f9d56c3SHuang Rui hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL; 4831f9d56c3SHuang Rui hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 4841f9d56c3SHuang Rui mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 4851f9d56c3SHuang Rui hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ - 4861f9d56c3SHuang Rui mmGCVM_INVALIDATE_ENG0_REQ; 4871f9d56c3SHuang Rui hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 4881f9d56c3SHuang Rui mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 4895befb6fcSHuang Rui 4905befb6fcSHuang Rui hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4915befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4925befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4935befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4945befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4955befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4965befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 4972577db91SHuang Rui 4982577db91SHuang Rui hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs; 499af01d47dSLikun Gao } 500fdb8483bSJohn Clements 5018ffff9b4SOak Zeng static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev) 502fdb8483bSJohn Clements { 503fdb8483bSJohn Clements u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL); 504fdb8483bSJohn Clements u32 max_region = 505fdb8483bSJohn Clements REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); 506fdb8483bSJohn Clements u32 max_num_physical_nodes = 0; 507fdb8483bSJohn Clements u32 max_physical_node_id = 0; 508fdb8483bSJohn Clements 509fdb8483bSJohn Clements switch (adev->asic_type) { 510fdb8483bSJohn Clements case CHIP_SIENNA_CICHLID: 511fdb8483bSJohn Clements max_num_physical_nodes = 4; 512fdb8483bSJohn Clements max_physical_node_id = 3; 513fdb8483bSJohn Clements break; 514fdb8483bSJohn Clements default: 515fdb8483bSJohn Clements return -EINVAL; 516fdb8483bSJohn Clements } 517fdb8483bSJohn Clements 518fdb8483bSJohn Clements /* PF_MAX_REGION=0 means xgmi is disabled */ 519fdb8483bSJohn Clements if (max_region) { 520fdb8483bSJohn Clements adev->gmc.xgmi.num_physical_nodes = max_region + 1; 521fdb8483bSJohn Clements if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) 522fdb8483bSJohn Clements return -EINVAL; 523fdb8483bSJohn Clements 524fdb8483bSJohn Clements adev->gmc.xgmi.physical_node_id = 525fdb8483bSJohn Clements REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); 526fdb8483bSJohn Clements if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) 527fdb8483bSJohn Clements return -EINVAL; 528fdb8483bSJohn Clements 529fdb8483bSJohn Clements adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( 530fdb8483bSJohn Clements RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), 531fdb8483bSJohn Clements GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; 532fdb8483bSJohn Clements } 533fdb8483bSJohn Clements 534fdb8483bSJohn Clements return 0; 535fdb8483bSJohn Clements } 5368ffff9b4SOak Zeng 537*b3accd6fSXiaomeng Hou static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev) 538*b3accd6fSXiaomeng Hou { 539*b3accd6fSXiaomeng Hou int i; 540*b3accd6fSXiaomeng Hou u32 tmp = 0, disabled_sa = 0; 541*b3accd6fSXiaomeng Hou u32 efuse_setting, vbios_setting; 542*b3accd6fSXiaomeng Hou 543*b3accd6fSXiaomeng Hou u32 max_sa_mask = amdgpu_gfx_create_bitmask( 544*b3accd6fSXiaomeng Hou adev->gfx.config.max_sh_per_se * 545*b3accd6fSXiaomeng Hou adev->gfx.config.max_shader_engines); 546*b3accd6fSXiaomeng Hou 547*b3accd6fSXiaomeng Hou if (adev->asic_type == CHIP_YELLOW_CARP) { 548*b3accd6fSXiaomeng Hou /* Get SA disabled bitmap from eFuse setting */ 549*b3accd6fSXiaomeng Hou efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 550*b3accd6fSXiaomeng Hou efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 551*b3accd6fSXiaomeng Hou efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 552*b3accd6fSXiaomeng Hou 553*b3accd6fSXiaomeng Hou /* Get SA disabled bitmap from VBIOS setting */ 554*b3accd6fSXiaomeng Hou vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 555*b3accd6fSXiaomeng Hou vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 556*b3accd6fSXiaomeng Hou vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 557*b3accd6fSXiaomeng Hou 558*b3accd6fSXiaomeng Hou disabled_sa |= efuse_setting | vbios_setting; 559*b3accd6fSXiaomeng Hou /* Make sure not to report harvested SAs beyond the max SA count */ 560*b3accd6fSXiaomeng Hou disabled_sa &= max_sa_mask; 561*b3accd6fSXiaomeng Hou 562*b3accd6fSXiaomeng Hou for (i = 0; disabled_sa > 0; i++) { 563*b3accd6fSXiaomeng Hou if (disabled_sa & 1) 564*b3accd6fSXiaomeng Hou tmp |= 0x3 << (i * 2); 565*b3accd6fSXiaomeng Hou disabled_sa >>= 1; 566*b3accd6fSXiaomeng Hou } 567*b3accd6fSXiaomeng Hou disabled_sa = tmp; 568*b3accd6fSXiaomeng Hou 569*b3accd6fSXiaomeng Hou WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa); 570*b3accd6fSXiaomeng Hou } 571*b3accd6fSXiaomeng Hou } 572*b3accd6fSXiaomeng Hou 5738ffff9b4SOak Zeng const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { 5748ffff9b4SOak Zeng .get_fb_location = gfxhub_v2_1_get_fb_location, 5758ffff9b4SOak Zeng .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset, 5768ffff9b4SOak Zeng .setup_vm_pt_regs = gfxhub_v2_1_setup_vm_pt_regs, 5778ffff9b4SOak Zeng .gart_enable = gfxhub_v2_1_gart_enable, 5788ffff9b4SOak Zeng .gart_disable = gfxhub_v2_1_gart_disable, 5798ffff9b4SOak Zeng .set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default, 5808ffff9b4SOak Zeng .init = gfxhub_v2_1_init, 5818ffff9b4SOak Zeng .get_xgmi_info = gfxhub_v2_1_get_xgmi_info, 582*b3accd6fSXiaomeng Hou .utcl2_harvest = gfxhub_v2_1_utcl2_harvest, 5838ffff9b4SOak Zeng }; 584