1af01d47dSLikun Gao /* 2af01d47dSLikun Gao * Copyright 2019 Advanced Micro Devices, Inc. 3af01d47dSLikun Gao * 4af01d47dSLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a 5af01d47dSLikun Gao * copy of this software and associated documentation files (the "Software"), 6af01d47dSLikun Gao * to deal in the Software without restriction, including without limitation 7af01d47dSLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8af01d47dSLikun Gao * and/or sell copies of the Software, and to permit persons to whom the 9af01d47dSLikun Gao * Software is furnished to do so, subject to the following conditions: 10af01d47dSLikun Gao * 11af01d47dSLikun Gao * The above copyright notice and this permission notice shall be included in 12af01d47dSLikun Gao * all copies or substantial portions of the Software. 13af01d47dSLikun Gao * 14af01d47dSLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15af01d47dSLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16af01d47dSLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17af01d47dSLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18af01d47dSLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19af01d47dSLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20af01d47dSLikun Gao * OTHER DEALINGS IN THE SOFTWARE. 21af01d47dSLikun Gao * 22af01d47dSLikun Gao */ 23af01d47dSLikun Gao 24af01d47dSLikun Gao #include "amdgpu.h" 25af01d47dSLikun Gao #include "gfxhub_v2_1.h" 26af01d47dSLikun Gao 27af01d47dSLikun Gao #include "gc/gc_10_3_0_offset.h" 28af01d47dSLikun Gao #include "gc/gc_10_3_0_sh_mask.h" 29af01d47dSLikun Gao #include "gc/gc_10_3_0_default.h" 30af01d47dSLikun Gao #include "navi10_enum.h" 31af01d47dSLikun Gao 32af01d47dSLikun Gao #include "soc15_common.h" 33af01d47dSLikun Gao 34af01d47dSLikun Gao u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev) 35af01d47dSLikun Gao { 36af01d47dSLikun Gao u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 37af01d47dSLikun Gao 38af01d47dSLikun Gao base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 39af01d47dSLikun Gao base <<= 24; 40af01d47dSLikun Gao 41af01d47dSLikun Gao return base; 42af01d47dSLikun Gao } 43af01d47dSLikun Gao 44af01d47dSLikun Gao u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev) 45af01d47dSLikun Gao { 46af01d47dSLikun Gao return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 47af01d47dSLikun Gao } 48af01d47dSLikun Gao 49af01d47dSLikun Gao void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 50af01d47dSLikun Gao uint64_t page_table_base) 51af01d47dSLikun Gao { 5213ae12d9SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 53af01d47dSLikun Gao 54af01d47dSLikun Gao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 5513ae12d9SHuang Rui hub->ctx_addr_distance * vmid, 5613ae12d9SHuang Rui lower_32_bits(page_table_base)); 57af01d47dSLikun Gao 58af01d47dSLikun Gao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 5913ae12d9SHuang Rui hub->ctx_addr_distance * vmid, 6013ae12d9SHuang Rui upper_32_bits(page_table_base)); 61af01d47dSLikun Gao } 62af01d47dSLikun Gao 63af01d47dSLikun Gao static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev) 64af01d47dSLikun Gao { 65af01d47dSLikun Gao uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 66af01d47dSLikun Gao 67af01d47dSLikun Gao gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base); 68af01d47dSLikun Gao 69af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 70af01d47dSLikun Gao (u32)(adev->gmc.gart_start >> 12)); 71af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 72af01d47dSLikun Gao (u32)(adev->gmc.gart_start >> 44)); 73af01d47dSLikun Gao 74af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 75af01d47dSLikun Gao (u32)(adev->gmc.gart_end >> 12)); 76af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 77af01d47dSLikun Gao (u32)(adev->gmc.gart_end >> 44)); 78af01d47dSLikun Gao } 79af01d47dSLikun Gao 80af01d47dSLikun Gao static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev) 81af01d47dSLikun Gao { 82af01d47dSLikun Gao uint64_t value; 83af01d47dSLikun Gao 84af01d47dSLikun Gao /* Disable AGP. */ 85af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 86af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); 87af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); 88af01d47dSLikun Gao 89af01d47dSLikun Gao /* Program the system aperture low logical page number. */ 90af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 91af01d47dSLikun Gao adev->gmc.vram_start >> 18); 92af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 93af01d47dSLikun Gao adev->gmc.vram_end >> 18); 94af01d47dSLikun Gao 95af01d47dSLikun Gao /* Set default page address. */ 96af01d47dSLikun Gao value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 97af01d47dSLikun Gao + adev->vm_manager.vram_base_offset; 98af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 99af01d47dSLikun Gao (u32)(value >> 12)); 100af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 101af01d47dSLikun Gao (u32)(value >> 44)); 102af01d47dSLikun Gao 103af01d47dSLikun Gao /* Program "protection fault". */ 104af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 105af01d47dSLikun Gao (u32)(adev->dummy_page_addr >> 12)); 106af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 107af01d47dSLikun Gao (u32)((u64)adev->dummy_page_addr >> 44)); 108af01d47dSLikun Gao 109af01d47dSLikun Gao WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 110af01d47dSLikun Gao ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 111af01d47dSLikun Gao } 112af01d47dSLikun Gao 113af01d47dSLikun Gao 114af01d47dSLikun Gao static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev) 115af01d47dSLikun Gao { 116af01d47dSLikun Gao uint32_t tmp; 117af01d47dSLikun Gao 118af01d47dSLikun Gao /* Setup TLB control */ 119af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 120af01d47dSLikun Gao 121af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 122af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 123af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 124af01d47dSLikun Gao ENABLE_ADVANCED_DRIVER_MODEL, 1); 125af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 126af01d47dSLikun Gao SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 127af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 128af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 129af01d47dSLikun Gao MTYPE, MTYPE_UC); /* UC, uncached */ 130af01d47dSLikun Gao 131af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 132af01d47dSLikun Gao } 133af01d47dSLikun Gao 134af01d47dSLikun Gao static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev) 135af01d47dSLikun Gao { 136af01d47dSLikun Gao uint32_t tmp; 137af01d47dSLikun Gao 138af01d47dSLikun Gao /* Setup L2 cache */ 139af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 140af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 141af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 142af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 143af01d47dSLikun Gao ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 144af01d47dSLikun Gao /* XXX for emulation, Refer to closed source code.*/ 145af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 146af01d47dSLikun Gao L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 147af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 148af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 149af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 150af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 151af01d47dSLikun Gao 152af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 153af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 154af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 155af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 156af01d47dSLikun Gao 157af01d47dSLikun Gao tmp = mmGCVM_L2_CNTL3_DEFAULT; 158af01d47dSLikun Gao if (adev->gmc.translate_further) { 159af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 160af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 161af01d47dSLikun Gao L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 162af01d47dSLikun Gao } else { 163af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 164af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 165af01d47dSLikun Gao L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 166af01d47dSLikun Gao } 167af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 168af01d47dSLikun Gao 169af01d47dSLikun Gao tmp = mmGCVM_L2_CNTL4_DEFAULT; 170af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 171af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 172af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 173af01d47dSLikun Gao 174af01d47dSLikun Gao tmp = mmGCVM_L2_CNTL5_DEFAULT; 175af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 176af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); 177af01d47dSLikun Gao } 178af01d47dSLikun Gao 179af01d47dSLikun Gao static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev) 180af01d47dSLikun Gao { 181af01d47dSLikun Gao uint32_t tmp; 182af01d47dSLikun Gao 183af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 184af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 185af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 186af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 187af01d47dSLikun Gao RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 188af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 189af01d47dSLikun Gao } 190af01d47dSLikun Gao 191af01d47dSLikun Gao static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev) 192af01d47dSLikun Gao { 193af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 194af01d47dSLikun Gao 0xFFFFFFFF); 195af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 196af01d47dSLikun Gao 0x0000000F); 197af01d47dSLikun Gao 198af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 199af01d47dSLikun Gao 0); 200af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 201af01d47dSLikun Gao 0); 202af01d47dSLikun Gao 203af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 204af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 205af01d47dSLikun Gao 206af01d47dSLikun Gao } 207af01d47dSLikun Gao 208af01d47dSLikun Gao static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev) 209af01d47dSLikun Gao { 21013ae12d9SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 211af01d47dSLikun Gao int i; 212af01d47dSLikun Gao uint32_t tmp; 213af01d47dSLikun Gao 214af01d47dSLikun Gao for (i = 0; i <= 14; i++) { 215af01d47dSLikun Gao tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 216af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 217af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 218af01d47dSLikun Gao adev->vm_manager.num_level); 219af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 220af01d47dSLikun Gao RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 221af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 222af01d47dSLikun Gao DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 223af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 224af01d47dSLikun Gao PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 225af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 226af01d47dSLikun Gao VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 227af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 228af01d47dSLikun Gao READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 229af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 230af01d47dSLikun Gao WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 231af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 232af01d47dSLikun Gao EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 233af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 234af01d47dSLikun Gao PAGE_TABLE_BLOCK_SIZE, 235af01d47dSLikun Gao adev->vm_manager.block_size - 9); 236af01d47dSLikun Gao /* Send no-retry XNACK on fault to suppress VM fault storm. */ 237af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 238af01d47dSLikun Gao RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 239af01d47dSLikun Gao !amdgpu_noretry); 24013ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 24113ae12d9SHuang Rui i * hub->ctx_distance, tmp); 24213ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 24313ae12d9SHuang Rui i * hub->ctx_addr_distance, 0); 24413ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 24513ae12d9SHuang Rui i * hub->ctx_addr_distance, 0); 24613ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 24713ae12d9SHuang Rui i * hub->ctx_addr_distance, 248af01d47dSLikun Gao lower_32_bits(adev->vm_manager.max_pfn - 1)); 24913ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 25013ae12d9SHuang Rui i * hub->ctx_addr_distance, 251af01d47dSLikun Gao upper_32_bits(adev->vm_manager.max_pfn - 1)); 252af01d47dSLikun Gao } 253af01d47dSLikun Gao } 254af01d47dSLikun Gao 255af01d47dSLikun Gao static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev) 256af01d47dSLikun Gao { 25713ae12d9SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 258af01d47dSLikun Gao unsigned i; 259af01d47dSLikun Gao 260af01d47dSLikun Gao for (i = 0 ; i < 18; ++i) { 261af01d47dSLikun Gao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 26213ae12d9SHuang Rui i * hub->eng_addr_distance, 0xffffffff); 263af01d47dSLikun Gao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 26413ae12d9SHuang Rui i * hub->eng_addr_distance, 0x1f); 265af01d47dSLikun Gao } 266af01d47dSLikun Gao } 267af01d47dSLikun Gao 268af01d47dSLikun Gao int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev) 269af01d47dSLikun Gao { 270af01d47dSLikun Gao if (amdgpu_sriov_vf(adev)) { 271af01d47dSLikun Gao /* 272af01d47dSLikun Gao * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 273af01d47dSLikun Gao * VF copy registers so vbios post doesn't program them, for 274af01d47dSLikun Gao * SRIOV driver need to program them 275af01d47dSLikun Gao */ 276af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, 277af01d47dSLikun Gao adev->gmc.vram_start >> 24); 278af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, 279af01d47dSLikun Gao adev->gmc.vram_end >> 24); 280af01d47dSLikun Gao } 281af01d47dSLikun Gao 282af01d47dSLikun Gao /* GART Enable. */ 283af01d47dSLikun Gao gfxhub_v2_1_init_gart_aperture_regs(adev); 284af01d47dSLikun Gao gfxhub_v2_1_init_system_aperture_regs(adev); 285af01d47dSLikun Gao gfxhub_v2_1_init_tlb_regs(adev); 286af01d47dSLikun Gao gfxhub_v2_1_init_cache_regs(adev); 287af01d47dSLikun Gao 288af01d47dSLikun Gao gfxhub_v2_1_enable_system_domain(adev); 289af01d47dSLikun Gao gfxhub_v2_1_disable_identity_aperture(adev); 290af01d47dSLikun Gao gfxhub_v2_1_setup_vmid_config(adev); 291af01d47dSLikun Gao gfxhub_v2_1_program_invalidation(adev); 292af01d47dSLikun Gao 293af01d47dSLikun Gao return 0; 294af01d47dSLikun Gao } 295af01d47dSLikun Gao 296af01d47dSLikun Gao void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev) 297af01d47dSLikun Gao { 29813ae12d9SHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 299af01d47dSLikun Gao u32 tmp; 300af01d47dSLikun Gao u32 i; 301af01d47dSLikun Gao 302af01d47dSLikun Gao /* Disable all tables */ 303af01d47dSLikun Gao for (i = 0; i < 16; i++) 30413ae12d9SHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 30513ae12d9SHuang Rui i * hub->ctx_distance, 0); 306af01d47dSLikun Gao 307af01d47dSLikun Gao /* Setup TLB control */ 308af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 309af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 310af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 311af01d47dSLikun Gao ENABLE_ADVANCED_DRIVER_MODEL, 0); 312af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 313af01d47dSLikun Gao 314af01d47dSLikun Gao /* Setup L2 cache */ 315af01d47dSLikun Gao WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 316af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 317af01d47dSLikun Gao } 318af01d47dSLikun Gao 319af01d47dSLikun Gao /** 320af01d47dSLikun Gao * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling 321af01d47dSLikun Gao * 322af01d47dSLikun Gao * @adev: amdgpu_device pointer 323af01d47dSLikun Gao * @value: true redirects VM faults to the default page 324af01d47dSLikun Gao */ 325af01d47dSLikun Gao void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev, 326af01d47dSLikun Gao bool value) 327af01d47dSLikun Gao { 328af01d47dSLikun Gao u32 tmp; 329af01d47dSLikun Gao tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 330af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 331af01d47dSLikun Gao RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 332af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 333af01d47dSLikun Gao PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 334af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 335af01d47dSLikun Gao PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 336af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 337af01d47dSLikun Gao PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 338af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 339af01d47dSLikun Gao TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 340af01d47dSLikun Gao value); 341af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 342af01d47dSLikun Gao NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 343af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 344af01d47dSLikun Gao DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 345af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 346af01d47dSLikun Gao VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 347af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 348af01d47dSLikun Gao READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 349af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 350af01d47dSLikun Gao WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 351af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 352af01d47dSLikun Gao EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 353af01d47dSLikun Gao if (!value) { 354af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 355af01d47dSLikun Gao CRASH_ON_NO_RETRY_FAULT, 1); 356af01d47dSLikun Gao tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 357af01d47dSLikun Gao CRASH_ON_RETRY_FAULT, 1); 358af01d47dSLikun Gao } 359af01d47dSLikun Gao WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 360af01d47dSLikun Gao } 361af01d47dSLikun Gao 362af01d47dSLikun Gao void gfxhub_v2_1_init(struct amdgpu_device *adev) 363af01d47dSLikun Gao { 364af01d47dSLikun Gao struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 365af01d47dSLikun Gao 366af01d47dSLikun Gao hub->ctx0_ptb_addr_lo32 = 367af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, 368af01d47dSLikun Gao mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 369af01d47dSLikun Gao hub->ctx0_ptb_addr_hi32 = 370af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, 371af01d47dSLikun Gao mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 372af01d47dSLikun Gao hub->vm_inv_eng0_sem = 373af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 374af01d47dSLikun Gao hub->vm_inv_eng0_req = 375af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 376af01d47dSLikun Gao hub->vm_inv_eng0_ack = 377af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 378af01d47dSLikun Gao hub->vm_context0_cntl = 379af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 380af01d47dSLikun Gao hub->vm_l2_pro_fault_status = 381af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 382af01d47dSLikun Gao hub->vm_l2_pro_fault_cntl = 383af01d47dSLikun Gao SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 3841f9d56c3SHuang Rui 3851f9d56c3SHuang Rui hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL; 3861f9d56c3SHuang Rui hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 3871f9d56c3SHuang Rui mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 3881f9d56c3SHuang Rui hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ - 3891f9d56c3SHuang Rui mmGCVM_INVALIDATE_ENG0_REQ; 3901f9d56c3SHuang Rui hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 3911f9d56c3SHuang Rui mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 3925befb6fcSHuang Rui 3935befb6fcSHuang Rui hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3945befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3955befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3965befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3975befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3985befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3995befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 400af01d47dSLikun Gao } 401fdb8483bSJohn Clements 402fdb8483bSJohn Clements int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev) 403fdb8483bSJohn Clements { 404fdb8483bSJohn Clements u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL); 405fdb8483bSJohn Clements u32 max_region = 406fdb8483bSJohn Clements REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); 407fdb8483bSJohn Clements u32 max_num_physical_nodes = 0; 408fdb8483bSJohn Clements u32 max_physical_node_id = 0; 409fdb8483bSJohn Clements 410fdb8483bSJohn Clements switch (adev->asic_type) { 411fdb8483bSJohn Clements case CHIP_SIENNA_CICHLID: 412fdb8483bSJohn Clements max_num_physical_nodes = 4; 413fdb8483bSJohn Clements max_physical_node_id = 3; 414fdb8483bSJohn Clements break; 415fdb8483bSJohn Clements default: 416fdb8483bSJohn Clements return -EINVAL; 417fdb8483bSJohn Clements } 418fdb8483bSJohn Clements 419fdb8483bSJohn Clements /* PF_MAX_REGION=0 means xgmi is disabled */ 420fdb8483bSJohn Clements if (max_region) { 421fdb8483bSJohn Clements adev->gmc.xgmi.num_physical_nodes = max_region + 1; 422fdb8483bSJohn Clements if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) 423fdb8483bSJohn Clements return -EINVAL; 424fdb8483bSJohn Clements 425fdb8483bSJohn Clements adev->gmc.xgmi.physical_node_id = 426fdb8483bSJohn Clements REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); 427fdb8483bSJohn Clements if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) 428fdb8483bSJohn Clements return -EINVAL; 429fdb8483bSJohn Clements 430fdb8483bSJohn Clements adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( 431fdb8483bSJohn Clements RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), 432fdb8483bSJohn Clements GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; 433fdb8483bSJohn Clements } 434fdb8483bSJohn Clements 435fdb8483bSJohn Clements return 0; 436fdb8483bSJohn Clements } 437