19c7c85f7SJonathan Kim /*
29c7c85f7SJonathan Kim  * Copyright 2019 Advanced Micro Devices, Inc.
39c7c85f7SJonathan Kim  *
49c7c85f7SJonathan Kim  * Permission is hereby granted, free of charge, to any person obtaining a
59c7c85f7SJonathan Kim  * copy of this software and associated documentation files (the "Software"),
69c7c85f7SJonathan Kim  * to deal in the Software without restriction, including without limitation
79c7c85f7SJonathan Kim  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
89c7c85f7SJonathan Kim  * and/or sell copies of the Software, and to permit persons to whom the
99c7c85f7SJonathan Kim  * Software is furnished to do so, subject to the following conditions:
109c7c85f7SJonathan Kim  *
119c7c85f7SJonathan Kim  * The above copyright notice and this permission notice shall be included in
129c7c85f7SJonathan Kim  * all copies or substantial portions of the Software.
139c7c85f7SJonathan Kim  *
149c7c85f7SJonathan Kim  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
159c7c85f7SJonathan Kim  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
169c7c85f7SJonathan Kim  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
179c7c85f7SJonathan Kim  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
189c7c85f7SJonathan Kim  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
199c7c85f7SJonathan Kim  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
209c7c85f7SJonathan Kim  * OTHER DEALINGS IN THE SOFTWARE.
219c7c85f7SJonathan Kim  *
229c7c85f7SJonathan Kim  */
239c7c85f7SJonathan Kim 
249c7c85f7SJonathan Kim #ifndef _AMDGPU_PMU_H_
259c7c85f7SJonathan Kim #define _AMDGPU_PMU_H_
269c7c85f7SJonathan Kim 
27*b4a7db71SJonathan Kim /* PMU types. */
289c7c85f7SJonathan Kim enum amdgpu_pmu_perf_type {
29*b4a7db71SJonathan Kim 	AMDGPU_PMU_PERF_TYPE_NONE = 0,
30*b4a7db71SJonathan Kim 	AMDGPU_PMU_PERF_TYPE_DF,
31*b4a7db71SJonathan Kim 	AMDGPU_PMU_PERF_TYPE_ALL
329c7c85f7SJonathan Kim };
339c7c85f7SJonathan Kim 
34*b4a7db71SJonathan Kim /*
35*b4a7db71SJonathan Kim  * PMU type AMDGPU_PMU_PERF_TYPE_ALL can hold events of different "type"
36*b4a7db71SJonathan Kim  * configurations.  Event config types are parsed from the 64-bit raw
37*b4a7db71SJonathan Kim  * config (See EVENT_CONFIG_TYPE_SHIFT and EVENT_CONFIG_TYPE_MASK) and
38*b4a7db71SJonathan Kim  * are registered into the HW perf events config_base.
39*b4a7db71SJonathan Kim  *
40*b4a7db71SJonathan Kim  * PMU types with only a single event configuration type
41*b4a7db71SJonathan Kim  * (non-AMDGPU_PMU_PERF_TYPE_ALL) have their event config type auto generated
42*b4a7db71SJonathan Kim  * when the performance counter is added.
43*b4a7db71SJonathan Kim  */
44*b4a7db71SJonathan Kim enum amdgpu_pmu_event_config_type {
45*b4a7db71SJonathan Kim 	AMDGPU_PMU_EVENT_CONFIG_TYPE_NONE = 0,
46*b4a7db71SJonathan Kim 	AMDGPU_PMU_EVENT_CONFIG_TYPE_DF,
47*b4a7db71SJonathan Kim 	AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI,
48*b4a7db71SJonathan Kim 	AMDGPU_PMU_EVENT_CONFIG_TYPE_MAX
49*b4a7db71SJonathan Kim };
50*b4a7db71SJonathan Kim 
51*b4a7db71SJonathan Kim #define AMDGPU_PMU_EVENT_CONFIG_TYPE_SHIFT	56
52*b4a7db71SJonathan Kim #define AMDGPU_PMU_EVENT_CONFIG_TYPE_MASK	0xff
53*b4a7db71SJonathan Kim 
549c7c85f7SJonathan Kim int amdgpu_pmu_init(struct amdgpu_device *adev);
559c7c85f7SJonathan Kim void amdgpu_pmu_fini(struct amdgpu_device *adev);
569c7c85f7SJonathan Kim 
579c7c85f7SJonathan Kim #endif /* _AMDGPU_PMU_H_ */
58