1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef _AMDGPU_PMU_H_
25 #define _AMDGPU_PMU_H_
26 
27 /* PMU types. */
28 enum amdgpu_pmu_perf_type {
29 	AMDGPU_PMU_PERF_TYPE_NONE = 0,
30 	AMDGPU_PMU_PERF_TYPE_DF,
31 	AMDGPU_PMU_PERF_TYPE_ALL
32 };
33 
34 /*
35  * PMU type AMDGPU_PMU_PERF_TYPE_ALL can hold events of different "type"
36  * configurations.  Event config types are parsed from the 64-bit raw
37  * config (See EVENT_CONFIG_TYPE_SHIFT and EVENT_CONFIG_TYPE_MASK) and
38  * are registered into the HW perf events config_base.
39  *
40  * PMU types with only a single event configuration type
41  * (non-AMDGPU_PMU_PERF_TYPE_ALL) have their event config type auto generated
42  * when the performance counter is added.
43  */
44 enum amdgpu_pmu_event_config_type {
45 	AMDGPU_PMU_EVENT_CONFIG_TYPE_NONE = 0,
46 	AMDGPU_PMU_EVENT_CONFIG_TYPE_DF,
47 	AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI,
48 	AMDGPU_PMU_EVENT_CONFIG_TYPE_MAX
49 };
50 
51 #define AMDGPU_PMU_EVENT_CONFIG_TYPE_SHIFT	56
52 #define AMDGPU_PMU_EVENT_CONFIG_TYPE_MASK	0xff
53 
54 int amdgpu_pmu_init(struct amdgpu_device *adev);
55 void amdgpu_pmu_fini(struct amdgpu_device *adev);
56 
57 #endif /* _AMDGPU_PMU_H_ */
58