xref: /openbmc/linux/drivers/fpga/dfl.h (revision 5c88af59)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Driver Header File for FPGA Device Feature List (DFL) Support
4  *
5  * Copyright (C) 2017-2018 Intel Corporation, Inc.
6  *
7  * Authors:
8  *   Kang Luwei <luwei.kang@intel.com>
9  *   Zhang Yi <yi.z.zhang@intel.com>
10  *   Wu Hao <hao.wu@intel.com>
11  *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
12  */
13 
14 #ifndef __FPGA_DFL_H
15 #define __FPGA_DFL_H
16 
17 #include <linux/bitfield.h>
18 #include <linux/cdev.h>
19 #include <linux/delay.h>
20 #include <linux/eventfd.h>
21 #include <linux/fs.h>
22 #include <linux/interrupt.h>
23 #include <linux/iopoll.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/mod_devicetable.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/uuid.h>
29 #include <linux/fpga/fpga-region.h>
30 
31 /* maximum supported number of ports */
32 #define MAX_DFL_FPGA_PORT_NUM 4
33 /* plus one for fme device */
34 #define MAX_DFL_FEATURE_DEV_NUM    (MAX_DFL_FPGA_PORT_NUM + 1)
35 
36 /* Reserved 0xfe for Header Group Register and 0xff for AFU */
37 #define FEATURE_ID_FIU_HEADER		0xfe
38 #define FEATURE_ID_AFU			0xff
39 
40 #define FME_FEATURE_ID_HEADER		FEATURE_ID_FIU_HEADER
41 #define FME_FEATURE_ID_THERMAL_MGMT	0x1
42 #define FME_FEATURE_ID_POWER_MGMT	0x2
43 #define FME_FEATURE_ID_GLOBAL_IPERF	0x3
44 #define FME_FEATURE_ID_GLOBAL_ERR	0x4
45 #define FME_FEATURE_ID_PR_MGMT		0x5
46 #define FME_FEATURE_ID_HSSI		0x6
47 #define FME_FEATURE_ID_GLOBAL_DPERF	0x7
48 
49 #define PORT_FEATURE_ID_HEADER		FEATURE_ID_FIU_HEADER
50 #define PORT_FEATURE_ID_AFU		FEATURE_ID_AFU
51 #define PORT_FEATURE_ID_ERROR		0x10
52 #define PORT_FEATURE_ID_UMSG		0x11
53 #define PORT_FEATURE_ID_UINT		0x12
54 #define PORT_FEATURE_ID_STP		0x13
55 
56 /*
57  * Device Feature Header Register Set
58  *
59  * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
60  * For AFUs, they have DFH + GUID as common header registers.
61  * For private features, they only have DFH register as common header.
62  */
63 #define DFH			0x0
64 #define GUID_L			0x8
65 #define GUID_H			0x10
66 #define NEXT_AFU		0x18
67 
68 #define DFH_SIZE		0x8
69 
70 /* Device Feature Header Register Bitfield */
71 #define DFH_ID			GENMASK_ULL(11, 0)	/* Feature ID */
72 #define DFH_ID_FIU_FME		0
73 #define DFH_ID_FIU_PORT		1
74 #define DFH_REVISION		GENMASK_ULL(15, 12)	/* Feature revision */
75 #define DFH_NEXT_HDR_OFST	GENMASK_ULL(39, 16)	/* Offset to next DFH */
76 #define DFH_EOL			BIT_ULL(40)		/* End of list */
77 #define DFH_TYPE		GENMASK_ULL(63, 60)	/* Feature type */
78 #define DFH_TYPE_AFU		1
79 #define DFH_TYPE_PRIVATE	3
80 #define DFH_TYPE_FIU		4
81 
82 /* Next AFU Register Bitfield */
83 #define NEXT_AFU_NEXT_DFH_OFST	GENMASK_ULL(23, 0)	/* Offset to next AFU */
84 
85 /* FME Header Register Set */
86 #define FME_HDR_DFH		DFH
87 #define FME_HDR_GUID_L		GUID_L
88 #define FME_HDR_GUID_H		GUID_H
89 #define FME_HDR_NEXT_AFU	NEXT_AFU
90 #define FME_HDR_CAP		0x30
91 #define FME_HDR_PORT_OFST(n)	(0x38 + ((n) * 0x8))
92 #define FME_HDR_BITSTREAM_ID	0x60
93 #define FME_HDR_BITSTREAM_MD	0x68
94 
95 /* FME Fab Capability Register Bitfield */
96 #define FME_CAP_FABRIC_VERID	GENMASK_ULL(7, 0)	/* Fabric version ID */
97 #define FME_CAP_SOCKET_ID	BIT_ULL(8)		/* Socket ID */
98 #define FME_CAP_PCIE0_LINK_AVL	BIT_ULL(12)		/* PCIE0 Link */
99 #define FME_CAP_PCIE1_LINK_AVL	BIT_ULL(13)		/* PCIE1 Link */
100 #define FME_CAP_COHR_LINK_AVL	BIT_ULL(14)		/* Coherent Link */
101 #define FME_CAP_IOMMU_AVL	BIT_ULL(16)		/* IOMMU available */
102 #define FME_CAP_NUM_PORTS	GENMASK_ULL(19, 17)	/* Number of ports */
103 #define FME_CAP_ADDR_WIDTH	GENMASK_ULL(29, 24)	/* Address bus width */
104 #define FME_CAP_CACHE_SIZE	GENMASK_ULL(43, 32)	/* cache size in KB */
105 #define FME_CAP_CACHE_ASSOC	GENMASK_ULL(47, 44)	/* Associativity */
106 
107 /* FME Port Offset Register Bitfield */
108 /* Offset to port device feature header */
109 #define FME_PORT_OFST_DFH_OFST	GENMASK_ULL(23, 0)
110 /* PCI Bar ID for this port */
111 #define FME_PORT_OFST_BAR_ID	GENMASK_ULL(34, 32)
112 /* AFU MMIO access permission. 1 - VF, 0 - PF. */
113 #define FME_PORT_OFST_ACC_CTRL	BIT_ULL(55)
114 #define FME_PORT_OFST_ACC_PF	0
115 #define FME_PORT_OFST_ACC_VF	1
116 #define FME_PORT_OFST_IMP	BIT_ULL(60)
117 
118 /* FME Error Capability Register */
119 #define FME_ERROR_CAP		0x70
120 
121 /* FME Error Capability Register Bitfield */
122 #define FME_ERROR_CAP_SUPP_INT	BIT_ULL(0)		/* Interrupt Support */
123 #define FME_ERROR_CAP_INT_VECT	GENMASK_ULL(12, 1)	/* Interrupt vector */
124 
125 /* PORT Header Register Set */
126 #define PORT_HDR_DFH		DFH
127 #define PORT_HDR_GUID_L		GUID_L
128 #define PORT_HDR_GUID_H		GUID_H
129 #define PORT_HDR_NEXT_AFU	NEXT_AFU
130 #define PORT_HDR_CAP		0x30
131 #define PORT_HDR_CTRL		0x38
132 #define PORT_HDR_STS		0x40
133 #define PORT_HDR_USRCLK_CMD0	0x50
134 #define PORT_HDR_USRCLK_CMD1	0x58
135 #define PORT_HDR_USRCLK_STS0	0x60
136 #define PORT_HDR_USRCLK_STS1	0x68
137 
138 /* Port Capability Register Bitfield */
139 #define PORT_CAP_PORT_NUM	GENMASK_ULL(1, 0)	/* ID of this port */
140 #define PORT_CAP_MMIO_SIZE	GENMASK_ULL(23, 8)	/* MMIO size in KB */
141 #define PORT_CAP_SUPP_INT_NUM	GENMASK_ULL(35, 32)	/* Interrupts num */
142 
143 /* Port Control Register Bitfield */
144 #define PORT_CTRL_SFTRST	BIT_ULL(0)		/* Port soft reset */
145 /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
146 #define PORT_CTRL_LATENCY	BIT_ULL(2)
147 #define PORT_CTRL_SFTRST_ACK	BIT_ULL(4)		/* HW ack for reset */
148 
149 /* Port Status Register Bitfield */
150 #define PORT_STS_AP2_EVT	BIT_ULL(13)		/* AP2 event detected */
151 #define PORT_STS_AP1_EVT	BIT_ULL(12)		/* AP1 event detected */
152 #define PORT_STS_PWR_STATE	GENMASK_ULL(11, 8)	/* AFU power states */
153 #define PORT_STS_PWR_STATE_NORM 0
154 #define PORT_STS_PWR_STATE_AP1	1			/* 50% throttling */
155 #define PORT_STS_PWR_STATE_AP2	2			/* 90% throttling */
156 #define PORT_STS_PWR_STATE_AP6	6			/* 100% throttling */
157 
158 /* Port Error Capability Register */
159 #define PORT_ERROR_CAP		0x38
160 
161 /* Port Error Capability Register Bitfield */
162 #define PORT_ERROR_CAP_SUPP_INT	BIT_ULL(0)		/* Interrupt Support */
163 #define PORT_ERROR_CAP_INT_VECT	GENMASK_ULL(12, 1)	/* Interrupt vector */
164 
165 /* Port Uint Capability Register */
166 #define PORT_UINT_CAP		0x8
167 
168 /* Port Uint Capability Register Bitfield */
169 #define PORT_UINT_CAP_INT_NUM	GENMASK_ULL(11, 0)	/* Interrupts num */
170 #define PORT_UINT_CAP_FST_VECT	GENMASK_ULL(23, 12)	/* First Vector */
171 
172 /**
173  * struct dfl_fpga_port_ops - port ops
174  *
175  * @name: name of this port ops, to match with port platform device.
176  * @owner: pointer to the module which owns this port ops.
177  * @node: node to link port ops to global list.
178  * @get_id: get port id from hardware.
179  * @enable_set: enable/disable the port.
180  */
181 struct dfl_fpga_port_ops {
182 	const char *name;
183 	struct module *owner;
184 	struct list_head node;
185 	int (*get_id)(struct platform_device *pdev);
186 	int (*enable_set)(struct platform_device *pdev, bool enable);
187 };
188 
189 void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
190 void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
191 struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
192 void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
193 int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);
194 
195 /**
196  * struct dfl_feature_id - dfl private feature id
197  *
198  * @id: unique dfl private feature id.
199  */
200 struct dfl_feature_id {
201 	u16 id;
202 };
203 
204 /**
205  * struct dfl_feature_driver - dfl private feature driver
206  *
207  * @id_table: id_table for dfl private features supported by this driver.
208  * @ops: ops of this dfl private feature driver.
209  */
210 struct dfl_feature_driver {
211 	const struct dfl_feature_id *id_table;
212 	const struct dfl_feature_ops *ops;
213 };
214 
215 /**
216  * struct dfl_feature_irq_ctx - dfl private feature interrupt context
217  *
218  * @irq: Linux IRQ number of this interrupt.
219  * @trigger: eventfd context to signal when interrupt happens.
220  * @name: irq name needed when requesting irq.
221  */
222 struct dfl_feature_irq_ctx {
223 	int irq;
224 	struct eventfd_ctx *trigger;
225 	char *name;
226 };
227 
228 /**
229  * struct dfl_feature - sub feature of the feature devices
230  *
231  * @dev: ptr to pdev of the feature device which has the sub feature.
232  * @id: sub feature id.
233  * @resource_index: each sub feature has one mmio resource for its registers.
234  *		    this index is used to find its mmio resource from the
235  *		    feature dev (platform device)'s reources.
236  * @ioaddr: mapped mmio resource address.
237  * @irq_ctx: interrupt context list.
238  * @nr_irqs: number of interrupt contexts.
239  * @ops: ops of this sub feature.
240  * @ddev: ptr to the dfl device of this sub feature.
241  * @priv: priv data of this feature.
242  */
243 struct dfl_feature {
244 	struct platform_device *dev;
245 	u16 id;
246 	int resource_index;
247 	void __iomem *ioaddr;
248 	struct dfl_feature_irq_ctx *irq_ctx;
249 	unsigned int nr_irqs;
250 	const struct dfl_feature_ops *ops;
251 	struct dfl_device *ddev;
252 	void *priv;
253 };
254 
255 #define FEATURE_DEV_ID_UNUSED	(-1)
256 
257 /**
258  * struct dfl_feature_platform_data - platform data for feature devices
259  *
260  * @node: node to link feature devs to container device's port_dev_list.
261  * @lock: mutex to protect platform data.
262  * @cdev: cdev of feature dev.
263  * @dev: ptr to platform device linked with this platform data.
264  * @dfl_cdev: ptr to container device.
265  * @id: id used for this feature device.
266  * @disable_count: count for port disable.
267  * @excl_open: set on feature device exclusive open.
268  * @open_count: count for feature device open.
269  * @num: number for sub features.
270  * @private: ptr to feature dev private data.
271  * @features: sub features of this feature dev.
272  */
273 struct dfl_feature_platform_data {
274 	struct list_head node;
275 	struct mutex lock;
276 	struct cdev cdev;
277 	struct platform_device *dev;
278 	struct dfl_fpga_cdev *dfl_cdev;
279 	int id;
280 	unsigned int disable_count;
281 	bool excl_open;
282 	int open_count;
283 	void *private;
284 	int num;
285 	struct dfl_feature features[];
286 };
287 
288 static inline
289 int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata,
290 			      bool excl)
291 {
292 	if (pdata->excl_open)
293 		return -EBUSY;
294 
295 	if (excl) {
296 		if (pdata->open_count)
297 			return -EBUSY;
298 
299 		pdata->excl_open = true;
300 	}
301 	pdata->open_count++;
302 
303 	return 0;
304 }
305 
306 static inline
307 void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
308 {
309 	pdata->excl_open = false;
310 
311 	if (WARN_ON(pdata->open_count <= 0))
312 		return;
313 
314 	pdata->open_count--;
315 }
316 
317 static inline
318 int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata)
319 {
320 	return pdata->open_count;
321 }
322 
323 static inline
324 void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
325 				void *private)
326 {
327 	pdata->private = private;
328 }
329 
330 static inline
331 void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)
332 {
333 	return pdata->private;
334 }
335 
336 struct dfl_feature_ops {
337 	int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
338 	void (*uinit)(struct platform_device *pdev,
339 		      struct dfl_feature *feature);
340 	long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
341 		      unsigned int cmd, unsigned long arg);
342 };
343 
344 #define DFL_FPGA_FEATURE_DEV_FME		"dfl-fme"
345 #define DFL_FPGA_FEATURE_DEV_PORT		"dfl-port"
346 
347 void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
348 int dfl_fpga_dev_feature_init(struct platform_device *pdev,
349 			      struct dfl_feature_driver *feature_drvs);
350 
351 int dfl_fpga_dev_ops_register(struct platform_device *pdev,
352 			      const struct file_operations *fops,
353 			      struct module *owner);
354 void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
355 
356 static inline
357 struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)
358 {
359 	struct dfl_feature_platform_data *pdata;
360 
361 	pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
362 			     cdev);
363 	return pdata->dev;
364 }
365 
366 #define dfl_fpga_dev_for_each_feature(pdata, feature)			    \
367 	for ((feature) = (pdata)->features;				    \
368 	   (feature) < (pdata)->features + (pdata)->num; (feature)++)
369 
370 static inline
371 struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u16 id)
372 {
373 	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
374 	struct dfl_feature *feature;
375 
376 	dfl_fpga_dev_for_each_feature(pdata, feature)
377 		if (feature->id == id)
378 			return feature;
379 
380 	return NULL;
381 }
382 
383 static inline
384 void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u16 id)
385 {
386 	struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
387 
388 	if (feature && feature->ioaddr)
389 		return feature->ioaddr;
390 
391 	WARN_ON(1);
392 	return NULL;
393 }
394 
395 static inline bool is_dfl_feature_present(struct device *dev, u16 id)
396 {
397 	return !!dfl_get_feature_ioaddr_by_id(dev, id);
398 }
399 
400 static inline
401 struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)
402 {
403 	return pdata->dev->dev.parent->parent;
404 }
405 
406 static inline bool dfl_feature_is_fme(void __iomem *base)
407 {
408 	u64 v = readq(base + DFH);
409 
410 	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
411 		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
412 }
413 
414 static inline bool dfl_feature_is_port(void __iomem *base)
415 {
416 	u64 v = readq(base + DFH);
417 
418 	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
419 		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
420 }
421 
422 static inline u8 dfl_feature_revision(void __iomem *base)
423 {
424 	return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
425 }
426 
427 /**
428  * struct dfl_fpga_enum_info - DFL FPGA enumeration information
429  *
430  * @dev: parent device.
431  * @dfls: list of device feature lists.
432  * @nr_irqs: number of irqs for all feature devices.
433  * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers.
434  */
435 struct dfl_fpga_enum_info {
436 	struct device *dev;
437 	struct list_head dfls;
438 	unsigned int nr_irqs;
439 	int *irq_table;
440 };
441 
442 /**
443  * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
444  *
445  * @start: base address of this device feature list.
446  * @len: size of this device feature list.
447  * @node: node in list of device feature lists.
448  */
449 struct dfl_fpga_enum_dfl {
450 	resource_size_t start;
451 	resource_size_t len;
452 	struct list_head node;
453 };
454 
455 struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
456 int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
457 			       resource_size_t start, resource_size_t len);
458 int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,
459 			       unsigned int nr_irqs, int *irq_table);
460 void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
461 
462 /**
463  * struct dfl_fpga_cdev - container device of DFL based FPGA
464  *
465  * @parent: parent device of this container device.
466  * @region: base fpga region.
467  * @fme_dev: FME feature device under this container device.
468  * @lock: mutex lock to protect the port device list.
469  * @port_dev_list: list of all port feature devices under this container device.
470  * @released_port_num: released port number under this container device.
471  */
472 struct dfl_fpga_cdev {
473 	struct device *parent;
474 	struct fpga_region *region;
475 	struct device *fme_dev;
476 	struct mutex lock;
477 	struct list_head port_dev_list;
478 	int released_port_num;
479 };
480 
481 struct dfl_fpga_cdev *
482 dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
483 void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
484 
485 /*
486  * need to drop the device reference with put_device() after use port platform
487  * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
488  * functions.
489  */
490 struct platform_device *
491 __dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
492 			  int (*match)(struct platform_device *, void *));
493 
494 static inline struct platform_device *
495 dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
496 			int (*match)(struct platform_device *, void *))
497 {
498 	struct platform_device *pdev;
499 
500 	mutex_lock(&cdev->lock);
501 	pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
502 	mutex_unlock(&cdev->lock);
503 
504 	return pdev;
505 }
506 
507 int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
508 int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
509 void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
510 int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
511 int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start,
512 			      unsigned int count, int32_t *fds);
513 long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev,
514 				    struct dfl_feature *feature,
515 				    unsigned long arg);
516 long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
517 			       struct dfl_feature *feature,
518 			       unsigned long arg);
519 
520 #endif /* __FPGA_DFL_H */
521