Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7 |
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#
a73c125b |
| 14-Jan-2023 |
Xu Yilun <yilun.xu@intel.com> |
fpga: dfl: more kernel-doc corrections
Fix more kernel-doc warnings in drivers/fpga/:
$ ./scripts/kernel-doc -none drivers/fpga/* drivers/fpga/dfl-afu.h:61: warning: expecting prototype for struct
fpga: dfl: more kernel-doc corrections
Fix more kernel-doc warnings in drivers/fpga/:
$ ./scripts/kernel-doc -none drivers/fpga/* drivers/fpga/dfl-afu.h:61: warning: expecting prototype for struct fpga_afu_dma_region. Prototype was for struct dfl_afu_dma_region instead drivers/fpga/dfl-afu-region.c:52: warning: Function parameter or member 'pdata' not described in 'afu_mmio_region_add' drivers/fpga/dfl-fme-perf.c:161: warning: Function parameter or member 'node' not described in 'fme_perf_priv' drivers/fpga/dfl-fme-pr.h:70: warning: expecting prototype for struct dfl_fme_bridge_pdata. Prototype was for struct dfl_fme_br_pdata instead drivers/fpga/dfl.h:256: warning: Function parameter or member 'revision' not described in 'dfl_feature'
Signed-off-by: Xu Yilun <yilun.xu@intel.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20230114155444.794712-1-yilun.xu@intel.com
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#
4747ab89 |
| 15-Jan-2023 |
Matthew Gerlach <matthew.gerlach@linux.intel.com> |
fpga: dfl: add basic support for DFHv1
Version 1 of the Device Feature Header (DFH) definition adds functionality to the Device Feature List (DFL) bus.
A DFHv1 header may have one or more parameter
fpga: dfl: add basic support for DFHv1
Version 1 of the Device Feature Header (DFH) definition adds functionality to the Device Feature List (DFL) bus.
A DFHv1 header may have one or more parameter blocks that further describes the HW to SW. Add support to the DFL bus to parse the MSI-X parameter.
The location of a feature's register set is explicitly described in DFHv1 and can be relative to the base of the DFHv1 or an absolute address. Parse the location and pass the information to DFL driver.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20230115151447.1353428-4-matthew.gerlach@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
0926d8d5 |
| 15-Jan-2023 |
Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com> |
fpga: dfl: Add DFHv1 Register Definitions
This patch adds the definitions for DFHv1 header and related register bitfields.
Signed-off-by: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.in
fpga: dfl: Add DFHv1 Register Definitions
This patch adds the definitions for DFHv1 header and related register bitfields.
Signed-off-by: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com> Co-developed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230115151447.1353428-3-matthew.gerlach@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38 |
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#
ae23f746 |
| 05-May-2022 |
Matthew Gerlach <matthew.gerlach@linux.intel.com> |
fpga: dfl: Allow Port to be linked to FME's DFL
Currently we use PORTn_OFFSET to locate PORT DFLs, and PORT DFLs are not connected FME DFL. But for some cases (e.g. Intel Open FPGA Stack device), PO
fpga: dfl: Allow Port to be linked to FME's DFL
Currently we use PORTn_OFFSET to locate PORT DFLs, and PORT DFLs are not connected FME DFL. But for some cases (e.g. Intel Open FPGA Stack device), PORT DFLs are connected to FME DFL directly, so we don't need to search PORT DFLs via PORTn_OFFSET again. If BAR value of PORTn_OFFSET is 0x7 (FME_PORT_OFST_BAR_SKIP) then driver will skip searching the DFL for that port. If BAR value is invalid, return -EINVAL.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Acked-by: Wu Hao <hao.wu@intel.com> Link: https://lore.kernel.org/r/20220505100617.703672-1-tianfei.zhang@intel.com Signed-off-by: Xu Yilun <yilun.xu@intel.com>
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Revision tags: v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51 |
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#
1604986c |
| 16-Jul-2021 |
Martin Hundebøll <mhu@silicom.dk> |
fpga: dfl: expose feature revision from struct dfl_device
DFL device drivers have a common need for checking feature revision information from the DFL header, as well as other common DFL information
fpga: dfl: expose feature revision from struct dfl_device
DFL device drivers have a common need for checking feature revision information from the DFL header, as well as other common DFL information like the already exposed feature id and type.
This patch exposes the feature revision information directly via the DFL device data structure.
Since the DFL core code has already read the DFL header, this this patch saves additional mmio reads from DFL device drivers too.
Acked-by: Wu Hao <hao.wu@intel.com> Acked-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Martin Hundebøll <mhu@silicom.dk> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Revision tags: v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39 |
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#
580e3137 |
| 19-May-2021 |
Tom Rix <trix@redhat.com> |
fpga: fix spelling mistakes
Run the fpga subsystem through aspell.
Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Fernando Pacheco <fpacheco@redhat.com> Signed-off-by: Moritz Fischer <mdf@ke
fpga: fix spelling mistakes
Run the fpga subsystem through aspell.
Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Fernando Pacheco <fpacheco@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Revision tags: v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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#
ecc1641a |
| 06-Jan-2021 |
Xu Yilun <yilun.xu@intel.com> |
fpga: dfl: move dfl bus related APIs to include/linux/dfl.h
Now the dfl drivers could be made as independent modules and put in different folders according to their functionalities. In order for sca
fpga: dfl: move dfl bus related APIs to include/linux/dfl.h
Now the dfl drivers could be made as independent modules and put in different folders according to their functionalities. In order for scattered dfl device drivers to include dfl bus APIs, move the dfl bus APIs to a new header file in the public folder.
[mdf@kernel.org: Fixed up header guards to match filename]
Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20210107043714.991646-7-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
9326eecd |
| 06-Jan-2021 |
Xu Yilun <yilun.xu@intel.com> |
fpga: dfl: move dfl_device_id to mod_devicetable.h
In order to support MODULE_DEVICE_TABLE() for dfl device driver, this patch moves struct dfl_device_id to mod_devicetable.h
Some brief description
fpga: dfl: move dfl_device_id to mod_devicetable.h
In order to support MODULE_DEVICE_TABLE() for dfl device driver, this patch moves struct dfl_device_id to mod_devicetable.h
Some brief description for DFL (Device Feature List) is added to make the DFL known to the whole kernel.
Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20210107043714.991646-5-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
e08b9e6d |
| 06-Jan-2021 |
Xu Yilun <yilun.xu@intel.com> |
fpga: dfl: fix the definitions of type & feature_id for dfl devices
The value of the field dfl_device.type comes from the 12 bits register field DFH_ID according to DFL spec. So this patch changes t
fpga: dfl: fix the definitions of type & feature_id for dfl devices
The value of the field dfl_device.type comes from the 12 bits register field DFH_ID according to DFL spec. So this patch changes the definition of the type field to u16.
Also it is not necessary to illustrate the valid bits of the type field in comments. Instead we should explicitly define the possible values in the enumeration type for it, because they are shared by hardware spec. We should not let the compiler decide these values.
Similar changes are also applied to dfl_device.feature_id.
This patch also fixed the MODALIAS format according to the changes above.
Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/20210107043714.991646-4-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8 |
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#
9ba3a0aa |
| 07-Sep-2020 |
Xu Yilun <yilun.xu@intel.com> |
fpga: dfl: create a dfl bus type to support DFL devices
A new bus type "dfl" is introduced for private features which are not initialized by DFL feature drivers (dfl-fme & dfl-afu drivers). So these
fpga: dfl: create a dfl bus type to support DFL devices
A new bus type "dfl" is introduced for private features which are not initialized by DFL feature drivers (dfl-fme & dfl-afu drivers). So these private features could be handled by separate driver modules.
DFL feature drivers (dfl-fme, dfl-port) will create DFL devices on enumeration. DFL drivers could be registered on this bus to match these DFL devices. They are matched by dfl type & feature_id.
[mdf@kernel.org: Add missing Documentation part to MAINTAINERS file]
Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Revision tags: v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60 |
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#
89eb35e8 |
| 19-Aug-2020 |
Xu Yilun <yilun.xu@intel.com> |
fpga: dfl: map feature mmio resources in their own feature drivers
This patch makes preparation for modularization of DFL sub feature drivers.
DFL based FPGA devices may contain some IP blocks whic
fpga: dfl: map feature mmio resources in their own feature drivers
This patch makes preparation for modularization of DFL sub feature drivers.
DFL based FPGA devices may contain some IP blocks which are already supported by kernel, most of them are supported by platform device drivers. We could create platform devices for these IP blocks and get them supported by these drivers.
An important issue is that platform device drivers usually requests mmio resources on probe. But now DFL mmio is mapped in DFL bus driver (e.g. dfl-pci) as a whole region. Then platform device drivers for sub features can't request their own mmio resources again. This is what the patch trying to resolve.
This patch changes the DFL enumeration. DFL bus driver will unmap mmio resources after first step enumeration and pass enumeration info to DFL framework. Then DFL framework will map the mmio resources again, do 2nd step enumeration, and also unmap the mmio resources. In this way, sub feature drivers could then request their own mmio resources as needed.
An exception is that mmio resource of FIU headers are still mapped in DFL bus driver. The FIU headers have some fundamental functions (sriov set, port enable/disable) needed for DFL bus devices and other sub features. They should not be unmapped as long as DFL bus device is alive.
Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Revision tags: v5.8.2, v5.4.59, v5.8.1, v5.4.58 |
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#
8a5de2de |
| 09-Aug-2020 |
Xu Yilun <yilun.xu@intel.com> |
fpga: dfl: change data type of feature id to u16
The feature id is stored in a 12 bit field in DFH. So a u16 variable is enough for feature id.
This patch changes all feature id related places to f
fpga: dfl: change data type of feature id to u16
The feature id is stored in a 12 bit field in DFH. So a u16 variable is enough for feature id.
This patch changes all feature id related places to fit u16.
Signed-off-by: Xu Yilun <yilun.xu@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Revision tags: v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47 |
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#
322b598b |
| 15-Jun-2020 |
Xu Yilun <yilun.xu@intel.com> |
fpga: dfl: introduce interrupt trigger setting API
FPGA user applications may be interested in interrupts generated by DFL features. For example, users can implement their own FPGA logics with inter
fpga: dfl: introduce interrupt trigger setting API
FPGA user applications may be interested in interrupts generated by DFL features. For example, users can implement their own FPGA logics with interrupts enabled in AFU (Accelerated Function Unit, dynamic region of DFL based FPGA). So user applications need to be notified to handle these interrupts.
In order to allow userspace applications to monitor interrupts, driver requires userspace to provide eventfds as interrupt notification channels. Applications then poll/select on the eventfds to get notified.
This patch introduces a generic helper functions to do eventfds binding with given interrupts.
Sub feature drivers are expected to use XXX_GET_IRQ_NUM to query irq info, and XXX_SET_IRQ to set eventfds for interrupts. This patch also introduces helper functions for these 2 ioctls.
Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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#
8d021039 |
| 15-Jun-2020 |
Xu Yilun <yilun.xu@intel.com> |
fpga: dfl: parse interrupt info for feature devices on enumeration
DFL based FPGA devices could support interrupts for different purposes, but current DFL framework only supports feature device enum
fpga: dfl: parse interrupt info for feature devices on enumeration
DFL based FPGA devices could support interrupts for different purposes, but current DFL framework only supports feature device enumeration with given MMIO resources information via common DFL headers. This patch introduces one new API dfl_fpga_enum_info_add_irq for low level bus drivers (e.g. PCIe device driver) to pass its interrupt resources information to DFL framework for enumeration, and also adds interrupt enumeration code in framework to parse and assign interrupt resources for enumerated feature devices and their own sub features.
With this patch, DFL framework enumerates interrupt resources for core features, including PORT Error Reporting, FME (FPGA Management Engine) Error Reporting and also AFU User Interrupts.
Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Acked-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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#
e1d9ec3a |
| 17-Jun-2020 |
Gustavo A. R. Silva <gustavoars@kernel.org> |
fpga: dfl: Use struct_size() in kzalloc()
Make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. Also, remove unnecessary function dfl_f
fpga: dfl: Use struct_size() in kzalloc()
Make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. Also, remove unnecessary function dfl_feature_platform_data_size().
This code was detected with the help of Coccinelle and, audited and fixed manually.
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Revision tags: v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27 |
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#
5a538815 |
| 19-Mar-2020 |
Gustavo A. R. Silva <gustavo@embeddedor.com> |
fpga: dfl.h: Replace zero-length array with flexible-array member
The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to decla
fpga: dfl.h: Replace zero-length array with flexible-array member
The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99:
struct foo { int stuff; struct boo array[]; };
By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on.
Also, notice that, dynamic memory allocations won't be affected by this change:
"Flexible array members have incomplete type, and so the sizeof operator may not be applied. As a quirk of the original implementation of zero-length arrays, sizeof evaluates to zero."[1]
This issue was found with the help of Coccinelle.
[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Revision tags: v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12 |
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#
b6862193 |
| 17-Nov-2019 |
Xu Yilun <yilun.xu@intel.com> |
fpga: dfl: support multiple opens on feature device node.
Each DFL functional block, e.g. AFU (Accelerated Function Unit) and FME (FPGA Management Engine), could implement more than one function wit
fpga: dfl: support multiple opens on feature device node.
Each DFL functional block, e.g. AFU (Accelerated Function Unit) and FME (FPGA Management Engine), could implement more than one function within its region, but current driver only allows one user application to access it by exclusive open on device node. So this is not convenient and flexible for userspace applications, as they have to combine lots of different functions into one single application.
This patch removes the limitation here to allow multiple opens to each feature device node for AFU and FME from userspace applications. If user still needs exclusive access to these device node, O_EXCL flag must be issued together with open.
Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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#
724142f8 |
| 26-Apr-2020 |
Wu Hao <hao.wu@intel.com> |
fpga: dfl: fme: add performance reporting support
This patch adds support for performance reporting private feature for FPGA Management Engine (FME). Now it supports several different performance co
fpga: dfl: fme: add performance reporting support
This patch adds support for performance reporting private feature for FPGA Management Engine (FME). Now it supports several different performance counters, including 'basic', 'cache', 'fabric', 'vtd' and 'vtd_sip'. It allows user to use standard linux tools to access these performance counters.
e.g. List all events by "perf list"
perf list | grep fme
dfl_fme0/cache_read_hit/ [Kernel PMU event] dfl_fme0/cache_read_miss/ [Kernel PMU event] ...
dfl_fme0/fab_mmio_read/ [Kernel PMU event] dfl_fme0/fab_mmio_write/ [Kernel PMU event] ...
dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event] dfl_fme0/fab_port_mmio_write,portid=?/ [Kernel PMU event] ...
dfl_fme0/vtd_port_devtlb_1g_fill,portid=?/ [Kernel PMU event] dfl_fme0/vtd_port_devtlb_2m_fill,portid=?/ [Kernel PMU event] ...
dfl_fme0/vtd_sip_iotlb_1g_hit/ [Kernel PMU event] dfl_fme0/vtd_sip_iotlb_1g_miss/ [Kernel PMU event] ...
dfl_fme0/clock [Kernel PMU event] ...
e.g. check increased counter value after run one application using "perf stat" command.
perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_mmio_write/ ./test
Performance counter stats for './test':
1 dfl_fme0/fab_mmio_read/ 2 dfl_fme0/fab_mmio_write/
1.009496520 seconds time elapsed
Please note that fabric counters support both fab_* and fab_port_*, but actually they are sharing one set of performance counters in hardware. If user wants to monitor overall data events on fab_* then fab_port_* can't be supported at the same time, see example below:
perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,portid=0/
Performance counter stats for 'system wide':
0 dfl_fme0/fab_mmio_read/ <not supported> dfl_fme0/fab_port_mmio_write,portid=0/
2.141064085 seconds time elapsed
Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Link: https://lore.kernel.org/r/1587949583-12058-3-git-send-email-hao.wu@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9 |
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#
f09991ad |
| 11-Aug-2019 |
Wu Hao <hao.wu@intel.com> |
fpga: dfl: afu: add userclock sysfs interfaces.
This patch introduces userclock sysfs interfaces for AFU, user could use these interfaces for clock setting to AFU.
Please note that, this is only wo
fpga: dfl: afu: add userclock sysfs interfaces.
This patch introduces userclock sysfs interfaces for AFU, user could use these interfaces for clock setting to AFU.
Please note that, this is only working for port header feature with revision 0, for later revisions, userclock setting is moved to a separated private feature, so one revision sysfs interface is exposed to userspace application for this purpose too.
Signed-off-by: Ananda Ravuri <ananda.ravuri@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Revision tags: v5.2.8, v5.2.7 |
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#
15bbb300 |
| 04-Aug-2019 |
Wu Hao <hao.wu@intel.com> |
fpga: dfl: add id_table for dfl private feature driver
This patch adds id_table for each dfl private feature driver, it allows to reuse same private feature driver to match and support multiple dfl
fpga: dfl: add id_table for dfl private feature driver
This patch adds id_table for each dfl private feature driver, it allows to reuse same private feature driver to match and support multiple dfl private features.
Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Moritz Fischer <mdf@kernel.org> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/1564914022-3710-6-git-send-email-hao.wu@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
d2ad5ac1 |
| 04-Aug-2019 |
Wu Hao <hao.wu@intel.com> |
fpga: dfl: afu: add AFU state related sysfs interfaces
This patch introduces more sysfs interfaces for Accelerated Function Unit (AFU). These interfaces allow users to read current AFU Power State (
fpga: dfl: afu: add AFU state related sysfs interfaces
This patch introduces more sysfs interfaces for Accelerated Function Unit (AFU). These interfaces allow users to read current AFU Power State (APx), read / clear AFU Power (APx) events which are sticky to identify transient APx state, and manage AFU's LTR (latency tolerance reporting).
Signed-off-by: Ananda Ravuri <ananda.ravuri@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/1564914022-3710-4-git-send-email-hao.wu@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
bdd4f307 |
| 04-Aug-2019 |
Wu Hao <hao.wu@intel.com> |
fpga: dfl: pci: enable SRIOV support.
This patch enables the standard sriov support. It allows user to enable SRIOV (and VFs), then user could pass through accelerators (VFs) into virtual machine or
fpga: dfl: pci: enable SRIOV support.
This patch enables the standard sriov support. It allows user to enable SRIOV (and VFs), then user could pass through accelerators (VFs) into virtual machine or use VFs directly in host.
Signed-off-by: Zhang Yi Z <yi.z.zhang@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/1564914022-3710-3-git-send-email-hao.wu@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
69bb18dd |
| 04-Aug-2019 |
Wu Hao <hao.wu@intel.com> |
fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support.
In order to support virtualization usage via PCIe SRIOV, this patch adds two ioctls under FPGA Management Engine (FME) to release
fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support.
In order to support virtualization usage via PCIe SRIOV, this patch adds two ioctls under FPGA Management Engine (FME) to release and assign back the port device. In order to safely turn Port from PF into VF and enable PCIe SRIOV, it requires user to invoke this PORT_RELEASE ioctl to release port firstly to remove userspace interfaces, and then configure the PF/VF access register in FME. After disable SRIOV, it requires user to invoke this PORT_ASSIGN ioctl to attach the port back to PF.
Ioctl interfaces: * DFL_FPGA_FME_PORT_RELEASE Release platform device of given port, it deletes port platform device to remove related userspace interfaces on PF. After this function, then it's safe to configure PF/VF access mode to VF, and enable VFs via SRIOV.
* DFL_FPGA_FME_PORT_ASSIGN Assign platform device of given port back to PF. After configure PF/VF access mode to PF, this ioctl adds port platform device back to re-enable related userspace interfaces on PF.
Signed-off-by: Zhang Yi Z <yi.z.zhang@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org> Link: https://lore.kernel.org/r/1564914022-3710-2-git-send-email-hao.wu@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4 |
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#
d06b004b |
| 29-Jun-2018 |
Wu Hao <hao.wu@intel.com> |
fpga: dfl: add dfl_fpga_check_port_id function.
This patch adds one common function in DFL framework. It uses port_ops get_id callback to get port id and compare it with given value. This function c
fpga: dfl: add dfl_fpga_check_port_id function.
This patch adds one common function in DFL framework. It uses port_ops get_id callback to get port id and compare it with given value. This function could be used as match function of the dfl_fpga_cdev_find_port function.
Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
6e8fd6e4 |
| 29-Jun-2018 |
Wu Hao <hao.wu@intel.com> |
fpga: dfl: add dfl_fpga_port_ops support.
In some cases, other DFL driver modules may need to access some port operations, e.g. disable / enable port for partial reconfiguration in FME module. In or
fpga: dfl: add dfl_fpga_port_ops support.
In some cases, other DFL driver modules may need to access some port operations, e.g. disable / enable port for partial reconfiguration in FME module. In order to avoid dependency between port and FME modules, this patch introduces the dfl_fpga_port_ops support in DFL framework. A global dfl_fpga_port_ops list is added in the DFL framework, and it allows other DFL modules to use these port operations registered to this list, even in virtualization case, the port platform device is turned into VF / guest VM and hidden in host, the registered port_ops is still usable. It resolves the dependency issues between modules, but once get port ops API returns a valid port ops, that means related port driver module has been module_get to prevent from unexpected unload, and put port ops API must be invoked after use.
These APIs introduced by this patch is listed below: * dfl_fpga_port_ops_add add one port ops to the global list.
* dfl_fpga_port_ops_del del one port ops from the global list.
* dfl_fpga_port_ops_get / dfl_fpga_port_ops_put get/put the port ops before/after use.
Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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