1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Driver Header File for FPGA Device Feature List (DFL) Support 4 * 5 * Copyright (C) 2017-2018 Intel Corporation, Inc. 6 * 7 * Authors: 8 * Kang Luwei <luwei.kang@intel.com> 9 * Zhang Yi <yi.z.zhang@intel.com> 10 * Wu Hao <hao.wu@intel.com> 11 * Xiao Guangrong <guangrong.xiao@linux.intel.com> 12 */ 13 14 #ifndef __FPGA_DFL_H 15 #define __FPGA_DFL_H 16 17 #include <linux/bitfield.h> 18 #include <linux/cdev.h> 19 #include <linux/delay.h> 20 #include <linux/eventfd.h> 21 #include <linux/fs.h> 22 #include <linux/interrupt.h> 23 #include <linux/iopoll.h> 24 #include <linux/io-64-nonatomic-lo-hi.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include <linux/uuid.h> 28 #include <linux/fpga/fpga-region.h> 29 30 /* maximum supported number of ports */ 31 #define MAX_DFL_FPGA_PORT_NUM 4 32 /* plus one for fme device */ 33 #define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1) 34 35 /* Reserved 0xfe for Header Group Register and 0xff for AFU */ 36 #define FEATURE_ID_FIU_HEADER 0xfe 37 #define FEATURE_ID_AFU 0xff 38 39 #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER 40 #define FME_FEATURE_ID_THERMAL_MGMT 0x1 41 #define FME_FEATURE_ID_POWER_MGMT 0x2 42 #define FME_FEATURE_ID_GLOBAL_IPERF 0x3 43 #define FME_FEATURE_ID_GLOBAL_ERR 0x4 44 #define FME_FEATURE_ID_PR_MGMT 0x5 45 #define FME_FEATURE_ID_HSSI 0x6 46 #define FME_FEATURE_ID_GLOBAL_DPERF 0x7 47 48 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER 49 #define PORT_FEATURE_ID_AFU FEATURE_ID_AFU 50 #define PORT_FEATURE_ID_ERROR 0x10 51 #define PORT_FEATURE_ID_UMSG 0x11 52 #define PORT_FEATURE_ID_UINT 0x12 53 #define PORT_FEATURE_ID_STP 0x13 54 55 /* 56 * Device Feature Header Register Set 57 * 58 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. 59 * For AFUs, they have DFH + GUID as common header registers. 60 * For private features, they only have DFH register as common header. 61 */ 62 #define DFH 0x0 63 #define GUID_L 0x8 64 #define GUID_H 0x10 65 #define NEXT_AFU 0x18 66 67 #define DFH_SIZE 0x8 68 69 /* Device Feature Header Register Bitfield */ 70 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ 71 #define DFH_ID_FIU_FME 0 72 #define DFH_ID_FIU_PORT 1 73 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ 74 #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ 75 #define DFH_EOL BIT_ULL(40) /* End of list */ 76 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ 77 #define DFH_TYPE_AFU 1 78 #define DFH_TYPE_PRIVATE 3 79 #define DFH_TYPE_FIU 4 80 81 /* Next AFU Register Bitfield */ 82 #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ 83 84 /* FME Header Register Set */ 85 #define FME_HDR_DFH DFH 86 #define FME_HDR_GUID_L GUID_L 87 #define FME_HDR_GUID_H GUID_H 88 #define FME_HDR_NEXT_AFU NEXT_AFU 89 #define FME_HDR_CAP 0x30 90 #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) 91 #define FME_HDR_BITSTREAM_ID 0x60 92 #define FME_HDR_BITSTREAM_MD 0x68 93 94 /* FME Fab Capability Register Bitfield */ 95 #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */ 96 #define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */ 97 #define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */ 98 #define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */ 99 #define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */ 100 #define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */ 101 #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */ 102 #define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */ 103 #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */ 104 #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */ 105 106 /* FME Port Offset Register Bitfield */ 107 /* Offset to port device feature header */ 108 #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0) 109 /* PCI Bar ID for this port */ 110 #define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32) 111 /* AFU MMIO access permission. 1 - VF, 0 - PF. */ 112 #define FME_PORT_OFST_ACC_CTRL BIT_ULL(55) 113 #define FME_PORT_OFST_ACC_PF 0 114 #define FME_PORT_OFST_ACC_VF 1 115 #define FME_PORT_OFST_IMP BIT_ULL(60) 116 117 /* FME Error Capability Register */ 118 #define FME_ERROR_CAP 0x70 119 120 /* FME Error Capability Register Bitfield */ 121 #define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */ 122 #define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */ 123 124 /* PORT Header Register Set */ 125 #define PORT_HDR_DFH DFH 126 #define PORT_HDR_GUID_L GUID_L 127 #define PORT_HDR_GUID_H GUID_H 128 #define PORT_HDR_NEXT_AFU NEXT_AFU 129 #define PORT_HDR_CAP 0x30 130 #define PORT_HDR_CTRL 0x38 131 #define PORT_HDR_STS 0x40 132 #define PORT_HDR_USRCLK_CMD0 0x50 133 #define PORT_HDR_USRCLK_CMD1 0x58 134 #define PORT_HDR_USRCLK_STS0 0x60 135 #define PORT_HDR_USRCLK_STS1 0x68 136 137 /* Port Capability Register Bitfield */ 138 #define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */ 139 #define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */ 140 #define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */ 141 142 /* Port Control Register Bitfield */ 143 #define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */ 144 /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/ 145 #define PORT_CTRL_LATENCY BIT_ULL(2) 146 #define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */ 147 148 /* Port Status Register Bitfield */ 149 #define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */ 150 #define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */ 151 #define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */ 152 #define PORT_STS_PWR_STATE_NORM 0 153 #define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */ 154 #define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */ 155 #define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */ 156 157 /* Port Error Capability Register */ 158 #define PORT_ERROR_CAP 0x38 159 160 /* Port Error Capability Register Bitfield */ 161 #define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */ 162 #define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */ 163 164 /* Port Uint Capability Register */ 165 #define PORT_UINT_CAP 0x8 166 167 /* Port Uint Capability Register Bitfield */ 168 #define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */ 169 #define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */ 170 171 /** 172 * struct dfl_fpga_port_ops - port ops 173 * 174 * @name: name of this port ops, to match with port platform device. 175 * @owner: pointer to the module which owns this port ops. 176 * @node: node to link port ops to global list. 177 * @get_id: get port id from hardware. 178 * @enable_set: enable/disable the port. 179 */ 180 struct dfl_fpga_port_ops { 181 const char *name; 182 struct module *owner; 183 struct list_head node; 184 int (*get_id)(struct platform_device *pdev); 185 int (*enable_set)(struct platform_device *pdev, bool enable); 186 }; 187 188 void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops); 189 void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops); 190 struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev); 191 void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops); 192 int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id); 193 194 /** 195 * struct dfl_feature_id - dfl private feature id 196 * 197 * @id: unique dfl private feature id. 198 */ 199 struct dfl_feature_id { 200 u64 id; 201 }; 202 203 /** 204 * struct dfl_feature_driver - dfl private feature driver 205 * 206 * @id_table: id_table for dfl private features supported by this driver. 207 * @ops: ops of this dfl private feature driver. 208 */ 209 struct dfl_feature_driver { 210 const struct dfl_feature_id *id_table; 211 const struct dfl_feature_ops *ops; 212 }; 213 214 /** 215 * struct dfl_feature_irq_ctx - dfl private feature interrupt context 216 * 217 * @irq: Linux IRQ number of this interrupt. 218 * @trigger: eventfd context to signal when interrupt happens. 219 * @name: irq name needed when requesting irq. 220 */ 221 struct dfl_feature_irq_ctx { 222 int irq; 223 struct eventfd_ctx *trigger; 224 char *name; 225 }; 226 227 /** 228 * struct dfl_feature - sub feature of the feature devices 229 * 230 * @dev: ptr to pdev of the feature device which has the sub feature. 231 * @id: sub feature id. 232 * @resource_index: each sub feature has one mmio resource for its registers. 233 * this index is used to find its mmio resource from the 234 * feature dev (platform device)'s reources. 235 * @ioaddr: mapped mmio resource address. 236 * @irq_ctx: interrupt context list. 237 * @nr_irqs: number of interrupt contexts. 238 * @ops: ops of this sub feature. 239 * @priv: priv data of this feature. 240 */ 241 struct dfl_feature { 242 struct platform_device *dev; 243 u64 id; 244 int resource_index; 245 void __iomem *ioaddr; 246 struct dfl_feature_irq_ctx *irq_ctx; 247 unsigned int nr_irqs; 248 const struct dfl_feature_ops *ops; 249 void *priv; 250 }; 251 252 #define FEATURE_DEV_ID_UNUSED (-1) 253 254 /** 255 * struct dfl_feature_platform_data - platform data for feature devices 256 * 257 * @node: node to link feature devs to container device's port_dev_list. 258 * @lock: mutex to protect platform data. 259 * @cdev: cdev of feature dev. 260 * @dev: ptr to platform device linked with this platform data. 261 * @dfl_cdev: ptr to container device. 262 * @id: id used for this feature device. 263 * @disable_count: count for port disable. 264 * @excl_open: set on feature device exclusive open. 265 * @open_count: count for feature device open. 266 * @num: number for sub features. 267 * @private: ptr to feature dev private data. 268 * @features: sub features of this feature dev. 269 */ 270 struct dfl_feature_platform_data { 271 struct list_head node; 272 struct mutex lock; 273 struct cdev cdev; 274 struct platform_device *dev; 275 struct dfl_fpga_cdev *dfl_cdev; 276 int id; 277 unsigned int disable_count; 278 bool excl_open; 279 int open_count; 280 void *private; 281 int num; 282 struct dfl_feature features[]; 283 }; 284 285 static inline 286 int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata, 287 bool excl) 288 { 289 if (pdata->excl_open) 290 return -EBUSY; 291 292 if (excl) { 293 if (pdata->open_count) 294 return -EBUSY; 295 296 pdata->excl_open = true; 297 } 298 pdata->open_count++; 299 300 return 0; 301 } 302 303 static inline 304 void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata) 305 { 306 pdata->excl_open = false; 307 308 if (WARN_ON(pdata->open_count <= 0)) 309 return; 310 311 pdata->open_count--; 312 } 313 314 static inline 315 int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata) 316 { 317 return pdata->open_count; 318 } 319 320 static inline 321 void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata, 322 void *private) 323 { 324 pdata->private = private; 325 } 326 327 static inline 328 void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata) 329 { 330 return pdata->private; 331 } 332 333 struct dfl_feature_ops { 334 int (*init)(struct platform_device *pdev, struct dfl_feature *feature); 335 void (*uinit)(struct platform_device *pdev, 336 struct dfl_feature *feature); 337 long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature, 338 unsigned int cmd, unsigned long arg); 339 }; 340 341 #define DFL_FPGA_FEATURE_DEV_FME "dfl-fme" 342 #define DFL_FPGA_FEATURE_DEV_PORT "dfl-port" 343 344 void dfl_fpga_dev_feature_uinit(struct platform_device *pdev); 345 int dfl_fpga_dev_feature_init(struct platform_device *pdev, 346 struct dfl_feature_driver *feature_drvs); 347 348 int dfl_fpga_dev_ops_register(struct platform_device *pdev, 349 const struct file_operations *fops, 350 struct module *owner); 351 void dfl_fpga_dev_ops_unregister(struct platform_device *pdev); 352 353 static inline 354 struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode) 355 { 356 struct dfl_feature_platform_data *pdata; 357 358 pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data, 359 cdev); 360 return pdata->dev; 361 } 362 363 #define dfl_fpga_dev_for_each_feature(pdata, feature) \ 364 for ((feature) = (pdata)->features; \ 365 (feature) < (pdata)->features + (pdata)->num; (feature)++) 366 367 static inline 368 struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u64 id) 369 { 370 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 371 struct dfl_feature *feature; 372 373 dfl_fpga_dev_for_each_feature(pdata, feature) 374 if (feature->id == id) 375 return feature; 376 377 return NULL; 378 } 379 380 static inline 381 void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u64 id) 382 { 383 struct dfl_feature *feature = dfl_get_feature_by_id(dev, id); 384 385 if (feature && feature->ioaddr) 386 return feature->ioaddr; 387 388 WARN_ON(1); 389 return NULL; 390 } 391 392 static inline bool is_dfl_feature_present(struct device *dev, u64 id) 393 { 394 return !!dfl_get_feature_ioaddr_by_id(dev, id); 395 } 396 397 static inline 398 struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata) 399 { 400 return pdata->dev->dev.parent->parent; 401 } 402 403 static inline bool dfl_feature_is_fme(void __iomem *base) 404 { 405 u64 v = readq(base + DFH); 406 407 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && 408 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME); 409 } 410 411 static inline bool dfl_feature_is_port(void __iomem *base) 412 { 413 u64 v = readq(base + DFH); 414 415 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && 416 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT); 417 } 418 419 static inline u8 dfl_feature_revision(void __iomem *base) 420 { 421 return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH)); 422 } 423 424 /** 425 * struct dfl_fpga_enum_info - DFL FPGA enumeration information 426 * 427 * @dev: parent device. 428 * @dfls: list of device feature lists. 429 * @nr_irqs: number of irqs for all feature devices. 430 * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers. 431 */ 432 struct dfl_fpga_enum_info { 433 struct device *dev; 434 struct list_head dfls; 435 unsigned int nr_irqs; 436 int *irq_table; 437 }; 438 439 /** 440 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info 441 * 442 * @start: base address of this device feature list. 443 * @len: size of this device feature list. 444 * @ioaddr: mapped base address of this device feature list. 445 * @node: node in list of device feature lists. 446 */ 447 struct dfl_fpga_enum_dfl { 448 resource_size_t start; 449 resource_size_t len; 450 451 void __iomem *ioaddr; 452 453 struct list_head node; 454 }; 455 456 struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev); 457 int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info, 458 resource_size_t start, resource_size_t len, 459 void __iomem *ioaddr); 460 int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info, 461 unsigned int nr_irqs, int *irq_table); 462 void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info); 463 464 /** 465 * struct dfl_fpga_cdev - container device of DFL based FPGA 466 * 467 * @parent: parent device of this container device. 468 * @region: base fpga region. 469 * @fme_dev: FME feature device under this container device. 470 * @lock: mutex lock to protect the port device list. 471 * @port_dev_list: list of all port feature devices under this container device. 472 * @released_port_num: released port number under this container device. 473 */ 474 struct dfl_fpga_cdev { 475 struct device *parent; 476 struct fpga_region *region; 477 struct device *fme_dev; 478 struct mutex lock; 479 struct list_head port_dev_list; 480 int released_port_num; 481 }; 482 483 struct dfl_fpga_cdev * 484 dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info); 485 void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev); 486 487 /* 488 * need to drop the device reference with put_device() after use port platform 489 * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port 490 * functions. 491 */ 492 struct platform_device * 493 __dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, 494 int (*match)(struct platform_device *, void *)); 495 496 static inline struct platform_device * 497 dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, 498 int (*match)(struct platform_device *, void *)) 499 { 500 struct platform_device *pdev; 501 502 mutex_lock(&cdev->lock); 503 pdev = __dfl_fpga_cdev_find_port(cdev, data, match); 504 mutex_unlock(&cdev->lock); 505 506 return pdev; 507 } 508 509 int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id); 510 int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id); 511 void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev); 512 int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf); 513 int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start, 514 unsigned int count, int32_t *fds); 515 long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev, 516 struct dfl_feature *feature, 517 unsigned long arg); 518 long dfl_feature_ioctl_set_irq(struct platform_device *pdev, 519 struct dfl_feature *feature, 520 unsigned long arg); 521 522 #endif /* __FPGA_DFL_H */ 523