164506017SSrujana Challa /* SPDX-License-Identifier: GPL-2.0-only
264506017SSrujana Challa * Copyright (C) 2020 Marvell.
364506017SSrujana Challa */
464506017SSrujana Challa #ifndef __OTX2_CPTLF_H
564506017SSrujana Challa #define __OTX2_CPTLF_H
664506017SSrujana Challa
778506c2aSSrujana Challa #include <linux/soc/marvell/octeontx2/asm.h>
864506017SSrujana Challa #include <mbox.h>
964506017SSrujana Challa #include <rvu.h>
1064506017SSrujana Challa #include "otx2_cpt_common.h"
1178506c2aSSrujana Challa #include "otx2_cpt_reqmgr.h"
1264506017SSrujana Challa
1364506017SSrujana Challa /*
1464506017SSrujana Challa * CPT instruction and pending queues user requested length in CPT_INST_S msgs
1564506017SSrujana Challa */
1664506017SSrujana Challa #define OTX2_CPT_USER_REQUESTED_QLEN_MSGS 8200
1764506017SSrujana Challa
1864506017SSrujana Challa /*
1964506017SSrujana Challa * CPT instruction queue size passed to HW is in units of 40*CPT_INST_S
2064506017SSrujana Challa * messages.
2164506017SSrujana Challa */
2264506017SSrujana Challa #define OTX2_CPT_SIZE_DIV40 (OTX2_CPT_USER_REQUESTED_QLEN_MSGS/40)
2364506017SSrujana Challa
2464506017SSrujana Challa /*
2564506017SSrujana Challa * CPT instruction and pending queues length in CPT_INST_S messages
2664506017SSrujana Challa */
2764506017SSrujana Challa #define OTX2_CPT_INST_QLEN_MSGS ((OTX2_CPT_SIZE_DIV40 - 1) * 40)
2864506017SSrujana Challa
29e236ab0dSSrujana Challa /*
30e236ab0dSSrujana Challa * LDWB is getting incorrectly used when IQB_LDWB = 1 and CPT instruction
31e236ab0dSSrujana Challa * queue has less than 320 free entries. So, increase HW instruction queue
32e236ab0dSSrujana Challa * size by 320 and give 320 entries less for SW/NIX RX as a workaround.
33e236ab0dSSrujana Challa */
34e236ab0dSSrujana Challa #define OTX2_CPT_INST_QLEN_EXTRA_BYTES (320 * OTX2_CPT_INST_SIZE)
35e236ab0dSSrujana Challa #define OTX2_CPT_EXTRA_SIZE_DIV40 (320/40)
36e236ab0dSSrujana Challa
3764506017SSrujana Challa /* CPT instruction queue length in bytes */
38e236ab0dSSrujana Challa #define OTX2_CPT_INST_QLEN_BYTES \
39e236ab0dSSrujana Challa ((OTX2_CPT_SIZE_DIV40 * 40 * OTX2_CPT_INST_SIZE) + \
40e236ab0dSSrujana Challa OTX2_CPT_INST_QLEN_EXTRA_BYTES)
4164506017SSrujana Challa
4264506017SSrujana Challa /* CPT instruction group queue length in bytes */
43e236ab0dSSrujana Challa #define OTX2_CPT_INST_GRP_QLEN_BYTES \
44e236ab0dSSrujana Challa ((OTX2_CPT_SIZE_DIV40 + OTX2_CPT_EXTRA_SIZE_DIV40) * 16)
4564506017SSrujana Challa
4664506017SSrujana Challa /* CPT FC length in bytes */
4764506017SSrujana Challa #define OTX2_CPT_Q_FC_LEN 128
4864506017SSrujana Challa
4964506017SSrujana Challa /* CPT instruction queue alignment */
5064506017SSrujana Challa #define OTX2_CPT_INST_Q_ALIGNMENT 128
5164506017SSrujana Challa
5264506017SSrujana Challa /* Mask which selects all engine groups */
5364506017SSrujana Challa #define OTX2_CPT_ALL_ENG_GRPS_MASK 0xFF
5464506017SSrujana Challa
5564506017SSrujana Challa /* Maximum LFs supported in OcteonTX2 for CPT */
5664506017SSrujana Challa #define OTX2_CPT_MAX_LFS_NUM 64
5764506017SSrujana Challa
5864506017SSrujana Challa /* Queue priority */
5964506017SSrujana Challa #define OTX2_CPT_QUEUE_HI_PRIO 0x1
6064506017SSrujana Challa #define OTX2_CPT_QUEUE_LOW_PRIO 0x0
6164506017SSrujana Challa
6264506017SSrujana Challa enum otx2_cptlf_state {
6364506017SSrujana Challa OTX2_CPTLF_IN_RESET,
6464506017SSrujana Challa OTX2_CPTLF_STARTED,
6564506017SSrujana Challa };
6664506017SSrujana Challa
6764506017SSrujana Challa struct otx2_cpt_inst_queue {
6864506017SSrujana Challa u8 *vaddr;
6964506017SSrujana Challa u8 *real_vaddr;
7064506017SSrujana Challa dma_addr_t dma_addr;
7164506017SSrujana Challa dma_addr_t real_dma_addr;
7264506017SSrujana Challa u32 size;
7364506017SSrujana Challa };
7464506017SSrujana Challa
7564506017SSrujana Challa struct otx2_cptlfs_info;
7664506017SSrujana Challa struct otx2_cptlf_wqe {
7764506017SSrujana Challa struct tasklet_struct work;
7864506017SSrujana Challa struct otx2_cptlfs_info *lfs;
7964506017SSrujana Challa u8 lf_num;
8064506017SSrujana Challa };
8164506017SSrujana Challa
8264506017SSrujana Challa struct otx2_cptlf_info {
8364506017SSrujana Challa struct otx2_cptlfs_info *lfs; /* Ptr to cptlfs_info struct */
8464506017SSrujana Challa void __iomem *lmtline; /* Address of LMTLINE */
8564506017SSrujana Challa void __iomem *ioreg; /* LMTLINE send register */
8664506017SSrujana Challa int msix_offset; /* MSI-X interrupts offset */
8764506017SSrujana Challa cpumask_var_t affinity_mask; /* IRQs affinity mask */
8864506017SSrujana Challa u8 irq_name[OTX2_CPT_LF_MSIX_VECTORS][32];/* Interrupts name */
8964506017SSrujana Challa u8 is_irq_reg[OTX2_CPT_LF_MSIX_VECTORS]; /* Is interrupt registered */
9064506017SSrujana Challa u8 slot; /* Slot number of this LF */
9164506017SSrujana Challa
9264506017SSrujana Challa struct otx2_cpt_inst_queue iqueue;/* Instruction queue */
938ec8015aSSrujana Challa struct otx2_cpt_pending_queue pqueue; /* Pending queue */
9464506017SSrujana Challa struct otx2_cptlf_wqe *wqe; /* Tasklet work info */
9564506017SSrujana Challa };
9664506017SSrujana Challa
9740a645f7SSrujana Challa struct cpt_hw_ops {
9840a645f7SSrujana Challa void (*send_cmd)(union otx2_cpt_inst_s *cptinst, u32 insts_num,
9940a645f7SSrujana Challa struct otx2_cptlf_info *lf);
10040a645f7SSrujana Challa u8 (*cpt_get_compcode)(union otx2_cpt_res_s *result);
10140a645f7SSrujana Challa u8 (*cpt_get_uc_compcode)(union otx2_cpt_res_s *result);
10240a645f7SSrujana Challa };
10340a645f7SSrujana Challa
10464506017SSrujana Challa struct otx2_cptlfs_info {
10564506017SSrujana Challa /* Registers start address of VF/PF LFs are attached to */
10664506017SSrujana Challa void __iomem *reg_base;
107eb33cd91SSrujana Challa #define LMTLINE_SIZE 128
108eb33cd91SSrujana Challa void __iomem *lmt_base;
10964506017SSrujana Challa struct pci_dev *pdev; /* Device LFs are attached to */
11064506017SSrujana Challa struct otx2_cptlf_info lf[OTX2_CPT_MAX_LFS_NUM];
11164506017SSrujana Challa struct otx2_mbox *mbox;
11240a645f7SSrujana Challa struct cpt_hw_ops *ops;
11364506017SSrujana Challa u8 are_lfs_attached; /* Whether CPT LFs are attached */
11464506017SSrujana Challa u8 lfs_num; /* Number of CPT LFs */
1158ec8015aSSrujana Challa u8 kcrypto_eng_grp_num; /* Kernel crypto engine group number */
1168ec8015aSSrujana Challa u8 kvf_limits; /* Kernel crypto limits */
11764506017SSrujana Challa atomic_t state; /* LF's state. started/reset */
118b2d17df3SSrujana Challa int blkaddr; /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */
11964506017SSrujana Challa };
12064506017SSrujana Challa
otx2_cpt_free_instruction_queues(struct otx2_cptlfs_info * lfs)12164506017SSrujana Challa static inline void otx2_cpt_free_instruction_queues(
12264506017SSrujana Challa struct otx2_cptlfs_info *lfs)
12364506017SSrujana Challa {
12464506017SSrujana Challa struct otx2_cpt_inst_queue *iq;
12564506017SSrujana Challa int i;
12664506017SSrujana Challa
12764506017SSrujana Challa for (i = 0; i < lfs->lfs_num; i++) {
12864506017SSrujana Challa iq = &lfs->lf[i].iqueue;
12964506017SSrujana Challa if (iq->real_vaddr)
13064506017SSrujana Challa dma_free_coherent(&lfs->pdev->dev,
13164506017SSrujana Challa iq->size,
13264506017SSrujana Challa iq->real_vaddr,
13364506017SSrujana Challa iq->real_dma_addr);
13464506017SSrujana Challa iq->real_vaddr = NULL;
13564506017SSrujana Challa iq->vaddr = NULL;
13664506017SSrujana Challa }
13764506017SSrujana Challa }
13864506017SSrujana Challa
otx2_cpt_alloc_instruction_queues(struct otx2_cptlfs_info * lfs)13964506017SSrujana Challa static inline int otx2_cpt_alloc_instruction_queues(
14064506017SSrujana Challa struct otx2_cptlfs_info *lfs)
14164506017SSrujana Challa {
14264506017SSrujana Challa struct otx2_cpt_inst_queue *iq;
14364506017SSrujana Challa int ret = 0, i;
14464506017SSrujana Challa
14564506017SSrujana Challa if (!lfs->lfs_num)
14664506017SSrujana Challa return -EINVAL;
14764506017SSrujana Challa
14864506017SSrujana Challa for (i = 0; i < lfs->lfs_num; i++) {
14964506017SSrujana Challa iq = &lfs->lf[i].iqueue;
15064506017SSrujana Challa iq->size = OTX2_CPT_INST_QLEN_BYTES +
15164506017SSrujana Challa OTX2_CPT_Q_FC_LEN +
15264506017SSrujana Challa OTX2_CPT_INST_GRP_QLEN_BYTES +
15364506017SSrujana Challa OTX2_CPT_INST_Q_ALIGNMENT;
15464506017SSrujana Challa iq->real_vaddr = dma_alloc_coherent(&lfs->pdev->dev, iq->size,
15564506017SSrujana Challa &iq->real_dma_addr, GFP_KERNEL);
15664506017SSrujana Challa if (!iq->real_vaddr) {
15764506017SSrujana Challa ret = -ENOMEM;
15864506017SSrujana Challa goto error;
15964506017SSrujana Challa }
16064506017SSrujana Challa iq->vaddr = iq->real_vaddr + OTX2_CPT_INST_GRP_QLEN_BYTES;
16164506017SSrujana Challa iq->dma_addr = iq->real_dma_addr + OTX2_CPT_INST_GRP_QLEN_BYTES;
16264506017SSrujana Challa
16364506017SSrujana Challa /* Align pointers */
16464506017SSrujana Challa iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_CPT_INST_Q_ALIGNMENT);
16564506017SSrujana Challa iq->dma_addr = PTR_ALIGN(iq->dma_addr,
16664506017SSrujana Challa OTX2_CPT_INST_Q_ALIGNMENT);
16764506017SSrujana Challa }
16864506017SSrujana Challa return 0;
16964506017SSrujana Challa
17064506017SSrujana Challa error:
17164506017SSrujana Challa otx2_cpt_free_instruction_queues(lfs);
17264506017SSrujana Challa return ret;
17364506017SSrujana Challa }
17464506017SSrujana Challa
otx2_cptlf_set_iqueues_base_addr(struct otx2_cptlfs_info * lfs)17564506017SSrujana Challa static inline void otx2_cptlf_set_iqueues_base_addr(
17664506017SSrujana Challa struct otx2_cptlfs_info *lfs)
17764506017SSrujana Challa {
17864506017SSrujana Challa union otx2_cptx_lf_q_base lf_q_base;
17964506017SSrujana Challa int slot;
18064506017SSrujana Challa
18164506017SSrujana Challa for (slot = 0; slot < lfs->lfs_num; slot++) {
18264506017SSrujana Challa lf_q_base.u = lfs->lf[slot].iqueue.dma_addr;
183*a4855a8cSSrujana Challa otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,
18464506017SSrujana Challa OTX2_CPT_LF_Q_BASE, lf_q_base.u);
18564506017SSrujana Challa }
18664506017SSrujana Challa }
18764506017SSrujana Challa
otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info * lf)18864506017SSrujana Challa static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf)
18964506017SSrujana Challa {
19064506017SSrujana Challa union otx2_cptx_lf_q_size lf_q_size = { .u = 0x0 };
19164506017SSrujana Challa
192e236ab0dSSrujana Challa lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40 +
193e236ab0dSSrujana Challa OTX2_CPT_EXTRA_SIZE_DIV40;
194*a4855a8cSSrujana Challa otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
19564506017SSrujana Challa OTX2_CPT_LF_Q_SIZE, lf_q_size.u);
19664506017SSrujana Challa }
19764506017SSrujana Challa
otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info * lfs)19864506017SSrujana Challa static inline void otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info *lfs)
19964506017SSrujana Challa {
20064506017SSrujana Challa int slot;
20164506017SSrujana Challa
20264506017SSrujana Challa for (slot = 0; slot < lfs->lfs_num; slot++)
20364506017SSrujana Challa otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]);
20464506017SSrujana Challa }
20564506017SSrujana Challa
otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info * lf)20664506017SSrujana Challa static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf)
20764506017SSrujana Challa {
20864506017SSrujana Challa union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 };
20964506017SSrujana Challa union otx2_cptx_lf_inprog lf_inprog;
210*a4855a8cSSrujana Challa u8 blkaddr = lf->lfs->blkaddr;
21164506017SSrujana Challa int timeout = 20;
21264506017SSrujana Challa
21364506017SSrujana Challa /* Disable instructions enqueuing */
214*a4855a8cSSrujana Challa otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
21564506017SSrujana Challa OTX2_CPT_LF_CTL, lf_ctl.u);
21664506017SSrujana Challa
21764506017SSrujana Challa /* Wait for instruction queue to become empty */
21864506017SSrujana Challa do {
219*a4855a8cSSrujana Challa lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr,
22064506017SSrujana Challa lf->slot, OTX2_CPT_LF_INPROG);
22164506017SSrujana Challa if (!lf_inprog.s.inflight)
22264506017SSrujana Challa break;
22364506017SSrujana Challa
22464506017SSrujana Challa usleep_range(10000, 20000);
22564506017SSrujana Challa if (timeout-- < 0) {
22664506017SSrujana Challa dev_err(&lf->lfs->pdev->dev,
22764506017SSrujana Challa "Error LF %d is still busy.\n", lf->slot);
22864506017SSrujana Challa break;
22964506017SSrujana Challa }
23064506017SSrujana Challa
23164506017SSrujana Challa } while (1);
23264506017SSrujana Challa
23364506017SSrujana Challa /*
23464506017SSrujana Challa * Disable executions in the LF's queue,
23564506017SSrujana Challa * the queue should be empty at this point
23664506017SSrujana Challa */
23764506017SSrujana Challa lf_inprog.s.eena = 0x0;
238*a4855a8cSSrujana Challa otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
23964506017SSrujana Challa OTX2_CPT_LF_INPROG, lf_inprog.u);
24064506017SSrujana Challa }
24164506017SSrujana Challa
otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info * lfs)24264506017SSrujana Challa static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs)
24364506017SSrujana Challa {
24464506017SSrujana Challa int slot;
24564506017SSrujana Challa
24664506017SSrujana Challa for (slot = 0; slot < lfs->lfs_num; slot++)
24764506017SSrujana Challa otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]);
24864506017SSrujana Challa }
24964506017SSrujana Challa
otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info * lf,bool enable)25064506017SSrujana Challa static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf,
25164506017SSrujana Challa bool enable)
25264506017SSrujana Challa {
253*a4855a8cSSrujana Challa u8 blkaddr = lf->lfs->blkaddr;
25464506017SSrujana Challa union otx2_cptx_lf_ctl lf_ctl;
25564506017SSrujana Challa
256*a4855a8cSSrujana Challa lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,
25764506017SSrujana Challa OTX2_CPT_LF_CTL);
25864506017SSrujana Challa
25964506017SSrujana Challa /* Set iqueue's enqueuing */
26064506017SSrujana Challa lf_ctl.s.ena = enable ? 0x1 : 0x0;
261*a4855a8cSSrujana Challa otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
26264506017SSrujana Challa OTX2_CPT_LF_CTL, lf_ctl.u);
26364506017SSrujana Challa }
26464506017SSrujana Challa
otx2_cptlf_enable_iqueue_enq(struct otx2_cptlf_info * lf)26564506017SSrujana Challa static inline void otx2_cptlf_enable_iqueue_enq(struct otx2_cptlf_info *lf)
26664506017SSrujana Challa {
26764506017SSrujana Challa otx2_cptlf_set_iqueue_enq(lf, true);
26864506017SSrujana Challa }
26964506017SSrujana Challa
otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info * lf,bool enable)27064506017SSrujana Challa static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf,
27164506017SSrujana Challa bool enable)
27264506017SSrujana Challa {
27364506017SSrujana Challa union otx2_cptx_lf_inprog lf_inprog;
274*a4855a8cSSrujana Challa u8 blkaddr = lf->lfs->blkaddr;
27564506017SSrujana Challa
276*a4855a8cSSrujana Challa lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,
27764506017SSrujana Challa OTX2_CPT_LF_INPROG);
27864506017SSrujana Challa
27964506017SSrujana Challa /* Set iqueue's execution */
28064506017SSrujana Challa lf_inprog.s.eena = enable ? 0x1 : 0x0;
281*a4855a8cSSrujana Challa otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
28264506017SSrujana Challa OTX2_CPT_LF_INPROG, lf_inprog.u);
28364506017SSrujana Challa }
28464506017SSrujana Challa
otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info * lf)28564506017SSrujana Challa static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf)
28664506017SSrujana Challa {
28764506017SSrujana Challa otx2_cptlf_set_iqueue_exec(lf, true);
28864506017SSrujana Challa }
28964506017SSrujana Challa
otx2_cptlf_disable_iqueue_exec(struct otx2_cptlf_info * lf)29064506017SSrujana Challa static inline void otx2_cptlf_disable_iqueue_exec(struct otx2_cptlf_info *lf)
29164506017SSrujana Challa {
29264506017SSrujana Challa otx2_cptlf_set_iqueue_exec(lf, false);
29364506017SSrujana Challa }
29464506017SSrujana Challa
otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info * lfs)29564506017SSrujana Challa static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs)
29664506017SSrujana Challa {
29764506017SSrujana Challa int slot;
29864506017SSrujana Challa
29964506017SSrujana Challa for (slot = 0; slot < lfs->lfs_num; slot++) {
30064506017SSrujana Challa otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]);
30164506017SSrujana Challa otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]);
30264506017SSrujana Challa }
30364506017SSrujana Challa }
30464506017SSrujana Challa
otx2_cpt_fill_inst(union otx2_cpt_inst_s * cptinst,struct otx2_cpt_iq_command * iq_cmd,u64 comp_baddr)30578506c2aSSrujana Challa static inline void otx2_cpt_fill_inst(union otx2_cpt_inst_s *cptinst,
30678506c2aSSrujana Challa struct otx2_cpt_iq_command *iq_cmd,
30778506c2aSSrujana Challa u64 comp_baddr)
30878506c2aSSrujana Challa {
30978506c2aSSrujana Challa cptinst->u[0] = 0x0;
31078506c2aSSrujana Challa cptinst->s.doneint = true;
31178506c2aSSrujana Challa cptinst->s.res_addr = comp_baddr;
31278506c2aSSrujana Challa cptinst->u[2] = 0x0;
31378506c2aSSrujana Challa cptinst->u[3] = 0x0;
31478506c2aSSrujana Challa cptinst->s.ei0 = iq_cmd->cmd.u;
31578506c2aSSrujana Challa cptinst->s.ei1 = iq_cmd->dptr;
31678506c2aSSrujana Challa cptinst->s.ei2 = iq_cmd->rptr;
31778506c2aSSrujana Challa cptinst->s.ei3 = iq_cmd->cptr.u;
31878506c2aSSrujana Challa }
31978506c2aSSrujana Challa
32078506c2aSSrujana Challa /*
32178506c2aSSrujana Challa * On OcteonTX2 platform the parameter insts_num is used as a count of
32278506c2aSSrujana Challa * instructions to be enqueued. The valid values for insts_num are:
32378506c2aSSrujana Challa * 1 - 1 CPT instruction will be enqueued during LMTST operation
32478506c2aSSrujana Challa * 2 - 2 CPT instructions will be enqueued during LMTST operation
32578506c2aSSrujana Challa */
otx2_cpt_send_cmd(union otx2_cpt_inst_s * cptinst,u32 insts_num,struct otx2_cptlf_info * lf)32678506c2aSSrujana Challa static inline void otx2_cpt_send_cmd(union otx2_cpt_inst_s *cptinst,
32778506c2aSSrujana Challa u32 insts_num, struct otx2_cptlf_info *lf)
32878506c2aSSrujana Challa {
32978506c2aSSrujana Challa void __iomem *lmtline = lf->lmtline;
33078506c2aSSrujana Challa long ret;
33178506c2aSSrujana Challa
33278506c2aSSrujana Challa /*
33378506c2aSSrujana Challa * Make sure memory areas pointed in CPT_INST_S
33478506c2aSSrujana Challa * are flushed before the instruction is sent to CPT
33578506c2aSSrujana Challa */
33678506c2aSSrujana Challa dma_wmb();
33778506c2aSSrujana Challa
33878506c2aSSrujana Challa do {
33978506c2aSSrujana Challa /* Copy CPT command to LMTLINE */
34078506c2aSSrujana Challa memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);
34178506c2aSSrujana Challa
34278506c2aSSrujana Challa /*
34378506c2aSSrujana Challa * LDEOR initiates atomic transfer to I/O device
34478506c2aSSrujana Challa * The following will cause the LMTST to fail (the LDEOR
34578506c2aSSrujana Challa * returns zero):
34678506c2aSSrujana Challa * - No stores have been performed to the LMTLINE since it was
34778506c2aSSrujana Challa * last invalidated.
34878506c2aSSrujana Challa * - The bytes which have been stored to LMTLINE since it was
34978506c2aSSrujana Challa * last invalidated form a pattern that is non-contiguous, does
35078506c2aSSrujana Challa * not start at byte 0, or does not end on a 8-byte boundary.
35178506c2aSSrujana Challa * (i.e.comprises a formation of other than 1–16 8-byte
35278506c2aSSrujana Challa * words.)
35378506c2aSSrujana Challa *
35478506c2aSSrujana Challa * These rules are designed such that an operating system
35578506c2aSSrujana Challa * context switch or hypervisor guest switch need have no
35678506c2aSSrujana Challa * knowledge of the LMTST operations; the switch code does not
35778506c2aSSrujana Challa * need to store to LMTCANCEL. Also note as LMTLINE data cannot
35878506c2aSSrujana Challa * be read, there is no information leakage between processes.
35978506c2aSSrujana Challa */
36078506c2aSSrujana Challa ret = otx2_lmt_flush(lf->ioreg);
36178506c2aSSrujana Challa
36278506c2aSSrujana Challa } while (!ret);
36378506c2aSSrujana Challa }
36478506c2aSSrujana Challa
otx2_cptlf_started(struct otx2_cptlfs_info * lfs)3658ec8015aSSrujana Challa static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs)
3668ec8015aSSrujana Challa {
3678ec8015aSSrujana Challa return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED;
3688ec8015aSSrujana Challa }
3698ec8015aSSrujana Challa
otx2_cptlf_set_dev_info(struct otx2_cptlfs_info * lfs,struct pci_dev * pdev,void __iomem * reg_base,struct otx2_mbox * mbox,int blkaddr)370*a4855a8cSSrujana Challa static inline void otx2_cptlf_set_dev_info(struct otx2_cptlfs_info *lfs,
371*a4855a8cSSrujana Challa struct pci_dev *pdev,
372*a4855a8cSSrujana Challa void __iomem *reg_base,
373*a4855a8cSSrujana Challa struct otx2_mbox *mbox,
374*a4855a8cSSrujana Challa int blkaddr)
375*a4855a8cSSrujana Challa {
376*a4855a8cSSrujana Challa lfs->pdev = pdev;
377*a4855a8cSSrujana Challa lfs->reg_base = reg_base;
378*a4855a8cSSrujana Challa lfs->mbox = mbox;
379*a4855a8cSSrujana Challa lfs->blkaddr = blkaddr;
380*a4855a8cSSrujana Challa }
381*a4855a8cSSrujana Challa
38264506017SSrujana Challa int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,
38364506017SSrujana Challa int lfs_num);
38464506017SSrujana Challa void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs);
38564506017SSrujana Challa int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs);
38664506017SSrujana Challa void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs);
38764506017SSrujana Challa void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs);
38864506017SSrujana Challa int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs);
38964506017SSrujana Challa
39064506017SSrujana Challa #endif /* __OTX2_CPTLF_H */
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