1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpufreq.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/opp.h> 16 #include <linux/platform_device.h> 17 #include <linux/regulator/consumer.h> 18 19 #define PU_SOC_VOLTAGE_NORMAL 1250000 20 #define PU_SOC_VOLTAGE_HIGH 1275000 21 #define FREQ_1P2_GHZ 1200000000 22 23 static struct regulator *arm_reg; 24 static struct regulator *pu_reg; 25 static struct regulator *soc_reg; 26 27 static struct clk *arm_clk; 28 static struct clk *pll1_sys_clk; 29 static struct clk *pll1_sw_clk; 30 static struct clk *step_clk; 31 static struct clk *pll2_pfd2_396m_clk; 32 33 static struct device *cpu_dev; 34 static struct cpufreq_frequency_table *freq_table; 35 static unsigned int transition_latency; 36 37 static int imx6q_verify_speed(struct cpufreq_policy *policy) 38 { 39 return cpufreq_frequency_table_verify(policy, freq_table); 40 } 41 42 static unsigned int imx6q_get_speed(unsigned int cpu) 43 { 44 return clk_get_rate(arm_clk) / 1000; 45 } 46 47 static int imx6q_set_target(struct cpufreq_policy *policy, 48 unsigned int target_freq, unsigned int relation) 49 { 50 struct cpufreq_freqs freqs; 51 struct opp *opp; 52 unsigned long freq_hz, volt, volt_old; 53 unsigned int index, cpu; 54 int ret; 55 56 ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, 57 relation, &index); 58 if (ret) { 59 dev_err(cpu_dev, "failed to match target frequency %d: %d\n", 60 target_freq, ret); 61 return ret; 62 } 63 64 freqs.new = freq_table[index].frequency; 65 freq_hz = freqs.new * 1000; 66 freqs.old = clk_get_rate(arm_clk) / 1000; 67 68 if (freqs.old == freqs.new) 69 return 0; 70 71 for_each_online_cpu(cpu) { 72 freqs.cpu = cpu; 73 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 74 } 75 76 rcu_read_lock(); 77 opp = opp_find_freq_ceil(cpu_dev, &freq_hz); 78 if (IS_ERR(opp)) { 79 rcu_read_unlock(); 80 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 81 return PTR_ERR(opp); 82 } 83 84 volt = opp_get_voltage(opp); 85 rcu_read_unlock(); 86 volt_old = regulator_get_voltage(arm_reg); 87 88 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 89 freqs.old / 1000, volt_old / 1000, 90 freqs.new / 1000, volt / 1000); 91 92 /* scaling up? scale voltage before frequency */ 93 if (freqs.new > freqs.old) { 94 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 95 if (ret) { 96 dev_err(cpu_dev, 97 "failed to scale vddarm up: %d\n", ret); 98 return ret; 99 } 100 101 /* 102 * Need to increase vddpu and vddsoc for safety 103 * if we are about to run at 1.2 GHz. 104 */ 105 if (freqs.new == FREQ_1P2_GHZ / 1000) { 106 regulator_set_voltage_tol(pu_reg, 107 PU_SOC_VOLTAGE_HIGH, 0); 108 regulator_set_voltage_tol(soc_reg, 109 PU_SOC_VOLTAGE_HIGH, 0); 110 } 111 } 112 113 /* 114 * The setpoints are selected per PLL/PDF frequencies, so we need to 115 * reprogram PLL for frequency scaling. The procedure of reprogramming 116 * PLL1 is as below. 117 * 118 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 119 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 120 * - Disable pll2_pfd2_396m_clk 121 */ 122 clk_prepare_enable(pll2_pfd2_396m_clk); 123 clk_set_parent(step_clk, pll2_pfd2_396m_clk); 124 clk_set_parent(pll1_sw_clk, step_clk); 125 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { 126 clk_set_rate(pll1_sys_clk, freqs.new * 1000); 127 /* 128 * If we are leaving 396 MHz set-point, we need to enable 129 * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep 130 * their use count correct. 131 */ 132 if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) { 133 clk_prepare_enable(pll1_sys_clk); 134 clk_disable_unprepare(pll2_pfd2_396m_clk); 135 } 136 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 137 clk_disable_unprepare(pll2_pfd2_396m_clk); 138 } else { 139 /* 140 * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient 141 * to provide the frequency. 142 */ 143 clk_disable_unprepare(pll1_sys_clk); 144 } 145 146 /* Ensure the arm clock divider is what we expect */ 147 ret = clk_set_rate(arm_clk, freqs.new * 1000); 148 if (ret) { 149 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 150 regulator_set_voltage_tol(arm_reg, volt_old, 0); 151 return ret; 152 } 153 154 /* scaling down? scale voltage after frequency */ 155 if (freqs.new < freqs.old) { 156 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 157 if (ret) 158 dev_warn(cpu_dev, 159 "failed to scale vddarm down: %d\n", ret); 160 161 if (freqs.old == FREQ_1P2_GHZ / 1000) { 162 regulator_set_voltage_tol(pu_reg, 163 PU_SOC_VOLTAGE_NORMAL, 0); 164 regulator_set_voltage_tol(soc_reg, 165 PU_SOC_VOLTAGE_NORMAL, 0); 166 } 167 } 168 169 for_each_online_cpu(cpu) { 170 freqs.cpu = cpu; 171 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 172 } 173 174 return 0; 175 } 176 177 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 178 { 179 int ret; 180 181 ret = cpufreq_frequency_table_cpuinfo(policy, freq_table); 182 if (ret) { 183 dev_err(cpu_dev, "invalid frequency table: %d\n", ret); 184 return ret; 185 } 186 187 policy->cpuinfo.transition_latency = transition_latency; 188 policy->cur = clk_get_rate(arm_clk) / 1000; 189 cpumask_setall(policy->cpus); 190 cpufreq_frequency_table_get_attr(freq_table, policy->cpu); 191 192 return 0; 193 } 194 195 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy) 196 { 197 cpufreq_frequency_table_put_attr(policy->cpu); 198 return 0; 199 } 200 201 static struct freq_attr *imx6q_cpufreq_attr[] = { 202 &cpufreq_freq_attr_scaling_available_freqs, 203 NULL, 204 }; 205 206 static struct cpufreq_driver imx6q_cpufreq_driver = { 207 .verify = imx6q_verify_speed, 208 .target = imx6q_set_target, 209 .get = imx6q_get_speed, 210 .init = imx6q_cpufreq_init, 211 .exit = imx6q_cpufreq_exit, 212 .name = "imx6q-cpufreq", 213 .attr = imx6q_cpufreq_attr, 214 }; 215 216 static int imx6q_cpufreq_probe(struct platform_device *pdev) 217 { 218 struct device_node *np; 219 struct opp *opp; 220 unsigned long min_volt, max_volt; 221 int num, ret; 222 223 cpu_dev = &pdev->dev; 224 225 np = of_find_node_by_path("/cpus/cpu@0"); 226 if (!np) { 227 dev_err(cpu_dev, "failed to find cpu0 node\n"); 228 return -ENOENT; 229 } 230 231 cpu_dev->of_node = np; 232 233 arm_clk = devm_clk_get(cpu_dev, "arm"); 234 pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys"); 235 pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw"); 236 step_clk = devm_clk_get(cpu_dev, "step"); 237 pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m"); 238 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || 239 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { 240 dev_err(cpu_dev, "failed to get clocks\n"); 241 ret = -ENOENT; 242 goto put_node; 243 } 244 245 arm_reg = devm_regulator_get(cpu_dev, "arm"); 246 pu_reg = devm_regulator_get(cpu_dev, "pu"); 247 soc_reg = devm_regulator_get(cpu_dev, "soc"); 248 if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) { 249 dev_err(cpu_dev, "failed to get regulators\n"); 250 ret = -ENOENT; 251 goto put_node; 252 } 253 254 /* We expect an OPP table supplied by platform */ 255 num = opp_get_opp_count(cpu_dev); 256 if (num < 0) { 257 ret = num; 258 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 259 goto put_node; 260 } 261 262 ret = opp_init_cpufreq_table(cpu_dev, &freq_table); 263 if (ret) { 264 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 265 goto put_node; 266 } 267 268 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 269 transition_latency = CPUFREQ_ETERNAL; 270 271 /* 272 * OPP is maintained in order of increasing frequency, and 273 * freq_table initialised from OPP is therefore sorted in the 274 * same order. 275 */ 276 rcu_read_lock(); 277 opp = opp_find_freq_exact(cpu_dev, 278 freq_table[0].frequency * 1000, true); 279 min_volt = opp_get_voltage(opp); 280 opp = opp_find_freq_exact(cpu_dev, 281 freq_table[--num].frequency * 1000, true); 282 max_volt = opp_get_voltage(opp); 283 rcu_read_unlock(); 284 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 285 if (ret > 0) 286 transition_latency += ret * 1000; 287 288 /* Count vddpu and vddsoc latency in for 1.2 GHz support */ 289 if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) { 290 ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL, 291 PU_SOC_VOLTAGE_HIGH); 292 if (ret > 0) 293 transition_latency += ret * 1000; 294 ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL, 295 PU_SOC_VOLTAGE_HIGH); 296 if (ret > 0) 297 transition_latency += ret * 1000; 298 } 299 300 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 301 if (ret) { 302 dev_err(cpu_dev, "failed register driver: %d\n", ret); 303 goto free_freq_table; 304 } 305 306 of_node_put(np); 307 return 0; 308 309 free_freq_table: 310 opp_free_cpufreq_table(cpu_dev, &freq_table); 311 put_node: 312 of_node_put(np); 313 return ret; 314 } 315 316 static int imx6q_cpufreq_remove(struct platform_device *pdev) 317 { 318 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 319 opp_free_cpufreq_table(cpu_dev, &freq_table); 320 321 return 0; 322 } 323 324 static struct platform_driver imx6q_cpufreq_platdrv = { 325 .driver = { 326 .name = "imx6q-cpufreq", 327 .owner = THIS_MODULE, 328 }, 329 .probe = imx6q_cpufreq_probe, 330 .remove = imx6q_cpufreq_remove, 331 }; 332 module_platform_driver(imx6q_cpufreq_platdrv); 333 334 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 335 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 336 MODULE_LICENSE("GPL"); 337