1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/nvmem-consumer.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/pm_opp.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 21 #define PU_SOC_VOLTAGE_NORMAL 1250000 22 #define PU_SOC_VOLTAGE_HIGH 1275000 23 #define FREQ_1P2_GHZ 1200000000 24 25 static struct regulator *arm_reg; 26 static struct regulator *pu_reg; 27 static struct regulator *soc_reg; 28 29 enum IMX6_CPUFREQ_CLKS { 30 ARM, 31 PLL1_SYS, 32 STEP, 33 PLL1_SW, 34 PLL2_PFD2_396M, 35 /* MX6UL requires two more clks */ 36 PLL2_BUS, 37 SECONDARY_SEL, 38 }; 39 #define IMX6Q_CPUFREQ_CLK_NUM 5 40 #define IMX6UL_CPUFREQ_CLK_NUM 7 41 42 static int num_clks; 43 static struct clk_bulk_data clks[] = { 44 { .id = "arm" }, 45 { .id = "pll1_sys" }, 46 { .id = "step" }, 47 { .id = "pll1_sw" }, 48 { .id = "pll2_pfd2_396m" }, 49 { .id = "pll2_bus" }, 50 { .id = "secondary_sel" }, 51 }; 52 53 static struct device *cpu_dev; 54 static bool free_opp; 55 static struct cpufreq_frequency_table *freq_table; 56 static unsigned int max_freq; 57 static unsigned int transition_latency; 58 59 static u32 *imx6_soc_volt; 60 static u32 soc_opp_count; 61 62 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 63 { 64 struct dev_pm_opp *opp; 65 unsigned long freq_hz, volt, volt_old; 66 unsigned int old_freq, new_freq; 67 bool pll1_sys_temp_enabled = false; 68 int ret; 69 70 new_freq = freq_table[index].frequency; 71 freq_hz = new_freq * 1000; 72 old_freq = clk_get_rate(clks[ARM].clk) / 1000; 73 74 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 75 if (IS_ERR(opp)) { 76 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 77 return PTR_ERR(opp); 78 } 79 80 volt = dev_pm_opp_get_voltage(opp); 81 dev_pm_opp_put(opp); 82 83 volt_old = regulator_get_voltage(arm_reg); 84 85 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 86 old_freq / 1000, volt_old / 1000, 87 new_freq / 1000, volt / 1000); 88 89 /* scaling up? scale voltage before frequency */ 90 if (new_freq > old_freq) { 91 if (!IS_ERR(pu_reg)) { 92 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 93 if (ret) { 94 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 95 return ret; 96 } 97 } 98 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 99 if (ret) { 100 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 101 return ret; 102 } 103 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 104 if (ret) { 105 dev_err(cpu_dev, 106 "failed to scale vddarm up: %d\n", ret); 107 return ret; 108 } 109 } 110 111 /* 112 * The setpoints are selected per PLL/PDF frequencies, so we need to 113 * reprogram PLL for frequency scaling. The procedure of reprogramming 114 * PLL1 is as below. 115 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change 116 * flow is slightly different from other i.MX6 OSC. 117 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: 118 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 119 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 120 * - Disable pll2_pfd2_396m_clk 121 */ 122 if (of_machine_is_compatible("fsl,imx6ul") || 123 of_machine_is_compatible("fsl,imx6ull")) { 124 /* 125 * When changing pll1_sw_clk's parent to pll1_sys_clk, 126 * CPU may run at higher than 528MHz, this will lead to 127 * the system unstable if the voltage is lower than the 128 * voltage of 528MHz, so lower the CPU frequency to one 129 * half before changing CPU frequency. 130 */ 131 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); 132 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 133 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) 134 clk_set_parent(clks[SECONDARY_SEL].clk, 135 clks[PLL2_BUS].clk); 136 else 137 clk_set_parent(clks[SECONDARY_SEL].clk, 138 clks[PLL2_PFD2_396M].clk); 139 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); 140 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 141 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) { 142 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 143 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 144 } 145 } else { 146 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); 147 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 148 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) { 149 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 150 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 151 } else { 152 /* pll1_sys needs to be enabled for divider rate change to work. */ 153 pll1_sys_temp_enabled = true; 154 clk_prepare_enable(clks[PLL1_SYS].clk); 155 } 156 } 157 158 /* Ensure the arm clock divider is what we expect */ 159 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000); 160 if (ret) { 161 int ret1; 162 163 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 164 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0); 165 if (ret1) 166 dev_warn(cpu_dev, 167 "failed to restore vddarm voltage: %d\n", ret1); 168 return ret; 169 } 170 171 /* PLL1 is only needed until after ARM-PODF is set. */ 172 if (pll1_sys_temp_enabled) 173 clk_disable_unprepare(clks[PLL1_SYS].clk); 174 175 /* scaling down? scale voltage after frequency */ 176 if (new_freq < old_freq) { 177 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 178 if (ret) 179 dev_warn(cpu_dev, 180 "failed to scale vddarm down: %d\n", ret); 181 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 182 if (ret) 183 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 184 if (!IS_ERR(pu_reg)) { 185 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 186 if (ret) 187 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 188 } 189 } 190 191 return 0; 192 } 193 194 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 195 { 196 int ret; 197 198 policy->clk = clks[ARM].clk; 199 ret = cpufreq_generic_init(policy, freq_table, transition_latency); 200 policy->suspend_freq = max_freq; 201 dev_pm_opp_of_register_em(policy->cpus); 202 203 return ret; 204 } 205 206 static struct cpufreq_driver imx6q_cpufreq_driver = { 207 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | 208 CPUFREQ_IS_COOLING_DEV, 209 .verify = cpufreq_generic_frequency_table_verify, 210 .target_index = imx6q_set_target, 211 .get = cpufreq_generic_get, 212 .init = imx6q_cpufreq_init, 213 .name = "imx6q-cpufreq", 214 .attr = cpufreq_generic_attr, 215 .suspend = cpufreq_generic_suspend, 216 }; 217 218 #define OCOTP_CFG3 0x440 219 #define OCOTP_CFG3_SPEED_SHIFT 16 220 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 221 #define OCOTP_CFG3_SPEED_996MHZ 0x2 222 #define OCOTP_CFG3_SPEED_852MHZ 0x1 223 224 static void imx6q_opp_check_speed_grading(struct device *dev) 225 { 226 struct device_node *np; 227 void __iomem *base; 228 u32 val; 229 230 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); 231 if (!np) 232 return; 233 234 base = of_iomap(np, 0); 235 if (!base) { 236 dev_err(dev, "failed to map ocotp\n"); 237 goto put_node; 238 } 239 240 /* 241 * SPEED_GRADING[1:0] defines the max speed of ARM: 242 * 2b'11: 1200000000Hz; 243 * 2b'10: 996000000Hz; 244 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 245 * 2b'00: 792000000Hz; 246 * We need to set the max speed of ARM according to fuse map. 247 */ 248 val = readl_relaxed(base + OCOTP_CFG3); 249 val >>= OCOTP_CFG3_SPEED_SHIFT; 250 val &= 0x3; 251 252 if (val < OCOTP_CFG3_SPEED_996MHZ) 253 if (dev_pm_opp_disable(dev, 996000000)) 254 dev_warn(dev, "failed to disable 996MHz OPP\n"); 255 256 if (of_machine_is_compatible("fsl,imx6q") || 257 of_machine_is_compatible("fsl,imx6qp")) { 258 if (val != OCOTP_CFG3_SPEED_852MHZ) 259 if (dev_pm_opp_disable(dev, 852000000)) 260 dev_warn(dev, "failed to disable 852MHz OPP\n"); 261 if (val != OCOTP_CFG3_SPEED_1P2GHZ) 262 if (dev_pm_opp_disable(dev, 1200000000)) 263 dev_warn(dev, "failed to disable 1.2GHz OPP\n"); 264 } 265 iounmap(base); 266 put_node: 267 of_node_put(np); 268 } 269 270 #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2 271 #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2 272 #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3 273 274 static int imx6ul_opp_check_speed_grading(struct device *dev) 275 { 276 u32 val; 277 int ret = 0; 278 279 if (of_find_property(dev->of_node, "nvmem-cells", NULL)) { 280 ret = nvmem_cell_read_u32(dev, "speed_grade", &val); 281 if (ret) 282 return ret; 283 } else { 284 struct device_node *np; 285 void __iomem *base; 286 287 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); 288 if (!np) 289 return -ENOENT; 290 291 base = of_iomap(np, 0); 292 of_node_put(np); 293 if (!base) { 294 dev_err(dev, "failed to map ocotp\n"); 295 return -EFAULT; 296 } 297 298 val = readl_relaxed(base + OCOTP_CFG3); 299 iounmap(base); 300 } 301 302 /* 303 * Speed GRADING[1:0] defines the max speed of ARM: 304 * 2b'00: Reserved; 305 * 2b'01: 528000000Hz; 306 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL; 307 * 2b'11: 900000000Hz on i.MX6ULL only; 308 * We need to set the max speed of ARM according to fuse map. 309 */ 310 val >>= OCOTP_CFG3_SPEED_SHIFT; 311 val &= 0x3; 312 313 if (of_machine_is_compatible("fsl,imx6ul")) { 314 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ) 315 if (dev_pm_opp_disable(dev, 696000000)) 316 dev_warn(dev, "failed to disable 696MHz OPP\n"); 317 } 318 319 if (of_machine_is_compatible("fsl,imx6ull")) { 320 if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ) 321 if (dev_pm_opp_disable(dev, 792000000)) 322 dev_warn(dev, "failed to disable 792MHz OPP\n"); 323 324 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ) 325 if (dev_pm_opp_disable(dev, 900000000)) 326 dev_warn(dev, "failed to disable 900MHz OPP\n"); 327 } 328 329 return ret; 330 } 331 332 static int imx6q_cpufreq_probe(struct platform_device *pdev) 333 { 334 struct device_node *np; 335 struct dev_pm_opp *opp; 336 unsigned long min_volt, max_volt; 337 int num, ret; 338 const struct property *prop; 339 const __be32 *val; 340 u32 nr, i, j; 341 342 cpu_dev = get_cpu_device(0); 343 if (!cpu_dev) { 344 pr_err("failed to get cpu0 device\n"); 345 return -ENODEV; 346 } 347 348 np = of_node_get(cpu_dev->of_node); 349 if (!np) { 350 dev_err(cpu_dev, "failed to find cpu0 node\n"); 351 return -ENOENT; 352 } 353 354 if (of_machine_is_compatible("fsl,imx6ul") || 355 of_machine_is_compatible("fsl,imx6ull")) 356 num_clks = IMX6UL_CPUFREQ_CLK_NUM; 357 else 358 num_clks = IMX6Q_CPUFREQ_CLK_NUM; 359 360 ret = clk_bulk_get(cpu_dev, num_clks, clks); 361 if (ret) 362 goto put_node; 363 364 arm_reg = regulator_get(cpu_dev, "arm"); 365 pu_reg = regulator_get_optional(cpu_dev, "pu"); 366 soc_reg = regulator_get(cpu_dev, "soc"); 367 if (PTR_ERR(arm_reg) == -EPROBE_DEFER || 368 PTR_ERR(soc_reg) == -EPROBE_DEFER || 369 PTR_ERR(pu_reg) == -EPROBE_DEFER) { 370 ret = -EPROBE_DEFER; 371 dev_dbg(cpu_dev, "regulators not ready, defer\n"); 372 goto put_reg; 373 } 374 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { 375 dev_err(cpu_dev, "failed to get regulators\n"); 376 ret = -ENOENT; 377 goto put_reg; 378 } 379 380 ret = dev_pm_opp_of_add_table(cpu_dev); 381 if (ret < 0) { 382 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 383 goto put_reg; 384 } 385 386 if (of_machine_is_compatible("fsl,imx6ul") || 387 of_machine_is_compatible("fsl,imx6ull")) { 388 ret = imx6ul_opp_check_speed_grading(cpu_dev); 389 if (ret) { 390 if (ret == -EPROBE_DEFER) 391 goto put_node; 392 393 dev_err(cpu_dev, "failed to read ocotp: %d\n", 394 ret); 395 goto put_node; 396 } 397 } else { 398 imx6q_opp_check_speed_grading(cpu_dev); 399 } 400 401 /* Because we have added the OPPs here, we must free them */ 402 free_opp = true; 403 num = dev_pm_opp_get_opp_count(cpu_dev); 404 if (num < 0) { 405 ret = num; 406 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 407 goto out_free_opp; 408 } 409 410 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 411 if (ret) { 412 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 413 goto out_free_opp; 414 } 415 416 /* Make imx6_soc_volt array's size same as arm opp number */ 417 imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt), 418 GFP_KERNEL); 419 if (imx6_soc_volt == NULL) { 420 ret = -ENOMEM; 421 goto free_freq_table; 422 } 423 424 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 425 if (!prop || !prop->value) 426 goto soc_opp_out; 427 428 /* 429 * Each OPP is a set of tuples consisting of frequency and 430 * voltage like <freq-kHz vol-uV>. 431 */ 432 nr = prop->length / sizeof(u32); 433 if (nr % 2 || (nr / 2) < num) 434 goto soc_opp_out; 435 436 for (j = 0; j < num; j++) { 437 val = prop->value; 438 for (i = 0; i < nr / 2; i++) { 439 unsigned long freq = be32_to_cpup(val++); 440 unsigned long volt = be32_to_cpup(val++); 441 if (freq_table[j].frequency == freq) { 442 imx6_soc_volt[soc_opp_count++] = volt; 443 break; 444 } 445 } 446 } 447 448 soc_opp_out: 449 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 450 if (soc_opp_count != num) { 451 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 452 for (j = 0; j < num; j++) 453 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 454 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 455 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 456 } 457 458 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 459 transition_latency = CPUFREQ_ETERNAL; 460 461 /* 462 * Calculate the ramp time for max voltage change in the 463 * VDDSOC and VDDPU regulators. 464 */ 465 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 466 if (ret > 0) 467 transition_latency += ret * 1000; 468 if (!IS_ERR(pu_reg)) { 469 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 470 if (ret > 0) 471 transition_latency += ret * 1000; 472 } 473 474 /* 475 * OPP is maintained in order of increasing frequency, and 476 * freq_table initialised from OPP is therefore sorted in the 477 * same order. 478 */ 479 max_freq = freq_table[--num].frequency; 480 opp = dev_pm_opp_find_freq_exact(cpu_dev, 481 freq_table[0].frequency * 1000, true); 482 min_volt = dev_pm_opp_get_voltage(opp); 483 dev_pm_opp_put(opp); 484 opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true); 485 max_volt = dev_pm_opp_get_voltage(opp); 486 dev_pm_opp_put(opp); 487 488 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 489 if (ret > 0) 490 transition_latency += ret * 1000; 491 492 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 493 if (ret) { 494 dev_err(cpu_dev, "failed register driver: %d\n", ret); 495 goto free_freq_table; 496 } 497 498 of_node_put(np); 499 return 0; 500 501 free_freq_table: 502 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 503 out_free_opp: 504 if (free_opp) 505 dev_pm_opp_of_remove_table(cpu_dev); 506 put_reg: 507 if (!IS_ERR(arm_reg)) 508 regulator_put(arm_reg); 509 if (!IS_ERR(pu_reg)) 510 regulator_put(pu_reg); 511 if (!IS_ERR(soc_reg)) 512 regulator_put(soc_reg); 513 514 clk_bulk_put(num_clks, clks); 515 put_node: 516 of_node_put(np); 517 518 return ret; 519 } 520 521 static int imx6q_cpufreq_remove(struct platform_device *pdev) 522 { 523 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 524 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 525 if (free_opp) 526 dev_pm_opp_of_remove_table(cpu_dev); 527 regulator_put(arm_reg); 528 if (!IS_ERR(pu_reg)) 529 regulator_put(pu_reg); 530 regulator_put(soc_reg); 531 532 clk_bulk_put(num_clks, clks); 533 534 return 0; 535 } 536 537 static struct platform_driver imx6q_cpufreq_platdrv = { 538 .driver = { 539 .name = "imx6q-cpufreq", 540 }, 541 .probe = imx6q_cpufreq_probe, 542 .remove = imx6q_cpufreq_remove, 543 }; 544 module_platform_driver(imx6q_cpufreq_platdrv); 545 546 MODULE_ALIAS("platform:imx6q-cpufreq"); 547 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 548 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 549 MODULE_LICENSE("GPL"); 550