1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/pm_opp.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 20 #define PU_SOC_VOLTAGE_NORMAL 1250000 21 #define PU_SOC_VOLTAGE_HIGH 1275000 22 #define FREQ_1P2_GHZ 1200000000 23 24 static struct regulator *arm_reg; 25 static struct regulator *pu_reg; 26 static struct regulator *soc_reg; 27 28 enum IMX6_CPUFREQ_CLKS { 29 ARM, 30 PLL1_SYS, 31 STEP, 32 PLL1_SW, 33 PLL2_PFD2_396M, 34 /* MX6UL requires two more clks */ 35 PLL2_BUS, 36 SECONDARY_SEL, 37 }; 38 #define IMX6Q_CPUFREQ_CLK_NUM 5 39 #define IMX6UL_CPUFREQ_CLK_NUM 7 40 41 static int num_clks; 42 static struct clk_bulk_data clks[] = { 43 { .id = "arm" }, 44 { .id = "pll1_sys" }, 45 { .id = "step" }, 46 { .id = "pll1_sw" }, 47 { .id = "pll2_pfd2_396m" }, 48 { .id = "pll2_bus" }, 49 { .id = "secondary_sel" }, 50 }; 51 52 static struct device *cpu_dev; 53 static bool free_opp; 54 static struct cpufreq_frequency_table *freq_table; 55 static unsigned int transition_latency; 56 57 static u32 *imx6_soc_volt; 58 static u32 soc_opp_count; 59 60 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 61 { 62 struct dev_pm_opp *opp; 63 unsigned long freq_hz, volt, volt_old; 64 unsigned int old_freq, new_freq; 65 bool pll1_sys_temp_enabled = false; 66 int ret; 67 68 new_freq = freq_table[index].frequency; 69 freq_hz = new_freq * 1000; 70 old_freq = clk_get_rate(clks[ARM].clk) / 1000; 71 72 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 73 if (IS_ERR(opp)) { 74 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 75 return PTR_ERR(opp); 76 } 77 78 volt = dev_pm_opp_get_voltage(opp); 79 dev_pm_opp_put(opp); 80 81 volt_old = regulator_get_voltage(arm_reg); 82 83 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 84 old_freq / 1000, volt_old / 1000, 85 new_freq / 1000, volt / 1000); 86 87 /* scaling up? scale voltage before frequency */ 88 if (new_freq > old_freq) { 89 if (!IS_ERR(pu_reg)) { 90 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 91 if (ret) { 92 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 93 return ret; 94 } 95 } 96 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 97 if (ret) { 98 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 99 return ret; 100 } 101 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 102 if (ret) { 103 dev_err(cpu_dev, 104 "failed to scale vddarm up: %d\n", ret); 105 return ret; 106 } 107 } 108 109 /* 110 * The setpoints are selected per PLL/PDF frequencies, so we need to 111 * reprogram PLL for frequency scaling. The procedure of reprogramming 112 * PLL1 is as below. 113 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change 114 * flow is slightly different from other i.MX6 OSC. 115 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: 116 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 117 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 118 * - Disable pll2_pfd2_396m_clk 119 */ 120 if (of_machine_is_compatible("fsl,imx6ul") || 121 of_machine_is_compatible("fsl,imx6ull")) { 122 /* 123 * When changing pll1_sw_clk's parent to pll1_sys_clk, 124 * CPU may run at higher than 528MHz, this will lead to 125 * the system unstable if the voltage is lower than the 126 * voltage of 528MHz, so lower the CPU frequency to one 127 * half before changing CPU frequency. 128 */ 129 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); 130 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 131 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) 132 clk_set_parent(clks[SECONDARY_SEL].clk, 133 clks[PLL2_BUS].clk); 134 else 135 clk_set_parent(clks[SECONDARY_SEL].clk, 136 clks[PLL2_PFD2_396M].clk); 137 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); 138 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 139 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) { 140 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 141 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 142 } 143 } else { 144 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); 145 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 146 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) { 147 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 148 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 149 } else { 150 /* pll1_sys needs to be enabled for divider rate change to work. */ 151 pll1_sys_temp_enabled = true; 152 clk_prepare_enable(clks[PLL1_SYS].clk); 153 } 154 } 155 156 /* Ensure the arm clock divider is what we expect */ 157 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000); 158 if (ret) { 159 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 160 regulator_set_voltage_tol(arm_reg, volt_old, 0); 161 return ret; 162 } 163 164 /* PLL1 is only needed until after ARM-PODF is set. */ 165 if (pll1_sys_temp_enabled) 166 clk_disable_unprepare(clks[PLL1_SYS].clk); 167 168 /* scaling down? scale voltage after frequency */ 169 if (new_freq < old_freq) { 170 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 171 if (ret) { 172 dev_warn(cpu_dev, 173 "failed to scale vddarm down: %d\n", ret); 174 ret = 0; 175 } 176 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 177 if (ret) { 178 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 179 ret = 0; 180 } 181 if (!IS_ERR(pu_reg)) { 182 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 183 if (ret) { 184 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 185 ret = 0; 186 } 187 } 188 } 189 190 return 0; 191 } 192 193 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 194 { 195 int ret; 196 197 policy->clk = clks[ARM].clk; 198 ret = cpufreq_generic_init(policy, freq_table, transition_latency); 199 policy->suspend_freq = policy->max; 200 201 return ret; 202 } 203 204 static struct cpufreq_driver imx6q_cpufreq_driver = { 205 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 206 .verify = cpufreq_generic_frequency_table_verify, 207 .target_index = imx6q_set_target, 208 .get = cpufreq_generic_get, 209 .init = imx6q_cpufreq_init, 210 .name = "imx6q-cpufreq", 211 .attr = cpufreq_generic_attr, 212 .suspend = cpufreq_generic_suspend, 213 }; 214 215 #define OCOTP_CFG3 0x440 216 #define OCOTP_CFG3_SPEED_SHIFT 16 217 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 218 #define OCOTP_CFG3_SPEED_996MHZ 0x2 219 #define OCOTP_CFG3_SPEED_852MHZ 0x1 220 221 static void imx6q_opp_check_speed_grading(struct device *dev) 222 { 223 struct device_node *np; 224 void __iomem *base; 225 u32 val; 226 227 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); 228 if (!np) 229 return; 230 231 base = of_iomap(np, 0); 232 if (!base) { 233 dev_err(dev, "failed to map ocotp\n"); 234 goto put_node; 235 } 236 237 /* 238 * SPEED_GRADING[1:0] defines the max speed of ARM: 239 * 2b'11: 1200000000Hz; 240 * 2b'10: 996000000Hz; 241 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 242 * 2b'00: 792000000Hz; 243 * We need to set the max speed of ARM according to fuse map. 244 */ 245 val = readl_relaxed(base + OCOTP_CFG3); 246 val >>= OCOTP_CFG3_SPEED_SHIFT; 247 val &= 0x3; 248 249 if (val < OCOTP_CFG3_SPEED_996MHZ) 250 if (dev_pm_opp_disable(dev, 996000000)) 251 dev_warn(dev, "failed to disable 996MHz OPP\n"); 252 253 if (of_machine_is_compatible("fsl,imx6q") || 254 of_machine_is_compatible("fsl,imx6qp")) { 255 if (val != OCOTP_CFG3_SPEED_852MHZ) 256 if (dev_pm_opp_disable(dev, 852000000)) 257 dev_warn(dev, "failed to disable 852MHz OPP\n"); 258 if (val != OCOTP_CFG3_SPEED_1P2GHZ) 259 if (dev_pm_opp_disable(dev, 1200000000)) 260 dev_warn(dev, "failed to disable 1.2GHz OPP\n"); 261 } 262 iounmap(base); 263 put_node: 264 of_node_put(np); 265 } 266 267 #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2 268 269 static void imx6ul_opp_check_speed_grading(struct device *dev) 270 { 271 struct device_node *np; 272 void __iomem *base; 273 u32 val; 274 275 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); 276 if (!np) 277 return; 278 279 base = of_iomap(np, 0); 280 if (!base) { 281 dev_err(dev, "failed to map ocotp\n"); 282 goto put_node; 283 } 284 285 /* 286 * Speed GRADING[1:0] defines the max speed of ARM: 287 * 2b'00: Reserved; 288 * 2b'01: 528000000Hz; 289 * 2b'10: 696000000Hz; 290 * 2b'11: Reserved; 291 * We need to set the max speed of ARM according to fuse map. 292 */ 293 val = readl_relaxed(base + OCOTP_CFG3); 294 val >>= OCOTP_CFG3_SPEED_SHIFT; 295 val &= 0x3; 296 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ) 297 if (dev_pm_opp_disable(dev, 696000000)) 298 dev_warn(dev, "failed to disable 696MHz OPP\n"); 299 iounmap(base); 300 put_node: 301 of_node_put(np); 302 } 303 304 static int imx6q_cpufreq_probe(struct platform_device *pdev) 305 { 306 struct device_node *np; 307 struct dev_pm_opp *opp; 308 unsigned long min_volt, max_volt; 309 int num, ret; 310 const struct property *prop; 311 const __be32 *val; 312 u32 nr, i, j; 313 314 cpu_dev = get_cpu_device(0); 315 if (!cpu_dev) { 316 pr_err("failed to get cpu0 device\n"); 317 return -ENODEV; 318 } 319 320 np = of_node_get(cpu_dev->of_node); 321 if (!np) { 322 dev_err(cpu_dev, "failed to find cpu0 node\n"); 323 return -ENOENT; 324 } 325 326 if (of_machine_is_compatible("fsl,imx6ul") || 327 of_machine_is_compatible("fsl,imx6ull")) 328 num_clks = IMX6UL_CPUFREQ_CLK_NUM; 329 else 330 num_clks = IMX6Q_CPUFREQ_CLK_NUM; 331 332 ret = clk_bulk_get(cpu_dev, num_clks, clks); 333 if (ret) 334 goto put_node; 335 336 arm_reg = regulator_get(cpu_dev, "arm"); 337 pu_reg = regulator_get_optional(cpu_dev, "pu"); 338 soc_reg = regulator_get(cpu_dev, "soc"); 339 if (PTR_ERR(arm_reg) == -EPROBE_DEFER || 340 PTR_ERR(soc_reg) == -EPROBE_DEFER || 341 PTR_ERR(pu_reg) == -EPROBE_DEFER) { 342 ret = -EPROBE_DEFER; 343 dev_dbg(cpu_dev, "regulators not ready, defer\n"); 344 goto put_reg; 345 } 346 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { 347 dev_err(cpu_dev, "failed to get regulators\n"); 348 ret = -ENOENT; 349 goto put_reg; 350 } 351 352 ret = dev_pm_opp_of_add_table(cpu_dev); 353 if (ret < 0) { 354 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 355 goto put_reg; 356 } 357 358 if (of_machine_is_compatible("fsl,imx6ul")) 359 imx6ul_opp_check_speed_grading(cpu_dev); 360 else 361 imx6q_opp_check_speed_grading(cpu_dev); 362 363 /* Because we have added the OPPs here, we must free them */ 364 free_opp = true; 365 num = dev_pm_opp_get_opp_count(cpu_dev); 366 if (num < 0) { 367 ret = num; 368 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 369 goto out_free_opp; 370 } 371 372 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 373 if (ret) { 374 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 375 goto out_free_opp; 376 } 377 378 /* Make imx6_soc_volt array's size same as arm opp number */ 379 imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL); 380 if (imx6_soc_volt == NULL) { 381 ret = -ENOMEM; 382 goto free_freq_table; 383 } 384 385 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 386 if (!prop || !prop->value) 387 goto soc_opp_out; 388 389 /* 390 * Each OPP is a set of tuples consisting of frequency and 391 * voltage like <freq-kHz vol-uV>. 392 */ 393 nr = prop->length / sizeof(u32); 394 if (nr % 2 || (nr / 2) < num) 395 goto soc_opp_out; 396 397 for (j = 0; j < num; j++) { 398 val = prop->value; 399 for (i = 0; i < nr / 2; i++) { 400 unsigned long freq = be32_to_cpup(val++); 401 unsigned long volt = be32_to_cpup(val++); 402 if (freq_table[j].frequency == freq) { 403 imx6_soc_volt[soc_opp_count++] = volt; 404 break; 405 } 406 } 407 } 408 409 soc_opp_out: 410 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 411 if (soc_opp_count != num) { 412 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 413 for (j = 0; j < num; j++) 414 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 415 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 416 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 417 } 418 419 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 420 transition_latency = CPUFREQ_ETERNAL; 421 422 /* 423 * Calculate the ramp time for max voltage change in the 424 * VDDSOC and VDDPU regulators. 425 */ 426 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 427 if (ret > 0) 428 transition_latency += ret * 1000; 429 if (!IS_ERR(pu_reg)) { 430 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 431 if (ret > 0) 432 transition_latency += ret * 1000; 433 } 434 435 /* 436 * OPP is maintained in order of increasing frequency, and 437 * freq_table initialised from OPP is therefore sorted in the 438 * same order. 439 */ 440 opp = dev_pm_opp_find_freq_exact(cpu_dev, 441 freq_table[0].frequency * 1000, true); 442 min_volt = dev_pm_opp_get_voltage(opp); 443 dev_pm_opp_put(opp); 444 opp = dev_pm_opp_find_freq_exact(cpu_dev, 445 freq_table[--num].frequency * 1000, true); 446 max_volt = dev_pm_opp_get_voltage(opp); 447 dev_pm_opp_put(opp); 448 449 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 450 if (ret > 0) 451 transition_latency += ret * 1000; 452 453 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 454 if (ret) { 455 dev_err(cpu_dev, "failed register driver: %d\n", ret); 456 goto free_freq_table; 457 } 458 459 of_node_put(np); 460 return 0; 461 462 free_freq_table: 463 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 464 out_free_opp: 465 if (free_opp) 466 dev_pm_opp_of_remove_table(cpu_dev); 467 put_reg: 468 if (!IS_ERR(arm_reg)) 469 regulator_put(arm_reg); 470 if (!IS_ERR(pu_reg)) 471 regulator_put(pu_reg); 472 if (!IS_ERR(soc_reg)) 473 regulator_put(soc_reg); 474 475 clk_bulk_put(num_clks, clks); 476 put_node: 477 of_node_put(np); 478 479 return ret; 480 } 481 482 static int imx6q_cpufreq_remove(struct platform_device *pdev) 483 { 484 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 485 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 486 if (free_opp) 487 dev_pm_opp_of_remove_table(cpu_dev); 488 regulator_put(arm_reg); 489 if (!IS_ERR(pu_reg)) 490 regulator_put(pu_reg); 491 regulator_put(soc_reg); 492 493 clk_bulk_put(num_clks, clks); 494 495 return 0; 496 } 497 498 static struct platform_driver imx6q_cpufreq_platdrv = { 499 .driver = { 500 .name = "imx6q-cpufreq", 501 }, 502 .probe = imx6q_cpufreq_probe, 503 .remove = imx6q_cpufreq_remove, 504 }; 505 module_platform_driver(imx6q_cpufreq_platdrv); 506 507 MODULE_ALIAS("platform:imx6q-cpufreq"); 508 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 509 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 510 MODULE_LICENSE("GPL"); 511