1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pm_opp.h> 16 #include <linux/platform_device.h> 17 #include <linux/regulator/consumer.h> 18 19 #define PU_SOC_VOLTAGE_NORMAL 1250000 20 #define PU_SOC_VOLTAGE_HIGH 1275000 21 #define FREQ_1P2_GHZ 1200000000 22 23 static struct regulator *arm_reg; 24 static struct regulator *pu_reg; 25 static struct regulator *soc_reg; 26 27 static struct clk *arm_clk; 28 static struct clk *pll1_sys_clk; 29 static struct clk *pll1_sw_clk; 30 static struct clk *step_clk; 31 static struct clk *pll2_pfd2_396m_clk; 32 33 static struct device *cpu_dev; 34 static struct cpufreq_frequency_table *freq_table; 35 static unsigned int transition_latency; 36 37 static u32 *imx6_soc_volt; 38 static u32 soc_opp_count; 39 40 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 41 { 42 struct dev_pm_opp *opp; 43 unsigned long freq_hz, volt, volt_old; 44 unsigned int old_freq, new_freq; 45 int ret; 46 47 new_freq = freq_table[index].frequency; 48 freq_hz = new_freq * 1000; 49 old_freq = clk_get_rate(arm_clk) / 1000; 50 51 rcu_read_lock(); 52 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 53 if (IS_ERR(opp)) { 54 rcu_read_unlock(); 55 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 56 return PTR_ERR(opp); 57 } 58 59 volt = dev_pm_opp_get_voltage(opp); 60 rcu_read_unlock(); 61 volt_old = regulator_get_voltage(arm_reg); 62 63 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 64 old_freq / 1000, volt_old / 1000, 65 new_freq / 1000, volt / 1000); 66 67 /* scaling up? scale voltage before frequency */ 68 if (new_freq > old_freq) { 69 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 70 if (ret) { 71 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 72 return ret; 73 } 74 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 75 if (ret) { 76 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 77 return ret; 78 } 79 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 80 if (ret) { 81 dev_err(cpu_dev, 82 "failed to scale vddarm up: %d\n", ret); 83 return ret; 84 } 85 } 86 87 /* 88 * The setpoints are selected per PLL/PDF frequencies, so we need to 89 * reprogram PLL for frequency scaling. The procedure of reprogramming 90 * PLL1 is as below. 91 * 92 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 93 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 94 * - Disable pll2_pfd2_396m_clk 95 */ 96 clk_set_parent(step_clk, pll2_pfd2_396m_clk); 97 clk_set_parent(pll1_sw_clk, step_clk); 98 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { 99 clk_set_rate(pll1_sys_clk, new_freq * 1000); 100 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 101 } 102 103 /* Ensure the arm clock divider is what we expect */ 104 ret = clk_set_rate(arm_clk, new_freq * 1000); 105 if (ret) { 106 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 107 regulator_set_voltage_tol(arm_reg, volt_old, 0); 108 return ret; 109 } 110 111 /* scaling down? scale voltage after frequency */ 112 if (new_freq < old_freq) { 113 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 114 if (ret) { 115 dev_warn(cpu_dev, 116 "failed to scale vddarm down: %d\n", ret); 117 ret = 0; 118 } 119 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 120 if (ret) { 121 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 122 ret = 0; 123 } 124 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 125 if (ret) { 126 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 127 ret = 0; 128 } 129 } 130 131 return 0; 132 } 133 134 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 135 { 136 policy->clk = arm_clk; 137 return cpufreq_generic_init(policy, freq_table, transition_latency); 138 } 139 140 static struct cpufreq_driver imx6q_cpufreq_driver = { 141 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 142 .verify = cpufreq_generic_frequency_table_verify, 143 .target_index = imx6q_set_target, 144 .get = cpufreq_generic_get, 145 .init = imx6q_cpufreq_init, 146 .name = "imx6q-cpufreq", 147 .attr = cpufreq_generic_attr, 148 }; 149 150 static int imx6q_cpufreq_probe(struct platform_device *pdev) 151 { 152 struct device_node *np; 153 struct dev_pm_opp *opp; 154 unsigned long min_volt, max_volt; 155 int num, ret; 156 const struct property *prop; 157 const __be32 *val; 158 u32 nr, i, j; 159 160 cpu_dev = get_cpu_device(0); 161 if (!cpu_dev) { 162 pr_err("failed to get cpu0 device\n"); 163 return -ENODEV; 164 } 165 166 np = of_node_get(cpu_dev->of_node); 167 if (!np) { 168 dev_err(cpu_dev, "failed to find cpu0 node\n"); 169 return -ENOENT; 170 } 171 172 arm_clk = clk_get(cpu_dev, "arm"); 173 pll1_sys_clk = clk_get(cpu_dev, "pll1_sys"); 174 pll1_sw_clk = clk_get(cpu_dev, "pll1_sw"); 175 step_clk = clk_get(cpu_dev, "step"); 176 pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m"); 177 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || 178 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { 179 dev_err(cpu_dev, "failed to get clocks\n"); 180 ret = -ENOENT; 181 goto put_clk; 182 } 183 184 arm_reg = regulator_get(cpu_dev, "arm"); 185 pu_reg = regulator_get(cpu_dev, "pu"); 186 soc_reg = regulator_get(cpu_dev, "soc"); 187 if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) { 188 dev_err(cpu_dev, "failed to get regulators\n"); 189 ret = -ENOENT; 190 goto put_reg; 191 } 192 193 /* 194 * We expect an OPP table supplied by platform. 195 * Just, incase the platform did not supply the OPP 196 * table, it will try to get it. 197 */ 198 num = dev_pm_opp_get_opp_count(cpu_dev); 199 if (num < 0) { 200 ret = of_init_opp_table(cpu_dev); 201 if (ret < 0) { 202 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 203 goto put_reg; 204 } 205 206 num = dev_pm_opp_get_opp_count(cpu_dev); 207 if (num < 0) { 208 ret = num; 209 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 210 goto put_reg; 211 } 212 } 213 214 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 215 if (ret) { 216 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 217 goto put_reg; 218 } 219 220 /* Make imx6_soc_volt array's size same as arm opp number */ 221 imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL); 222 if (imx6_soc_volt == NULL) { 223 ret = -ENOMEM; 224 goto free_freq_table; 225 } 226 227 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 228 if (!prop || !prop->value) 229 goto soc_opp_out; 230 231 /* 232 * Each OPP is a set of tuples consisting of frequency and 233 * voltage like <freq-kHz vol-uV>. 234 */ 235 nr = prop->length / sizeof(u32); 236 if (nr % 2 || (nr / 2) < num) 237 goto soc_opp_out; 238 239 for (j = 0; j < num; j++) { 240 val = prop->value; 241 for (i = 0; i < nr / 2; i++) { 242 unsigned long freq = be32_to_cpup(val++); 243 unsigned long volt = be32_to_cpup(val++); 244 if (freq_table[j].frequency == freq) { 245 imx6_soc_volt[soc_opp_count++] = volt; 246 break; 247 } 248 } 249 } 250 251 soc_opp_out: 252 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 253 if (soc_opp_count != num) { 254 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 255 for (j = 0; j < num; j++) 256 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 257 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 258 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 259 } 260 261 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 262 transition_latency = CPUFREQ_ETERNAL; 263 264 /* 265 * Calculate the ramp time for max voltage change in the 266 * VDDSOC and VDDPU regulators. 267 */ 268 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 269 if (ret > 0) 270 transition_latency += ret * 1000; 271 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 272 if (ret > 0) 273 transition_latency += ret * 1000; 274 275 /* 276 * OPP is maintained in order of increasing frequency, and 277 * freq_table initialised from OPP is therefore sorted in the 278 * same order. 279 */ 280 rcu_read_lock(); 281 opp = dev_pm_opp_find_freq_exact(cpu_dev, 282 freq_table[0].frequency * 1000, true); 283 min_volt = dev_pm_opp_get_voltage(opp); 284 opp = dev_pm_opp_find_freq_exact(cpu_dev, 285 freq_table[--num].frequency * 1000, true); 286 max_volt = dev_pm_opp_get_voltage(opp); 287 rcu_read_unlock(); 288 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 289 if (ret > 0) 290 transition_latency += ret * 1000; 291 292 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 293 if (ret) { 294 dev_err(cpu_dev, "failed register driver: %d\n", ret); 295 goto free_freq_table; 296 } 297 298 of_node_put(np); 299 return 0; 300 301 free_freq_table: 302 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 303 put_reg: 304 if (!IS_ERR(arm_reg)) 305 regulator_put(arm_reg); 306 if (!IS_ERR(pu_reg)) 307 regulator_put(pu_reg); 308 if (!IS_ERR(soc_reg)) 309 regulator_put(soc_reg); 310 put_clk: 311 if (!IS_ERR(arm_clk)) 312 clk_put(arm_clk); 313 if (!IS_ERR(pll1_sys_clk)) 314 clk_put(pll1_sys_clk); 315 if (!IS_ERR(pll1_sw_clk)) 316 clk_put(pll1_sw_clk); 317 if (!IS_ERR(step_clk)) 318 clk_put(step_clk); 319 if (!IS_ERR(pll2_pfd2_396m_clk)) 320 clk_put(pll2_pfd2_396m_clk); 321 of_node_put(np); 322 return ret; 323 } 324 325 static int imx6q_cpufreq_remove(struct platform_device *pdev) 326 { 327 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 328 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 329 regulator_put(arm_reg); 330 regulator_put(pu_reg); 331 regulator_put(soc_reg); 332 clk_put(arm_clk); 333 clk_put(pll1_sys_clk); 334 clk_put(pll1_sw_clk); 335 clk_put(step_clk); 336 clk_put(pll2_pfd2_396m_clk); 337 338 return 0; 339 } 340 341 static struct platform_driver imx6q_cpufreq_platdrv = { 342 .driver = { 343 .name = "imx6q-cpufreq", 344 .owner = THIS_MODULE, 345 }, 346 .probe = imx6q_cpufreq_probe, 347 .remove = imx6q_cpufreq_remove, 348 }; 349 module_platform_driver(imx6q_cpufreq_platdrv); 350 351 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 352 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 353 MODULE_LICENSE("GPL"); 354