1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/pm_opp.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 20 #define PU_SOC_VOLTAGE_NORMAL 1250000 21 #define PU_SOC_VOLTAGE_HIGH 1275000 22 #define FREQ_1P2_GHZ 1200000000 23 24 static struct regulator *arm_reg; 25 static struct regulator *pu_reg; 26 static struct regulator *soc_reg; 27 28 static struct clk *arm_clk; 29 static struct clk *pll1_sys_clk; 30 static struct clk *pll1_sw_clk; 31 static struct clk *step_clk; 32 static struct clk *pll2_pfd2_396m_clk; 33 34 static struct device *cpu_dev; 35 static struct cpufreq_frequency_table *freq_table; 36 static unsigned int transition_latency; 37 38 static unsigned int imx6q_get_speed(unsigned int cpu) 39 { 40 return clk_get_rate(arm_clk) / 1000; 41 } 42 43 static int imx6q_set_target(struct cpufreq_policy *policy, 44 unsigned int target_freq, unsigned int relation) 45 { 46 struct cpufreq_freqs freqs; 47 struct dev_pm_opp *opp; 48 unsigned long freq_hz, volt, volt_old; 49 unsigned int index; 50 int ret; 51 52 ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, 53 relation, &index); 54 if (ret) { 55 dev_err(cpu_dev, "failed to match target frequency %d: %d\n", 56 target_freq, ret); 57 return ret; 58 } 59 60 freqs.new = freq_table[index].frequency; 61 freq_hz = freqs.new * 1000; 62 freqs.old = clk_get_rate(arm_clk) / 1000; 63 64 if (freqs.old == freqs.new) 65 return 0; 66 67 rcu_read_lock(); 68 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 69 if (IS_ERR(opp)) { 70 rcu_read_unlock(); 71 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 72 return PTR_ERR(opp); 73 } 74 75 volt = dev_pm_opp_get_voltage(opp); 76 rcu_read_unlock(); 77 volt_old = regulator_get_voltage(arm_reg); 78 79 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 80 freqs.old / 1000, volt_old / 1000, 81 freqs.new / 1000, volt / 1000); 82 83 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); 84 85 /* scaling up? scale voltage before frequency */ 86 if (freqs.new > freqs.old) { 87 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 88 if (ret) { 89 dev_err(cpu_dev, 90 "failed to scale vddarm up: %d\n", ret); 91 freqs.new = freqs.old; 92 goto post_notify; 93 } 94 95 /* 96 * Need to increase vddpu and vddsoc for safety 97 * if we are about to run at 1.2 GHz. 98 */ 99 if (freqs.new == FREQ_1P2_GHZ / 1000) { 100 regulator_set_voltage_tol(pu_reg, 101 PU_SOC_VOLTAGE_HIGH, 0); 102 regulator_set_voltage_tol(soc_reg, 103 PU_SOC_VOLTAGE_HIGH, 0); 104 } 105 } 106 107 /* 108 * The setpoints are selected per PLL/PDF frequencies, so we need to 109 * reprogram PLL for frequency scaling. The procedure of reprogramming 110 * PLL1 is as below. 111 * 112 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 113 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 114 * - Disable pll2_pfd2_396m_clk 115 */ 116 clk_set_parent(step_clk, pll2_pfd2_396m_clk); 117 clk_set_parent(pll1_sw_clk, step_clk); 118 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { 119 clk_set_rate(pll1_sys_clk, freqs.new * 1000); 120 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 121 } 122 123 /* Ensure the arm clock divider is what we expect */ 124 ret = clk_set_rate(arm_clk, freqs.new * 1000); 125 if (ret) { 126 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 127 regulator_set_voltage_tol(arm_reg, volt_old, 0); 128 freqs.new = freqs.old; 129 goto post_notify; 130 } 131 132 /* scaling down? scale voltage after frequency */ 133 if (freqs.new < freqs.old) { 134 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 135 if (ret) { 136 dev_warn(cpu_dev, 137 "failed to scale vddarm down: %d\n", ret); 138 ret = 0; 139 } 140 141 if (freqs.old == FREQ_1P2_GHZ / 1000) { 142 regulator_set_voltage_tol(pu_reg, 143 PU_SOC_VOLTAGE_NORMAL, 0); 144 regulator_set_voltage_tol(soc_reg, 145 PU_SOC_VOLTAGE_NORMAL, 0); 146 } 147 } 148 149 post_notify: 150 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); 151 152 return ret; 153 } 154 155 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 156 { 157 return cpufreq_generic_init(policy, freq_table, transition_latency); 158 } 159 160 static struct cpufreq_driver imx6q_cpufreq_driver = { 161 .verify = cpufreq_generic_frequency_table_verify, 162 .target = imx6q_set_target, 163 .get = imx6q_get_speed, 164 .init = imx6q_cpufreq_init, 165 .exit = cpufreq_generic_exit, 166 .name = "imx6q-cpufreq", 167 .attr = cpufreq_generic_attr, 168 }; 169 170 static int imx6q_cpufreq_probe(struct platform_device *pdev) 171 { 172 struct device_node *np; 173 struct dev_pm_opp *opp; 174 unsigned long min_volt, max_volt; 175 int num, ret; 176 177 cpu_dev = get_cpu_device(0); 178 if (!cpu_dev) { 179 pr_err("failed to get cpu0 device\n"); 180 return -ENODEV; 181 } 182 183 np = of_node_get(cpu_dev->of_node); 184 if (!np) { 185 dev_err(cpu_dev, "failed to find cpu0 node\n"); 186 return -ENOENT; 187 } 188 189 arm_clk = devm_clk_get(cpu_dev, "arm"); 190 pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys"); 191 pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw"); 192 step_clk = devm_clk_get(cpu_dev, "step"); 193 pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m"); 194 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || 195 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { 196 dev_err(cpu_dev, "failed to get clocks\n"); 197 ret = -ENOENT; 198 goto put_node; 199 } 200 201 arm_reg = devm_regulator_get(cpu_dev, "arm"); 202 pu_reg = devm_regulator_get(cpu_dev, "pu"); 203 soc_reg = devm_regulator_get(cpu_dev, "soc"); 204 if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) { 205 dev_err(cpu_dev, "failed to get regulators\n"); 206 ret = -ENOENT; 207 goto put_node; 208 } 209 210 /* We expect an OPP table supplied by platform */ 211 num = dev_pm_opp_get_opp_count(cpu_dev); 212 if (num < 0) { 213 ret = num; 214 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 215 goto put_node; 216 } 217 218 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 219 if (ret) { 220 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 221 goto put_node; 222 } 223 224 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 225 transition_latency = CPUFREQ_ETERNAL; 226 227 /* 228 * OPP is maintained in order of increasing frequency, and 229 * freq_table initialised from OPP is therefore sorted in the 230 * same order. 231 */ 232 rcu_read_lock(); 233 opp = dev_pm_opp_find_freq_exact(cpu_dev, 234 freq_table[0].frequency * 1000, true); 235 min_volt = dev_pm_opp_get_voltage(opp); 236 opp = dev_pm_opp_find_freq_exact(cpu_dev, 237 freq_table[--num].frequency * 1000, true); 238 max_volt = dev_pm_opp_get_voltage(opp); 239 rcu_read_unlock(); 240 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 241 if (ret > 0) 242 transition_latency += ret * 1000; 243 244 /* Count vddpu and vddsoc latency in for 1.2 GHz support */ 245 if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) { 246 ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL, 247 PU_SOC_VOLTAGE_HIGH); 248 if (ret > 0) 249 transition_latency += ret * 1000; 250 ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL, 251 PU_SOC_VOLTAGE_HIGH); 252 if (ret > 0) 253 transition_latency += ret * 1000; 254 } 255 256 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 257 if (ret) { 258 dev_err(cpu_dev, "failed register driver: %d\n", ret); 259 goto free_freq_table; 260 } 261 262 of_node_put(np); 263 return 0; 264 265 free_freq_table: 266 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 267 put_node: 268 of_node_put(np); 269 return ret; 270 } 271 272 static int imx6q_cpufreq_remove(struct platform_device *pdev) 273 { 274 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 275 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 276 277 return 0; 278 } 279 280 static struct platform_driver imx6q_cpufreq_platdrv = { 281 .driver = { 282 .name = "imx6q-cpufreq", 283 .owner = THIS_MODULE, 284 }, 285 .probe = imx6q_cpufreq_probe, 286 .remove = imx6q_cpufreq_remove, 287 }; 288 module_platform_driver(imx6q_cpufreq_platdrv); 289 290 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 291 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 292 MODULE_LICENSE("GPL"); 293