1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pm_opp.h> 16 #include <linux/platform_device.h> 17 #include <linux/regulator/consumer.h> 18 19 #define PU_SOC_VOLTAGE_NORMAL 1250000 20 #define PU_SOC_VOLTAGE_HIGH 1275000 21 #define FREQ_1P2_GHZ 1200000000 22 23 static struct regulator *arm_reg; 24 static struct regulator *pu_reg; 25 static struct regulator *soc_reg; 26 27 static struct clk *arm_clk; 28 static struct clk *pll1_sys_clk; 29 static struct clk *pll1_sw_clk; 30 static struct clk *step_clk; 31 static struct clk *pll2_pfd2_396m_clk; 32 33 /* clk used by i.MX6UL */ 34 static struct clk *pll2_bus_clk; 35 static struct clk *secondary_sel_clk; 36 37 static struct device *cpu_dev; 38 static bool free_opp; 39 static struct cpufreq_frequency_table *freq_table; 40 static unsigned int transition_latency; 41 42 static u32 *imx6_soc_volt; 43 static u32 soc_opp_count; 44 45 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 46 { 47 struct dev_pm_opp *opp; 48 unsigned long freq_hz, volt, volt_old; 49 unsigned int old_freq, new_freq; 50 int ret; 51 52 new_freq = freq_table[index].frequency; 53 freq_hz = new_freq * 1000; 54 old_freq = clk_get_rate(arm_clk) / 1000; 55 56 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 57 if (IS_ERR(opp)) { 58 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 59 return PTR_ERR(opp); 60 } 61 62 volt = dev_pm_opp_get_voltage(opp); 63 dev_pm_opp_put(opp); 64 65 volt_old = regulator_get_voltage(arm_reg); 66 67 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 68 old_freq / 1000, volt_old / 1000, 69 new_freq / 1000, volt / 1000); 70 71 /* scaling up? scale voltage before frequency */ 72 if (new_freq > old_freq) { 73 if (!IS_ERR(pu_reg)) { 74 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 75 if (ret) { 76 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 77 return ret; 78 } 79 } 80 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 81 if (ret) { 82 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 83 return ret; 84 } 85 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 86 if (ret) { 87 dev_err(cpu_dev, 88 "failed to scale vddarm up: %d\n", ret); 89 return ret; 90 } 91 } 92 93 /* 94 * The setpoints are selected per PLL/PDF frequencies, so we need to 95 * reprogram PLL for frequency scaling. The procedure of reprogramming 96 * PLL1 is as below. 97 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change 98 * flow is slightly different from other i.MX6 OSC. 99 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: 100 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 101 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 102 * - Disable pll2_pfd2_396m_clk 103 */ 104 if (of_machine_is_compatible("fsl,imx6ul") || 105 of_machine_is_compatible("fsl,imx6ull")) { 106 /* 107 * When changing pll1_sw_clk's parent to pll1_sys_clk, 108 * CPU may run at higher than 528MHz, this will lead to 109 * the system unstable if the voltage is lower than the 110 * voltage of 528MHz, so lower the CPU frequency to one 111 * half before changing CPU frequency. 112 */ 113 clk_set_rate(arm_clk, (old_freq >> 1) * 1000); 114 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 115 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) 116 clk_set_parent(secondary_sel_clk, pll2_bus_clk); 117 else 118 clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); 119 clk_set_parent(step_clk, secondary_sel_clk); 120 clk_set_parent(pll1_sw_clk, step_clk); 121 } else { 122 clk_set_parent(step_clk, pll2_pfd2_396m_clk); 123 clk_set_parent(pll1_sw_clk, step_clk); 124 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { 125 clk_set_rate(pll1_sys_clk, new_freq * 1000); 126 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 127 } 128 } 129 130 /* Ensure the arm clock divider is what we expect */ 131 ret = clk_set_rate(arm_clk, new_freq * 1000); 132 if (ret) { 133 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 134 regulator_set_voltage_tol(arm_reg, volt_old, 0); 135 return ret; 136 } 137 138 /* scaling down? scale voltage after frequency */ 139 if (new_freq < old_freq) { 140 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 141 if (ret) { 142 dev_warn(cpu_dev, 143 "failed to scale vddarm down: %d\n", ret); 144 ret = 0; 145 } 146 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 147 if (ret) { 148 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 149 ret = 0; 150 } 151 if (!IS_ERR(pu_reg)) { 152 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 153 if (ret) { 154 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 155 ret = 0; 156 } 157 } 158 } 159 160 return 0; 161 } 162 163 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 164 { 165 int ret; 166 167 policy->clk = arm_clk; 168 ret = cpufreq_generic_init(policy, freq_table, transition_latency); 169 policy->suspend_freq = policy->max; 170 171 return ret; 172 } 173 174 static struct cpufreq_driver imx6q_cpufreq_driver = { 175 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 176 .verify = cpufreq_generic_frequency_table_verify, 177 .target_index = imx6q_set_target, 178 .get = cpufreq_generic_get, 179 .init = imx6q_cpufreq_init, 180 .name = "imx6q-cpufreq", 181 .attr = cpufreq_generic_attr, 182 .suspend = cpufreq_generic_suspend, 183 }; 184 185 static int imx6q_cpufreq_probe(struct platform_device *pdev) 186 { 187 struct device_node *np; 188 struct dev_pm_opp *opp; 189 unsigned long min_volt, max_volt; 190 int num, ret; 191 const struct property *prop; 192 const __be32 *val; 193 u32 nr, i, j; 194 195 cpu_dev = get_cpu_device(0); 196 if (!cpu_dev) { 197 pr_err("failed to get cpu0 device\n"); 198 return -ENODEV; 199 } 200 201 np = of_node_get(cpu_dev->of_node); 202 if (!np) { 203 dev_err(cpu_dev, "failed to find cpu0 node\n"); 204 return -ENOENT; 205 } 206 207 arm_clk = clk_get(cpu_dev, "arm"); 208 pll1_sys_clk = clk_get(cpu_dev, "pll1_sys"); 209 pll1_sw_clk = clk_get(cpu_dev, "pll1_sw"); 210 step_clk = clk_get(cpu_dev, "step"); 211 pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m"); 212 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || 213 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { 214 dev_err(cpu_dev, "failed to get clocks\n"); 215 ret = -ENOENT; 216 goto put_clk; 217 } 218 219 if (of_machine_is_compatible("fsl,imx6ul") || 220 of_machine_is_compatible("fsl,imx6ull")) { 221 pll2_bus_clk = clk_get(cpu_dev, "pll2_bus"); 222 secondary_sel_clk = clk_get(cpu_dev, "secondary_sel"); 223 if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) { 224 dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n"); 225 ret = -ENOENT; 226 goto put_clk; 227 } 228 } 229 230 arm_reg = regulator_get(cpu_dev, "arm"); 231 pu_reg = regulator_get_optional(cpu_dev, "pu"); 232 soc_reg = regulator_get(cpu_dev, "soc"); 233 if (PTR_ERR(arm_reg) == -EPROBE_DEFER || 234 PTR_ERR(soc_reg) == -EPROBE_DEFER || 235 PTR_ERR(pu_reg) == -EPROBE_DEFER) { 236 ret = -EPROBE_DEFER; 237 dev_dbg(cpu_dev, "regulators not ready, defer\n"); 238 goto put_reg; 239 } 240 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { 241 dev_err(cpu_dev, "failed to get regulators\n"); 242 ret = -ENOENT; 243 goto put_reg; 244 } 245 246 /* 247 * We expect an OPP table supplied by platform. 248 * Just, incase the platform did not supply the OPP 249 * table, it will try to get it. 250 */ 251 num = dev_pm_opp_get_opp_count(cpu_dev); 252 if (num < 0) { 253 ret = dev_pm_opp_of_add_table(cpu_dev); 254 if (ret < 0) { 255 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 256 goto put_reg; 257 } 258 259 /* Because we have added the OPPs here, we must free them */ 260 free_opp = true; 261 262 num = dev_pm_opp_get_opp_count(cpu_dev); 263 if (num < 0) { 264 ret = num; 265 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 266 goto out_free_opp; 267 } 268 } 269 270 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 271 if (ret) { 272 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 273 goto out_free_opp; 274 } 275 276 /* Make imx6_soc_volt array's size same as arm opp number */ 277 imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL); 278 if (imx6_soc_volt == NULL) { 279 ret = -ENOMEM; 280 goto free_freq_table; 281 } 282 283 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 284 if (!prop || !prop->value) 285 goto soc_opp_out; 286 287 /* 288 * Each OPP is a set of tuples consisting of frequency and 289 * voltage like <freq-kHz vol-uV>. 290 */ 291 nr = prop->length / sizeof(u32); 292 if (nr % 2 || (nr / 2) < num) 293 goto soc_opp_out; 294 295 for (j = 0; j < num; j++) { 296 val = prop->value; 297 for (i = 0; i < nr / 2; i++) { 298 unsigned long freq = be32_to_cpup(val++); 299 unsigned long volt = be32_to_cpup(val++); 300 if (freq_table[j].frequency == freq) { 301 imx6_soc_volt[soc_opp_count++] = volt; 302 break; 303 } 304 } 305 } 306 307 soc_opp_out: 308 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 309 if (soc_opp_count != num) { 310 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 311 for (j = 0; j < num; j++) 312 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 313 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 314 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 315 } 316 317 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 318 transition_latency = CPUFREQ_ETERNAL; 319 320 /* 321 * Calculate the ramp time for max voltage change in the 322 * VDDSOC and VDDPU regulators. 323 */ 324 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 325 if (ret > 0) 326 transition_latency += ret * 1000; 327 if (!IS_ERR(pu_reg)) { 328 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 329 if (ret > 0) 330 transition_latency += ret * 1000; 331 } 332 333 /* 334 * OPP is maintained in order of increasing frequency, and 335 * freq_table initialised from OPP is therefore sorted in the 336 * same order. 337 */ 338 opp = dev_pm_opp_find_freq_exact(cpu_dev, 339 freq_table[0].frequency * 1000, true); 340 min_volt = dev_pm_opp_get_voltage(opp); 341 dev_pm_opp_put(opp); 342 opp = dev_pm_opp_find_freq_exact(cpu_dev, 343 freq_table[--num].frequency * 1000, true); 344 max_volt = dev_pm_opp_get_voltage(opp); 345 dev_pm_opp_put(opp); 346 347 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 348 if (ret > 0) 349 transition_latency += ret * 1000; 350 351 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 352 if (ret) { 353 dev_err(cpu_dev, "failed register driver: %d\n", ret); 354 goto free_freq_table; 355 } 356 357 of_node_put(np); 358 return 0; 359 360 free_freq_table: 361 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 362 out_free_opp: 363 if (free_opp) 364 dev_pm_opp_of_remove_table(cpu_dev); 365 put_reg: 366 if (!IS_ERR(arm_reg)) 367 regulator_put(arm_reg); 368 if (!IS_ERR(pu_reg)) 369 regulator_put(pu_reg); 370 if (!IS_ERR(soc_reg)) 371 regulator_put(soc_reg); 372 put_clk: 373 if (!IS_ERR(arm_clk)) 374 clk_put(arm_clk); 375 if (!IS_ERR(pll1_sys_clk)) 376 clk_put(pll1_sys_clk); 377 if (!IS_ERR(pll1_sw_clk)) 378 clk_put(pll1_sw_clk); 379 if (!IS_ERR(step_clk)) 380 clk_put(step_clk); 381 if (!IS_ERR(pll2_pfd2_396m_clk)) 382 clk_put(pll2_pfd2_396m_clk); 383 if (!IS_ERR(pll2_bus_clk)) 384 clk_put(pll2_bus_clk); 385 if (!IS_ERR(secondary_sel_clk)) 386 clk_put(secondary_sel_clk); 387 of_node_put(np); 388 return ret; 389 } 390 391 static int imx6q_cpufreq_remove(struct platform_device *pdev) 392 { 393 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 394 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 395 if (free_opp) 396 dev_pm_opp_of_remove_table(cpu_dev); 397 regulator_put(arm_reg); 398 if (!IS_ERR(pu_reg)) 399 regulator_put(pu_reg); 400 regulator_put(soc_reg); 401 clk_put(arm_clk); 402 clk_put(pll1_sys_clk); 403 clk_put(pll1_sw_clk); 404 clk_put(step_clk); 405 clk_put(pll2_pfd2_396m_clk); 406 clk_put(pll2_bus_clk); 407 clk_put(secondary_sel_clk); 408 409 return 0; 410 } 411 412 static struct platform_driver imx6q_cpufreq_platdrv = { 413 .driver = { 414 .name = "imx6q-cpufreq", 415 }, 416 .probe = imx6q_cpufreq_probe, 417 .remove = imx6q_cpufreq_remove, 418 }; 419 module_platform_driver(imx6q_cpufreq_platdrv); 420 421 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 422 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 423 MODULE_LICENSE("GPL"); 424