1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/pm_opp.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 20 #define PU_SOC_VOLTAGE_NORMAL 1250000 21 #define PU_SOC_VOLTAGE_HIGH 1275000 22 #define FREQ_1P2_GHZ 1200000000 23 24 static struct regulator *arm_reg; 25 static struct regulator *pu_reg; 26 static struct regulator *soc_reg; 27 28 static struct clk *arm_clk; 29 static struct clk *pll1_sys_clk; 30 static struct clk *pll1_sw_clk; 31 static struct clk *step_clk; 32 static struct clk *pll2_pfd2_396m_clk; 33 34 static struct device *cpu_dev; 35 static struct cpufreq_frequency_table *freq_table; 36 static unsigned int transition_latency; 37 38 static u32 *imx6_soc_volt; 39 static u32 soc_opp_count; 40 41 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 42 { 43 struct dev_pm_opp *opp; 44 unsigned long freq_hz, volt, volt_old; 45 unsigned int old_freq, new_freq; 46 int ret; 47 48 new_freq = freq_table[index].frequency; 49 freq_hz = new_freq * 1000; 50 old_freq = clk_get_rate(arm_clk) / 1000; 51 52 rcu_read_lock(); 53 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 54 if (IS_ERR(opp)) { 55 rcu_read_unlock(); 56 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 57 return PTR_ERR(opp); 58 } 59 60 volt = dev_pm_opp_get_voltage(opp); 61 rcu_read_unlock(); 62 volt_old = regulator_get_voltage(arm_reg); 63 64 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 65 old_freq / 1000, volt_old / 1000, 66 new_freq / 1000, volt / 1000); 67 68 /* scaling up? scale voltage before frequency */ 69 if (new_freq > old_freq) { 70 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 71 if (ret) { 72 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 73 return ret; 74 } 75 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 76 if (ret) { 77 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 78 return ret; 79 } 80 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 81 if (ret) { 82 dev_err(cpu_dev, 83 "failed to scale vddarm up: %d\n", ret); 84 return ret; 85 } 86 } 87 88 /* 89 * The setpoints are selected per PLL/PDF frequencies, so we need to 90 * reprogram PLL for frequency scaling. The procedure of reprogramming 91 * PLL1 is as below. 92 * 93 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 94 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 95 * - Disable pll2_pfd2_396m_clk 96 */ 97 clk_set_parent(step_clk, pll2_pfd2_396m_clk); 98 clk_set_parent(pll1_sw_clk, step_clk); 99 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { 100 clk_set_rate(pll1_sys_clk, new_freq * 1000); 101 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 102 } 103 104 /* Ensure the arm clock divider is what we expect */ 105 ret = clk_set_rate(arm_clk, new_freq * 1000); 106 if (ret) { 107 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 108 regulator_set_voltage_tol(arm_reg, volt_old, 0); 109 return ret; 110 } 111 112 /* scaling down? scale voltage after frequency */ 113 if (new_freq < old_freq) { 114 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 115 if (ret) { 116 dev_warn(cpu_dev, 117 "failed to scale vddarm down: %d\n", ret); 118 ret = 0; 119 } 120 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 121 if (ret) { 122 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 123 ret = 0; 124 } 125 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 126 if (ret) { 127 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 128 ret = 0; 129 } 130 } 131 132 return 0; 133 } 134 135 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 136 { 137 policy->clk = arm_clk; 138 return cpufreq_generic_init(policy, freq_table, transition_latency); 139 } 140 141 static struct cpufreq_driver imx6q_cpufreq_driver = { 142 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 143 .verify = cpufreq_generic_frequency_table_verify, 144 .target_index = imx6q_set_target, 145 .get = cpufreq_generic_get, 146 .init = imx6q_cpufreq_init, 147 .exit = cpufreq_generic_exit, 148 .name = "imx6q-cpufreq", 149 .attr = cpufreq_generic_attr, 150 }; 151 152 static int imx6q_cpufreq_probe(struct platform_device *pdev) 153 { 154 struct device_node *np; 155 struct dev_pm_opp *opp; 156 unsigned long min_volt, max_volt; 157 int num, ret; 158 const struct property *prop; 159 const __be32 *val; 160 u32 nr, i, j; 161 162 cpu_dev = get_cpu_device(0); 163 if (!cpu_dev) { 164 pr_err("failed to get cpu0 device\n"); 165 return -ENODEV; 166 } 167 168 np = of_node_get(cpu_dev->of_node); 169 if (!np) { 170 dev_err(cpu_dev, "failed to find cpu0 node\n"); 171 return -ENOENT; 172 } 173 174 arm_clk = devm_clk_get(cpu_dev, "arm"); 175 pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys"); 176 pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw"); 177 step_clk = devm_clk_get(cpu_dev, "step"); 178 pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m"); 179 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || 180 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { 181 dev_err(cpu_dev, "failed to get clocks\n"); 182 ret = -ENOENT; 183 goto put_node; 184 } 185 186 arm_reg = devm_regulator_get(cpu_dev, "arm"); 187 pu_reg = devm_regulator_get(cpu_dev, "pu"); 188 soc_reg = devm_regulator_get(cpu_dev, "soc"); 189 if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) { 190 dev_err(cpu_dev, "failed to get regulators\n"); 191 ret = -ENOENT; 192 goto put_node; 193 } 194 195 /* 196 * We expect an OPP table supplied by platform. 197 * Just, incase the platform did not supply the OPP 198 * table, it will try to get it. 199 */ 200 num = dev_pm_opp_get_opp_count(cpu_dev); 201 if (num < 0) { 202 ret = of_init_opp_table(cpu_dev); 203 if (ret < 0) { 204 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 205 goto put_node; 206 } 207 208 num = dev_pm_opp_get_opp_count(cpu_dev); 209 if (num < 0) { 210 ret = num; 211 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 212 goto put_node; 213 } 214 } 215 216 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 217 if (ret) { 218 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 219 goto put_node; 220 } 221 222 /* Make imx6_soc_volt array's size same as arm opp number */ 223 imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL); 224 if (imx6_soc_volt == NULL) { 225 ret = -ENOMEM; 226 goto free_freq_table; 227 } 228 229 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 230 if (!prop || !prop->value) 231 goto soc_opp_out; 232 233 /* 234 * Each OPP is a set of tuples consisting of frequency and 235 * voltage like <freq-kHz vol-uV>. 236 */ 237 nr = prop->length / sizeof(u32); 238 if (nr % 2 || (nr / 2) < num) 239 goto soc_opp_out; 240 241 for (j = 0; j < num; j++) { 242 val = prop->value; 243 for (i = 0; i < nr / 2; i++) { 244 unsigned long freq = be32_to_cpup(val++); 245 unsigned long volt = be32_to_cpup(val++); 246 if (freq_table[j].frequency == freq) { 247 imx6_soc_volt[soc_opp_count++] = volt; 248 break; 249 } 250 } 251 } 252 253 soc_opp_out: 254 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 255 if (soc_opp_count != num) { 256 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 257 for (j = 0; j < num; j++) 258 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 259 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 260 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 261 } 262 263 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 264 transition_latency = CPUFREQ_ETERNAL; 265 266 /* 267 * Calculate the ramp time for max voltage change in the 268 * VDDSOC and VDDPU regulators. 269 */ 270 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 271 if (ret > 0) 272 transition_latency += ret * 1000; 273 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 274 if (ret > 0) 275 transition_latency += ret * 1000; 276 277 /* 278 * OPP is maintained in order of increasing frequency, and 279 * freq_table initialised from OPP is therefore sorted in the 280 * same order. 281 */ 282 rcu_read_lock(); 283 opp = dev_pm_opp_find_freq_exact(cpu_dev, 284 freq_table[0].frequency * 1000, true); 285 min_volt = dev_pm_opp_get_voltage(opp); 286 opp = dev_pm_opp_find_freq_exact(cpu_dev, 287 freq_table[--num].frequency * 1000, true); 288 max_volt = dev_pm_opp_get_voltage(opp); 289 rcu_read_unlock(); 290 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 291 if (ret > 0) 292 transition_latency += ret * 1000; 293 294 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 295 if (ret) { 296 dev_err(cpu_dev, "failed register driver: %d\n", ret); 297 goto free_freq_table; 298 } 299 300 of_node_put(np); 301 return 0; 302 303 free_freq_table: 304 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 305 put_node: 306 of_node_put(np); 307 return ret; 308 } 309 310 static int imx6q_cpufreq_remove(struct platform_device *pdev) 311 { 312 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 313 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 314 315 return 0; 316 } 317 318 static struct platform_driver imx6q_cpufreq_platdrv = { 319 .driver = { 320 .name = "imx6q-cpufreq", 321 .owner = THIS_MODULE, 322 }, 323 .probe = imx6q_cpufreq_probe, 324 .remove = imx6q_cpufreq_remove, 325 }; 326 module_platform_driver(imx6q_cpufreq_platdrv); 327 328 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 329 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 330 MODULE_LICENSE("GPL"); 331