1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/opp.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 20 #define PU_SOC_VOLTAGE_NORMAL 1250000 21 #define PU_SOC_VOLTAGE_HIGH 1275000 22 #define FREQ_1P2_GHZ 1200000000 23 24 static struct regulator *arm_reg; 25 static struct regulator *pu_reg; 26 static struct regulator *soc_reg; 27 28 static struct clk *arm_clk; 29 static struct clk *pll1_sys_clk; 30 static struct clk *pll1_sw_clk; 31 static struct clk *step_clk; 32 static struct clk *pll2_pfd2_396m_clk; 33 34 static struct device *cpu_dev; 35 static struct cpufreq_frequency_table *freq_table; 36 static unsigned int transition_latency; 37 38 static int imx6q_verify_speed(struct cpufreq_policy *policy) 39 { 40 return cpufreq_frequency_table_verify(policy, freq_table); 41 } 42 43 static unsigned int imx6q_get_speed(unsigned int cpu) 44 { 45 return clk_get_rate(arm_clk) / 1000; 46 } 47 48 static int imx6q_set_target(struct cpufreq_policy *policy, 49 unsigned int target_freq, unsigned int relation) 50 { 51 struct cpufreq_freqs freqs; 52 struct opp *opp; 53 unsigned long freq_hz, volt, volt_old; 54 unsigned int index; 55 int ret; 56 57 ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, 58 relation, &index); 59 if (ret) { 60 dev_err(cpu_dev, "failed to match target frequency %d: %d\n", 61 target_freq, ret); 62 return ret; 63 } 64 65 freqs.new = freq_table[index].frequency; 66 freq_hz = freqs.new * 1000; 67 freqs.old = clk_get_rate(arm_clk) / 1000; 68 69 if (freqs.old == freqs.new) 70 return 0; 71 72 rcu_read_lock(); 73 opp = opp_find_freq_ceil(cpu_dev, &freq_hz); 74 if (IS_ERR(opp)) { 75 rcu_read_unlock(); 76 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 77 return PTR_ERR(opp); 78 } 79 80 volt = opp_get_voltage(opp); 81 rcu_read_unlock(); 82 volt_old = regulator_get_voltage(arm_reg); 83 84 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 85 freqs.old / 1000, volt_old / 1000, 86 freqs.new / 1000, volt / 1000); 87 88 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); 89 90 /* scaling up? scale voltage before frequency */ 91 if (freqs.new > freqs.old) { 92 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 93 if (ret) { 94 dev_err(cpu_dev, 95 "failed to scale vddarm up: %d\n", ret); 96 freqs.new = freqs.old; 97 goto post_notify; 98 } 99 100 /* 101 * Need to increase vddpu and vddsoc for safety 102 * if we are about to run at 1.2 GHz. 103 */ 104 if (freqs.new == FREQ_1P2_GHZ / 1000) { 105 regulator_set_voltage_tol(pu_reg, 106 PU_SOC_VOLTAGE_HIGH, 0); 107 regulator_set_voltage_tol(soc_reg, 108 PU_SOC_VOLTAGE_HIGH, 0); 109 } 110 } 111 112 /* 113 * The setpoints are selected per PLL/PDF frequencies, so we need to 114 * reprogram PLL for frequency scaling. The procedure of reprogramming 115 * PLL1 is as below. 116 * 117 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 118 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 119 * - Disable pll2_pfd2_396m_clk 120 */ 121 clk_set_parent(step_clk, pll2_pfd2_396m_clk); 122 clk_set_parent(pll1_sw_clk, step_clk); 123 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { 124 clk_set_rate(pll1_sys_clk, freqs.new * 1000); 125 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 126 } 127 128 /* Ensure the arm clock divider is what we expect */ 129 ret = clk_set_rate(arm_clk, freqs.new * 1000); 130 if (ret) { 131 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 132 regulator_set_voltage_tol(arm_reg, volt_old, 0); 133 freqs.new = freqs.old; 134 goto post_notify; 135 } 136 137 /* scaling down? scale voltage after frequency */ 138 if (freqs.new < freqs.old) { 139 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 140 if (ret) { 141 dev_warn(cpu_dev, 142 "failed to scale vddarm down: %d\n", ret); 143 ret = 0; 144 } 145 146 if (freqs.old == FREQ_1P2_GHZ / 1000) { 147 regulator_set_voltage_tol(pu_reg, 148 PU_SOC_VOLTAGE_NORMAL, 0); 149 regulator_set_voltage_tol(soc_reg, 150 PU_SOC_VOLTAGE_NORMAL, 0); 151 } 152 } 153 154 post_notify: 155 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); 156 157 return ret; 158 } 159 160 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 161 { 162 int ret; 163 164 ret = cpufreq_frequency_table_cpuinfo(policy, freq_table); 165 if (ret) { 166 dev_err(cpu_dev, "invalid frequency table: %d\n", ret); 167 return ret; 168 } 169 170 policy->cpuinfo.transition_latency = transition_latency; 171 policy->cur = clk_get_rate(arm_clk) / 1000; 172 cpumask_setall(policy->cpus); 173 cpufreq_frequency_table_get_attr(freq_table, policy->cpu); 174 175 return 0; 176 } 177 178 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy) 179 { 180 cpufreq_frequency_table_put_attr(policy->cpu); 181 return 0; 182 } 183 184 static struct freq_attr *imx6q_cpufreq_attr[] = { 185 &cpufreq_freq_attr_scaling_available_freqs, 186 NULL, 187 }; 188 189 static struct cpufreq_driver imx6q_cpufreq_driver = { 190 .verify = imx6q_verify_speed, 191 .target = imx6q_set_target, 192 .get = imx6q_get_speed, 193 .init = imx6q_cpufreq_init, 194 .exit = imx6q_cpufreq_exit, 195 .name = "imx6q-cpufreq", 196 .attr = imx6q_cpufreq_attr, 197 }; 198 199 static int imx6q_cpufreq_probe(struct platform_device *pdev) 200 { 201 struct device_node *np; 202 struct opp *opp; 203 unsigned long min_volt, max_volt; 204 int num, ret; 205 206 cpu_dev = get_cpu_device(0); 207 if (!cpu_dev) { 208 pr_err("failed to get cpu0 device\n"); 209 return -ENODEV; 210 } 211 212 np = of_node_get(cpu_dev->of_node); 213 if (!np) { 214 dev_err(cpu_dev, "failed to find cpu0 node\n"); 215 return -ENOENT; 216 } 217 218 arm_clk = devm_clk_get(cpu_dev, "arm"); 219 pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys"); 220 pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw"); 221 step_clk = devm_clk_get(cpu_dev, "step"); 222 pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m"); 223 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || 224 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { 225 dev_err(cpu_dev, "failed to get clocks\n"); 226 ret = -ENOENT; 227 goto put_node; 228 } 229 230 arm_reg = devm_regulator_get(cpu_dev, "arm"); 231 pu_reg = devm_regulator_get(cpu_dev, "pu"); 232 soc_reg = devm_regulator_get(cpu_dev, "soc"); 233 if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) { 234 dev_err(cpu_dev, "failed to get regulators\n"); 235 ret = -ENOENT; 236 goto put_node; 237 } 238 239 /* We expect an OPP table supplied by platform */ 240 num = opp_get_opp_count(cpu_dev); 241 if (num < 0) { 242 ret = num; 243 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 244 goto put_node; 245 } 246 247 ret = opp_init_cpufreq_table(cpu_dev, &freq_table); 248 if (ret) { 249 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 250 goto put_node; 251 } 252 253 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 254 transition_latency = CPUFREQ_ETERNAL; 255 256 /* 257 * OPP is maintained in order of increasing frequency, and 258 * freq_table initialised from OPP is therefore sorted in the 259 * same order. 260 */ 261 rcu_read_lock(); 262 opp = opp_find_freq_exact(cpu_dev, 263 freq_table[0].frequency * 1000, true); 264 min_volt = opp_get_voltage(opp); 265 opp = opp_find_freq_exact(cpu_dev, 266 freq_table[--num].frequency * 1000, true); 267 max_volt = opp_get_voltage(opp); 268 rcu_read_unlock(); 269 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 270 if (ret > 0) 271 transition_latency += ret * 1000; 272 273 /* Count vddpu and vddsoc latency in for 1.2 GHz support */ 274 if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) { 275 ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL, 276 PU_SOC_VOLTAGE_HIGH); 277 if (ret > 0) 278 transition_latency += ret * 1000; 279 ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL, 280 PU_SOC_VOLTAGE_HIGH); 281 if (ret > 0) 282 transition_latency += ret * 1000; 283 } 284 285 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 286 if (ret) { 287 dev_err(cpu_dev, "failed register driver: %d\n", ret); 288 goto free_freq_table; 289 } 290 291 of_node_put(np); 292 return 0; 293 294 free_freq_table: 295 opp_free_cpufreq_table(cpu_dev, &freq_table); 296 put_node: 297 of_node_put(np); 298 return ret; 299 } 300 301 static int imx6q_cpufreq_remove(struct platform_device *pdev) 302 { 303 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 304 opp_free_cpufreq_table(cpu_dev, &freq_table); 305 306 return 0; 307 } 308 309 static struct platform_driver imx6q_cpufreq_platdrv = { 310 .driver = { 311 .name = "imx6q-cpufreq", 312 .owner = THIS_MODULE, 313 }, 314 .probe = imx6q_cpufreq_probe, 315 .remove = imx6q_cpufreq_remove, 316 }; 317 module_platform_driver(imx6q_cpufreq_platdrv); 318 319 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 320 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 321 MODULE_LICENSE("GPL"); 322