1 /* 2 * TI composite clock support 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * Tero Kristo <t-kristo@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk-provider.h> 19 #include <linux/slab.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/clk/ti.h> 24 #include <linux/list.h> 25 26 #include "clock.h" 27 28 #undef pr_fmt 29 #define pr_fmt(fmt) "%s: " fmt, __func__ 30 31 static unsigned long ti_composite_recalc_rate(struct clk_hw *hw, 32 unsigned long parent_rate) 33 { 34 return ti_clk_divider_ops.recalc_rate(hw, parent_rate); 35 } 36 37 static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate, 38 unsigned long *prate) 39 { 40 return -EINVAL; 41 } 42 43 static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate, 44 unsigned long parent_rate) 45 { 46 return -EINVAL; 47 } 48 49 static const struct clk_ops ti_composite_divider_ops = { 50 .recalc_rate = &ti_composite_recalc_rate, 51 .round_rate = &ti_composite_round_rate, 52 .set_rate = &ti_composite_set_rate, 53 }; 54 55 static const struct clk_ops ti_composite_gate_ops = { 56 .enable = &omap2_dflt_clk_enable, 57 .disable = &omap2_dflt_clk_disable, 58 .is_enabled = &omap2_dflt_clk_is_enabled, 59 }; 60 61 struct component_clk { 62 int num_parents; 63 const char **parent_names; 64 struct device_node *node; 65 int type; 66 struct clk_hw *hw; 67 struct list_head link; 68 }; 69 70 static const char * const component_clk_types[] __initconst = { 71 "gate", "divider", "mux" 72 }; 73 74 static LIST_HEAD(component_clks); 75 76 static struct device_node *_get_component_node(struct device_node *node, int i) 77 { 78 int rc; 79 struct of_phandle_args clkspec; 80 81 rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i, 82 &clkspec); 83 if (rc) 84 return NULL; 85 86 return clkspec.np; 87 } 88 89 static struct component_clk *_lookup_component(struct device_node *node) 90 { 91 struct component_clk *comp; 92 93 list_for_each_entry(comp, &component_clks, link) { 94 if (comp->node == node) 95 return comp; 96 } 97 return NULL; 98 } 99 100 struct clk_hw_omap_comp { 101 struct clk_hw hw; 102 struct device_node *comp_nodes[CLK_COMPONENT_TYPE_MAX]; 103 struct component_clk *comp_clks[CLK_COMPONENT_TYPE_MAX]; 104 }; 105 106 static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx) 107 { 108 if (!clk) 109 return NULL; 110 111 if (!clk->comp_clks[idx]) 112 return NULL; 113 114 return clk->comp_clks[idx]->hw; 115 } 116 117 #define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw) 118 119 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS) 120 struct clk *ti_clk_register_composite(struct ti_clk *setup) 121 { 122 struct ti_clk_composite *comp; 123 struct clk_hw *gate; 124 struct clk_hw *mux; 125 struct clk_hw *div; 126 int num_parents = 1; 127 const char * const *parent_names = NULL; 128 struct clk *clk; 129 int ret; 130 131 comp = setup->data; 132 133 div = ti_clk_build_component_div(comp->divider); 134 gate = ti_clk_build_component_gate(comp->gate); 135 mux = ti_clk_build_component_mux(comp->mux); 136 137 if (div) 138 parent_names = &comp->divider->parent; 139 140 if (gate) 141 parent_names = &comp->gate->parent; 142 143 if (mux) { 144 num_parents = comp->mux->num_parents; 145 parent_names = comp->mux->parents; 146 } 147 148 clk = clk_register_composite(NULL, setup->name, 149 parent_names, num_parents, mux, 150 &ti_clk_mux_ops, div, 151 &ti_composite_divider_ops, gate, 152 &ti_composite_gate_ops, 0); 153 154 ret = ti_clk_add_alias(NULL, clk, setup->name); 155 if (ret) { 156 clk_unregister(clk); 157 return ERR_PTR(ret); 158 } 159 160 return clk; 161 } 162 #endif 163 164 static void __init _register_composite(void *user, 165 struct device_node *node) 166 { 167 struct clk_hw *hw = user; 168 struct clk *clk; 169 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); 170 struct component_clk *comp; 171 int num_parents = 0; 172 const char **parent_names = NULL; 173 int i; 174 int ret; 175 176 /* Check for presence of each component clock */ 177 for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) { 178 if (!cclk->comp_nodes[i]) 179 continue; 180 181 comp = _lookup_component(cclk->comp_nodes[i]); 182 if (!comp) { 183 pr_debug("component %s not ready for %s, retry\n", 184 cclk->comp_nodes[i]->name, node->name); 185 if (!ti_clk_retry_init(node, hw, 186 _register_composite)) 187 return; 188 189 goto cleanup; 190 } 191 if (cclk->comp_clks[comp->type] != NULL) { 192 pr_err("duplicate component types for %s (%s)!\n", 193 node->name, component_clk_types[comp->type]); 194 goto cleanup; 195 } 196 197 cclk->comp_clks[comp->type] = comp; 198 199 /* Mark this node as found */ 200 cclk->comp_nodes[i] = NULL; 201 } 202 203 /* All components exists, proceed with registration */ 204 for (i = CLK_COMPONENT_TYPE_MAX - 1; i >= 0; i--) { 205 comp = cclk->comp_clks[i]; 206 if (!comp) 207 continue; 208 if (comp->num_parents) { 209 num_parents = comp->num_parents; 210 parent_names = comp->parent_names; 211 break; 212 } 213 } 214 215 if (!num_parents) { 216 pr_err("%s: no parents found for %s!\n", __func__, node->name); 217 goto cleanup; 218 } 219 220 clk = clk_register_composite(NULL, node->name, 221 parent_names, num_parents, 222 _get_hw(cclk, CLK_COMPONENT_TYPE_MUX), 223 &ti_clk_mux_ops, 224 _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER), 225 &ti_composite_divider_ops, 226 _get_hw(cclk, CLK_COMPONENT_TYPE_GATE), 227 &ti_composite_gate_ops, 0); 228 229 if (!IS_ERR(clk)) { 230 ret = ti_clk_add_alias(NULL, clk, node->name); 231 if (ret) { 232 clk_unregister(clk); 233 goto cleanup; 234 } 235 of_clk_add_provider(node, of_clk_src_simple_get, clk); 236 } 237 238 cleanup: 239 /* Free component clock list entries */ 240 for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) { 241 if (!cclk->comp_clks[i]) 242 continue; 243 list_del(&cclk->comp_clks[i]->link); 244 kfree(cclk->comp_clks[i]); 245 } 246 247 kfree(cclk); 248 } 249 250 static void __init of_ti_composite_clk_setup(struct device_node *node) 251 { 252 unsigned int num_clks; 253 int i; 254 struct clk_hw_omap_comp *cclk; 255 256 /* Number of component clocks to be put inside this clock */ 257 num_clks = of_clk_get_parent_count(node); 258 259 if (!num_clks) { 260 pr_err("composite clk %s must have component(s)\n", node->name); 261 return; 262 } 263 264 cclk = kzalloc(sizeof(*cclk), GFP_KERNEL); 265 if (!cclk) 266 return; 267 268 /* Get device node pointers for each component clock */ 269 for (i = 0; i < num_clks; i++) 270 cclk->comp_nodes[i] = _get_component_node(node, i); 271 272 _register_composite(&cclk->hw, node); 273 } 274 CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock", 275 of_ti_composite_clk_setup); 276 277 /** 278 * ti_clk_add_component - add a component clock to the pool 279 * @node: device node of the component clock 280 * @hw: hardware clock definition for the component clock 281 * @type: type of the component clock 282 * 283 * Adds a component clock to the list of available components, so that 284 * it can be registered by a composite clock. 285 */ 286 int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw, 287 int type) 288 { 289 unsigned int num_parents; 290 const char **parent_names; 291 struct component_clk *clk; 292 293 num_parents = of_clk_get_parent_count(node); 294 295 if (!num_parents) { 296 pr_err("component-clock %s must have parent(s)\n", node->name); 297 return -EINVAL; 298 } 299 300 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); 301 if (!parent_names) 302 return -ENOMEM; 303 304 of_clk_parent_fill(node, parent_names, num_parents); 305 306 clk = kzalloc(sizeof(*clk), GFP_KERNEL); 307 if (!clk) { 308 kfree(parent_names); 309 return -ENOMEM; 310 } 311 312 clk->num_parents = num_parents; 313 clk->parent_names = parent_names; 314 clk->hw = hw; 315 clk->node = node; 316 clk->type = type; 317 list_add(&clk->link, &component_clks); 318 319 return 0; 320 } 321