1 /* 2 * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de> 3 * 4 * based on drivers/clk/tegra/clk.h 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 #ifndef __SOCFPGA_CLK_H 18 #define __SOCFPGA_CLK_H 19 20 #include <linux/clk-provider.h> 21 #include <linux/clkdev.h> 22 23 /* Clock Manager offsets */ 24 #define CLKMGR_CTRL 0x0 25 #define CLKMGR_BYPASS 0x4 26 #define CLKMGR_L4SRC 0x70 27 #define CLKMGR_PERPLL_SRC 0xAC 28 29 #define SOCFPGA_MAX_PARENTS 3 30 31 extern void __iomem *clk_mgr_base_addr; 32 33 void __init socfpga_pll_init(struct device_node *node); 34 void __init socfpga_periph_init(struct device_node *node); 35 void __init socfpga_gate_init(struct device_node *node); 36 37 struct socfpga_pll { 38 struct clk_gate hw; 39 }; 40 41 struct socfpga_gate_clk { 42 struct clk_gate hw; 43 char *parent_name; 44 u32 fixed_div; 45 void __iomem *div_reg; 46 u32 width; /* only valid if div_reg != 0 */ 47 u32 shift; /* only valid if div_reg != 0 */ 48 u32 clk_phase[2]; 49 }; 50 51 struct socfpga_periph_clk { 52 struct clk_gate hw; 53 char *parent_name; 54 u32 fixed_div; 55 }; 56 57 #endif /* SOCFPGA_CLK_H */ 58