1 /* 2 * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de> 3 * 4 * based on drivers/clk/tegra/clk.h 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 17 #ifndef __SOCFPGA_CLK_H 18 #define __SOCFPGA_CLK_H 19 20 #include <linux/clk-provider.h> 21 #include <linux/clkdev.h> 22 23 /* Clock Manager offsets */ 24 #define CLKMGR_CTRL 0x0 25 #define CLKMGR_BYPASS 0x4 26 #define CLKMGR_L4SRC 0x70 27 #define CLKMGR_PERPLL_SRC 0xAC 28 29 #define SOCFPGA_MAX_PARENTS 5 30 #define div_mask(width) ((1 << (width)) - 1) 31 32 #define streq(a, b) (strcmp((a), (b)) == 0) 33 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ 34 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) 35 36 extern void __iomem *clk_mgr_base_addr; 37 extern void __iomem *clk_mgr_a10_base_addr; 38 39 void __init socfpga_pll_init(struct device_node *node); 40 void __init socfpga_periph_init(struct device_node *node); 41 void __init socfpga_gate_init(struct device_node *node); 42 void socfpga_a10_pll_init(struct device_node *node); 43 void socfpga_a10_periph_init(struct device_node *node); 44 void socfpga_a10_gate_init(struct device_node *node); 45 46 struct socfpga_pll { 47 struct clk_gate hw; 48 }; 49 50 struct socfpga_gate_clk { 51 struct clk_gate hw; 52 char *parent_name; 53 u32 fixed_div; 54 void __iomem *div_reg; 55 struct regmap *sys_mgr_base_addr; 56 u32 width; /* only valid if div_reg != 0 */ 57 u32 shift; /* only valid if div_reg != 0 */ 58 u32 clk_phase[2]; 59 }; 60 61 struct socfpga_periph_clk { 62 struct clk_gate hw; 63 char *parent_name; 64 u32 fixed_div; 65 void __iomem *div_reg; 66 u32 width; /* only valid if div_reg != 0 */ 67 u32 shift; /* only valid if div_reg != 0 */ 68 }; 69 70 #endif /* SOCFPGA_CLK_H */ 71