1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 16 #include "clk.h" 17 #include <dt-bindings/clock/exynos7-clk.h> 18 19 /* Register Offset definitions for CMU_TOPC (0x10570000) */ 20 #define CC_PLL_LOCK 0x0000 21 #define BUS0_PLL_LOCK 0x0004 22 #define BUS1_DPLL_LOCK 0x0008 23 #define MFC_PLL_LOCK 0x000C 24 #define AUD_PLL_LOCK 0x0010 25 #define CC_PLL_CON0 0x0100 26 #define BUS0_PLL_CON0 0x0110 27 #define BUS1_DPLL_CON0 0x0120 28 #define MFC_PLL_CON0 0x0130 29 #define AUD_PLL_CON0 0x0140 30 #define MUX_SEL_TOPC0 0x0200 31 #define MUX_SEL_TOPC1 0x0204 32 #define MUX_SEL_TOPC2 0x0208 33 #define MUX_SEL_TOPC3 0x020C 34 #define DIV_TOPC0 0x0600 35 #define DIV_TOPC1 0x0604 36 #define DIV_TOPC3 0x060C 37 38 static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { 39 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), 40 FFACTOR(0, "ffac_topc_bus0_pll_div4", 41 "ffac_topc_bus0_pll_div2", 1, 2, 0), 42 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0), 43 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0), 44 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0), 45 }; 46 47 /* List of parent clocks for Muxes in CMU_TOPC */ 48 PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 49 PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 50 PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 51 PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; 52 53 PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc", 54 "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc", 55 "mout_sclk_mfc_pll_cmuc" }; 56 57 PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl", 58 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; 59 PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl", 60 "ffac_topc_bus1_pll_div2"}; 61 PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl", 62 "ffac_topc_cc_pll_div2"}; 63 PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl", 64 "ffac_topc_mfc_pll_div2"}; 65 66 67 PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl", 68 "ffac_topc_bus0_pll_div2"}; 69 70 static unsigned long topc_clk_regs[] __initdata = { 71 CC_PLL_LOCK, 72 BUS0_PLL_LOCK, 73 BUS1_DPLL_LOCK, 74 MFC_PLL_LOCK, 75 AUD_PLL_LOCK, 76 CC_PLL_CON0, 77 BUS0_PLL_CON0, 78 BUS1_DPLL_CON0, 79 MFC_PLL_CON0, 80 AUD_PLL_CON0, 81 MUX_SEL_TOPC0, 82 MUX_SEL_TOPC1, 83 MUX_SEL_TOPC2, 84 MUX_SEL_TOPC3, 85 DIV_TOPC0, 86 DIV_TOPC1, 87 DIV_TOPC3, 88 }; 89 90 static struct samsung_mux_clock topc_mux_clks[] __initdata = { 91 MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), 92 MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1), 93 MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1), 94 MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1), 95 96 MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p, 97 MUX_SEL_TOPC0, 16, 2), 98 MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p, 99 MUX_SEL_TOPC0, 20, 1), 100 MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p, 101 MUX_SEL_TOPC0, 24, 1), 102 MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p, 103 MUX_SEL_TOPC0, 28, 1), 104 105 MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, 106 MUX_SEL_TOPC1, 16, 1), 107 108 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 109 110 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 111 }; 112 113 static struct samsung_div_clock topc_div_clks[] __initdata = { 114 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 115 DIV_TOPC0, 4, 4), 116 117 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 118 DIV_TOPC1, 24, 4), 119 120 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out", 121 DIV_TOPC3, 0, 3), 122 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl", 123 DIV_TOPC3, 8, 3), 124 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl", 125 DIV_TOPC3, 12, 3), 126 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", 127 DIV_TOPC3, 16, 3), 128 }; 129 130 static struct samsung_pll_clock topc_pll_clks[] __initdata = { 131 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 132 BUS0_PLL_CON0, NULL), 133 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 134 CC_PLL_CON0, NULL), 135 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, 136 BUS1_DPLL_CON0, NULL), 137 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 138 MFC_PLL_CON0, NULL), 139 PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 140 AUD_PLL_CON0, NULL), 141 }; 142 143 static struct samsung_cmu_info topc_cmu_info __initdata = { 144 .pll_clks = topc_pll_clks, 145 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 146 .mux_clks = topc_mux_clks, 147 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 148 .div_clks = topc_div_clks, 149 .nr_div_clks = ARRAY_SIZE(topc_div_clks), 150 .fixed_factor_clks = topc_fixed_factor_clks, 151 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 152 .nr_clk_ids = TOPC_NR_CLK, 153 .clk_regs = topc_clk_regs, 154 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), 155 }; 156 157 static void __init exynos7_clk_topc_init(struct device_node *np) 158 { 159 samsung_cmu_register_one(np, &topc_cmu_info); 160 } 161 162 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", 163 exynos7_clk_topc_init); 164 165 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ 166 #define MUX_SEL_TOP00 0x0200 167 #define MUX_SEL_TOP01 0x0204 168 #define MUX_SEL_TOP03 0x020C 169 #define MUX_SEL_TOP0_PERIC3 0x023C 170 #define DIV_TOP03 0x060C 171 #define DIV_TOP0_PERIC3 0x063C 172 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 173 174 /* List of parent clocks for Muxes in CMU_TOP0 */ 175 PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; 176 PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" }; 177 PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" }; 178 PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" }; 179 180 PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll", 181 "ffac_top0_bus0_pll_div2"}; 182 PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll", 183 "ffac_top0_bus1_pll_div2"}; 184 PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll", 185 "ffac_top0_cc_pll_div2"}; 186 PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll", 187 "ffac_top0_mfc_pll_div2"}; 188 189 PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll", 190 "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll", 191 "mout_top0_half_mfc_pll"}; 192 193 static unsigned long top0_clk_regs[] __initdata = { 194 MUX_SEL_TOP00, 195 MUX_SEL_TOP01, 196 MUX_SEL_TOP03, 197 MUX_SEL_TOP0_PERIC3, 198 DIV_TOP03, 199 DIV_TOP0_PERIC3, 200 ENABLE_SCLK_TOP0_PERIC3, 201 }; 202 203 static struct samsung_mux_clock top0_mux_clks[] __initdata = { 204 MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1), 205 MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1), 206 MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1), 207 MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1), 208 209 MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p, 210 MUX_SEL_TOP01, 4, 1), 211 MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p, 212 MUX_SEL_TOP01, 8, 1), 213 MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p, 214 MUX_SEL_TOP01, 12, 1), 215 MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p, 216 MUX_SEL_TOP01, 16, 1), 217 218 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 219 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 220 221 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 222 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 223 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 224 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 225 }; 226 227 static struct samsung_div_clock top0_div_clks[] __initdata = { 228 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 229 DIV_TOP03, 12, 6), 230 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 231 DIV_TOP03, 20, 6), 232 233 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 234 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 235 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 236 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 237 }; 238 239 static struct samsung_gate_clock top0_gate_clks[] __initdata = { 240 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 241 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 242 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 243 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), 244 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", 245 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 246 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 247 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 248 }; 249 250 static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { 251 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0), 252 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0), 253 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0), 254 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0), 255 }; 256 257 static struct samsung_cmu_info top0_cmu_info __initdata = { 258 .mux_clks = top0_mux_clks, 259 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 260 .div_clks = top0_div_clks, 261 .nr_div_clks = ARRAY_SIZE(top0_div_clks), 262 .gate_clks = top0_gate_clks, 263 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), 264 .fixed_factor_clks = top0_fixed_factor_clks, 265 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), 266 .nr_clk_ids = TOP0_NR_CLK, 267 .clk_regs = top0_clk_regs, 268 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), 269 }; 270 271 static void __init exynos7_clk_top0_init(struct device_node *np) 272 { 273 samsung_cmu_register_one(np, &top0_cmu_info); 274 } 275 276 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 277 exynos7_clk_top0_init); 278 279 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ 280 #define MUX_SEL_TOP10 0x0200 281 #define MUX_SEL_TOP11 0x0204 282 #define MUX_SEL_TOP13 0x020C 283 #define MUX_SEL_TOP1_FSYS0 0x0224 284 #define MUX_SEL_TOP1_FSYS1 0x0228 285 #define DIV_TOP13 0x060C 286 #define DIV_TOP1_FSYS0 0x0624 287 #define DIV_TOP1_FSYS1 0x0628 288 #define ENABLE_ACLK_TOP13 0x080C 289 #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 290 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 291 292 /* List of parent clocks for Muxes in CMU_TOP1 */ 293 PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; 294 PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" }; 295 PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" }; 296 PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" }; 297 298 PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll", 299 "ffac_top1_bus0_pll_div2"}; 300 PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll", 301 "ffac_top1_bus1_pll_div2"}; 302 PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll", 303 "ffac_top1_cc_pll_div2"}; 304 PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll", 305 "ffac_top1_mfc_pll_div2"}; 306 307 PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll", 308 "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll", 309 "mout_top1_half_mfc_pll"}; 310 311 static unsigned long top1_clk_regs[] __initdata = { 312 MUX_SEL_TOP10, 313 MUX_SEL_TOP11, 314 MUX_SEL_TOP13, 315 MUX_SEL_TOP1_FSYS0, 316 MUX_SEL_TOP1_FSYS1, 317 DIV_TOP13, 318 DIV_TOP1_FSYS0, 319 DIV_TOP1_FSYS1, 320 ENABLE_ACLK_TOP13, 321 ENABLE_SCLK_TOP1_FSYS0, 322 ENABLE_SCLK_TOP1_FSYS1, 323 }; 324 325 static struct samsung_mux_clock top1_mux_clks[] __initdata = { 326 MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1), 327 MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1), 328 MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p, 329 MUX_SEL_TOP10, 12, 1), 330 MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p, 331 MUX_SEL_TOP10, 16, 1), 332 333 MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p, 334 MUX_SEL_TOP11, 4, 1), 335 MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p, 336 MUX_SEL_TOP11, 8, 1), 337 MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p, 338 MUX_SEL_TOP11, 12, 1), 339 MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p, 340 MUX_SEL_TOP11, 16, 1), 341 342 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), 343 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 344 345 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2), 346 347 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2), 348 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2), 349 }; 350 351 static struct samsung_div_clock top1_div_clks[] __initdata = { 352 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 353 DIV_TOP13, 24, 4), 354 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 355 DIV_TOP13, 28, 4), 356 357 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 358 DIV_TOP1_FSYS0, 24, 4), 359 360 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 361 DIV_TOP1_FSYS1, 24, 4), 362 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", 363 DIV_TOP1_FSYS1, 28, 4), 364 }; 365 366 static struct samsung_gate_clock top1_gate_clks[] __initdata = { 367 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 368 ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0), 369 370 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 371 ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0), 372 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", 373 ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0), 374 }; 375 376 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { 377 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0), 378 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0), 379 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0), 380 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0), 381 }; 382 383 static struct samsung_cmu_info top1_cmu_info __initdata = { 384 .mux_clks = top1_mux_clks, 385 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 386 .div_clks = top1_div_clks, 387 .nr_div_clks = ARRAY_SIZE(top1_div_clks), 388 .gate_clks = top1_gate_clks, 389 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), 390 .fixed_factor_clks = top1_fixed_factor_clks, 391 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), 392 .nr_clk_ids = TOP1_NR_CLK, 393 .clk_regs = top1_clk_regs, 394 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), 395 }; 396 397 static void __init exynos7_clk_top1_init(struct device_node *np) 398 { 399 samsung_cmu_register_one(np, &top1_cmu_info); 400 } 401 402 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", 403 exynos7_clk_top1_init); 404 405 /* Register Offset definitions for CMU_CCORE (0x105B0000) */ 406 #define MUX_SEL_CCORE 0x0200 407 #define DIV_CCORE 0x0600 408 #define ENABLE_ACLK_CCORE0 0x0800 409 #define ENABLE_ACLK_CCORE1 0x0804 410 #define ENABLE_PCLK_CCORE 0x0900 411 412 /* 413 * List of parent clocks for Muxes in CMU_CCORE 414 */ 415 PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" }; 416 417 static unsigned long ccore_clk_regs[] __initdata = { 418 MUX_SEL_CCORE, 419 ENABLE_PCLK_CCORE, 420 }; 421 422 static struct samsung_mux_clock ccore_mux_clks[] __initdata = { 423 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p, 424 MUX_SEL_CCORE, 1, 1), 425 }; 426 427 static struct samsung_gate_clock ccore_gate_clks[] __initdata = { 428 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 429 ENABLE_PCLK_CCORE, 8, 0, 0), 430 }; 431 432 static struct samsung_cmu_info ccore_cmu_info __initdata = { 433 .mux_clks = ccore_mux_clks, 434 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 435 .gate_clks = ccore_gate_clks, 436 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), 437 .nr_clk_ids = CCORE_NR_CLK, 438 .clk_regs = ccore_clk_regs, 439 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), 440 }; 441 442 static void __init exynos7_clk_ccore_init(struct device_node *np) 443 { 444 samsung_cmu_register_one(np, &ccore_cmu_info); 445 } 446 447 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", 448 exynos7_clk_ccore_init); 449 450 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ 451 #define MUX_SEL_PERIC0 0x0200 452 #define ENABLE_PCLK_PERIC0 0x0900 453 #define ENABLE_SCLK_PERIC0 0x0A00 454 455 /* List of parent clocks for Muxes in CMU_PERIC0 */ 456 PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" }; 457 PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" }; 458 459 static unsigned long peric0_clk_regs[] __initdata = { 460 MUX_SEL_PERIC0, 461 ENABLE_PCLK_PERIC0, 462 ENABLE_SCLK_PERIC0, 463 }; 464 465 static struct samsung_mux_clock peric0_mux_clks[] __initdata = { 466 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p, 467 MUX_SEL_PERIC0, 0, 1), 468 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p, 469 MUX_SEL_PERIC0, 16, 1), 470 }; 471 472 static struct samsung_gate_clock peric0_gate_clks[] __initdata = { 473 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 474 ENABLE_PCLK_PERIC0, 8, 0, 0), 475 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 476 ENABLE_PCLK_PERIC0, 9, 0, 0), 477 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", 478 ENABLE_PCLK_PERIC0, 10, 0, 0), 479 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", 480 ENABLE_PCLK_PERIC0, 11, 0, 0), 481 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", 482 ENABLE_PCLK_PERIC0, 12, 0, 0), 483 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", 484 ENABLE_PCLK_PERIC0, 13, 0, 0), 485 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", 486 ENABLE_PCLK_PERIC0, 14, 0, 0), 487 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 488 ENABLE_PCLK_PERIC0, 16, 0, 0), 489 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", 490 ENABLE_PCLK_PERIC0, 20, 0, 0), 491 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 492 ENABLE_PCLK_PERIC0, 21, 0, 0), 493 494 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", 495 ENABLE_SCLK_PERIC0, 16, 0, 0), 496 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 497 }; 498 499 static struct samsung_cmu_info peric0_cmu_info __initdata = { 500 .mux_clks = peric0_mux_clks, 501 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 502 .gate_clks = peric0_gate_clks, 503 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 504 .nr_clk_ids = PERIC0_NR_CLK, 505 .clk_regs = peric0_clk_regs, 506 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 507 }; 508 509 static void __init exynos7_clk_peric0_init(struct device_node *np) 510 { 511 samsung_cmu_register_one(np, &peric0_cmu_info); 512 } 513 514 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 515 #define MUX_SEL_PERIC10 0x0200 516 #define MUX_SEL_PERIC11 0x0204 517 #define ENABLE_PCLK_PERIC1 0x0900 518 #define ENABLE_SCLK_PERIC10 0x0A00 519 520 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", 521 exynos7_clk_peric0_init); 522 523 /* List of parent clocks for Muxes in CMU_PERIC1 */ 524 PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; 525 PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; 526 PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; 527 PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; 528 529 static unsigned long peric1_clk_regs[] __initdata = { 530 MUX_SEL_PERIC10, 531 MUX_SEL_PERIC11, 532 ENABLE_PCLK_PERIC1, 533 ENABLE_SCLK_PERIC10, 534 }; 535 536 static struct samsung_mux_clock peric1_mux_clks[] __initdata = { 537 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, 538 MUX_SEL_PERIC10, 0, 1), 539 540 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, 541 MUX_SEL_PERIC11, 20, 1), 542 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, 543 MUX_SEL_PERIC11, 24, 1), 544 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p, 545 MUX_SEL_PERIC11, 28, 1), 546 }; 547 548 static struct samsung_gate_clock peric1_gate_clks[] __initdata = { 549 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 550 ENABLE_PCLK_PERIC1, 4, 0, 0), 551 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 552 ENABLE_PCLK_PERIC1, 5, 0, 0), 553 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", 554 ENABLE_PCLK_PERIC1, 6, 0, 0), 555 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", 556 ENABLE_PCLK_PERIC1, 7, 0, 0), 557 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", 558 ENABLE_PCLK_PERIC1, 8, 0, 0), 559 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", 560 ENABLE_PCLK_PERIC1, 9, 0, 0), 561 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", 562 ENABLE_PCLK_PERIC1, 10, 0, 0), 563 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 564 ENABLE_PCLK_PERIC1, 11, 0, 0), 565 566 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 567 ENABLE_SCLK_PERIC10, 9, 0, 0), 568 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", 569 ENABLE_SCLK_PERIC10, 10, 0, 0), 570 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 571 ENABLE_SCLK_PERIC10, 11, 0, 0), 572 }; 573 574 static struct samsung_cmu_info peric1_cmu_info __initdata = { 575 .mux_clks = peric1_mux_clks, 576 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 577 .gate_clks = peric1_gate_clks, 578 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 579 .nr_clk_ids = PERIC1_NR_CLK, 580 .clk_regs = peric1_clk_regs, 581 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 582 }; 583 584 static void __init exynos7_clk_peric1_init(struct device_node *np) 585 { 586 samsung_cmu_register_one(np, &peric1_cmu_info); 587 } 588 589 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", 590 exynos7_clk_peric1_init); 591 592 /* Register Offset definitions for CMU_PERIS (0x10040000) */ 593 #define MUX_SEL_PERIS 0x0200 594 #define ENABLE_PCLK_PERIS 0x0900 595 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 596 #define ENABLE_SCLK_PERIS 0x0A00 597 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 598 599 /* List of parent clocks for Muxes in CMU_PERIS */ 600 PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; 601 602 static unsigned long peris_clk_regs[] __initdata = { 603 MUX_SEL_PERIS, 604 ENABLE_PCLK_PERIS, 605 ENABLE_PCLK_PERIS_SECURE_CHIPID, 606 ENABLE_SCLK_PERIS, 607 ENABLE_SCLK_PERIS_SECURE_CHIPID, 608 }; 609 610 static struct samsung_mux_clock peris_mux_clks[] __initdata = { 611 MUX(0, "mout_aclk_peris_66_user", 612 mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1), 613 }; 614 615 static struct samsung_gate_clock peris_gate_clks[] __initdata = { 616 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 617 ENABLE_PCLK_PERIS, 6, 0, 0), 618 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 619 ENABLE_PCLK_PERIS, 10, 0, 0), 620 621 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", 622 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 623 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", 624 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 625 626 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 627 }; 628 629 static struct samsung_cmu_info peris_cmu_info __initdata = { 630 .mux_clks = peris_mux_clks, 631 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 632 .gate_clks = peris_gate_clks, 633 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 634 .nr_clk_ids = PERIS_NR_CLK, 635 .clk_regs = peris_clk_regs, 636 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 637 }; 638 639 static void __init exynos7_clk_peris_init(struct device_node *np) 640 { 641 samsung_cmu_register_one(np, &peris_cmu_info); 642 } 643 644 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", 645 exynos7_clk_peris_init); 646 647 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 648 #define MUX_SEL_FSYS00 0x0200 649 #define MUX_SEL_FSYS01 0x0204 650 #define ENABLE_ACLK_FSYS01 0x0804 651 652 /* 653 * List of parent clocks for Muxes in CMU_FSYS0 654 */ 655 PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; 656 PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; 657 658 static unsigned long fsys0_clk_regs[] __initdata = { 659 MUX_SEL_FSYS00, 660 MUX_SEL_FSYS01, 661 ENABLE_ACLK_FSYS01, 662 }; 663 664 static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { 665 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p, 666 MUX_SEL_FSYS00, 24, 1), 667 668 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), 669 }; 670 671 static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 672 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 673 ENABLE_ACLK_FSYS01, 31, 0, 0), 674 }; 675 676 static struct samsung_cmu_info fsys0_cmu_info __initdata = { 677 .mux_clks = fsys0_mux_clks, 678 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 679 .gate_clks = fsys0_gate_clks, 680 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 681 .nr_clk_ids = TOP1_NR_CLK, 682 .clk_regs = fsys0_clk_regs, 683 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 684 }; 685 686 static void __init exynos7_clk_fsys0_init(struct device_node *np) 687 { 688 samsung_cmu_register_one(np, &fsys0_cmu_info); 689 } 690 691 CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", 692 exynos7_clk_fsys0_init); 693 694 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ 695 #define MUX_SEL_FSYS10 0x0200 696 #define MUX_SEL_FSYS11 0x0204 697 #define ENABLE_ACLK_FSYS1 0x0800 698 699 /* 700 * List of parent clocks for Muxes in CMU_FSYS1 701 */ 702 PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" }; 703 PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" }; 704 PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" }; 705 706 static unsigned long fsys1_clk_regs[] __initdata = { 707 MUX_SEL_FSYS10, 708 MUX_SEL_FSYS11, 709 ENABLE_ACLK_FSYS1, 710 }; 711 712 static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { 713 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p, 714 MUX_SEL_FSYS10, 28, 1), 715 716 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1), 717 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1), 718 }; 719 720 static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { 721 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", 722 ENABLE_ACLK_FSYS1, 29, 0, 0), 723 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", 724 ENABLE_ACLK_FSYS1, 30, 0, 0), 725 }; 726 727 static struct samsung_cmu_info fsys1_cmu_info __initdata = { 728 .mux_clks = fsys1_mux_clks, 729 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 730 .gate_clks = fsys1_gate_clks, 731 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 732 .nr_clk_ids = TOP1_NR_CLK, 733 .clk_regs = fsys1_clk_regs, 734 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 735 }; 736 737 static void __init exynos7_clk_fsys1_init(struct device_node *np) 738 { 739 samsung_cmu_register_one(np, &fsys1_cmu_info); 740 } 741 742 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 743 exynos7_clk_fsys1_init); 744