1532abc3aSNaveen Krishna Ch /* 2532abc3aSNaveen Krishna Ch * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3532abc3aSNaveen Krishna Ch * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4532abc3aSNaveen Krishna Ch * 5532abc3aSNaveen Krishna Ch * This program is free software; you can redistribute it and/or modify 6532abc3aSNaveen Krishna Ch * it under the terms of the GNU General Public License version 2 as 7532abc3aSNaveen Krishna Ch * published by the Free Software Foundation. 8532abc3aSNaveen Krishna Ch * 9532abc3aSNaveen Krishna Ch */ 10532abc3aSNaveen Krishna Ch 11532abc3aSNaveen Krishna Ch #include <linux/clk-provider.h> 12532abc3aSNaveen Krishna Ch #include <linux/of.h> 13532abc3aSNaveen Krishna Ch 14532abc3aSNaveen Krishna Ch #include "clk.h" 15532abc3aSNaveen Krishna Ch #include <dt-bindings/clock/exynos7-clk.h> 16532abc3aSNaveen Krishna Ch 17532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_TOPC (0x10570000) */ 18532abc3aSNaveen Krishna Ch #define CC_PLL_LOCK 0x0000 19532abc3aSNaveen Krishna Ch #define BUS0_PLL_LOCK 0x0004 20532abc3aSNaveen Krishna Ch #define BUS1_DPLL_LOCK 0x0008 21532abc3aSNaveen Krishna Ch #define MFC_PLL_LOCK 0x000C 22532abc3aSNaveen Krishna Ch #define AUD_PLL_LOCK 0x0010 23532abc3aSNaveen Krishna Ch #define CC_PLL_CON0 0x0100 24532abc3aSNaveen Krishna Ch #define BUS0_PLL_CON0 0x0110 25532abc3aSNaveen Krishna Ch #define BUS1_DPLL_CON0 0x0120 26532abc3aSNaveen Krishna Ch #define MFC_PLL_CON0 0x0130 27532abc3aSNaveen Krishna Ch #define AUD_PLL_CON0 0x0140 28532abc3aSNaveen Krishna Ch #define MUX_SEL_TOPC0 0x0200 29532abc3aSNaveen Krishna Ch #define MUX_SEL_TOPC1 0x0204 30f5e127cdSNaveen Krishna Ch #define MUX_SEL_TOPC2 0x0208 31532abc3aSNaveen Krishna Ch #define MUX_SEL_TOPC3 0x020C 32f5e127cdSNaveen Krishna Ch #define DIV_TOPC0 0x0600 33532abc3aSNaveen Krishna Ch #define DIV_TOPC1 0x0604 34532abc3aSNaveen Krishna Ch #define DIV_TOPC3 0x060C 3549cab82cSTony K Nadackal #define ENABLE_ACLK_TOPC1 0x0804 36532abc3aSNaveen Krishna Ch 37532abc3aSNaveen Krishna Ch static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { 38532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), 39532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_bus0_pll_div4", 40532abc3aSNaveen Krishna Ch "ffac_topc_bus0_pll_div2", 1, 2, 0), 41532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0), 42532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0), 43532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0), 44532abc3aSNaveen Krishna Ch }; 45532abc3aSNaveen Krishna Ch 46532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_TOPC */ 479f930a39SPadmavathi Venna PNAME(mout_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; 48532abc3aSNaveen Krishna Ch PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 49532abc3aSNaveen Krishna Ch PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 50532abc3aSNaveen Krishna Ch PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 51532abc3aSNaveen Krishna Ch PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; 52532abc3aSNaveen Krishna Ch 53532abc3aSNaveen Krishna Ch PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc", 54532abc3aSNaveen Krishna Ch "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc", 55532abc3aSNaveen Krishna Ch "mout_sclk_mfc_pll_cmuc" }; 56532abc3aSNaveen Krishna Ch 57532abc3aSNaveen Krishna Ch PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl", 58532abc3aSNaveen Krishna Ch "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; 59532abc3aSNaveen Krishna Ch PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl", 60532abc3aSNaveen Krishna Ch "ffac_topc_bus1_pll_div2"}; 61532abc3aSNaveen Krishna Ch PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl", 62532abc3aSNaveen Krishna Ch "ffac_topc_cc_pll_div2"}; 63532abc3aSNaveen Krishna Ch PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl", 64532abc3aSNaveen Krishna Ch "ffac_topc_mfc_pll_div2"}; 65532abc3aSNaveen Krishna Ch 66532abc3aSNaveen Krishna Ch 67532abc3aSNaveen Krishna Ch PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl", 68532abc3aSNaveen Krishna Ch "ffac_topc_bus0_pll_div2"}; 69532abc3aSNaveen Krishna Ch 70532abc3aSNaveen Krishna Ch static unsigned long topc_clk_regs[] __initdata = { 71532abc3aSNaveen Krishna Ch CC_PLL_LOCK, 72532abc3aSNaveen Krishna Ch BUS0_PLL_LOCK, 73532abc3aSNaveen Krishna Ch BUS1_DPLL_LOCK, 74532abc3aSNaveen Krishna Ch MFC_PLL_LOCK, 75532abc3aSNaveen Krishna Ch AUD_PLL_LOCK, 76532abc3aSNaveen Krishna Ch CC_PLL_CON0, 77532abc3aSNaveen Krishna Ch BUS0_PLL_CON0, 78532abc3aSNaveen Krishna Ch BUS1_DPLL_CON0, 79532abc3aSNaveen Krishna Ch MFC_PLL_CON0, 80532abc3aSNaveen Krishna Ch AUD_PLL_CON0, 81532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 82532abc3aSNaveen Krishna Ch MUX_SEL_TOPC1, 83f5e127cdSNaveen Krishna Ch MUX_SEL_TOPC2, 84532abc3aSNaveen Krishna Ch MUX_SEL_TOPC3, 85f5e127cdSNaveen Krishna Ch DIV_TOPC0, 86532abc3aSNaveen Krishna Ch DIV_TOPC1, 87532abc3aSNaveen Krishna Ch DIV_TOPC3, 88532abc3aSNaveen Krishna Ch }; 89532abc3aSNaveen Krishna Ch 90532abc3aSNaveen Krishna Ch static struct samsung_mux_clock topc_mux_clks[] __initdata = { 91532abc3aSNaveen Krishna Ch MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), 92532abc3aSNaveen Krishna Ch MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1), 93532abc3aSNaveen Krishna Ch MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1), 94532abc3aSNaveen Krishna Ch MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1), 95532abc3aSNaveen Krishna Ch 96532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p, 97532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 16, 2), 98532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p, 99532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 20, 1), 100532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p, 101532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 24, 1), 102532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p, 103532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 28, 1), 104532abc3aSNaveen Krishna Ch 105fa9f3a52SAlim Akhtar MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1), 106532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, 107532abc3aSNaveen Krishna Ch MUX_SEL_TOPC1, 16, 1), 108532abc3aSNaveen Krishna Ch 109f5e127cdSNaveen Krishna Ch MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 110f5e127cdSNaveen Krishna Ch 11149cab82cSTony K Nadackal MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2), 112532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 113532abc3aSNaveen Krishna Ch }; 114532abc3aSNaveen Krishna Ch 115532abc3aSNaveen Krishna Ch static struct samsung_div_clock topc_div_clks[] __initdata = { 116f5e127cdSNaveen Krishna Ch DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 117f5e127cdSNaveen Krishna Ch DIV_TOPC0, 4, 4), 118f5e127cdSNaveen Krishna Ch 11949cab82cSTony K Nadackal DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532", 12049cab82cSTony K Nadackal DIV_TOPC1, 20, 4), 121532abc3aSNaveen Krishna Ch DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 122532abc3aSNaveen Krishna Ch DIV_TOPC1, 24, 4), 123532abc3aSNaveen Krishna Ch 124532abc3aSNaveen Krishna Ch DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out", 125fa9f3a52SAlim Akhtar DIV_TOPC3, 0, 4), 126532abc3aSNaveen Krishna Ch DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl", 127fa9f3a52SAlim Akhtar DIV_TOPC3, 8, 4), 128532abc3aSNaveen Krishna Ch DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl", 129fa9f3a52SAlim Akhtar DIV_TOPC3, 12, 4), 130532abc3aSNaveen Krishna Ch DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", 131fa9f3a52SAlim Akhtar DIV_TOPC3, 16, 4), 1329f930a39SPadmavathi Venna DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl", 133fa9f3a52SAlim Akhtar DIV_TOPC3, 28, 4), 1349f930a39SPadmavathi Venna }; 1359f930a39SPadmavathi Venna 1369f930a39SPadmavathi Venna static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { 1379f930a39SPadmavathi Venna PLL_36XX_RATE(491520000, 20, 1, 0, 31457), 1389f930a39SPadmavathi Venna {}, 139532abc3aSNaveen Krishna Ch }; 140532abc3aSNaveen Krishna Ch 14149cab82cSTony K Nadackal static struct samsung_gate_clock topc_gate_clks[] __initdata = { 14249cab82cSTony K Nadackal GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", 14349cab82cSTony K Nadackal ENABLE_ACLK_TOPC1, 20, 0, 0), 14449cab82cSTony K Nadackal }; 14549cab82cSTony K Nadackal 146532abc3aSNaveen Krishna Ch static struct samsung_pll_clock topc_pll_clks[] __initdata = { 147532abc3aSNaveen Krishna Ch PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 148532abc3aSNaveen Krishna Ch BUS0_PLL_CON0, NULL), 149532abc3aSNaveen Krishna Ch PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 150532abc3aSNaveen Krishna Ch CC_PLL_CON0, NULL), 151532abc3aSNaveen Krishna Ch PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, 152532abc3aSNaveen Krishna Ch BUS1_DPLL_CON0, NULL), 153532abc3aSNaveen Krishna Ch PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 154532abc3aSNaveen Krishna Ch MFC_PLL_CON0, NULL), 1559f930a39SPadmavathi Venna PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 1569f930a39SPadmavathi Venna AUD_PLL_CON0, pll1460x_24mhz_tbl), 157532abc3aSNaveen Krishna Ch }; 158532abc3aSNaveen Krishna Ch 159532abc3aSNaveen Krishna Ch static struct samsung_cmu_info topc_cmu_info __initdata = { 160532abc3aSNaveen Krishna Ch .pll_clks = topc_pll_clks, 161532abc3aSNaveen Krishna Ch .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 162532abc3aSNaveen Krishna Ch .mux_clks = topc_mux_clks, 163532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 164532abc3aSNaveen Krishna Ch .div_clks = topc_div_clks, 165532abc3aSNaveen Krishna Ch .nr_div_clks = ARRAY_SIZE(topc_div_clks), 16649cab82cSTony K Nadackal .gate_clks = topc_gate_clks, 16749cab82cSTony K Nadackal .nr_gate_clks = ARRAY_SIZE(topc_gate_clks), 168532abc3aSNaveen Krishna Ch .fixed_factor_clks = topc_fixed_factor_clks, 169532abc3aSNaveen Krishna Ch .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 170532abc3aSNaveen Krishna Ch .nr_clk_ids = TOPC_NR_CLK, 171532abc3aSNaveen Krishna Ch .clk_regs = topc_clk_regs, 172532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), 173532abc3aSNaveen Krishna Ch }; 174532abc3aSNaveen Krishna Ch 175532abc3aSNaveen Krishna Ch static void __init exynos7_clk_topc_init(struct device_node *np) 176532abc3aSNaveen Krishna Ch { 177532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &topc_cmu_info); 178532abc3aSNaveen Krishna Ch } 179532abc3aSNaveen Krishna Ch 180532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", 181532abc3aSNaveen Krishna Ch exynos7_clk_topc_init); 182532abc3aSNaveen Krishna Ch 183532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ 184532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP00 0x0200 185532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP01 0x0204 186532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP03 0x020C 1879f930a39SPadmavathi Venna #define MUX_SEL_TOP0_PERIC0 0x0230 188ee74b56aSPadmavathi Venna #define MUX_SEL_TOP0_PERIC1 0x0234 189ee74b56aSPadmavathi Venna #define MUX_SEL_TOP0_PERIC2 0x0238 190532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP0_PERIC3 0x023C 191532abc3aSNaveen Krishna Ch #define DIV_TOP03 0x060C 1929f930a39SPadmavathi Venna #define DIV_TOP0_PERIC0 0x0630 193ee74b56aSPadmavathi Venna #define DIV_TOP0_PERIC1 0x0634 194ee74b56aSPadmavathi Venna #define DIV_TOP0_PERIC2 0x0638 195532abc3aSNaveen Krishna Ch #define DIV_TOP0_PERIC3 0x063C 1969f930a39SPadmavathi Venna #define ENABLE_SCLK_TOP0_PERIC0 0x0A30 197ee74b56aSPadmavathi Venna #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 198ee74b56aSPadmavathi Venna #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 199532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 200532abc3aSNaveen Krishna Ch 201532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_TOP0 */ 202532abc3aSNaveen Krishna Ch PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; 203532abc3aSNaveen Krishna Ch PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" }; 204532abc3aSNaveen Krishna Ch PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" }; 205532abc3aSNaveen Krishna Ch PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" }; 2069f930a39SPadmavathi Venna PNAME(mout_aud_pll_p) = { "fin_pll", "dout_sclk_aud_pll" }; 207532abc3aSNaveen Krishna Ch 208532abc3aSNaveen Krishna Ch PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll", 209532abc3aSNaveen Krishna Ch "ffac_top0_bus0_pll_div2"}; 210532abc3aSNaveen Krishna Ch PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll", 211532abc3aSNaveen Krishna Ch "ffac_top0_bus1_pll_div2"}; 212532abc3aSNaveen Krishna Ch PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll", 213532abc3aSNaveen Krishna Ch "ffac_top0_cc_pll_div2"}; 214532abc3aSNaveen Krishna Ch PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll", 215532abc3aSNaveen Krishna Ch "ffac_top0_mfc_pll_div2"}; 216532abc3aSNaveen Krishna Ch 217532abc3aSNaveen Krishna Ch PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll", 218532abc3aSNaveen Krishna Ch "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll", 219532abc3aSNaveen Krishna Ch "mout_top0_half_mfc_pll"}; 2209f930a39SPadmavathi Venna PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", 2219f930a39SPadmavathi Venna "ioclk_audiocdclk1", "ioclk_spdif_extclk", 2229f930a39SPadmavathi Venna "mout_top0_aud_pll", "mout_top0_half_bus0_pll", 2239f930a39SPadmavathi Venna "mout_top0_half_bus1_pll"}; 2249f930a39SPadmavathi Venna PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll", 2259f930a39SPadmavathi Venna "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"}; 226532abc3aSNaveen Krishna Ch 227532abc3aSNaveen Krishna Ch static unsigned long top0_clk_regs[] __initdata = { 228532abc3aSNaveen Krishna Ch MUX_SEL_TOP00, 229532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 230532abc3aSNaveen Krishna Ch MUX_SEL_TOP03, 2319f930a39SPadmavathi Venna MUX_SEL_TOP0_PERIC0, 232ee74b56aSPadmavathi Venna MUX_SEL_TOP0_PERIC1, 233ee74b56aSPadmavathi Venna MUX_SEL_TOP0_PERIC2, 234532abc3aSNaveen Krishna Ch MUX_SEL_TOP0_PERIC3, 235532abc3aSNaveen Krishna Ch DIV_TOP03, 2369f930a39SPadmavathi Venna DIV_TOP0_PERIC0, 237ee74b56aSPadmavathi Venna DIV_TOP0_PERIC1, 238ee74b56aSPadmavathi Venna DIV_TOP0_PERIC2, 239532abc3aSNaveen Krishna Ch DIV_TOP0_PERIC3, 2409f930a39SPadmavathi Venna ENABLE_SCLK_TOP0_PERIC0, 241ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC1, 242ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC2, 243532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 244532abc3aSNaveen Krishna Ch }; 245532abc3aSNaveen Krishna Ch 246532abc3aSNaveen Krishna Ch static struct samsung_mux_clock top0_mux_clks[] __initdata = { 2479f930a39SPadmavathi Venna MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1), 248532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1), 249532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1), 250532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1), 251532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1), 252532abc3aSNaveen Krishna Ch 253532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p, 254532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 4, 1), 255532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p, 256532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 8, 1), 257532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p, 258532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 12, 1), 259532abc3aSNaveen Krishna Ch MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p, 260532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 16, 1), 261532abc3aSNaveen Krishna Ch 262532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 263532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 264532abc3aSNaveen Krishna Ch 2659f930a39SPadmavathi Venna MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3), 2669f930a39SPadmavathi Venna MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2), 2679f930a39SPadmavathi Venna MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2), 2689f930a39SPadmavathi Venna 269ee74b56aSPadmavathi Venna MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2), 270ee74b56aSPadmavathi Venna MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2), 271ee74b56aSPadmavathi Venna 272ee74b56aSPadmavathi Venna MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2), 273ee74b56aSPadmavathi Venna MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2), 274532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 275532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 276532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 277532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 278ee74b56aSPadmavathi Venna MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), 279532abc3aSNaveen Krishna Ch }; 280532abc3aSNaveen Krishna Ch 281532abc3aSNaveen Krishna Ch static struct samsung_div_clock top0_div_clks[] __initdata = { 282532abc3aSNaveen Krishna Ch DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 283532abc3aSNaveen Krishna Ch DIV_TOP03, 12, 6), 284532abc3aSNaveen Krishna Ch DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 285532abc3aSNaveen Krishna Ch DIV_TOP03, 20, 6), 286532abc3aSNaveen Krishna Ch 2879f930a39SPadmavathi Venna DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4), 2889f930a39SPadmavathi Venna DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12), 2899f930a39SPadmavathi Venna DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10), 2909f930a39SPadmavathi Venna 291ee74b56aSPadmavathi Venna DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12), 292ee74b56aSPadmavathi Venna DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12), 293ee74b56aSPadmavathi Venna 294ee74b56aSPadmavathi Venna DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12), 295ee74b56aSPadmavathi Venna DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12), 296ee74b56aSPadmavathi Venna 297532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 298532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 299532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 300532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 301ee74b56aSPadmavathi Venna DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), 302532abc3aSNaveen Krishna Ch }; 303532abc3aSNaveen Krishna Ch 304532abc3aSNaveen Krishna Ch static struct samsung_gate_clock top0_gate_clks[] __initdata = { 3059f930a39SPadmavathi Venna GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", 3069f930a39SPadmavathi Venna ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 3079f930a39SPadmavathi Venna GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1", 3089f930a39SPadmavathi Venna ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 3099f930a39SPadmavathi Venna GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1", 3109f930a39SPadmavathi Venna ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0), 3119f930a39SPadmavathi Venna 312ee74b56aSPadmavathi Venna GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1", 313ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0), 314ee74b56aSPadmavathi Venna GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0", 315ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 316ee74b56aSPadmavathi Venna 317ee74b56aSPadmavathi Venna GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3", 318ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0), 319ee74b56aSPadmavathi Venna GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2", 320ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0), 321532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 322532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 323532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 324532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), 325532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", 326532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 327532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 328532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 329ee74b56aSPadmavathi Venna GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4", 330ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), 331532abc3aSNaveen Krishna Ch }; 332532abc3aSNaveen Krishna Ch 333532abc3aSNaveen Krishna Ch static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { 334532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0), 335532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0), 336532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0), 337532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0), 338532abc3aSNaveen Krishna Ch }; 339532abc3aSNaveen Krishna Ch 340532abc3aSNaveen Krishna Ch static struct samsung_cmu_info top0_cmu_info __initdata = { 341532abc3aSNaveen Krishna Ch .mux_clks = top0_mux_clks, 342532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 343532abc3aSNaveen Krishna Ch .div_clks = top0_div_clks, 344532abc3aSNaveen Krishna Ch .nr_div_clks = ARRAY_SIZE(top0_div_clks), 345532abc3aSNaveen Krishna Ch .gate_clks = top0_gate_clks, 346532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), 347532abc3aSNaveen Krishna Ch .fixed_factor_clks = top0_fixed_factor_clks, 348532abc3aSNaveen Krishna Ch .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), 349532abc3aSNaveen Krishna Ch .nr_clk_ids = TOP0_NR_CLK, 350532abc3aSNaveen Krishna Ch .clk_regs = top0_clk_regs, 351532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), 352532abc3aSNaveen Krishna Ch }; 353532abc3aSNaveen Krishna Ch 354532abc3aSNaveen Krishna Ch static void __init exynos7_clk_top0_init(struct device_node *np) 355532abc3aSNaveen Krishna Ch { 356532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &top0_cmu_info); 357532abc3aSNaveen Krishna Ch } 358532abc3aSNaveen Krishna Ch 359532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 360532abc3aSNaveen Krishna Ch exynos7_clk_top0_init); 361532abc3aSNaveen Krishna Ch 3626d0c8c72SNaveen Krishna Ch /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ 3636d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP10 0x0200 3646d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP11 0x0204 3656d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP13 0x020C 3666d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP1_FSYS0 0x0224 3676d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP1_FSYS1 0x0228 368cfc7588aSAlim Akhtar #define MUX_SEL_TOP1_FSYS11 0x022C 3696d0c8c72SNaveen Krishna Ch #define DIV_TOP13 0x060C 3706d0c8c72SNaveen Krishna Ch #define DIV_TOP1_FSYS0 0x0624 3716d0c8c72SNaveen Krishna Ch #define DIV_TOP1_FSYS1 0x0628 372cfc7588aSAlim Akhtar #define DIV_TOP1_FSYS11 0x062C 3736d0c8c72SNaveen Krishna Ch #define ENABLE_ACLK_TOP13 0x080C 3746d0c8c72SNaveen Krishna Ch #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 3756d0c8c72SNaveen Krishna Ch #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 376cfc7588aSAlim Akhtar #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C 3776d0c8c72SNaveen Krishna Ch 3786d0c8c72SNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_TOP1 */ 3796d0c8c72SNaveen Krishna Ch PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; 3806d0c8c72SNaveen Krishna Ch PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" }; 3816d0c8c72SNaveen Krishna Ch PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" }; 3826d0c8c72SNaveen Krishna Ch PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" }; 3836d0c8c72SNaveen Krishna Ch 3846d0c8c72SNaveen Krishna Ch PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll", 3856d0c8c72SNaveen Krishna Ch "ffac_top1_bus0_pll_div2"}; 3866d0c8c72SNaveen Krishna Ch PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll", 3876d0c8c72SNaveen Krishna Ch "ffac_top1_bus1_pll_div2"}; 3886d0c8c72SNaveen Krishna Ch PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll", 3896d0c8c72SNaveen Krishna Ch "ffac_top1_cc_pll_div2"}; 3906d0c8c72SNaveen Krishna Ch PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll", 3916d0c8c72SNaveen Krishna Ch "ffac_top1_mfc_pll_div2"}; 3926d0c8c72SNaveen Krishna Ch 3936d0c8c72SNaveen Krishna Ch PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll", 3946d0c8c72SNaveen Krishna Ch "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll", 3956d0c8c72SNaveen Krishna Ch "mout_top1_half_mfc_pll"}; 3966d0c8c72SNaveen Krishna Ch 3976d0c8c72SNaveen Krishna Ch static unsigned long top1_clk_regs[] __initdata = { 3986d0c8c72SNaveen Krishna Ch MUX_SEL_TOP10, 3996d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 4006d0c8c72SNaveen Krishna Ch MUX_SEL_TOP13, 4016d0c8c72SNaveen Krishna Ch MUX_SEL_TOP1_FSYS0, 4026d0c8c72SNaveen Krishna Ch MUX_SEL_TOP1_FSYS1, 403cfc7588aSAlim Akhtar MUX_SEL_TOP1_FSYS11, 4046d0c8c72SNaveen Krishna Ch DIV_TOP13, 4056d0c8c72SNaveen Krishna Ch DIV_TOP1_FSYS0, 4066d0c8c72SNaveen Krishna Ch DIV_TOP1_FSYS1, 407cfc7588aSAlim Akhtar DIV_TOP1_FSYS11, 4086d0c8c72SNaveen Krishna Ch ENABLE_ACLK_TOP13, 4096d0c8c72SNaveen Krishna Ch ENABLE_SCLK_TOP1_FSYS0, 4106d0c8c72SNaveen Krishna Ch ENABLE_SCLK_TOP1_FSYS1, 411cfc7588aSAlim Akhtar ENABLE_SCLK_TOP1_FSYS11, 4126d0c8c72SNaveen Krishna Ch }; 4136d0c8c72SNaveen Krishna Ch 4146d0c8c72SNaveen Krishna Ch static struct samsung_mux_clock top1_mux_clks[] __initdata = { 4156d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1), 4166d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1), 4176d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p, 4186d0c8c72SNaveen Krishna Ch MUX_SEL_TOP10, 12, 1), 4196d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p, 4206d0c8c72SNaveen Krishna Ch MUX_SEL_TOP10, 16, 1), 4216d0c8c72SNaveen Krishna Ch 4226d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p, 4236d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 4, 1), 4246d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p, 4256d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 8, 1), 4266d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p, 4276d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 12, 1), 4286d0c8c72SNaveen Krishna Ch MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p, 4296d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 16, 1), 4306d0c8c72SNaveen Krishna Ch 4316d0c8c72SNaveen Krishna Ch MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), 4326d0c8c72SNaveen Krishna Ch MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 4336d0c8c72SNaveen Krishna Ch 434cfc7588aSAlim Akhtar MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2), 43583f191a7SVivek Gautam MUX(0, "mout_sclk_usbdrd300", mout_top1_group1, 43683f191a7SVivek Gautam MUX_SEL_TOP1_FSYS0, 28, 2), 4376d0c8c72SNaveen Krishna Ch 438cfc7588aSAlim Akhtar MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2), 439cfc7588aSAlim Akhtar MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2), 4406d0c8c72SNaveen Krishna Ch }; 4416d0c8c72SNaveen Krishna Ch 4426d0c8c72SNaveen Krishna Ch static struct samsung_div_clock top1_div_clks[] __initdata = { 4436d0c8c72SNaveen Krishna Ch DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 4446d0c8c72SNaveen Krishna Ch DIV_TOP13, 24, 4), 4456d0c8c72SNaveen Krishna Ch DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 4466d0c8c72SNaveen Krishna Ch DIV_TOP13, 28, 4), 4476d0c8c72SNaveen Krishna Ch 4486d0c8c72SNaveen Krishna Ch DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 449cfc7588aSAlim Akhtar DIV_TOP1_FSYS0, 16, 10), 45083f191a7SVivek Gautam DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300", 45183f191a7SVivek Gautam DIV_TOP1_FSYS0, 28, 4), 4526d0c8c72SNaveen Krishna Ch 4536d0c8c72SNaveen Krishna Ch DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 454cfc7588aSAlim Akhtar DIV_TOP1_FSYS11, 0, 10), 4556d0c8c72SNaveen Krishna Ch DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", 456cfc7588aSAlim Akhtar DIV_TOP1_FSYS11, 12, 10), 4576d0c8c72SNaveen Krishna Ch }; 4586d0c8c72SNaveen Krishna Ch 4596d0c8c72SNaveen Krishna Ch static struct samsung_gate_clock top1_gate_clks[] __initdata = { 4606d0c8c72SNaveen Krishna Ch GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 461cfc7588aSAlim Akhtar ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), 46283f191a7SVivek Gautam GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", 46383f191a7SVivek Gautam ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0), 4646d0c8c72SNaveen Krishna Ch 4656d0c8c72SNaveen Krishna Ch GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 466cfc7588aSAlim Akhtar ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), 4676d0c8c72SNaveen Krishna Ch GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", 468cfc7588aSAlim Akhtar ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), 4696d0c8c72SNaveen Krishna Ch }; 4706d0c8c72SNaveen Krishna Ch 4716d0c8c72SNaveen Krishna Ch static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { 4726d0c8c72SNaveen Krishna Ch FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0), 4736d0c8c72SNaveen Krishna Ch FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0), 4746d0c8c72SNaveen Krishna Ch FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0), 4756d0c8c72SNaveen Krishna Ch FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0), 4766d0c8c72SNaveen Krishna Ch }; 4776d0c8c72SNaveen Krishna Ch 4786d0c8c72SNaveen Krishna Ch static struct samsung_cmu_info top1_cmu_info __initdata = { 4796d0c8c72SNaveen Krishna Ch .mux_clks = top1_mux_clks, 4806d0c8c72SNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 4816d0c8c72SNaveen Krishna Ch .div_clks = top1_div_clks, 4826d0c8c72SNaveen Krishna Ch .nr_div_clks = ARRAY_SIZE(top1_div_clks), 4836d0c8c72SNaveen Krishna Ch .gate_clks = top1_gate_clks, 4846d0c8c72SNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), 4856d0c8c72SNaveen Krishna Ch .fixed_factor_clks = top1_fixed_factor_clks, 4866d0c8c72SNaveen Krishna Ch .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), 4876d0c8c72SNaveen Krishna Ch .nr_clk_ids = TOP1_NR_CLK, 4886d0c8c72SNaveen Krishna Ch .clk_regs = top1_clk_regs, 4896d0c8c72SNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), 4906d0c8c72SNaveen Krishna Ch }; 4916d0c8c72SNaveen Krishna Ch 4926d0c8c72SNaveen Krishna Ch static void __init exynos7_clk_top1_init(struct device_node *np) 4936d0c8c72SNaveen Krishna Ch { 4946d0c8c72SNaveen Krishna Ch samsung_cmu_register_one(np, &top1_cmu_info); 4956d0c8c72SNaveen Krishna Ch } 4966d0c8c72SNaveen Krishna Ch 4976d0c8c72SNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", 4986d0c8c72SNaveen Krishna Ch exynos7_clk_top1_init); 4996d0c8c72SNaveen Krishna Ch 500f5e127cdSNaveen Krishna Ch /* Register Offset definitions for CMU_CCORE (0x105B0000) */ 501f5e127cdSNaveen Krishna Ch #define MUX_SEL_CCORE 0x0200 502f5e127cdSNaveen Krishna Ch #define DIV_CCORE 0x0600 503f5e127cdSNaveen Krishna Ch #define ENABLE_ACLK_CCORE0 0x0800 504f5e127cdSNaveen Krishna Ch #define ENABLE_ACLK_CCORE1 0x0804 505f5e127cdSNaveen Krishna Ch #define ENABLE_PCLK_CCORE 0x0900 506f5e127cdSNaveen Krishna Ch 507f5e127cdSNaveen Krishna Ch /* 508f5e127cdSNaveen Krishna Ch * List of parent clocks for Muxes in CMU_CCORE 509f5e127cdSNaveen Krishna Ch */ 510f5e127cdSNaveen Krishna Ch PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" }; 511f5e127cdSNaveen Krishna Ch 512f5e127cdSNaveen Krishna Ch static unsigned long ccore_clk_regs[] __initdata = { 513f5e127cdSNaveen Krishna Ch MUX_SEL_CCORE, 514f5e127cdSNaveen Krishna Ch ENABLE_PCLK_CCORE, 515f5e127cdSNaveen Krishna Ch }; 516f5e127cdSNaveen Krishna Ch 517f5e127cdSNaveen Krishna Ch static struct samsung_mux_clock ccore_mux_clks[] __initdata = { 518f5e127cdSNaveen Krishna Ch MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p, 519f5e127cdSNaveen Krishna Ch MUX_SEL_CCORE, 1, 1), 520f5e127cdSNaveen Krishna Ch }; 521f5e127cdSNaveen Krishna Ch 522f5e127cdSNaveen Krishna Ch static struct samsung_gate_clock ccore_gate_clks[] __initdata = { 523f5e127cdSNaveen Krishna Ch GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 524f5e127cdSNaveen Krishna Ch ENABLE_PCLK_CCORE, 8, 0, 0), 525f5e127cdSNaveen Krishna Ch }; 526f5e127cdSNaveen Krishna Ch 527f5e127cdSNaveen Krishna Ch static struct samsung_cmu_info ccore_cmu_info __initdata = { 528f5e127cdSNaveen Krishna Ch .mux_clks = ccore_mux_clks, 529f5e127cdSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 530f5e127cdSNaveen Krishna Ch .gate_clks = ccore_gate_clks, 531f5e127cdSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), 532f5e127cdSNaveen Krishna Ch .nr_clk_ids = CCORE_NR_CLK, 533f5e127cdSNaveen Krishna Ch .clk_regs = ccore_clk_regs, 534f5e127cdSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), 535f5e127cdSNaveen Krishna Ch }; 536f5e127cdSNaveen Krishna Ch 537f5e127cdSNaveen Krishna Ch static void __init exynos7_clk_ccore_init(struct device_node *np) 538f5e127cdSNaveen Krishna Ch { 539f5e127cdSNaveen Krishna Ch samsung_cmu_register_one(np, &ccore_cmu_info); 540f5e127cdSNaveen Krishna Ch } 541f5e127cdSNaveen Krishna Ch 542f5e127cdSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", 543f5e127cdSNaveen Krishna Ch exynos7_clk_ccore_init); 544f5e127cdSNaveen Krishna Ch 545532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ 546532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIC0 0x0200 547532abc3aSNaveen Krishna Ch #define ENABLE_PCLK_PERIC0 0x0900 548532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_PERIC0 0x0A00 549532abc3aSNaveen Krishna Ch 550532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_PERIC0 */ 551532abc3aSNaveen Krishna Ch PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" }; 552532abc3aSNaveen Krishna Ch PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" }; 553532abc3aSNaveen Krishna Ch 554532abc3aSNaveen Krishna Ch static unsigned long peric0_clk_regs[] __initdata = { 555532abc3aSNaveen Krishna Ch MUX_SEL_PERIC0, 556532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC0, 557532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC0, 558532abc3aSNaveen Krishna Ch }; 559532abc3aSNaveen Krishna Ch 560532abc3aSNaveen Krishna Ch static struct samsung_mux_clock peric0_mux_clks[] __initdata = { 561532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p, 562532abc3aSNaveen Krishna Ch MUX_SEL_PERIC0, 0, 1), 563532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p, 564532abc3aSNaveen Krishna Ch MUX_SEL_PERIC0, 16, 1), 565532abc3aSNaveen Krishna Ch }; 566532abc3aSNaveen Krishna Ch 567532abc3aSNaveen Krishna Ch static struct samsung_gate_clock peric0_gate_clks[] __initdata = { 56857a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 56957a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 8, 0, 0), 57057a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 57157a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 9, 0, 0), 57257a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", 57357a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 10, 0, 0), 57457a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", 57557a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 11, 0, 0), 57657a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", 57757a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 12, 0, 0), 57857a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", 57957a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 13, 0, 0), 58057a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", 58157a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 14, 0, 0), 582532abc3aSNaveen Krishna Ch GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 583532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC0, 16, 0, 0), 584932e9822SAbhilash Kesavan GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", 585932e9822SAbhilash Kesavan ENABLE_PCLK_PERIC0, 20, 0, 0), 5862ab2dfe5SNaveen Krishna Ch GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 5872ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 21, 0, 0), 588532abc3aSNaveen Krishna Ch 589532abc3aSNaveen Krishna Ch GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", 590532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC0, 16, 0, 0), 5912ab2dfe5SNaveen Krishna Ch GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 592532abc3aSNaveen Krishna Ch }; 593532abc3aSNaveen Krishna Ch 594532abc3aSNaveen Krishna Ch static struct samsung_cmu_info peric0_cmu_info __initdata = { 595532abc3aSNaveen Krishna Ch .mux_clks = peric0_mux_clks, 596532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 597532abc3aSNaveen Krishna Ch .gate_clks = peric0_gate_clks, 598532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 599532abc3aSNaveen Krishna Ch .nr_clk_ids = PERIC0_NR_CLK, 600532abc3aSNaveen Krishna Ch .clk_regs = peric0_clk_regs, 601532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 602532abc3aSNaveen Krishna Ch }; 603532abc3aSNaveen Krishna Ch 604532abc3aSNaveen Krishna Ch static void __init exynos7_clk_peric0_init(struct device_node *np) 605532abc3aSNaveen Krishna Ch { 606532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &peric0_cmu_info); 607532abc3aSNaveen Krishna Ch } 608532abc3aSNaveen Krishna Ch 609532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 610532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIC10 0x0200 611532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIC11 0x0204 612ee74b56aSPadmavathi Venna #define MUX_SEL_PERIC12 0x0208 613532abc3aSNaveen Krishna Ch #define ENABLE_PCLK_PERIC1 0x0900 614532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_PERIC10 0x0A00 615532abc3aSNaveen Krishna Ch 616532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", 617532abc3aSNaveen Krishna Ch exynos7_clk_peric0_init); 618532abc3aSNaveen Krishna Ch 619532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_PERIC1 */ 620532abc3aSNaveen Krishna Ch PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; 621532abc3aSNaveen Krishna Ch PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; 622532abc3aSNaveen Krishna Ch PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; 623532abc3aSNaveen Krishna Ch PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; 624ee74b56aSPadmavathi Venna PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" }; 625ee74b56aSPadmavathi Venna PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" }; 626ee74b56aSPadmavathi Venna PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" }; 627ee74b56aSPadmavathi Venna PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" }; 628ee74b56aSPadmavathi Venna PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" }; 629532abc3aSNaveen Krishna Ch 630532abc3aSNaveen Krishna Ch static unsigned long peric1_clk_regs[] __initdata = { 631532abc3aSNaveen Krishna Ch MUX_SEL_PERIC10, 632532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 633ee74b56aSPadmavathi Venna MUX_SEL_PERIC12, 634532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 635532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 636532abc3aSNaveen Krishna Ch }; 637532abc3aSNaveen Krishna Ch 638532abc3aSNaveen Krishna Ch static struct samsung_mux_clock peric1_mux_clks[] __initdata = { 639532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, 640532abc3aSNaveen Krishna Ch MUX_SEL_PERIC10, 0, 1), 641532abc3aSNaveen Krishna Ch 642ee74b56aSPadmavathi Venna MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p, 643ee74b56aSPadmavathi Venna MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), 644ee74b56aSPadmavathi Venna MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p, 645ee74b56aSPadmavathi Venna MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), 646ee74b56aSPadmavathi Venna MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p, 647ee74b56aSPadmavathi Venna MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), 648ee74b56aSPadmavathi Venna MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p, 649ee74b56aSPadmavathi Venna MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), 650ee74b56aSPadmavathi Venna MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p, 651ee74b56aSPadmavathi Venna MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), 652532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, 653532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 20, 1), 654532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, 655532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 24, 1), 656532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p, 657532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 28, 1), 658532abc3aSNaveen Krishna Ch }; 659532abc3aSNaveen Krishna Ch 660532abc3aSNaveen Krishna Ch static struct samsung_gate_clock peric1_gate_clks[] __initdata = { 66157a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 66257a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 4, 0, 0), 66357a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 66457a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 5, 0, 0), 66557a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", 66657a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 6, 0, 0), 66757a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", 66857a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 7, 0, 0), 66957a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", 67057a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 8, 0, 0), 671532abc3aSNaveen Krishna Ch GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", 672532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 9, 0, 0), 673532abc3aSNaveen Krishna Ch GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", 674532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 10, 0, 0), 675532abc3aSNaveen Krishna Ch GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 676532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 11, 0, 0), 677ee74b56aSPadmavathi Venna GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user", 678ee74b56aSPadmavathi Venna ENABLE_PCLK_PERIC1, 12, 0, 0), 679ee74b56aSPadmavathi Venna GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user", 680ee74b56aSPadmavathi Venna ENABLE_PCLK_PERIC1, 13, 0, 0), 681ee74b56aSPadmavathi Venna GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user", 682ee74b56aSPadmavathi Venna ENABLE_PCLK_PERIC1, 14, 0, 0), 683ee74b56aSPadmavathi Venna GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user", 684ee74b56aSPadmavathi Venna ENABLE_PCLK_PERIC1, 15, 0, 0), 685ee74b56aSPadmavathi Venna GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user", 686ee74b56aSPadmavathi Venna ENABLE_PCLK_PERIC1, 16, 0, 0), 6879f930a39SPadmavathi Venna GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user", 6889f930a39SPadmavathi Venna ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0), 6899f930a39SPadmavathi Venna GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user", 6909f930a39SPadmavathi Venna ENABLE_PCLK_PERIC1, 18, 0, 0), 6919f930a39SPadmavathi Venna GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user", 6929f930a39SPadmavathi Venna ENABLE_PCLK_PERIC1, 19, 0, 0), 693532abc3aSNaveen Krishna Ch 694532abc3aSNaveen Krishna Ch GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 695532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 9, 0, 0), 696532abc3aSNaveen Krishna Ch GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", 697532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 10, 0, 0), 698532abc3aSNaveen Krishna Ch GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 699532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 11, 0, 0), 700ee74b56aSPadmavathi Venna GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user", 701ee74b56aSPadmavathi Venna ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0), 702ee74b56aSPadmavathi Venna GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user", 703ee74b56aSPadmavathi Venna ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0), 704ee74b56aSPadmavathi Venna GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user", 705ee74b56aSPadmavathi Venna ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0), 706ee74b56aSPadmavathi Venna GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user", 707ee74b56aSPadmavathi Venna ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0), 708ee74b56aSPadmavathi Venna GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user", 709ee74b56aSPadmavathi Venna ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0), 7109f930a39SPadmavathi Venna GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1", 7119f930a39SPadmavathi Venna ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0), 7129f930a39SPadmavathi Venna GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1", 7139f930a39SPadmavathi Venna ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0), 7149f930a39SPadmavathi Venna GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif", 7159f930a39SPadmavathi Venna ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), 716532abc3aSNaveen Krishna Ch }; 717532abc3aSNaveen Krishna Ch 718532abc3aSNaveen Krishna Ch static struct samsung_cmu_info peric1_cmu_info __initdata = { 719532abc3aSNaveen Krishna Ch .mux_clks = peric1_mux_clks, 720532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 721532abc3aSNaveen Krishna Ch .gate_clks = peric1_gate_clks, 722532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 723532abc3aSNaveen Krishna Ch .nr_clk_ids = PERIC1_NR_CLK, 724532abc3aSNaveen Krishna Ch .clk_regs = peric1_clk_regs, 725532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 726532abc3aSNaveen Krishna Ch }; 727532abc3aSNaveen Krishna Ch 728532abc3aSNaveen Krishna Ch static void __init exynos7_clk_peric1_init(struct device_node *np) 729532abc3aSNaveen Krishna Ch { 730532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &peric1_cmu_info); 731532abc3aSNaveen Krishna Ch } 732532abc3aSNaveen Krishna Ch 733532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", 734532abc3aSNaveen Krishna Ch exynos7_clk_peric1_init); 735532abc3aSNaveen Krishna Ch 736532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_PERIS (0x10040000) */ 737532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIS 0x0200 7382ab2dfe5SNaveen Krishna Ch #define ENABLE_PCLK_PERIS 0x0900 739532abc3aSNaveen Krishna Ch #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 7402ab2dfe5SNaveen Krishna Ch #define ENABLE_SCLK_PERIS 0x0A00 741532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 742532abc3aSNaveen Krishna Ch 743532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_PERIS */ 744532abc3aSNaveen Krishna Ch PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; 745532abc3aSNaveen Krishna Ch 746532abc3aSNaveen Krishna Ch static unsigned long peris_clk_regs[] __initdata = { 747532abc3aSNaveen Krishna Ch MUX_SEL_PERIS, 7482ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIS, 749532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIS_SECURE_CHIPID, 7502ab2dfe5SNaveen Krishna Ch ENABLE_SCLK_PERIS, 751532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIS_SECURE_CHIPID, 752532abc3aSNaveen Krishna Ch }; 753532abc3aSNaveen Krishna Ch 754532abc3aSNaveen Krishna Ch static struct samsung_mux_clock peris_mux_clks[] __initdata = { 755532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peris_66_user", 756532abc3aSNaveen Krishna Ch mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1), 757532abc3aSNaveen Krishna Ch }; 758532abc3aSNaveen Krishna Ch 759532abc3aSNaveen Krishna Ch static struct samsung_gate_clock peris_gate_clks[] __initdata = { 7602ab2dfe5SNaveen Krishna Ch GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 7612ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIS, 6, 0, 0), 7622ab2dfe5SNaveen Krishna Ch GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 7632ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIS, 10, 0, 0), 7642ab2dfe5SNaveen Krishna Ch 765532abc3aSNaveen Krishna Ch GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", 766532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 767532abc3aSNaveen Krishna Ch GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", 768532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 7692ab2dfe5SNaveen Krishna Ch 7702ab2dfe5SNaveen Krishna Ch GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 771532abc3aSNaveen Krishna Ch }; 772532abc3aSNaveen Krishna Ch 773532abc3aSNaveen Krishna Ch static struct samsung_cmu_info peris_cmu_info __initdata = { 774532abc3aSNaveen Krishna Ch .mux_clks = peris_mux_clks, 775532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 776532abc3aSNaveen Krishna Ch .gate_clks = peris_gate_clks, 777532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 778532abc3aSNaveen Krishna Ch .nr_clk_ids = PERIS_NR_CLK, 779532abc3aSNaveen Krishna Ch .clk_regs = peris_clk_regs, 780532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 781532abc3aSNaveen Krishna Ch }; 782532abc3aSNaveen Krishna Ch 783532abc3aSNaveen Krishna Ch static void __init exynos7_clk_peris_init(struct device_node *np) 784532abc3aSNaveen Krishna Ch { 785532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &peris_cmu_info); 786532abc3aSNaveen Krishna Ch } 787532abc3aSNaveen Krishna Ch 788532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", 789532abc3aSNaveen Krishna Ch exynos7_clk_peris_init); 7906d0c8c72SNaveen Krishna Ch 7916d0c8c72SNaveen Krishna Ch /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 7926d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS00 0x0200 7936d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS01 0x0204 79483f191a7SVivek Gautam #define MUX_SEL_FSYS02 0x0208 79583f191a7SVivek Gautam #define ENABLE_ACLK_FSYS00 0x0800 7966d0c8c72SNaveen Krishna Ch #define ENABLE_ACLK_FSYS01 0x0804 79783f191a7SVivek Gautam #define ENABLE_SCLK_FSYS01 0x0A04 79883f191a7SVivek Gautam #define ENABLE_SCLK_FSYS02 0x0A08 79983f191a7SVivek Gautam #define ENABLE_SCLK_FSYS04 0x0A10 8006d0c8c72SNaveen Krishna Ch 8016d0c8c72SNaveen Krishna Ch /* 8026d0c8c72SNaveen Krishna Ch * List of parent clocks for Muxes in CMU_FSYS0 8036d0c8c72SNaveen Krishna Ch */ 8046d0c8c72SNaveen Krishna Ch PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; 8056d0c8c72SNaveen Krishna Ch PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; 8066d0c8c72SNaveen Krishna Ch 80783f191a7SVivek Gautam PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" }; 80883f191a7SVivek Gautam PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll", 80983f191a7SVivek Gautam "phyclk_usbdrd300_udrd30_phyclock" }; 81083f191a7SVivek Gautam PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll", 81183f191a7SVivek Gautam "phyclk_usbdrd300_udrd30_pipe_pclk" }; 81283f191a7SVivek Gautam 81383f191a7SVivek Gautam /* fixed rate clocks used in the FSYS0 block */ 81483f191a7SVivek Gautam struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { 81583f191a7SVivek Gautam FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 81683f191a7SVivek Gautam CLK_IS_ROOT, 60000000), 81783f191a7SVivek Gautam FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 81883f191a7SVivek Gautam CLK_IS_ROOT, 125000000), 81983f191a7SVivek Gautam }; 82083f191a7SVivek Gautam 8216d0c8c72SNaveen Krishna Ch static unsigned long fsys0_clk_regs[] __initdata = { 8226d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS00, 8236d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS01, 82483f191a7SVivek Gautam MUX_SEL_FSYS02, 82583f191a7SVivek Gautam ENABLE_ACLK_FSYS00, 8266d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS01, 82783f191a7SVivek Gautam ENABLE_SCLK_FSYS01, 82883f191a7SVivek Gautam ENABLE_SCLK_FSYS02, 82983f191a7SVivek Gautam ENABLE_SCLK_FSYS04, 8306d0c8c72SNaveen Krishna Ch }; 8316d0c8c72SNaveen Krishna Ch 8326d0c8c72SNaveen Krishna Ch static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { 8336d0c8c72SNaveen Krishna Ch MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p, 8346d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS00, 24, 1), 8356d0c8c72SNaveen Krishna Ch 8366d0c8c72SNaveen Krishna Ch MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), 83783f191a7SVivek Gautam MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p, 83883f191a7SVivek Gautam MUX_SEL_FSYS01, 28, 1), 83983f191a7SVivek Gautam 84083f191a7SVivek Gautam MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 84183f191a7SVivek Gautam mout_phyclk_usbdrd300_udrd30_pipe_pclk_p, 84283f191a7SVivek Gautam MUX_SEL_FSYS02, 24, 1), 84383f191a7SVivek Gautam MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user", 84483f191a7SVivek Gautam mout_phyclk_usbdrd300_udrd30_phyclk_p, 84583f191a7SVivek Gautam MUX_SEL_FSYS02, 28, 1), 8466d0c8c72SNaveen Krishna Ch }; 8476d0c8c72SNaveen Krishna Ch 8486d0c8c72SNaveen Krishna Ch static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 8499cc2a0c9SPadmavathi Venna GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", 8509cc2a0c9SPadmavathi Venna ENABLE_ACLK_FSYS00, 3, 0, 0), 8519cc2a0c9SPadmavathi Venna GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", 8529cc2a0c9SPadmavathi Venna ENABLE_ACLK_FSYS00, 4, 0, 0), 8537cca2e07SAlim Akhtar GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", 8547cca2e07SAlim Akhtar "mout_aclk_fsys0_200_user", 8557cca2e07SAlim Akhtar ENABLE_ACLK_FSYS00, 19, 0, 0), 85683f191a7SVivek Gautam 85783f191a7SVivek Gautam GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", 85883f191a7SVivek Gautam ENABLE_ACLK_FSYS01, 29, 0, 0), 8596d0c8c72SNaveen Krishna Ch GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 8606d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS01, 31, 0, 0), 86183f191a7SVivek Gautam 86283f191a7SVivek Gautam GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk", 86383f191a7SVivek Gautam "mout_sclk_usbdrd300_user", 86483f191a7SVivek Gautam ENABLE_SCLK_FSYS01, 4, 0, 0), 86583f191a7SVivek Gautam GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll", 86683f191a7SVivek Gautam ENABLE_SCLK_FSYS01, 8, 0, 0), 86783f191a7SVivek Gautam 86883f191a7SVivek Gautam GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER, 86983f191a7SVivek Gautam "phyclk_usbdrd300_udrd30_pipe_pclk_user", 87083f191a7SVivek Gautam "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 87183f191a7SVivek Gautam ENABLE_SCLK_FSYS02, 24, 0, 0), 87283f191a7SVivek Gautam GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER, 87383f191a7SVivek Gautam "phyclk_usbdrd300_udrd30_phyclk_user", 87483f191a7SVivek Gautam "mout_phyclk_usbdrd300_udrd30_phyclk_user", 87583f191a7SVivek Gautam ENABLE_SCLK_FSYS02, 28, 0, 0), 87683f191a7SVivek Gautam 87783f191a7SVivek Gautam GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy", 87883f191a7SVivek Gautam "fin_pll", 87983f191a7SVivek Gautam ENABLE_SCLK_FSYS04, 28, 0, 0), 8806d0c8c72SNaveen Krishna Ch }; 8816d0c8c72SNaveen Krishna Ch 8826d0c8c72SNaveen Krishna Ch static struct samsung_cmu_info fsys0_cmu_info __initdata = { 8836d0c8c72SNaveen Krishna Ch .mux_clks = fsys0_mux_clks, 8846d0c8c72SNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 8856d0c8c72SNaveen Krishna Ch .gate_clks = fsys0_gate_clks, 8866d0c8c72SNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 8877cca2e07SAlim Akhtar .nr_clk_ids = FSYS0_NR_CLK, 8886d0c8c72SNaveen Krishna Ch .clk_regs = fsys0_clk_regs, 8896d0c8c72SNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 8906d0c8c72SNaveen Krishna Ch }; 8916d0c8c72SNaveen Krishna Ch 8926d0c8c72SNaveen Krishna Ch static void __init exynos7_clk_fsys0_init(struct device_node *np) 8936d0c8c72SNaveen Krishna Ch { 8946d0c8c72SNaveen Krishna Ch samsung_cmu_register_one(np, &fsys0_cmu_info); 8956d0c8c72SNaveen Krishna Ch } 8966d0c8c72SNaveen Krishna Ch 8976d0c8c72SNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", 8986d0c8c72SNaveen Krishna Ch exynos7_clk_fsys0_init); 8996d0c8c72SNaveen Krishna Ch 9006d0c8c72SNaveen Krishna Ch /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ 9016d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS10 0x0200 9026d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS11 0x0204 9036d0c8c72SNaveen Krishna Ch #define ENABLE_ACLK_FSYS1 0x0800 9046d0c8c72SNaveen Krishna Ch 9056d0c8c72SNaveen Krishna Ch /* 9066d0c8c72SNaveen Krishna Ch * List of parent clocks for Muxes in CMU_FSYS1 9076d0c8c72SNaveen Krishna Ch */ 9086d0c8c72SNaveen Krishna Ch PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" }; 9096d0c8c72SNaveen Krishna Ch PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" }; 9106d0c8c72SNaveen Krishna Ch PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" }; 9116d0c8c72SNaveen Krishna Ch 9126d0c8c72SNaveen Krishna Ch static unsigned long fsys1_clk_regs[] __initdata = { 9136d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS10, 9146d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS11, 9156d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS1, 9166d0c8c72SNaveen Krishna Ch }; 9176d0c8c72SNaveen Krishna Ch 9186d0c8c72SNaveen Krishna Ch static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { 9196d0c8c72SNaveen Krishna Ch MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p, 9206d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS10, 28, 1), 9216d0c8c72SNaveen Krishna Ch 9226d0c8c72SNaveen Krishna Ch MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1), 9236d0c8c72SNaveen Krishna Ch MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1), 9246d0c8c72SNaveen Krishna Ch }; 9256d0c8c72SNaveen Krishna Ch 9266d0c8c72SNaveen Krishna Ch static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { 9276d0c8c72SNaveen Krishna Ch GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", 9286d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS1, 29, 0, 0), 9296d0c8c72SNaveen Krishna Ch GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", 9306d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS1, 30, 0, 0), 9316d0c8c72SNaveen Krishna Ch }; 9326d0c8c72SNaveen Krishna Ch 9336d0c8c72SNaveen Krishna Ch static struct samsung_cmu_info fsys1_cmu_info __initdata = { 9346d0c8c72SNaveen Krishna Ch .mux_clks = fsys1_mux_clks, 9356d0c8c72SNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 9366d0c8c72SNaveen Krishna Ch .gate_clks = fsys1_gate_clks, 9376d0c8c72SNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 9386d0c8c72SNaveen Krishna Ch .nr_clk_ids = TOP1_NR_CLK, 9396d0c8c72SNaveen Krishna Ch .clk_regs = fsys1_clk_regs, 9406d0c8c72SNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 9416d0c8c72SNaveen Krishna Ch }; 9426d0c8c72SNaveen Krishna Ch 9436d0c8c72SNaveen Krishna Ch static void __init exynos7_clk_fsys1_init(struct device_node *np) 9446d0c8c72SNaveen Krishna Ch { 9456d0c8c72SNaveen Krishna Ch samsung_cmu_register_one(np, &fsys1_cmu_info); 9466d0c8c72SNaveen Krishna Ch } 9476d0c8c72SNaveen Krishna Ch 9486d0c8c72SNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 9496d0c8c72SNaveen Krishna Ch exynos7_clk_fsys1_init); 95049cab82cSTony K Nadackal 95149cab82cSTony K Nadackal #define MUX_SEL_MSCL 0x0200 95249cab82cSTony K Nadackal #define DIV_MSCL 0x0600 95349cab82cSTony K Nadackal #define ENABLE_ACLK_MSCL 0x0800 95449cab82cSTony K Nadackal #define ENABLE_PCLK_MSCL 0x0900 95549cab82cSTony K Nadackal 95649cab82cSTony K Nadackal /* List of parent clocks for Muxes in CMU_MSCL */ 95749cab82cSTony K Nadackal PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; 95849cab82cSTony K Nadackal 95949cab82cSTony K Nadackal static unsigned long mscl_clk_regs[] __initdata = { 96049cab82cSTony K Nadackal MUX_SEL_MSCL, 96149cab82cSTony K Nadackal DIV_MSCL, 96249cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 96349cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 96449cab82cSTony K Nadackal }; 96549cab82cSTony K Nadackal 96649cab82cSTony K Nadackal static struct samsung_mux_clock mscl_mux_clks[] __initdata = { 96749cab82cSTony K Nadackal MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", 96849cab82cSTony K Nadackal mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), 96949cab82cSTony K Nadackal }; 97049cab82cSTony K Nadackal static struct samsung_div_clock mscl_div_clks[] __initdata = { 97149cab82cSTony K Nadackal DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", 97249cab82cSTony K Nadackal DIV_MSCL, 0, 3), 97349cab82cSTony K Nadackal }; 97449cab82cSTony K Nadackal static struct samsung_gate_clock mscl_gate_clks[] __initdata = { 97549cab82cSTony K Nadackal 97649cab82cSTony K Nadackal GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", 97749cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 31, 0, 0), 97849cab82cSTony K Nadackal GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532", 97949cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 30, 0, 0), 98049cab82cSTony K Nadackal GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532", 98149cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 29, 0, 0), 98249cab82cSTony K Nadackal GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532", 98349cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 28, 0, 0), 98449cab82cSTony K Nadackal GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0", 98549cab82cSTony K Nadackal "usermux_aclk_mscl_532", 98649cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 27, 0, 0), 98749cab82cSTony K Nadackal GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1", 98849cab82cSTony K Nadackal "usermux_aclk_mscl_532", 98949cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 26, 0, 0), 99049cab82cSTony K Nadackal GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532", 99149cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 25, 0, 0), 99249cab82cSTony K Nadackal GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532", 99349cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 24, 0, 0), 99449cab82cSTony K Nadackal GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge", 99549cab82cSTony K Nadackal "usermux_aclk_mscl_532", 99649cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 23, 0, 0), 99749cab82cSTony K Nadackal GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532", 99849cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 22, 0, 0), 99949cab82cSTony K Nadackal GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532", 100049cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 21, 0, 0), 100149cab82cSTony K Nadackal GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532", 100249cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 20, 0, 0), 100349cab82cSTony K Nadackal GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532", 100449cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 19, 0, 0), 100549cab82cSTony K Nadackal GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532", 100649cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 18, 0, 0), 100749cab82cSTony K Nadackal GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532", 100849cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 17, 0, 0), 100949cab82cSTony K Nadackal GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532", 101049cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 16, 0, 0), 101149cab82cSTony K Nadackal GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p", 101249cab82cSTony K Nadackal "usermux_aclk_mscl_532", 101349cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 15, 0, 0), 101449cab82cSTony K Nadackal GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p", 101549cab82cSTony K Nadackal "usermux_aclk_mscl_532", 101649cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 14, 0, 0), 101749cab82cSTony K Nadackal 101849cab82cSTony K Nadackal GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl", 101949cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 31, 0, 0), 102049cab82cSTony K Nadackal GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl", 102149cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 30, 0, 0), 102249cab82cSTony K Nadackal GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl", 102349cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 29, 0, 0), 102449cab82cSTony K Nadackal GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl", 102549cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 28, 0, 0), 102649cab82cSTony K Nadackal GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl", 102749cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 27, 0, 0), 102849cab82cSTony K Nadackal GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl", 102949cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 26, 0, 0), 103049cab82cSTony K Nadackal GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl", 103149cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 25, 0, 0), 103249cab82cSTony K Nadackal GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl", 103349cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 24, 0, 0), 103449cab82cSTony K Nadackal GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl", 103549cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 23, 0, 0), 103649cab82cSTony K Nadackal GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl", 103749cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 22, 0, 0), 103849cab82cSTony K Nadackal GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl", 103949cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 21, 0, 0), 104049cab82cSTony K Nadackal GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl", 104149cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 20, 0, 0), 104249cab82cSTony K Nadackal }; 104349cab82cSTony K Nadackal 104449cab82cSTony K Nadackal static struct samsung_cmu_info mscl_cmu_info __initdata = { 104549cab82cSTony K Nadackal .mux_clks = mscl_mux_clks, 104649cab82cSTony K Nadackal .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 104749cab82cSTony K Nadackal .div_clks = mscl_div_clks, 104849cab82cSTony K Nadackal .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 104949cab82cSTony K Nadackal .gate_clks = mscl_gate_clks, 105049cab82cSTony K Nadackal .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 105149cab82cSTony K Nadackal .nr_clk_ids = MSCL_NR_CLK, 105249cab82cSTony K Nadackal .clk_regs = mscl_clk_regs, 105349cab82cSTony K Nadackal .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 105449cab82cSTony K Nadackal }; 105549cab82cSTony K Nadackal 105649cab82cSTony K Nadackal static void __init exynos7_clk_mscl_init(struct device_node *np) 105749cab82cSTony K Nadackal { 105849cab82cSTony K Nadackal samsung_cmu_register_one(np, &mscl_cmu_info); 105949cab82cSTony K Nadackal } 106049cab82cSTony K Nadackal 106149cab82cSTony K Nadackal CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", 106249cab82cSTony K Nadackal exynos7_clk_mscl_init); 10639f930a39SPadmavathi Venna 10649f930a39SPadmavathi Venna /* Register Offset definitions for CMU_AUD (0x114C0000) */ 10659f930a39SPadmavathi Venna #define MUX_SEL_AUD 0x0200 10669f930a39SPadmavathi Venna #define DIV_AUD0 0x0600 10679f930a39SPadmavathi Venna #define DIV_AUD1 0x0604 10689f930a39SPadmavathi Venna #define ENABLE_ACLK_AUD 0x0800 10699f930a39SPadmavathi Venna #define ENABLE_PCLK_AUD 0x0900 10709f930a39SPadmavathi Venna #define ENABLE_SCLK_AUD 0x0A00 10719f930a39SPadmavathi Venna 10729f930a39SPadmavathi Venna /* 10739f930a39SPadmavathi Venna * List of parent clocks for Muxes in CMU_AUD 10749f930a39SPadmavathi Venna */ 10759f930a39SPadmavathi Venna PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; 10769f930a39SPadmavathi Venna PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; 10779f930a39SPadmavathi Venna 10789f930a39SPadmavathi Venna static unsigned long aud_clk_regs[] __initdata = { 10799f930a39SPadmavathi Venna MUX_SEL_AUD, 10809f930a39SPadmavathi Venna DIV_AUD0, 10819f930a39SPadmavathi Venna DIV_AUD1, 10829f930a39SPadmavathi Venna ENABLE_ACLK_AUD, 10839f930a39SPadmavathi Venna ENABLE_PCLK_AUD, 10849f930a39SPadmavathi Venna ENABLE_SCLK_AUD, 10859f930a39SPadmavathi Venna }; 10869f930a39SPadmavathi Venna 10879f930a39SPadmavathi Venna static struct samsung_mux_clock aud_mux_clks[] __initdata = { 10889f930a39SPadmavathi Venna MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), 10899f930a39SPadmavathi Venna MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), 10909f930a39SPadmavathi Venna MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), 10919f930a39SPadmavathi Venna }; 10929f930a39SPadmavathi Venna 10939f930a39SPadmavathi Venna static struct samsung_div_clock aud_div_clks[] __initdata = { 10949f930a39SPadmavathi Venna DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), 10959f930a39SPadmavathi Venna DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), 10969f930a39SPadmavathi Venna DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), 10979f930a39SPadmavathi Venna 10989f930a39SPadmavathi Venna DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4), 10999f930a39SPadmavathi Venna DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8), 11009f930a39SPadmavathi Venna DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4), 11019f930a39SPadmavathi Venna DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5), 11029f930a39SPadmavathi Venna DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), 11039f930a39SPadmavathi Venna }; 11049f930a39SPadmavathi Venna 11059f930a39SPadmavathi Venna static struct samsung_gate_clock aud_gate_clks[] __initdata = { 11069f930a39SPadmavathi Venna GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", 11079f930a39SPadmavathi Venna ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 11089f930a39SPadmavathi Venna GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", 11099f930a39SPadmavathi Venna ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0), 11109f930a39SPadmavathi Venna GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0), 11119f930a39SPadmavathi Venna GATE(0, "sclk_slimbus", "dout_sclk_slimbus", 11129f930a39SPadmavathi Venna ENABLE_SCLK_AUD, 30, 0, 0), 11139f930a39SPadmavathi Venna 11149f930a39SPadmavathi Venna GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), 11159f930a39SPadmavathi Venna GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), 11169f930a39SPadmavathi Venna GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), 11179f930a39SPadmavathi Venna GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), 11189f930a39SPadmavathi Venna GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), 11199f930a39SPadmavathi Venna GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), 11209f930a39SPadmavathi Venna GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud", 11219f930a39SPadmavathi Venna ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), 11229f930a39SPadmavathi Venna GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud", 11239f930a39SPadmavathi Venna ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 11249f930a39SPadmavathi Venna GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0), 11259f930a39SPadmavathi Venna GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0), 11269f930a39SPadmavathi Venna 11279f930a39SPadmavathi Venna GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0), 11289f930a39SPadmavathi Venna GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud", 11299f930a39SPadmavathi Venna ENABLE_ACLK_AUD, 28, 0, 0), 11309f930a39SPadmavathi Venna GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), 11319f930a39SPadmavathi Venna }; 11329f930a39SPadmavathi Venna 11339f930a39SPadmavathi Venna static struct samsung_cmu_info aud_cmu_info __initdata = { 11349f930a39SPadmavathi Venna .mux_clks = aud_mux_clks, 11359f930a39SPadmavathi Venna .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 11369f930a39SPadmavathi Venna .div_clks = aud_div_clks, 11379f930a39SPadmavathi Venna .nr_div_clks = ARRAY_SIZE(aud_div_clks), 11389f930a39SPadmavathi Venna .gate_clks = aud_gate_clks, 11399f930a39SPadmavathi Venna .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 11409f930a39SPadmavathi Venna .nr_clk_ids = AUD_NR_CLK, 11419f930a39SPadmavathi Venna .clk_regs = aud_clk_regs, 11429f930a39SPadmavathi Venna .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 11439f930a39SPadmavathi Venna }; 11449f930a39SPadmavathi Venna 11459f930a39SPadmavathi Venna static void __init exynos7_clk_aud_init(struct device_node *np) 11469f930a39SPadmavathi Venna { 11479f930a39SPadmavathi Venna samsung_cmu_register_one(np, &aud_cmu_info); 11489f930a39SPadmavathi Venna } 11499f930a39SPadmavathi Venna 11509f930a39SPadmavathi Venna CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", 11519f930a39SPadmavathi Venna exynos7_clk_aud_init); 1152