1532abc3aSNaveen Krishna Ch /* 2532abc3aSNaveen Krishna Ch * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3532abc3aSNaveen Krishna Ch * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4532abc3aSNaveen Krishna Ch * 5532abc3aSNaveen Krishna Ch * This program is free software; you can redistribute it and/or modify 6532abc3aSNaveen Krishna Ch * it under the terms of the GNU General Public License version 2 as 7532abc3aSNaveen Krishna Ch * published by the Free Software Foundation. 8532abc3aSNaveen Krishna Ch * 9532abc3aSNaveen Krishna Ch */ 10532abc3aSNaveen Krishna Ch 11532abc3aSNaveen Krishna Ch #include <linux/clk-provider.h> 12532abc3aSNaveen Krishna Ch #include <linux/of.h> 13532abc3aSNaveen Krishna Ch 14532abc3aSNaveen Krishna Ch #include "clk.h" 15532abc3aSNaveen Krishna Ch #include <dt-bindings/clock/exynos7-clk.h> 16532abc3aSNaveen Krishna Ch 17532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_TOPC (0x10570000) */ 18532abc3aSNaveen Krishna Ch #define CC_PLL_LOCK 0x0000 19532abc3aSNaveen Krishna Ch #define BUS0_PLL_LOCK 0x0004 20532abc3aSNaveen Krishna Ch #define BUS1_DPLL_LOCK 0x0008 21532abc3aSNaveen Krishna Ch #define MFC_PLL_LOCK 0x000C 22532abc3aSNaveen Krishna Ch #define AUD_PLL_LOCK 0x0010 23532abc3aSNaveen Krishna Ch #define CC_PLL_CON0 0x0100 24532abc3aSNaveen Krishna Ch #define BUS0_PLL_CON0 0x0110 25532abc3aSNaveen Krishna Ch #define BUS1_DPLL_CON0 0x0120 26532abc3aSNaveen Krishna Ch #define MFC_PLL_CON0 0x0130 27532abc3aSNaveen Krishna Ch #define AUD_PLL_CON0 0x0140 28532abc3aSNaveen Krishna Ch #define MUX_SEL_TOPC0 0x0200 29532abc3aSNaveen Krishna Ch #define MUX_SEL_TOPC1 0x0204 30f5e127cdSNaveen Krishna Ch #define MUX_SEL_TOPC2 0x0208 31532abc3aSNaveen Krishna Ch #define MUX_SEL_TOPC3 0x020C 32f5e127cdSNaveen Krishna Ch #define DIV_TOPC0 0x0600 33532abc3aSNaveen Krishna Ch #define DIV_TOPC1 0x0604 34532abc3aSNaveen Krishna Ch #define DIV_TOPC3 0x060C 352cbb5157SAlim Akhtar #define ENABLE_ACLK_TOPC0 0x0800 3649cab82cSTony K Nadackal #define ENABLE_ACLK_TOPC1 0x0804 372cbb5157SAlim Akhtar #define ENABLE_SCLK_TOPC1 0x0A04 38532abc3aSNaveen Krishna Ch 39532abc3aSNaveen Krishna Ch static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { 40dc504b22SAlim Akhtar FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0), 41532abc3aSNaveen Krishna Ch FFACTOR(0, "ffac_topc_bus0_pll_div4", 42532abc3aSNaveen Krishna Ch "ffac_topc_bus0_pll_div2", 1, 2, 0), 43dc504b22SAlim Akhtar FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0), 44dc504b22SAlim Akhtar FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0), 45dc504b22SAlim Akhtar FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0), 46532abc3aSNaveen Krishna Ch }; 47532abc3aSNaveen Krishna Ch 48532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_TOPC */ 49dc504b22SAlim Akhtar PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; 50dc504b22SAlim Akhtar PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 51dc504b22SAlim Akhtar PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 52dc504b22SAlim Akhtar PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 53dc504b22SAlim Akhtar PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; 54532abc3aSNaveen Krishna Ch 55dc504b22SAlim Akhtar PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half", 56dc504b22SAlim Akhtar "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half", 57dc504b22SAlim Akhtar "mout_topc_mfc_pll_half" }; 58532abc3aSNaveen Krishna Ch 59dc504b22SAlim Akhtar PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll", 60532abc3aSNaveen Krishna Ch "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; 61dc504b22SAlim Akhtar PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll", 62532abc3aSNaveen Krishna Ch "ffac_topc_bus1_pll_div2"}; 63dc504b22SAlim Akhtar PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll", 64532abc3aSNaveen Krishna Ch "ffac_topc_cc_pll_div2"}; 65dc504b22SAlim Akhtar PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll", 66532abc3aSNaveen Krishna Ch "ffac_topc_mfc_pll_div2"}; 67532abc3aSNaveen Krishna Ch 68532abc3aSNaveen Krishna Ch 69dc504b22SAlim Akhtar PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll", 70532abc3aSNaveen Krishna Ch "ffac_topc_bus0_pll_div2"}; 71532abc3aSNaveen Krishna Ch 72532abc3aSNaveen Krishna Ch static unsigned long topc_clk_regs[] __initdata = { 73532abc3aSNaveen Krishna Ch CC_PLL_LOCK, 74532abc3aSNaveen Krishna Ch BUS0_PLL_LOCK, 75532abc3aSNaveen Krishna Ch BUS1_DPLL_LOCK, 76532abc3aSNaveen Krishna Ch MFC_PLL_LOCK, 77532abc3aSNaveen Krishna Ch AUD_PLL_LOCK, 78532abc3aSNaveen Krishna Ch CC_PLL_CON0, 79532abc3aSNaveen Krishna Ch BUS0_PLL_CON0, 80532abc3aSNaveen Krishna Ch BUS1_DPLL_CON0, 81532abc3aSNaveen Krishna Ch MFC_PLL_CON0, 82532abc3aSNaveen Krishna Ch AUD_PLL_CON0, 83532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 84532abc3aSNaveen Krishna Ch MUX_SEL_TOPC1, 85f5e127cdSNaveen Krishna Ch MUX_SEL_TOPC2, 86532abc3aSNaveen Krishna Ch MUX_SEL_TOPC3, 87f5e127cdSNaveen Krishna Ch DIV_TOPC0, 88532abc3aSNaveen Krishna Ch DIV_TOPC1, 89532abc3aSNaveen Krishna Ch DIV_TOPC3, 90532abc3aSNaveen Krishna Ch }; 91532abc3aSNaveen Krishna Ch 92532abc3aSNaveen Krishna Ch static struct samsung_mux_clock topc_mux_clks[] __initdata = { 93dc504b22SAlim Akhtar MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, 94dc504b22SAlim Akhtar MUX_SEL_TOPC0, 0, 1), 95dc504b22SAlim Akhtar MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, 96dc504b22SAlim Akhtar MUX_SEL_TOPC0, 4, 1), 97dc504b22SAlim Akhtar MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p, 98dc504b22SAlim Akhtar MUX_SEL_TOPC0, 8, 1), 99dc504b22SAlim Akhtar MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p, 100dc504b22SAlim Akhtar MUX_SEL_TOPC0, 12, 1), 101dc504b22SAlim Akhtar MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p, 102532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 16, 2), 103dc504b22SAlim Akhtar MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p, 104532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 20, 1), 105dc504b22SAlim Akhtar MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p, 106532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 24, 1), 107dc504b22SAlim Akhtar MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p, 108532abc3aSNaveen Krishna Ch MUX_SEL_TOPC0, 28, 1), 109532abc3aSNaveen Krishna Ch 110dc504b22SAlim Akhtar MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p, 111dc504b22SAlim Akhtar MUX_SEL_TOPC1, 0, 1), 112dc504b22SAlim Akhtar MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p, 113532abc3aSNaveen Krishna Ch MUX_SEL_TOPC1, 16, 1), 114532abc3aSNaveen Krishna Ch 115f5e127cdSNaveen Krishna Ch MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 116f5e127cdSNaveen Krishna Ch 11749cab82cSTony K Nadackal MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2), 118532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 119532abc3aSNaveen Krishna Ch }; 120532abc3aSNaveen Krishna Ch 121532abc3aSNaveen Krishna Ch static struct samsung_div_clock topc_div_clks[] __initdata = { 122f5e127cdSNaveen Krishna Ch DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 123f5e127cdSNaveen Krishna Ch DIV_TOPC0, 4, 4), 124f5e127cdSNaveen Krishna Ch 12549cab82cSTony K Nadackal DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532", 12649cab82cSTony K Nadackal DIV_TOPC1, 20, 4), 127532abc3aSNaveen Krishna Ch DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 128532abc3aSNaveen Krishna Ch DIV_TOPC1, 24, 4), 129532abc3aSNaveen Krishna Ch 130dc504b22SAlim Akhtar DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out", 131fa9f3a52SAlim Akhtar DIV_TOPC3, 0, 4), 132dc504b22SAlim Akhtar DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll", 133fa9f3a52SAlim Akhtar DIV_TOPC3, 8, 4), 134dc504b22SAlim Akhtar DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll", 135fa9f3a52SAlim Akhtar DIV_TOPC3, 12, 4), 136dc504b22SAlim Akhtar DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll", 137fa9f3a52SAlim Akhtar DIV_TOPC3, 16, 4), 138dc504b22SAlim Akhtar DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll", 139fa9f3a52SAlim Akhtar DIV_TOPC3, 28, 4), 1409f930a39SPadmavathi Venna }; 1419f930a39SPadmavathi Venna 1429f930a39SPadmavathi Venna static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { 1439f930a39SPadmavathi Venna PLL_36XX_RATE(491520000, 20, 1, 0, 31457), 1449f930a39SPadmavathi Venna {}, 145532abc3aSNaveen Krishna Ch }; 146532abc3aSNaveen Krishna Ch 14749cab82cSTony K Nadackal static struct samsung_gate_clock topc_gate_clks[] __initdata = { 1482cbb5157SAlim Akhtar GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133", 1492cbb5157SAlim Akhtar ENABLE_ACLK_TOPC0, 4, 0, 0), 1502cbb5157SAlim Akhtar 15149cab82cSTony K Nadackal GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", 15249cab82cSTony K Nadackal ENABLE_ACLK_TOPC1, 20, 0, 0), 1532cbb5157SAlim Akhtar 1542cbb5157SAlim Akhtar GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66", 1552cbb5157SAlim Akhtar ENABLE_ACLK_TOPC1, 24, 0, 0), 1562cbb5157SAlim Akhtar 1572cbb5157SAlim Akhtar GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll", 1582cbb5157SAlim Akhtar ENABLE_SCLK_TOPC1, 20, 0, 0), 1592cbb5157SAlim Akhtar GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll", 1602cbb5157SAlim Akhtar ENABLE_SCLK_TOPC1, 17, 0, 0), 1612cbb5157SAlim Akhtar GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll", 1622cbb5157SAlim Akhtar ENABLE_SCLK_TOPC1, 16, 0, 0), 1632cbb5157SAlim Akhtar GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll", 1642cbb5157SAlim Akhtar ENABLE_SCLK_TOPC1, 13, 0, 0), 1652cbb5157SAlim Akhtar GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll", 1662cbb5157SAlim Akhtar ENABLE_SCLK_TOPC1, 12, 0, 0), 1672cbb5157SAlim Akhtar GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll", 1682cbb5157SAlim Akhtar ENABLE_SCLK_TOPC1, 5, 0, 0), 1692cbb5157SAlim Akhtar GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll", 1702cbb5157SAlim Akhtar ENABLE_SCLK_TOPC1, 4, 0, 0), 1712cbb5157SAlim Akhtar GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll", 1722cbb5157SAlim Akhtar ENABLE_SCLK_TOPC1, 1, 0, 0), 1732cbb5157SAlim Akhtar GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll", 1742cbb5157SAlim Akhtar ENABLE_SCLK_TOPC1, 0, 0, 0), 17549cab82cSTony K Nadackal }; 17649cab82cSTony K Nadackal 177532abc3aSNaveen Krishna Ch static struct samsung_pll_clock topc_pll_clks[] __initdata = { 178532abc3aSNaveen Krishna Ch PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 179532abc3aSNaveen Krishna Ch BUS0_PLL_CON0, NULL), 180532abc3aSNaveen Krishna Ch PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 181532abc3aSNaveen Krishna Ch CC_PLL_CON0, NULL), 182532abc3aSNaveen Krishna Ch PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, 183532abc3aSNaveen Krishna Ch BUS1_DPLL_CON0, NULL), 184532abc3aSNaveen Krishna Ch PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 185532abc3aSNaveen Krishna Ch MFC_PLL_CON0, NULL), 1869f930a39SPadmavathi Venna PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 1879f930a39SPadmavathi Venna AUD_PLL_CON0, pll1460x_24mhz_tbl), 188532abc3aSNaveen Krishna Ch }; 189532abc3aSNaveen Krishna Ch 190532abc3aSNaveen Krishna Ch static struct samsung_cmu_info topc_cmu_info __initdata = { 191532abc3aSNaveen Krishna Ch .pll_clks = topc_pll_clks, 192532abc3aSNaveen Krishna Ch .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 193532abc3aSNaveen Krishna Ch .mux_clks = topc_mux_clks, 194532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 195532abc3aSNaveen Krishna Ch .div_clks = topc_div_clks, 196532abc3aSNaveen Krishna Ch .nr_div_clks = ARRAY_SIZE(topc_div_clks), 19749cab82cSTony K Nadackal .gate_clks = topc_gate_clks, 19849cab82cSTony K Nadackal .nr_gate_clks = ARRAY_SIZE(topc_gate_clks), 199532abc3aSNaveen Krishna Ch .fixed_factor_clks = topc_fixed_factor_clks, 200532abc3aSNaveen Krishna Ch .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 201532abc3aSNaveen Krishna Ch .nr_clk_ids = TOPC_NR_CLK, 202532abc3aSNaveen Krishna Ch .clk_regs = topc_clk_regs, 203532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), 204532abc3aSNaveen Krishna Ch }; 205532abc3aSNaveen Krishna Ch 206532abc3aSNaveen Krishna Ch static void __init exynos7_clk_topc_init(struct device_node *np) 207532abc3aSNaveen Krishna Ch { 208532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &topc_cmu_info); 209532abc3aSNaveen Krishna Ch } 210532abc3aSNaveen Krishna Ch 211532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", 212532abc3aSNaveen Krishna Ch exynos7_clk_topc_init); 213532abc3aSNaveen Krishna Ch 214532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ 215532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP00 0x0200 216532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP01 0x0204 217532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP03 0x020C 2189f930a39SPadmavathi Venna #define MUX_SEL_TOP0_PERIC0 0x0230 219ee74b56aSPadmavathi Venna #define MUX_SEL_TOP0_PERIC1 0x0234 220ee74b56aSPadmavathi Venna #define MUX_SEL_TOP0_PERIC2 0x0238 221532abc3aSNaveen Krishna Ch #define MUX_SEL_TOP0_PERIC3 0x023C 222532abc3aSNaveen Krishna Ch #define DIV_TOP03 0x060C 2239f930a39SPadmavathi Venna #define DIV_TOP0_PERIC0 0x0630 224ee74b56aSPadmavathi Venna #define DIV_TOP0_PERIC1 0x0634 225ee74b56aSPadmavathi Venna #define DIV_TOP0_PERIC2 0x0638 226532abc3aSNaveen Krishna Ch #define DIV_TOP0_PERIC3 0x063C 2273f54fb1eSAlim Akhtar #define ENABLE_ACLK_TOP03 0x080C 2289f930a39SPadmavathi Venna #define ENABLE_SCLK_TOP0_PERIC0 0x0A30 229ee74b56aSPadmavathi Venna #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 230ee74b56aSPadmavathi Venna #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 231532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 232532abc3aSNaveen Krishna Ch 233532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_TOP0 */ 234cf5ee64cSAlim Akhtar PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" }; 235cf5ee64cSAlim Akhtar PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" }; 236cf5ee64cSAlim Akhtar PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" }; 237cf5ee64cSAlim Akhtar PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" }; 238cf5ee64cSAlim Akhtar PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" }; 239532abc3aSNaveen Krishna Ch 240cf5ee64cSAlim Akhtar PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user", 241532abc3aSNaveen Krishna Ch "ffac_top0_bus0_pll_div2"}; 242cf5ee64cSAlim Akhtar PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user", 243532abc3aSNaveen Krishna Ch "ffac_top0_bus1_pll_div2"}; 244cf5ee64cSAlim Akhtar PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user", 245532abc3aSNaveen Krishna Ch "ffac_top0_cc_pll_div2"}; 246cf5ee64cSAlim Akhtar PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user", 247532abc3aSNaveen Krishna Ch "ffac_top0_mfc_pll_div2"}; 248532abc3aSNaveen Krishna Ch 249cf5ee64cSAlim Akhtar PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half", 250cf5ee64cSAlim Akhtar "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half", 251cf5ee64cSAlim Akhtar "mout_top0_mfc_pll_half"}; 2529f930a39SPadmavathi Venna PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", 2539f930a39SPadmavathi Venna "ioclk_audiocdclk1", "ioclk_spdif_extclk", 254cf5ee64cSAlim Akhtar "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half", 255cf5ee64cSAlim Akhtar "mout_top0_bus1_pll_half"}; 256cf5ee64cSAlim Akhtar PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user", 257cf5ee64cSAlim Akhtar "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"}; 258532abc3aSNaveen Krishna Ch 259532abc3aSNaveen Krishna Ch static unsigned long top0_clk_regs[] __initdata = { 260532abc3aSNaveen Krishna Ch MUX_SEL_TOP00, 261532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 262532abc3aSNaveen Krishna Ch MUX_SEL_TOP03, 2639f930a39SPadmavathi Venna MUX_SEL_TOP0_PERIC0, 264ee74b56aSPadmavathi Venna MUX_SEL_TOP0_PERIC1, 265ee74b56aSPadmavathi Venna MUX_SEL_TOP0_PERIC2, 266532abc3aSNaveen Krishna Ch MUX_SEL_TOP0_PERIC3, 267532abc3aSNaveen Krishna Ch DIV_TOP03, 2689f930a39SPadmavathi Venna DIV_TOP0_PERIC0, 269ee74b56aSPadmavathi Venna DIV_TOP0_PERIC1, 270ee74b56aSPadmavathi Venna DIV_TOP0_PERIC2, 271532abc3aSNaveen Krishna Ch DIV_TOP0_PERIC3, 2729f930a39SPadmavathi Venna ENABLE_SCLK_TOP0_PERIC0, 273ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC1, 274ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC2, 275532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 276532abc3aSNaveen Krishna Ch }; 277532abc3aSNaveen Krishna Ch 278532abc3aSNaveen Krishna Ch static struct samsung_mux_clock top0_mux_clks[] __initdata = { 279cf5ee64cSAlim Akhtar MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p, 280cf5ee64cSAlim Akhtar MUX_SEL_TOP00, 0, 1), 281cf5ee64cSAlim Akhtar MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p, 282cf5ee64cSAlim Akhtar MUX_SEL_TOP00, 4, 1), 283cf5ee64cSAlim Akhtar MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p, 284cf5ee64cSAlim Akhtar MUX_SEL_TOP00, 8, 1), 285cf5ee64cSAlim Akhtar MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p, 286cf5ee64cSAlim Akhtar MUX_SEL_TOP00, 12, 1), 287cf5ee64cSAlim Akhtar MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p, 288cf5ee64cSAlim Akhtar MUX_SEL_TOP00, 16, 1), 289532abc3aSNaveen Krishna Ch 290cf5ee64cSAlim Akhtar MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p, 291532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 4, 1), 292cf5ee64cSAlim Akhtar MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p, 293532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 8, 1), 294cf5ee64cSAlim Akhtar MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p, 295532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 12, 1), 296cf5ee64cSAlim Akhtar MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p, 297532abc3aSNaveen Krishna Ch MUX_SEL_TOP01, 16, 1), 298532abc3aSNaveen Krishna Ch 299532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 300532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 301532abc3aSNaveen Krishna Ch 3029f930a39SPadmavathi Venna MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3), 3039f930a39SPadmavathi Venna MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2), 3049f930a39SPadmavathi Venna MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2), 3059f930a39SPadmavathi Venna 306ee74b56aSPadmavathi Venna MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2), 307ee74b56aSPadmavathi Venna MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2), 308ee74b56aSPadmavathi Venna 309ee74b56aSPadmavathi Venna MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2), 310ee74b56aSPadmavathi Venna MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2), 311532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 312532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 313532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 314532abc3aSNaveen Krishna Ch MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 315ee74b56aSPadmavathi Venna MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), 316532abc3aSNaveen Krishna Ch }; 317532abc3aSNaveen Krishna Ch 318532abc3aSNaveen Krishna Ch static struct samsung_div_clock top0_div_clks[] __initdata = { 319532abc3aSNaveen Krishna Ch DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 320532abc3aSNaveen Krishna Ch DIV_TOP03, 12, 6), 321532abc3aSNaveen Krishna Ch DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 322532abc3aSNaveen Krishna Ch DIV_TOP03, 20, 6), 323532abc3aSNaveen Krishna Ch 3249f930a39SPadmavathi Venna DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4), 3259f930a39SPadmavathi Venna DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12), 3269f930a39SPadmavathi Venna DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10), 3279f930a39SPadmavathi Venna 328ee74b56aSPadmavathi Venna DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12), 329ee74b56aSPadmavathi Venna DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12), 330ee74b56aSPadmavathi Venna 331ee74b56aSPadmavathi Venna DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12), 332ee74b56aSPadmavathi Venna DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12), 333ee74b56aSPadmavathi Venna 334532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 335532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 336532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 337532abc3aSNaveen Krishna Ch DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 338ee74b56aSPadmavathi Venna DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), 339532abc3aSNaveen Krishna Ch }; 340532abc3aSNaveen Krishna Ch 341532abc3aSNaveen Krishna Ch static struct samsung_gate_clock top0_gate_clks[] __initdata = { 3423f54fb1eSAlim Akhtar GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66", 3433f54fb1eSAlim Akhtar ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0), 34433b8b739SAlim Akhtar GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66", 34533b8b739SAlim Akhtar ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0), 3463f54fb1eSAlim Akhtar 3479f930a39SPadmavathi Venna GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", 3489f930a39SPadmavathi Venna ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 3499f930a39SPadmavathi Venna GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1", 3509f930a39SPadmavathi Venna ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 3519f930a39SPadmavathi Venna GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1", 3529f930a39SPadmavathi Venna ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0), 3539f930a39SPadmavathi Venna 354ee74b56aSPadmavathi Venna GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1", 355ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0), 356ee74b56aSPadmavathi Venna GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0", 357ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 358ee74b56aSPadmavathi Venna 359ee74b56aSPadmavathi Venna GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3", 360ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0), 361ee74b56aSPadmavathi Venna GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2", 362ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0), 363532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 364532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 365532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 366532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), 367532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", 368532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 369532abc3aSNaveen Krishna Ch GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 370532abc3aSNaveen Krishna Ch ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 371ee74b56aSPadmavathi Venna GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4", 372ee74b56aSPadmavathi Venna ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), 373532abc3aSNaveen Krishna Ch }; 374532abc3aSNaveen Krishna Ch 375532abc3aSNaveen Krishna Ch static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { 376cf5ee64cSAlim Akhtar FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user", 377cf5ee64cSAlim Akhtar 1, 2, 0), 378cf5ee64cSAlim Akhtar FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user", 379cf5ee64cSAlim Akhtar 1, 2, 0), 380cf5ee64cSAlim Akhtar FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0), 381cf5ee64cSAlim Akhtar FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0), 382532abc3aSNaveen Krishna Ch }; 383532abc3aSNaveen Krishna Ch 384532abc3aSNaveen Krishna Ch static struct samsung_cmu_info top0_cmu_info __initdata = { 385532abc3aSNaveen Krishna Ch .mux_clks = top0_mux_clks, 386532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 387532abc3aSNaveen Krishna Ch .div_clks = top0_div_clks, 388532abc3aSNaveen Krishna Ch .nr_div_clks = ARRAY_SIZE(top0_div_clks), 389532abc3aSNaveen Krishna Ch .gate_clks = top0_gate_clks, 390532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), 391532abc3aSNaveen Krishna Ch .fixed_factor_clks = top0_fixed_factor_clks, 392532abc3aSNaveen Krishna Ch .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), 393532abc3aSNaveen Krishna Ch .nr_clk_ids = TOP0_NR_CLK, 394532abc3aSNaveen Krishna Ch .clk_regs = top0_clk_regs, 395532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), 396532abc3aSNaveen Krishna Ch }; 397532abc3aSNaveen Krishna Ch 398532abc3aSNaveen Krishna Ch static void __init exynos7_clk_top0_init(struct device_node *np) 399532abc3aSNaveen Krishna Ch { 400532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &top0_cmu_info); 401532abc3aSNaveen Krishna Ch } 402532abc3aSNaveen Krishna Ch 403532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 404532abc3aSNaveen Krishna Ch exynos7_clk_top0_init); 405532abc3aSNaveen Krishna Ch 4066d0c8c72SNaveen Krishna Ch /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ 4076d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP10 0x0200 4086d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP11 0x0204 4096d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP13 0x020C 4106d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP1_FSYS0 0x0224 4116d0c8c72SNaveen Krishna Ch #define MUX_SEL_TOP1_FSYS1 0x0228 412cfc7588aSAlim Akhtar #define MUX_SEL_TOP1_FSYS11 0x022C 4136d0c8c72SNaveen Krishna Ch #define DIV_TOP13 0x060C 4146d0c8c72SNaveen Krishna Ch #define DIV_TOP1_FSYS0 0x0624 4156d0c8c72SNaveen Krishna Ch #define DIV_TOP1_FSYS1 0x0628 416cfc7588aSAlim Akhtar #define DIV_TOP1_FSYS11 0x062C 4176d0c8c72SNaveen Krishna Ch #define ENABLE_ACLK_TOP13 0x080C 4186d0c8c72SNaveen Krishna Ch #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 4196d0c8c72SNaveen Krishna Ch #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 420cfc7588aSAlim Akhtar #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C 4216d0c8c72SNaveen Krishna Ch 4226d0c8c72SNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_TOP1 */ 4239b3ad363SAlim Akhtar PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" }; 4249b3ad363SAlim Akhtar PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" }; 4259b3ad363SAlim Akhtar PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" }; 4269b3ad363SAlim Akhtar PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" }; 4276d0c8c72SNaveen Krishna Ch 4289b3ad363SAlim Akhtar PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user", 4296d0c8c72SNaveen Krishna Ch "ffac_top1_bus0_pll_div2"}; 4309b3ad363SAlim Akhtar PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user", 4316d0c8c72SNaveen Krishna Ch "ffac_top1_bus1_pll_div2"}; 4329b3ad363SAlim Akhtar PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user", 4336d0c8c72SNaveen Krishna Ch "ffac_top1_cc_pll_div2"}; 4349b3ad363SAlim Akhtar PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user", 4356d0c8c72SNaveen Krishna Ch "ffac_top1_mfc_pll_div2"}; 4366d0c8c72SNaveen Krishna Ch 4379b3ad363SAlim Akhtar PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half", 4389b3ad363SAlim Akhtar "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half", 4399b3ad363SAlim Akhtar "mout_top1_mfc_pll_half"}; 4406d0c8c72SNaveen Krishna Ch 4416d0c8c72SNaveen Krishna Ch static unsigned long top1_clk_regs[] __initdata = { 4426d0c8c72SNaveen Krishna Ch MUX_SEL_TOP10, 4436d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 4446d0c8c72SNaveen Krishna Ch MUX_SEL_TOP13, 4456d0c8c72SNaveen Krishna Ch MUX_SEL_TOP1_FSYS0, 4466d0c8c72SNaveen Krishna Ch MUX_SEL_TOP1_FSYS1, 447cfc7588aSAlim Akhtar MUX_SEL_TOP1_FSYS11, 4486d0c8c72SNaveen Krishna Ch DIV_TOP13, 4496d0c8c72SNaveen Krishna Ch DIV_TOP1_FSYS0, 4506d0c8c72SNaveen Krishna Ch DIV_TOP1_FSYS1, 451cfc7588aSAlim Akhtar DIV_TOP1_FSYS11, 4526d0c8c72SNaveen Krishna Ch ENABLE_ACLK_TOP13, 4536d0c8c72SNaveen Krishna Ch ENABLE_SCLK_TOP1_FSYS0, 4546d0c8c72SNaveen Krishna Ch ENABLE_SCLK_TOP1_FSYS1, 455cfc7588aSAlim Akhtar ENABLE_SCLK_TOP1_FSYS11, 4566d0c8c72SNaveen Krishna Ch }; 4576d0c8c72SNaveen Krishna Ch 4586d0c8c72SNaveen Krishna Ch static struct samsung_mux_clock top1_mux_clks[] __initdata = { 4599b3ad363SAlim Akhtar MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p, 4609b3ad363SAlim Akhtar MUX_SEL_TOP10, 4, 1), 4619b3ad363SAlim Akhtar MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p, 4629b3ad363SAlim Akhtar MUX_SEL_TOP10, 8, 1), 4639b3ad363SAlim Akhtar MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p, 4646d0c8c72SNaveen Krishna Ch MUX_SEL_TOP10, 12, 1), 4659b3ad363SAlim Akhtar MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p, 4666d0c8c72SNaveen Krishna Ch MUX_SEL_TOP10, 16, 1), 4676d0c8c72SNaveen Krishna Ch 4689b3ad363SAlim Akhtar MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p, 4696d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 4, 1), 4709b3ad363SAlim Akhtar MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p, 4716d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 8, 1), 4729b3ad363SAlim Akhtar MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p, 4736d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 12, 1), 4749b3ad363SAlim Akhtar MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p, 4756d0c8c72SNaveen Krishna Ch MUX_SEL_TOP11, 16, 1), 4766d0c8c72SNaveen Krishna Ch 4776d0c8c72SNaveen Krishna Ch MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), 4786d0c8c72SNaveen Krishna Ch MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 4796d0c8c72SNaveen Krishna Ch 480cfc7588aSAlim Akhtar MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2), 48183f191a7SVivek Gautam MUX(0, "mout_sclk_usbdrd300", mout_top1_group1, 48283f191a7SVivek Gautam MUX_SEL_TOP1_FSYS0, 28, 2), 4836d0c8c72SNaveen Krishna Ch 484cfc7588aSAlim Akhtar MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2), 485cfc7588aSAlim Akhtar MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2), 4866d0c8c72SNaveen Krishna Ch }; 4876d0c8c72SNaveen Krishna Ch 4886d0c8c72SNaveen Krishna Ch static struct samsung_div_clock top1_div_clks[] __initdata = { 4896d0c8c72SNaveen Krishna Ch DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 4906d0c8c72SNaveen Krishna Ch DIV_TOP13, 24, 4), 4916d0c8c72SNaveen Krishna Ch DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 4926d0c8c72SNaveen Krishna Ch DIV_TOP13, 28, 4), 4936d0c8c72SNaveen Krishna Ch 4946d0c8c72SNaveen Krishna Ch DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 495cfc7588aSAlim Akhtar DIV_TOP1_FSYS0, 16, 10), 49683f191a7SVivek Gautam DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300", 49783f191a7SVivek Gautam DIV_TOP1_FSYS0, 28, 4), 4986d0c8c72SNaveen Krishna Ch 4996d0c8c72SNaveen Krishna Ch DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 500cfc7588aSAlim Akhtar DIV_TOP1_FSYS11, 0, 10), 5016d0c8c72SNaveen Krishna Ch DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", 502cfc7588aSAlim Akhtar DIV_TOP1_FSYS11, 12, 10), 5036d0c8c72SNaveen Krishna Ch }; 5046d0c8c72SNaveen Krishna Ch 5056d0c8c72SNaveen Krishna Ch static struct samsung_gate_clock top1_gate_clks[] __initdata = { 5066d0c8c72SNaveen Krishna Ch GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 507cfc7588aSAlim Akhtar ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), 50883f191a7SVivek Gautam GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", 50983f191a7SVivek Gautam ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0), 5106d0c8c72SNaveen Krishna Ch 5116d0c8c72SNaveen Krishna Ch GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 512cfc7588aSAlim Akhtar ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), 5136d0c8c72SNaveen Krishna Ch GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", 514cfc7588aSAlim Akhtar ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), 515a259a61bSAlim Akhtar 516a259a61bSAlim Akhtar GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200", 517a259a61bSAlim Akhtar ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0), 518753195a7SAlim Akhtar GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", 519753195a7SAlim Akhtar ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), 5206d0c8c72SNaveen Krishna Ch }; 5216d0c8c72SNaveen Krishna Ch 5226d0c8c72SNaveen Krishna Ch static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { 5239b3ad363SAlim Akhtar FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user", 5249b3ad363SAlim Akhtar 1, 2, 0), 5259b3ad363SAlim Akhtar FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user", 5269b3ad363SAlim Akhtar 1, 2, 0), 5279b3ad363SAlim Akhtar FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0), 5289b3ad363SAlim Akhtar FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0), 5296d0c8c72SNaveen Krishna Ch }; 5306d0c8c72SNaveen Krishna Ch 5316d0c8c72SNaveen Krishna Ch static struct samsung_cmu_info top1_cmu_info __initdata = { 5326d0c8c72SNaveen Krishna Ch .mux_clks = top1_mux_clks, 5336d0c8c72SNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 5346d0c8c72SNaveen Krishna Ch .div_clks = top1_div_clks, 5356d0c8c72SNaveen Krishna Ch .nr_div_clks = ARRAY_SIZE(top1_div_clks), 5366d0c8c72SNaveen Krishna Ch .gate_clks = top1_gate_clks, 5376d0c8c72SNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), 5386d0c8c72SNaveen Krishna Ch .fixed_factor_clks = top1_fixed_factor_clks, 5396d0c8c72SNaveen Krishna Ch .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), 5406d0c8c72SNaveen Krishna Ch .nr_clk_ids = TOP1_NR_CLK, 5416d0c8c72SNaveen Krishna Ch .clk_regs = top1_clk_regs, 5426d0c8c72SNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), 5436d0c8c72SNaveen Krishna Ch }; 5446d0c8c72SNaveen Krishna Ch 5456d0c8c72SNaveen Krishna Ch static void __init exynos7_clk_top1_init(struct device_node *np) 5466d0c8c72SNaveen Krishna Ch { 5476d0c8c72SNaveen Krishna Ch samsung_cmu_register_one(np, &top1_cmu_info); 5486d0c8c72SNaveen Krishna Ch } 5496d0c8c72SNaveen Krishna Ch 5506d0c8c72SNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", 5516d0c8c72SNaveen Krishna Ch exynos7_clk_top1_init); 5526d0c8c72SNaveen Krishna Ch 553f5e127cdSNaveen Krishna Ch /* Register Offset definitions for CMU_CCORE (0x105B0000) */ 554f5e127cdSNaveen Krishna Ch #define MUX_SEL_CCORE 0x0200 555f5e127cdSNaveen Krishna Ch #define DIV_CCORE 0x0600 556f5e127cdSNaveen Krishna Ch #define ENABLE_ACLK_CCORE0 0x0800 557f5e127cdSNaveen Krishna Ch #define ENABLE_ACLK_CCORE1 0x0804 558f5e127cdSNaveen Krishna Ch #define ENABLE_PCLK_CCORE 0x0900 559f5e127cdSNaveen Krishna Ch 560f5e127cdSNaveen Krishna Ch /* 561f5e127cdSNaveen Krishna Ch * List of parent clocks for Muxes in CMU_CCORE 562f5e127cdSNaveen Krishna Ch */ 56356365ee8SAlim Akhtar PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" }; 564f5e127cdSNaveen Krishna Ch 565f5e127cdSNaveen Krishna Ch static unsigned long ccore_clk_regs[] __initdata = { 566f5e127cdSNaveen Krishna Ch MUX_SEL_CCORE, 567f5e127cdSNaveen Krishna Ch ENABLE_PCLK_CCORE, 568f5e127cdSNaveen Krishna Ch }; 569f5e127cdSNaveen Krishna Ch 570f5e127cdSNaveen Krishna Ch static struct samsung_mux_clock ccore_mux_clks[] __initdata = { 57156365ee8SAlim Akhtar MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p, 572f5e127cdSNaveen Krishna Ch MUX_SEL_CCORE, 1, 1), 573f5e127cdSNaveen Krishna Ch }; 574f5e127cdSNaveen Krishna Ch 575f5e127cdSNaveen Krishna Ch static struct samsung_gate_clock ccore_gate_clks[] __initdata = { 576f5e127cdSNaveen Krishna Ch GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 577f5e127cdSNaveen Krishna Ch ENABLE_PCLK_CCORE, 8, 0, 0), 578f5e127cdSNaveen Krishna Ch }; 579f5e127cdSNaveen Krishna Ch 580f5e127cdSNaveen Krishna Ch static struct samsung_cmu_info ccore_cmu_info __initdata = { 581f5e127cdSNaveen Krishna Ch .mux_clks = ccore_mux_clks, 582f5e127cdSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 583f5e127cdSNaveen Krishna Ch .gate_clks = ccore_gate_clks, 584f5e127cdSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), 585f5e127cdSNaveen Krishna Ch .nr_clk_ids = CCORE_NR_CLK, 586f5e127cdSNaveen Krishna Ch .clk_regs = ccore_clk_regs, 587f5e127cdSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), 588f5e127cdSNaveen Krishna Ch }; 589f5e127cdSNaveen Krishna Ch 590f5e127cdSNaveen Krishna Ch static void __init exynos7_clk_ccore_init(struct device_node *np) 591f5e127cdSNaveen Krishna Ch { 592f5e127cdSNaveen Krishna Ch samsung_cmu_register_one(np, &ccore_cmu_info); 593f5e127cdSNaveen Krishna Ch } 594f5e127cdSNaveen Krishna Ch 595f5e127cdSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", 596f5e127cdSNaveen Krishna Ch exynos7_clk_ccore_init); 597f5e127cdSNaveen Krishna Ch 598532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ 599532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIC0 0x0200 600532abc3aSNaveen Krishna Ch #define ENABLE_PCLK_PERIC0 0x0900 601532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_PERIC0 0x0A00 602532abc3aSNaveen Krishna Ch 603532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_PERIC0 */ 6043f54fb1eSAlim Akhtar PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" }; 6053f54fb1eSAlim Akhtar PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" }; 606532abc3aSNaveen Krishna Ch 607532abc3aSNaveen Krishna Ch static unsigned long peric0_clk_regs[] __initdata = { 608532abc3aSNaveen Krishna Ch MUX_SEL_PERIC0, 609532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC0, 610532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC0, 611532abc3aSNaveen Krishna Ch }; 612532abc3aSNaveen Krishna Ch 613532abc3aSNaveen Krishna Ch static struct samsung_mux_clock peric0_mux_clks[] __initdata = { 6143f54fb1eSAlim Akhtar MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p, 615532abc3aSNaveen Krishna Ch MUX_SEL_PERIC0, 0, 1), 6163f54fb1eSAlim Akhtar MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p, 617532abc3aSNaveen Krishna Ch MUX_SEL_PERIC0, 16, 1), 618532abc3aSNaveen Krishna Ch }; 619532abc3aSNaveen Krishna Ch 620532abc3aSNaveen Krishna Ch static struct samsung_gate_clock peric0_gate_clks[] __initdata = { 62157a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 62257a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 8, 0, 0), 62357a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 62457a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 9, 0, 0), 62557a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", 62657a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 10, 0, 0), 62757a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", 62857a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 11, 0, 0), 62957a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", 63057a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 12, 0, 0), 63157a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", 63257a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 13, 0, 0), 63357a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", 63457a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 14, 0, 0), 635532abc3aSNaveen Krishna Ch GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 636532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC0, 16, 0, 0), 637932e9822SAbhilash Kesavan GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", 638932e9822SAbhilash Kesavan ENABLE_PCLK_PERIC0, 20, 0, 0), 6392ab2dfe5SNaveen Krishna Ch GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 6402ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIC0, 21, 0, 0), 641532abc3aSNaveen Krishna Ch 642532abc3aSNaveen Krishna Ch GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", 643532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC0, 16, 0, 0), 6442ab2dfe5SNaveen Krishna Ch GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 645532abc3aSNaveen Krishna Ch }; 646532abc3aSNaveen Krishna Ch 647532abc3aSNaveen Krishna Ch static struct samsung_cmu_info peric0_cmu_info __initdata = { 648532abc3aSNaveen Krishna Ch .mux_clks = peric0_mux_clks, 649532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 650532abc3aSNaveen Krishna Ch .gate_clks = peric0_gate_clks, 651532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 652532abc3aSNaveen Krishna Ch .nr_clk_ids = PERIC0_NR_CLK, 653532abc3aSNaveen Krishna Ch .clk_regs = peric0_clk_regs, 654532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 655532abc3aSNaveen Krishna Ch }; 656532abc3aSNaveen Krishna Ch 657532abc3aSNaveen Krishna Ch static void __init exynos7_clk_peric0_init(struct device_node *np) 658532abc3aSNaveen Krishna Ch { 659532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &peric0_cmu_info); 660532abc3aSNaveen Krishna Ch } 661532abc3aSNaveen Krishna Ch 662532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 663532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIC10 0x0200 664532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIC11 0x0204 665ee74b56aSPadmavathi Venna #define MUX_SEL_PERIC12 0x0208 666532abc3aSNaveen Krishna Ch #define ENABLE_PCLK_PERIC1 0x0900 667532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_PERIC10 0x0A00 668532abc3aSNaveen Krishna Ch 669532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", 670532abc3aSNaveen Krishna Ch exynos7_clk_peric0_init); 671532abc3aSNaveen Krishna Ch 672532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_PERIC1 */ 67333b8b739SAlim Akhtar PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" }; 67433b8b739SAlim Akhtar PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" }; 67533b8b739SAlim Akhtar PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" }; 67633b8b739SAlim Akhtar PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" }; 67733b8b739SAlim Akhtar PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" }; 67833b8b739SAlim Akhtar PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" }; 67933b8b739SAlim Akhtar PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" }; 68033b8b739SAlim Akhtar PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" }; 68133b8b739SAlim Akhtar PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" }; 682532abc3aSNaveen Krishna Ch 683532abc3aSNaveen Krishna Ch static unsigned long peric1_clk_regs[] __initdata = { 684532abc3aSNaveen Krishna Ch MUX_SEL_PERIC10, 685532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 686ee74b56aSPadmavathi Venna MUX_SEL_PERIC12, 687532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 688532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 689532abc3aSNaveen Krishna Ch }; 690532abc3aSNaveen Krishna Ch 691532abc3aSNaveen Krishna Ch static struct samsung_mux_clock peric1_mux_clks[] __initdata = { 69233b8b739SAlim Akhtar MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p, 693532abc3aSNaveen Krishna Ch MUX_SEL_PERIC10, 0, 1), 694532abc3aSNaveen Krishna Ch 69533b8b739SAlim Akhtar MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p, 696ee74b56aSPadmavathi Venna MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), 69733b8b739SAlim Akhtar MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p, 698ee74b56aSPadmavathi Venna MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), 69933b8b739SAlim Akhtar MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p, 700ee74b56aSPadmavathi Venna MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), 70133b8b739SAlim Akhtar MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p, 702ee74b56aSPadmavathi Venna MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), 70333b8b739SAlim Akhtar MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p, 704ee74b56aSPadmavathi Venna MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), 70533b8b739SAlim Akhtar MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p, 706532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 20, 1), 70733b8b739SAlim Akhtar MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p, 708532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 24, 1), 70933b8b739SAlim Akhtar MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p, 710532abc3aSNaveen Krishna Ch MUX_SEL_PERIC11, 28, 1), 711532abc3aSNaveen Krishna Ch }; 712532abc3aSNaveen Krishna Ch 713532abc3aSNaveen Krishna Ch static struct samsung_gate_clock peric1_gate_clks[] __initdata = { 71457a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 71557a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 4, 0, 0), 71657a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 71757a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 5, 0, 0), 71857a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", 71957a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 6, 0, 0), 72057a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", 72157a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 7, 0, 0), 72257a2b485SNaveen Krishna Ch GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", 72357a2b485SNaveen Krishna Ch ENABLE_PCLK_PERIC1, 8, 0, 0), 724532abc3aSNaveen Krishna Ch GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", 725532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 9, 0, 0), 726532abc3aSNaveen Krishna Ch GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", 727532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 10, 0, 0), 728532abc3aSNaveen Krishna Ch GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 729532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIC1, 11, 0, 0), 730ee74b56aSPadmavathi Venna GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user", 731ee74b56aSPadmavathi Venna ENABLE_PCLK_PERIC1, 12, 0, 0), 732ee74b56aSPadmavathi Venna GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user", 733ee74b56aSPadmavathi Venna ENABLE_PCLK_PERIC1, 13, 0, 0), 734ee74b56aSPadmavathi Venna GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user", 735ee74b56aSPadmavathi Venna ENABLE_PCLK_PERIC1, 14, 0, 0), 736ee74b56aSPadmavathi Venna GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user", 737ee74b56aSPadmavathi Venna ENABLE_PCLK_PERIC1, 15, 0, 0), 738ee74b56aSPadmavathi Venna GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user", 739ee74b56aSPadmavathi Venna ENABLE_PCLK_PERIC1, 16, 0, 0), 7409f930a39SPadmavathi Venna GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user", 7419f930a39SPadmavathi Venna ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0), 7429f930a39SPadmavathi Venna GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user", 7439f930a39SPadmavathi Venna ENABLE_PCLK_PERIC1, 18, 0, 0), 7449f930a39SPadmavathi Venna GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user", 7459f930a39SPadmavathi Venna ENABLE_PCLK_PERIC1, 19, 0, 0), 746532abc3aSNaveen Krishna Ch 747532abc3aSNaveen Krishna Ch GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 748532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 9, 0, 0), 749532abc3aSNaveen Krishna Ch GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", 750532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 10, 0, 0), 751532abc3aSNaveen Krishna Ch GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 752532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIC10, 11, 0, 0), 753ee74b56aSPadmavathi Venna GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user", 754ee74b56aSPadmavathi Venna ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0), 755ee74b56aSPadmavathi Venna GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user", 756ee74b56aSPadmavathi Venna ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0), 757ee74b56aSPadmavathi Venna GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user", 758ee74b56aSPadmavathi Venna ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0), 759ee74b56aSPadmavathi Venna GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user", 760ee74b56aSPadmavathi Venna ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0), 761ee74b56aSPadmavathi Venna GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user", 762ee74b56aSPadmavathi Venna ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0), 7639f930a39SPadmavathi Venna GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1", 7649f930a39SPadmavathi Venna ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0), 7659f930a39SPadmavathi Venna GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1", 7669f930a39SPadmavathi Venna ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0), 7679f930a39SPadmavathi Venna GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif", 7689f930a39SPadmavathi Venna ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), 769532abc3aSNaveen Krishna Ch }; 770532abc3aSNaveen Krishna Ch 771532abc3aSNaveen Krishna Ch static struct samsung_cmu_info peric1_cmu_info __initdata = { 772532abc3aSNaveen Krishna Ch .mux_clks = peric1_mux_clks, 773532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 774532abc3aSNaveen Krishna Ch .gate_clks = peric1_gate_clks, 775532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 776532abc3aSNaveen Krishna Ch .nr_clk_ids = PERIC1_NR_CLK, 777532abc3aSNaveen Krishna Ch .clk_regs = peric1_clk_regs, 778532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 779532abc3aSNaveen Krishna Ch }; 780532abc3aSNaveen Krishna Ch 781532abc3aSNaveen Krishna Ch static void __init exynos7_clk_peric1_init(struct device_node *np) 782532abc3aSNaveen Krishna Ch { 783532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &peric1_cmu_info); 784532abc3aSNaveen Krishna Ch } 785532abc3aSNaveen Krishna Ch 786532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", 787532abc3aSNaveen Krishna Ch exynos7_clk_peric1_init); 788532abc3aSNaveen Krishna Ch 789532abc3aSNaveen Krishna Ch /* Register Offset definitions for CMU_PERIS (0x10040000) */ 790532abc3aSNaveen Krishna Ch #define MUX_SEL_PERIS 0x0200 7912ab2dfe5SNaveen Krishna Ch #define ENABLE_PCLK_PERIS 0x0900 792532abc3aSNaveen Krishna Ch #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 7932ab2dfe5SNaveen Krishna Ch #define ENABLE_SCLK_PERIS 0x0A00 794532abc3aSNaveen Krishna Ch #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 795532abc3aSNaveen Krishna Ch 796532abc3aSNaveen Krishna Ch /* List of parent clocks for Muxes in CMU_PERIS */ 7976ce0f5cfSAlim Akhtar PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" }; 798532abc3aSNaveen Krishna Ch 799532abc3aSNaveen Krishna Ch static unsigned long peris_clk_regs[] __initdata = { 800532abc3aSNaveen Krishna Ch MUX_SEL_PERIS, 8012ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIS, 802532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIS_SECURE_CHIPID, 8032ab2dfe5SNaveen Krishna Ch ENABLE_SCLK_PERIS, 804532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIS_SECURE_CHIPID, 805532abc3aSNaveen Krishna Ch }; 806532abc3aSNaveen Krishna Ch 807532abc3aSNaveen Krishna Ch static struct samsung_mux_clock peris_mux_clks[] __initdata = { 808532abc3aSNaveen Krishna Ch MUX(0, "mout_aclk_peris_66_user", 8096ce0f5cfSAlim Akhtar mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1), 810532abc3aSNaveen Krishna Ch }; 811532abc3aSNaveen Krishna Ch 812532abc3aSNaveen Krishna Ch static struct samsung_gate_clock peris_gate_clks[] __initdata = { 8132ab2dfe5SNaveen Krishna Ch GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 8142ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIS, 6, 0, 0), 8152ab2dfe5SNaveen Krishna Ch GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 8162ab2dfe5SNaveen Krishna Ch ENABLE_PCLK_PERIS, 10, 0, 0), 8172ab2dfe5SNaveen Krishna Ch 818532abc3aSNaveen Krishna Ch GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", 819532abc3aSNaveen Krishna Ch ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 820532abc3aSNaveen Krishna Ch GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", 821532abc3aSNaveen Krishna Ch ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 8222ab2dfe5SNaveen Krishna Ch 8232ab2dfe5SNaveen Krishna Ch GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 824532abc3aSNaveen Krishna Ch }; 825532abc3aSNaveen Krishna Ch 826532abc3aSNaveen Krishna Ch static struct samsung_cmu_info peris_cmu_info __initdata = { 827532abc3aSNaveen Krishna Ch .mux_clks = peris_mux_clks, 828532abc3aSNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 829532abc3aSNaveen Krishna Ch .gate_clks = peris_gate_clks, 830532abc3aSNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 831532abc3aSNaveen Krishna Ch .nr_clk_ids = PERIS_NR_CLK, 832532abc3aSNaveen Krishna Ch .clk_regs = peris_clk_regs, 833532abc3aSNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 834532abc3aSNaveen Krishna Ch }; 835532abc3aSNaveen Krishna Ch 836532abc3aSNaveen Krishna Ch static void __init exynos7_clk_peris_init(struct device_node *np) 837532abc3aSNaveen Krishna Ch { 838532abc3aSNaveen Krishna Ch samsung_cmu_register_one(np, &peris_cmu_info); 839532abc3aSNaveen Krishna Ch } 840532abc3aSNaveen Krishna Ch 841532abc3aSNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", 842532abc3aSNaveen Krishna Ch exynos7_clk_peris_init); 8436d0c8c72SNaveen Krishna Ch 8446d0c8c72SNaveen Krishna Ch /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 8456d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS00 0x0200 8466d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS01 0x0204 84783f191a7SVivek Gautam #define MUX_SEL_FSYS02 0x0208 84883f191a7SVivek Gautam #define ENABLE_ACLK_FSYS00 0x0800 8496d0c8c72SNaveen Krishna Ch #define ENABLE_ACLK_FSYS01 0x0804 85083f191a7SVivek Gautam #define ENABLE_SCLK_FSYS01 0x0A04 85183f191a7SVivek Gautam #define ENABLE_SCLK_FSYS02 0x0A08 85283f191a7SVivek Gautam #define ENABLE_SCLK_FSYS04 0x0A10 8536d0c8c72SNaveen Krishna Ch 8546d0c8c72SNaveen Krishna Ch /* 8556d0c8c72SNaveen Krishna Ch * List of parent clocks for Muxes in CMU_FSYS0 8566d0c8c72SNaveen Krishna Ch */ 857a259a61bSAlim Akhtar PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" }; 858a259a61bSAlim Akhtar PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" }; 8596d0c8c72SNaveen Krishna Ch 860a259a61bSAlim Akhtar PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" }; 861a259a61bSAlim Akhtar PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll", 86283f191a7SVivek Gautam "phyclk_usbdrd300_udrd30_phyclock" }; 863a259a61bSAlim Akhtar PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll", 86483f191a7SVivek Gautam "phyclk_usbdrd300_udrd30_pipe_pclk" }; 86583f191a7SVivek Gautam 86683f191a7SVivek Gautam /* fixed rate clocks used in the FSYS0 block */ 86783f191a7SVivek Gautam struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { 86883f191a7SVivek Gautam FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 86983f191a7SVivek Gautam CLK_IS_ROOT, 60000000), 87083f191a7SVivek Gautam FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 87183f191a7SVivek Gautam CLK_IS_ROOT, 125000000), 87283f191a7SVivek Gautam }; 87383f191a7SVivek Gautam 8746d0c8c72SNaveen Krishna Ch static unsigned long fsys0_clk_regs[] __initdata = { 8756d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS00, 8766d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS01, 87783f191a7SVivek Gautam MUX_SEL_FSYS02, 87883f191a7SVivek Gautam ENABLE_ACLK_FSYS00, 8796d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS01, 88083f191a7SVivek Gautam ENABLE_SCLK_FSYS01, 88183f191a7SVivek Gautam ENABLE_SCLK_FSYS02, 88283f191a7SVivek Gautam ENABLE_SCLK_FSYS04, 8836d0c8c72SNaveen Krishna Ch }; 8846d0c8c72SNaveen Krishna Ch 8856d0c8c72SNaveen Krishna Ch static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { 886a259a61bSAlim Akhtar MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p, 8876d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS00, 24, 1), 8886d0c8c72SNaveen Krishna Ch 889a259a61bSAlim Akhtar MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p, 890a259a61bSAlim Akhtar MUX_SEL_FSYS01, 24, 1), 891a259a61bSAlim Akhtar MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p, 89283f191a7SVivek Gautam MUX_SEL_FSYS01, 28, 1), 89383f191a7SVivek Gautam 89483f191a7SVivek Gautam MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 895a259a61bSAlim Akhtar mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p, 89683f191a7SVivek Gautam MUX_SEL_FSYS02, 24, 1), 89783f191a7SVivek Gautam MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user", 898a259a61bSAlim Akhtar mout_phyclk_usbdrd300_udrd30_phyclk_user_p, 89983f191a7SVivek Gautam MUX_SEL_FSYS02, 28, 1), 9006d0c8c72SNaveen Krishna Ch }; 9016d0c8c72SNaveen Krishna Ch 9026d0c8c72SNaveen Krishna Ch static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 9039cc2a0c9SPadmavathi Venna GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", 9049cc2a0c9SPadmavathi Venna ENABLE_ACLK_FSYS00, 3, 0, 0), 9059cc2a0c9SPadmavathi Venna GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", 9069cc2a0c9SPadmavathi Venna ENABLE_ACLK_FSYS00, 4, 0, 0), 9077cca2e07SAlim Akhtar GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", 9087cca2e07SAlim Akhtar "mout_aclk_fsys0_200_user", 9097cca2e07SAlim Akhtar ENABLE_ACLK_FSYS00, 19, 0, 0), 91083f191a7SVivek Gautam 91183f191a7SVivek Gautam GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", 91283f191a7SVivek Gautam ENABLE_ACLK_FSYS01, 29, 0, 0), 9136d0c8c72SNaveen Krishna Ch GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 9146d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS01, 31, 0, 0), 91583f191a7SVivek Gautam 91683f191a7SVivek Gautam GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk", 91783f191a7SVivek Gautam "mout_sclk_usbdrd300_user", 91883f191a7SVivek Gautam ENABLE_SCLK_FSYS01, 4, 0, 0), 91983f191a7SVivek Gautam GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll", 92083f191a7SVivek Gautam ENABLE_SCLK_FSYS01, 8, 0, 0), 92183f191a7SVivek Gautam 92283f191a7SVivek Gautam GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER, 92383f191a7SVivek Gautam "phyclk_usbdrd300_udrd30_pipe_pclk_user", 92483f191a7SVivek Gautam "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 92583f191a7SVivek Gautam ENABLE_SCLK_FSYS02, 24, 0, 0), 92683f191a7SVivek Gautam GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER, 92783f191a7SVivek Gautam "phyclk_usbdrd300_udrd30_phyclk_user", 92883f191a7SVivek Gautam "mout_phyclk_usbdrd300_udrd30_phyclk_user", 92983f191a7SVivek Gautam ENABLE_SCLK_FSYS02, 28, 0, 0), 93083f191a7SVivek Gautam 93183f191a7SVivek Gautam GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy", 93283f191a7SVivek Gautam "fin_pll", 93383f191a7SVivek Gautam ENABLE_SCLK_FSYS04, 28, 0, 0), 9346d0c8c72SNaveen Krishna Ch }; 9356d0c8c72SNaveen Krishna Ch 9366d0c8c72SNaveen Krishna Ch static struct samsung_cmu_info fsys0_cmu_info __initdata = { 9376d0c8c72SNaveen Krishna Ch .mux_clks = fsys0_mux_clks, 9386d0c8c72SNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 9396d0c8c72SNaveen Krishna Ch .gate_clks = fsys0_gate_clks, 9406d0c8c72SNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 9417cca2e07SAlim Akhtar .nr_clk_ids = FSYS0_NR_CLK, 9426d0c8c72SNaveen Krishna Ch .clk_regs = fsys0_clk_regs, 9436d0c8c72SNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 9446d0c8c72SNaveen Krishna Ch }; 9456d0c8c72SNaveen Krishna Ch 9466d0c8c72SNaveen Krishna Ch static void __init exynos7_clk_fsys0_init(struct device_node *np) 9476d0c8c72SNaveen Krishna Ch { 9486d0c8c72SNaveen Krishna Ch samsung_cmu_register_one(np, &fsys0_cmu_info); 9496d0c8c72SNaveen Krishna Ch } 9506d0c8c72SNaveen Krishna Ch 9516d0c8c72SNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", 9526d0c8c72SNaveen Krishna Ch exynos7_clk_fsys0_init); 9536d0c8c72SNaveen Krishna Ch 9546d0c8c72SNaveen Krishna Ch /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ 9556d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS10 0x0200 9566d0c8c72SNaveen Krishna Ch #define MUX_SEL_FSYS11 0x0204 9576d0c8c72SNaveen Krishna Ch #define ENABLE_ACLK_FSYS1 0x0800 9586d0c8c72SNaveen Krishna Ch 9596d0c8c72SNaveen Krishna Ch /* 9606d0c8c72SNaveen Krishna Ch * List of parent clocks for Muxes in CMU_FSYS1 9616d0c8c72SNaveen Krishna Ch */ 962753195a7SAlim Akhtar PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" }; 963753195a7SAlim Akhtar PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" }; 964753195a7SAlim Akhtar PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" }; 9656d0c8c72SNaveen Krishna Ch 9666d0c8c72SNaveen Krishna Ch static unsigned long fsys1_clk_regs[] __initdata = { 9676d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS10, 9686d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS11, 9696d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS1, 9706d0c8c72SNaveen Krishna Ch }; 9716d0c8c72SNaveen Krishna Ch 9726d0c8c72SNaveen Krishna Ch static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { 973753195a7SAlim Akhtar MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p, 9746d0c8c72SNaveen Krishna Ch MUX_SEL_FSYS10, 28, 1), 9756d0c8c72SNaveen Krishna Ch 976753195a7SAlim Akhtar MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p, 977753195a7SAlim Akhtar MUX_SEL_FSYS11, 24, 1), 978753195a7SAlim Akhtar MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p, 979753195a7SAlim Akhtar MUX_SEL_FSYS11, 28, 1), 9806d0c8c72SNaveen Krishna Ch }; 9816d0c8c72SNaveen Krishna Ch 9826d0c8c72SNaveen Krishna Ch static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { 9836d0c8c72SNaveen Krishna Ch GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", 9846d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS1, 29, 0, 0), 9856d0c8c72SNaveen Krishna Ch GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", 9866d0c8c72SNaveen Krishna Ch ENABLE_ACLK_FSYS1, 30, 0, 0), 9876d0c8c72SNaveen Krishna Ch }; 9886d0c8c72SNaveen Krishna Ch 9896d0c8c72SNaveen Krishna Ch static struct samsung_cmu_info fsys1_cmu_info __initdata = { 9906d0c8c72SNaveen Krishna Ch .mux_clks = fsys1_mux_clks, 9916d0c8c72SNaveen Krishna Ch .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 9926d0c8c72SNaveen Krishna Ch .gate_clks = fsys1_gate_clks, 9936d0c8c72SNaveen Krishna Ch .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 994167c9e4dSAlim Akhtar .nr_clk_ids = FSYS1_NR_CLK, 9956d0c8c72SNaveen Krishna Ch .clk_regs = fsys1_clk_regs, 9966d0c8c72SNaveen Krishna Ch .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 9976d0c8c72SNaveen Krishna Ch }; 9986d0c8c72SNaveen Krishna Ch 9996d0c8c72SNaveen Krishna Ch static void __init exynos7_clk_fsys1_init(struct device_node *np) 10006d0c8c72SNaveen Krishna Ch { 10016d0c8c72SNaveen Krishna Ch samsung_cmu_register_one(np, &fsys1_cmu_info); 10026d0c8c72SNaveen Krishna Ch } 10036d0c8c72SNaveen Krishna Ch 10046d0c8c72SNaveen Krishna Ch CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 10056d0c8c72SNaveen Krishna Ch exynos7_clk_fsys1_init); 100649cab82cSTony K Nadackal 100749cab82cSTony K Nadackal #define MUX_SEL_MSCL 0x0200 100849cab82cSTony K Nadackal #define DIV_MSCL 0x0600 100949cab82cSTony K Nadackal #define ENABLE_ACLK_MSCL 0x0800 101049cab82cSTony K Nadackal #define ENABLE_PCLK_MSCL 0x0900 101149cab82cSTony K Nadackal 101249cab82cSTony K Nadackal /* List of parent clocks for Muxes in CMU_MSCL */ 101349cab82cSTony K Nadackal PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; 101449cab82cSTony K Nadackal 101549cab82cSTony K Nadackal static unsigned long mscl_clk_regs[] __initdata = { 101649cab82cSTony K Nadackal MUX_SEL_MSCL, 101749cab82cSTony K Nadackal DIV_MSCL, 101849cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 101949cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 102049cab82cSTony K Nadackal }; 102149cab82cSTony K Nadackal 102249cab82cSTony K Nadackal static struct samsung_mux_clock mscl_mux_clks[] __initdata = { 102349cab82cSTony K Nadackal MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", 102449cab82cSTony K Nadackal mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), 102549cab82cSTony K Nadackal }; 102649cab82cSTony K Nadackal static struct samsung_div_clock mscl_div_clks[] __initdata = { 102749cab82cSTony K Nadackal DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", 102849cab82cSTony K Nadackal DIV_MSCL, 0, 3), 102949cab82cSTony K Nadackal }; 103049cab82cSTony K Nadackal static struct samsung_gate_clock mscl_gate_clks[] __initdata = { 103149cab82cSTony K Nadackal 103249cab82cSTony K Nadackal GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", 103349cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 31, 0, 0), 103449cab82cSTony K Nadackal GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532", 103549cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 30, 0, 0), 103649cab82cSTony K Nadackal GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532", 103749cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 29, 0, 0), 103849cab82cSTony K Nadackal GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532", 103949cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 28, 0, 0), 104049cab82cSTony K Nadackal GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0", 104149cab82cSTony K Nadackal "usermux_aclk_mscl_532", 104249cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 27, 0, 0), 104349cab82cSTony K Nadackal GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1", 104449cab82cSTony K Nadackal "usermux_aclk_mscl_532", 104549cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 26, 0, 0), 104649cab82cSTony K Nadackal GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532", 104749cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 25, 0, 0), 104849cab82cSTony K Nadackal GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532", 104949cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 24, 0, 0), 105049cab82cSTony K Nadackal GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge", 105149cab82cSTony K Nadackal "usermux_aclk_mscl_532", 105249cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 23, 0, 0), 105349cab82cSTony K Nadackal GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532", 105449cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 22, 0, 0), 105549cab82cSTony K Nadackal GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532", 105649cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 21, 0, 0), 105749cab82cSTony K Nadackal GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532", 105849cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 20, 0, 0), 105949cab82cSTony K Nadackal GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532", 106049cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 19, 0, 0), 106149cab82cSTony K Nadackal GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532", 106249cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 18, 0, 0), 106349cab82cSTony K Nadackal GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532", 106449cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 17, 0, 0), 106549cab82cSTony K Nadackal GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532", 106649cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 16, 0, 0), 106749cab82cSTony K Nadackal GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p", 106849cab82cSTony K Nadackal "usermux_aclk_mscl_532", 106949cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 15, 0, 0), 107049cab82cSTony K Nadackal GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p", 107149cab82cSTony K Nadackal "usermux_aclk_mscl_532", 107249cab82cSTony K Nadackal ENABLE_ACLK_MSCL, 14, 0, 0), 107349cab82cSTony K Nadackal 107449cab82cSTony K Nadackal GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl", 107549cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 31, 0, 0), 107649cab82cSTony K Nadackal GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl", 107749cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 30, 0, 0), 107849cab82cSTony K Nadackal GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl", 107949cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 29, 0, 0), 108049cab82cSTony K Nadackal GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl", 108149cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 28, 0, 0), 108249cab82cSTony K Nadackal GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl", 108349cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 27, 0, 0), 108449cab82cSTony K Nadackal GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl", 108549cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 26, 0, 0), 108649cab82cSTony K Nadackal GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl", 108749cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 25, 0, 0), 108849cab82cSTony K Nadackal GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl", 108949cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 24, 0, 0), 109049cab82cSTony K Nadackal GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl", 109149cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 23, 0, 0), 109249cab82cSTony K Nadackal GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl", 109349cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 22, 0, 0), 109449cab82cSTony K Nadackal GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl", 109549cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 21, 0, 0), 109649cab82cSTony K Nadackal GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl", 109749cab82cSTony K Nadackal ENABLE_PCLK_MSCL, 20, 0, 0), 109849cab82cSTony K Nadackal }; 109949cab82cSTony K Nadackal 110049cab82cSTony K Nadackal static struct samsung_cmu_info mscl_cmu_info __initdata = { 110149cab82cSTony K Nadackal .mux_clks = mscl_mux_clks, 110249cab82cSTony K Nadackal .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 110349cab82cSTony K Nadackal .div_clks = mscl_div_clks, 110449cab82cSTony K Nadackal .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 110549cab82cSTony K Nadackal .gate_clks = mscl_gate_clks, 110649cab82cSTony K Nadackal .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 110749cab82cSTony K Nadackal .nr_clk_ids = MSCL_NR_CLK, 110849cab82cSTony K Nadackal .clk_regs = mscl_clk_regs, 110949cab82cSTony K Nadackal .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 111049cab82cSTony K Nadackal }; 111149cab82cSTony K Nadackal 111249cab82cSTony K Nadackal static void __init exynos7_clk_mscl_init(struct device_node *np) 111349cab82cSTony K Nadackal { 111449cab82cSTony K Nadackal samsung_cmu_register_one(np, &mscl_cmu_info); 111549cab82cSTony K Nadackal } 111649cab82cSTony K Nadackal 111749cab82cSTony K Nadackal CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", 111849cab82cSTony K Nadackal exynos7_clk_mscl_init); 11199f930a39SPadmavathi Venna 11209f930a39SPadmavathi Venna /* Register Offset definitions for CMU_AUD (0x114C0000) */ 11219f930a39SPadmavathi Venna #define MUX_SEL_AUD 0x0200 11229f930a39SPadmavathi Venna #define DIV_AUD0 0x0600 11239f930a39SPadmavathi Venna #define DIV_AUD1 0x0604 11249f930a39SPadmavathi Venna #define ENABLE_ACLK_AUD 0x0800 11259f930a39SPadmavathi Venna #define ENABLE_PCLK_AUD 0x0900 11269f930a39SPadmavathi Venna #define ENABLE_SCLK_AUD 0x0A00 11279f930a39SPadmavathi Venna 11289f930a39SPadmavathi Venna /* 11299f930a39SPadmavathi Venna * List of parent clocks for Muxes in CMU_AUD 11309f930a39SPadmavathi Venna */ 11319f930a39SPadmavathi Venna PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; 11329f930a39SPadmavathi Venna PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; 11339f930a39SPadmavathi Venna 11349f930a39SPadmavathi Venna static unsigned long aud_clk_regs[] __initdata = { 11359f930a39SPadmavathi Venna MUX_SEL_AUD, 11369f930a39SPadmavathi Venna DIV_AUD0, 11379f930a39SPadmavathi Venna DIV_AUD1, 11389f930a39SPadmavathi Venna ENABLE_ACLK_AUD, 11399f930a39SPadmavathi Venna ENABLE_PCLK_AUD, 11409f930a39SPadmavathi Venna ENABLE_SCLK_AUD, 11419f930a39SPadmavathi Venna }; 11429f930a39SPadmavathi Venna 11439f930a39SPadmavathi Venna static struct samsung_mux_clock aud_mux_clks[] __initdata = { 11449f930a39SPadmavathi Venna MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), 11459f930a39SPadmavathi Venna MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), 11469f930a39SPadmavathi Venna MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), 11479f930a39SPadmavathi Venna }; 11489f930a39SPadmavathi Venna 11499f930a39SPadmavathi Venna static struct samsung_div_clock aud_div_clks[] __initdata = { 11509f930a39SPadmavathi Venna DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), 11519f930a39SPadmavathi Venna DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), 11529f930a39SPadmavathi Venna DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), 11539f930a39SPadmavathi Venna 11549f930a39SPadmavathi Venna DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4), 11559f930a39SPadmavathi Venna DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8), 11569f930a39SPadmavathi Venna DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4), 11579f930a39SPadmavathi Venna DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5), 11589f930a39SPadmavathi Venna DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), 11599f930a39SPadmavathi Venna }; 11609f930a39SPadmavathi Venna 11619f930a39SPadmavathi Venna static struct samsung_gate_clock aud_gate_clks[] __initdata = { 11629f930a39SPadmavathi Venna GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", 11639f930a39SPadmavathi Venna ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 11649f930a39SPadmavathi Venna GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", 11659f930a39SPadmavathi Venna ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0), 11669f930a39SPadmavathi Venna GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0), 11679f930a39SPadmavathi Venna GATE(0, "sclk_slimbus", "dout_sclk_slimbus", 11689f930a39SPadmavathi Venna ENABLE_SCLK_AUD, 30, 0, 0), 11699f930a39SPadmavathi Venna 11709f930a39SPadmavathi Venna GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), 11719f930a39SPadmavathi Venna GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), 11729f930a39SPadmavathi Venna GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), 11739f930a39SPadmavathi Venna GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), 11749f930a39SPadmavathi Venna GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), 11759f930a39SPadmavathi Venna GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), 11769f930a39SPadmavathi Venna GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud", 11779f930a39SPadmavathi Venna ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), 11789f930a39SPadmavathi Venna GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud", 11799f930a39SPadmavathi Venna ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 11809f930a39SPadmavathi Venna GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0), 11819f930a39SPadmavathi Venna GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0), 11829f930a39SPadmavathi Venna 11839f930a39SPadmavathi Venna GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0), 11849f930a39SPadmavathi Venna GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud", 11859f930a39SPadmavathi Venna ENABLE_ACLK_AUD, 28, 0, 0), 11869f930a39SPadmavathi Venna GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), 11879f930a39SPadmavathi Venna }; 11889f930a39SPadmavathi Venna 11899f930a39SPadmavathi Venna static struct samsung_cmu_info aud_cmu_info __initdata = { 11909f930a39SPadmavathi Venna .mux_clks = aud_mux_clks, 11919f930a39SPadmavathi Venna .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 11929f930a39SPadmavathi Venna .div_clks = aud_div_clks, 11939f930a39SPadmavathi Venna .nr_div_clks = ARRAY_SIZE(aud_div_clks), 11949f930a39SPadmavathi Venna .gate_clks = aud_gate_clks, 11959f930a39SPadmavathi Venna .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 11969f930a39SPadmavathi Venna .nr_clk_ids = AUD_NR_CLK, 11979f930a39SPadmavathi Venna .clk_regs = aud_clk_regs, 11989f930a39SPadmavathi Venna .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 11999f930a39SPadmavathi Venna }; 12009f930a39SPadmavathi Venna 12019f930a39SPadmavathi Venna static void __init exynos7_clk_aud_init(struct device_node *np) 12029f930a39SPadmavathi Venna { 12039f930a39SPadmavathi Venna samsung_cmu_register_one(np, &aud_cmu_info); 12049f930a39SPadmavathi Venna } 12059f930a39SPadmavathi Venna 12069f930a39SPadmavathi Venna CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", 12079f930a39SPadmavathi Venna exynos7_clk_aud_init); 1208