1 /* 2 * R-Car Gen3 Clock Pulse Generator 3 * 4 * Copyright (C) 2015-2016 Glider bvba 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 */ 10 11 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ 12 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ 13 14 enum rcar_gen3_clk_types { 15 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 16 CLK_TYPE_GEN3_PLL0, 17 CLK_TYPE_GEN3_PLL1, 18 CLK_TYPE_GEN3_PLL2, 19 CLK_TYPE_GEN3_PLL3, 20 CLK_TYPE_GEN3_PLL4, 21 CLK_TYPE_GEN3_SD, 22 CLK_TYPE_GEN3_R, 23 CLK_TYPE_GEN3_PE, 24 CLK_TYPE_GEN3_Z, 25 CLK_TYPE_GEN3_Z2, 26 }; 27 28 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 29 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 30 31 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 32 _div_clean) \ 33 DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ 34 (_parent_sscg) << 16 | (_parent_clean), \ 35 .div = (_div_sscg) << 16 | (_div_clean)) 36 37 struct rcar_gen3_cpg_pll_config { 38 u8 extal_div; 39 u8 pll1_mult; 40 u8 pll1_div; 41 u8 pll3_mult; 42 u8 pll3_div; 43 }; 44 45 #define CPG_RCKCR 0x240 46 47 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, 48 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 49 struct clk **clks, void __iomem *base, 50 struct raw_notifier_head *notifiers); 51 int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 52 unsigned int clk_extalr, u32 mode); 53 54 #endif 55