1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * R-Car Gen3 Clock Pulse Generator 4 * 5 * Copyright (C) 2015-2018 Glider bvba 6 * 7 */ 8 9 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ 10 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ 11 12 enum rcar_gen3_clk_types { 13 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 14 CLK_TYPE_GEN3_PLL0, 15 CLK_TYPE_GEN3_PLL1, 16 CLK_TYPE_GEN3_PLL2, 17 CLK_TYPE_GEN3_PLL3, 18 CLK_TYPE_GEN3_PLL4, 19 CLK_TYPE_GEN3_SD, 20 CLK_TYPE_GEN3_R, 21 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ 22 CLK_TYPE_GEN3_Z, 23 CLK_TYPE_GEN3_Z2, 24 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ 25 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ 26 27 /* SoC specific definitions start here */ 28 CLK_TYPE_GEN3_SOC_BASE, 29 }; 30 31 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 32 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 33 34 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 35 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ 36 (_parent0) << 16 | (_parent1), \ 37 .div = (_div0) << 16 | (_div1), .offset = _md) 38 39 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 40 _div_clean) \ 41 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \ 42 _parent_clean, _div_clean) 43 44 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ 45 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) 46 47 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ 48 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ 49 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) 50 51 struct rcar_gen3_cpg_pll_config { 52 u8 extal_div; 53 u8 pll1_mult; 54 u8 pll1_div; 55 u8 pll3_mult; 56 u8 pll3_div; 57 u8 osc_prediv; 58 }; 59 60 #define CPG_RCKCR 0x240 61 62 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, 63 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 64 struct clk **clks, void __iomem *base, 65 struct raw_notifier_head *notifiers); 66 int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 67 unsigned int clk_extalr, u32 mode); 68 69 #endif 70